Searched refs:ATTR (Results 1 - 25 of 105) sorted by last modified time

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/external/mesa3d/src/mesa/state_tracker/
H A Dst_cb_drawtex.c140 #define SET_ATTRIB(VERT, ATTR, X, Y, Z, W) \
142 GLuint k = (((VERT) * numAttribs + (ATTR)) * 4); \
/external/mesa3d/src/mesa/swrast_setup/
H A Dss_context.c96 #define EMIT_ATTR( ATTR, STYLE, MEMBER ) \
98 map[e].attrib = (ATTR); \
/external/mesa3d/src/mesa/vbo/
H A Dvbo_attrib_tmp.h29 #define ATTR1FV( A, V ) ATTR( A, 1, GL_FLOAT, (V)[0], 0, 0, 1 )
30 #define ATTR2FV( A, V ) ATTR( A, 2, GL_FLOAT, (V)[0], (V)[1], 0, 1 )
31 #define ATTR3FV( A, V ) ATTR( A, 3, GL_FLOAT, (V)[0], (V)[1], (V)[2], 1 )
32 #define ATTR4FV( A, V ) ATTR( A, 4, GL_FLOAT, (V)[0], (V)[1], (V)[2], (V)[3] )
34 #define ATTR1F( A, X ) ATTR( A, 1, GL_FLOAT, X, 0, 0, 1 )
35 #define ATTR2F( A, X, Y ) ATTR( A, 2, GL_FLOAT, X, Y, 0, 1 )
36 #define ATTR3F( A, X, Y, Z ) ATTR( A, 3, GL_FLOAT, X, Y, Z, 1 )
37 #define ATTR4F( A, X, Y, Z, W ) ATTR( A, 4, GL_FLOAT, X, Y, Z, W )
40 #define ATTRI( A, N, X, Y, Z, W) ATTR( A, N, GL_INT, \
55 #define ATTRUI( A, N, X, Y, Z, W) ATTR(
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H A Dvbo_exec_api.c405 #define ATTR( A, N, T, V0, V1, V2, V3 ) \ macro
1401 ATTR(VBO_ATTRIB_GENERIC0 + index, 4, GL_FLOAT, x, y, z, w);
H A Dvbo_save_api.c697 #define ATTR(A, N, T, V0, V1, V2, V3) \ macro
732 #define MAT( ATTR, N, face, params ) \
735 MAT_ATTR( ATTR, N, params ); /* front */ \
737 MAT_ATTR( ATTR + 1, N, params ); /* back */ \
/external/mesa3d/src/mesa/drivers/dri/i915/
H A Di830_vtbl.c51 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
53 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
H A Di915_context.h299 #define EMIT_ATTR( ATTR, STYLE, S4, SZ ) \
301 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vec4.h53 ATTR, enumerator in enum:brw::register_file
H A Dbrw_vec4_copy_propagation.cpp197 value.file != ATTR)
H A Dbrw_vec4_emit.cpp61 /* We have to support ATTR as a destination for GL_FIXED fixup. */
62 if (inst->dst.file == ATTR) {
73 if (inst->src[i].file != ATTR)
247 case ATTR:
H A Dbrw_vec4_visitor.cpp797 reg = new(mem_ctx) dst_reg(ATTR, ir->location);
857 reg = new(mem_ctx) dst_reg(ATTR, VERT_ATTRIB_MAX);
2287 emit(MOV(reg, src_reg(dst_reg(ATTR, VERT_ATTRIB_EDGEFLAG,
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_swtcl.c62 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
64 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
H A Dr200_vertprog.h144 /* (1.0,1.0,1.0,1.0) vector (ATTR, plain ) */
145 #define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE)
149 #define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE)
157 /* components of ATTR register */
158 #define VSF_ATTR_X(reg) EASY_VSF_SOURCE(reg, X, X, X, X, ATTR, NONE)
159 #define VSF_ATTR_Y(reg) EASY_VSF_SOURCE(reg, Y, Y, Y, Y, ATTR, NONE)
160 #define VSF_ATTR_Z(reg) EASY_VSF_SOURCE(reg, Z, Z, Z, Z, ATTR, NONE)
161 #define VSF_ATTR_W(reg) EASY_VSF_SOURCE(reg, W, W, W, W, ATTR, NONE)
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_swtcl.c67 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
69 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
/external/llvm/test/MC/ARM/
H A Ddirective-arch-armv2.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 2
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4
24 @ CHECK-ATTR
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H A Ddirective-arch-armv2a.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 2A
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4
24 @ CHECK-ATTR
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H A Ddirective-arch-armv3.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 3
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4
24 @ CHECK-ATTR
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H A Ddirective-arch-armv3m.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 3M
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4
24 @ CHECK-ATTR
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H A Ddirective-arch-armv4.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 4
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4
24 @ CHECK-ATTR
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H A Ddirective-arch-armv4t.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 4T
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v4T
24 @ CHECK-ATTR
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H A Ddirective-arch-armv5.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 5
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v5T
24 @ CHECK-ATTR
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H A Ddirective-arch-armv5t.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 5T
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v5T
24 @ CHECK-ATTR
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H A Ddirective-arch-armv5te.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 5TE
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v5TE
24 @ CHECK-ATTR
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H A Ddirective-arch-armv6-m.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 6-M
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v6-M
24 @ CHECK-ATTR
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H A Ddirective-arch-armv6.s9 @ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR
16 @ CHECK-ATTR: FileAttributes {
17 @ CHECK-ATTR: Attribute {
18 @ CHECK-ATTR: TagName: CPU_name
19 @ CHECK-ATTR: Value: 6
20 @ CHECK-ATTR: }
21 @ CHECK-ATTR: Attribute {
22 @ CHECK-ATTR: TagName: CPU_arch
23 @ CHECK-ATTR: Description: ARM v6
24 @ CHECK-ATTR
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