/external/valgrind/main/VEX/priv/ |
H A D | host_amd64_isel.c | 940 AMD64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr ); 943 if (e->Iex.Load.end != Iend_LE) 2080 && e->Iex.Load.end == Iend_LE) { 2081 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); 2575 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2578 vassert(e->Iex.Load.ty == Ity_F32); 2579 am = iselIntExpr_AMode(env, e->Iex.Load.addr); 2790 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2793 vassert(e->Iex.Load.ty == Ity_F64); 2794 am = iselIntExpr_AMode(env, e->Iex.Load [all...] |
H A D | host_arm64_isel.c | 1634 if (e->Iex.Load.end != Iend_LE) 1638 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); 1643 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); 1648 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); 1653 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); 2006 = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I32); 2023 = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I8); 2496 //ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2498 //ZZ vassert(e->Iex.Load.ty == Ity_I64); 2499 //ZZ rA = iselIntExpr_R(env, e->Iex.Load [all...] |
H A D | host_arm_isel.c | 1210 if (e->Iex.Load.end != Iend_LE) 1214 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr ); 1219 ARMAMode2* amode = iselIntExpr_AMode2 ( env, e->Iex.Load.addr ); 1226 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr ); 1951 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 1953 vassert(e->Iex.Load.ty == Ity_I64); 1954 rA = iselIntExpr_R(env, e->Iex.Load.addr); 2195 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2197 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr); 3817 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load [all...] |
H A D | host_mips_defs.c | 1364 i->Min.Load.sz = sz; 1365 i->Min.Load.src = src; 1366 i->Min.Load.dst = dst; 1754 Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR); 1755 UChar sz = i->Min.Load.sz; 1758 ppHRegMIPS(i->Min.Load.dst, mode64); 1760 ppMIPSAMode(i->Min.Load.src, mode64); 2054 addRegUsage_MIPSAMode(u, i->Min.Load.src); 2055 addHRegUse(u, HRmWrite, i->Min.Load.dst); 2206 mapRegs_MIPSAMode(m, i->Min.Load [all...] |
H A D | host_mips_defs.h | 328 Min_LoadL, /* mips Load Linked Word - LL */ 510 } Load; member in union:__anon31937::__anon31938
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H A D | host_mips_isel.c | 353 /* Load 2*I32 regs to fp reg */ 809 MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty); 811 if (e->Iex.Load.end != Iend_LE 812 && e->Iex.Load.end != Iend_BE) 2292 HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr); 2982 vassert(e->Iex.Load.ty == Ity_F32 2983 || (e->Iex.Load.ty == Ity_F64 && fp_mode64)); 2985 MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty); 2986 if (e->Iex.Load.ty == Ity_F64) { 3000 if (e->Iex.Load [all...] |
H A D | host_ppc_defs.c | 929 i->Pin.Load.sz = sz; 930 i->Pin.Load.src = src; 931 i->Pin.Load.dst = dst; 1710 Bool idxd = toBool(i->Pin.Load.src->tag == Pam_RR); 1711 UChar sz = i->Pin.Load.sz; 1714 ppHRegPPC(i->Pin.Load.dst); 1716 ppPPCAMode(i->Pin.Load.src); 2379 addRegUsage_PPCAMode(u, i->Pin.Load.src); 2380 addHRegUse(u, HRmWrite, i->Pin.Load.dst); 2726 mapRegs_PPCAMode(m, i->Pin.Load [all...] |
H A D | host_ppc_defs.h | 685 } Load; member in union:__anon31998::__anon31999 686 /* Load-and-reserve (lwarx, ldarx) */ 771 /* Load FP Status & Control Register */ 875 /* Load AltiVec Status & Control Register */
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H A D | host_ppc_isel.c | 529 /* Load 2*I32 regs to fp reg */ 555 /* Load I64 reg to fp reg */ 1295 /* Load src to vector[low lane] */ 1385 if (e->Iex.Load.end != Iend_BE) 1388 am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ ); 3078 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { 3081 HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr); 3667 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { 3670 vassert(e->Iex.Load.ty == Ity_F32); 3671 am_addr = iselWordExpr_AMode(env, e->Iex.Load [all...] |
H A D | host_s390_isel.c | 1100 s390_amode *am = s390_isel_amode(env, expr->Iex.Load.addr); 1102 if (expr->Iex.Load.end != Iend_BE) 1834 /* Load a literal into a register. Create a "load immediate" 1912 dst.variant.am = s390_isel_amode(env, expr->Iex.Load.addr); 1964 if (expr->Iex.Load.end != Iend_BE) 1967 addr_hi = expr->Iex.Load.addr; 2258 s390_amode *am = s390_isel_amode(env, expr->Iex.Load.addr); 2260 if (expr->Iex.Load.end != Iend_BE) 2280 /* Load a literal into a register. Create a "load immediate" 2615 if (expr->Iex.Load [all...] |
H A D | host_x86_isel.c | 868 X86AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr ); 871 if (e->Iex.Load.end != Iend_LE) 1669 && e->Iex.Load.end == Iend_LE) { 1670 X86AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr); 2121 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2124 vassert(e->Iex.Load.ty == Ity_I64); 2127 am0 = iselIntExpr_AMode(env, e->Iex.Load.addr); 2895 if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { 2898 vassert(e->Iex.Load.ty == Ity_F32); 2899 am = iselIntExpr_AMode(env, e->Iex.Load [all...] |
H A D | ir_defs.c | 1242 vex_printf( "LD%s:", e->Iex.Load.end==Iend_LE ? "le" : "be" ); 1243 ppIRType(e->Iex.Load.ty); 1245 ppIRExpr(e->Iex.Load.addr); 1765 e->Iex.Load.end = end; 1766 e->Iex.Load.ty = ty; 1767 e->Iex.Load.addr = addr; 2214 return IRExpr_Load(e->Iex.Load.end, 2215 e->Iex.Load.ty, 2216 deepCopyIRExpr(e->Iex.Load.addr)); 3397 return e->Iex.Load [all...] |
H A D | ir_match.c | 82 if (p->Iex.Load.end != e->Iex.Load.end) return False; 83 if (p->Iex.Load.ty != e->Iex.Load.ty) return False; 84 if (!matchWrk(mi, p->Iex.Load.addr, e->Iex.Load.addr))
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H A D | ir_opt.c | 277 return isIRAtom(e->Iex.Load.addr); 349 IRExpr_Load(ex->Iex.Load.end, 350 ex->Iex.Load.ty, 351 flatten_Expr(bb, ex->Iex.Load.addr)))); 1025 Get's, GetI's or Load's, even when accessing the same location, will be 2438 vassert(isIRAtom(ex->Iex.Load.addr)); 2440 ex->Iex.Load.end, 2441 ex->Iex.Load.ty, 2442 subst_Expr(env, ex->Iex.Load.addr) 2887 addUses_Expr(set, e->Iex.Load [all...] |
/external/valgrind/main/VEX/pub/ |
H A D | libvex_ir.h | 1772 'e.Iex.Load.<fieldname>'. 1881 Load-Linkeds (and Store-Conditionals) are instead represented 1882 by IRStmt.LLSC since Load-Linkeds have side effects and so 1890 } Load; member in union:_IRExpr::__anon32286 2285 preceding Linked-Load, and needs to be handed through to the 2658 /* Either Load-Linked or Store-Conditional, depending on 2661 If STOREDATA is NULL then this is a Load-Linked, meaning 2666 result = Load-Linked(addr, end)
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/external/valgrind/main/VEX/ |
H A D | test_main.c | 2168 return expr2vbits_LDle( mce, e->Iex.Load.ty, 2169 e->Iex.Load.addr, 0/*addr bias*/ ); 2570 return isBogusAtom(e->Iex.Load.addr);
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/external/valgrind/main/cachegrind/ |
H A D | cg_main.c | 1137 IRExpr* aexpr = data->Iex.Load.addr; 1140 addEvent_Dr( &cgs, curr_inode, sizeofIRType(data->Iex.Load.ty),
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/external/valgrind/main/callgrind/ |
H A D | main.c | 1052 IRExpr* aexpr = data->Iex.Load.addr; 1056 sizeofIRType(data->Iex.Load.ty), aexpr );
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/external/valgrind/main/drd/ |
H A D | drd_load_store.c | 680 IRExpr* addr_expr = data->Iex.Load.addr; 684 sizeofIRType(data->Iex.Load.ty), 687 instrument_load(bb, addr_expr, sizeofIRType(data->Iex.Load.ty),
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/external/valgrind/main/exp-bbv/tests/amd64-linux/ |
H A D | ll.S | 173 # Load /proc/cpuinfo into buffer 234 # Load into esi
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/external/valgrind/main/exp-bbv/tests/arm-linux/ |
H A D | ll.S | 162 @ Load /proc/cpuinfo into buffer
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/external/valgrind/main/exp-bbv/tests/ppc32-linux/ |
H A D | ll.S | 193 # Load /proc/cpuinfo into buffer
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/external/valgrind/main/exp-bbv/tests/x86/ |
H A D | rep_prefix.S | 33 # Load and Store Instructions
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/external/valgrind/main/exp-bbv/tests/x86-linux/ |
H A D | ll.S | 165 # Load /proc/cpuinfo into buffer 229 # Load into esi
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/external/valgrind/main/exp-dhat/ |
H A D | dh_main.c | 924 IRExpr* aexpr = data->Iex.Load.addr; 928 sizeofIRType(data->Iex.Load.ty),
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