/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 315 unsigned Reg, EVT VT) const { 319 if (!MRI.isLiveIn(Reg)) { 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg); 313 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
|
H A D | AMDGPUISelLowering.h | 32 /// CreateLiveInRegister - Helper function that adds Reg to the LiveIn list 34 /// Reg. 36 unsigned Reg, EVT VT) const;
|
H A D | AMDGPUInstrInfo.cpp | 165 unsigned Reg, bool UnfoldLoad, 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
|
H A D | AMDGPUInstrInfo.h | 102 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
H A D | R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 263 if (!MRI.isLiveOut(Reg)) { 264 MRI.addLiveOut(Reg); 266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2)); 283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
|
H A D | R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg(); local 350 switch (Reg) {
|
H A D | SIISelLowering.cpp | 367 unsigned Reg = dstClass->getRegister(SGPRIndex); local 369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
|
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 91 unsigned getHWRegIndexGen(unsigned int Reg) const; 95 unsigned getHWRegChanGen(unsigned int Reg) const;
|
/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
H A D | prog_optimize.c | 842 GLuint Reg; /** The temporary register index */ member in struct:interval 893 if (list->Intervals[k].Reg == inv->Reg) { 1078 inv.Reg = i; 1092 printf("Reg[%d] live [%d, %d]:", 1093 inv->Reg, inv->Start, inv->End); 1166 printf("Consider register %u\n", live->Reg); 1183 const GLint regNew = registerMap[inv->Reg]; 1187 printf(" expire interval for reg %u\n", inv->Reg); 1209 registerMap[live->Reg] [all...] |
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ProgramState.h | 337 bool isTainted(const MemRegion *Reg, TaintTagType Kind=TaintTagGeneric) const; 340 DynamicTypeInfo getDynamicTypeInfo(const MemRegion *Reg) const; 343 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg, 347 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg, argument 350 return setDynamicTypeInfo(Reg, DynamicTypeInfo(NewTy, CanBeSubClassed));
|
/external/clang/lib/CodeGen/ |
H A D | CGValue.h | 344 static LValue MakeGlobalReg(llvm::Value *Reg, argument 349 R.V = Reg;
|
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngine.cpp | 226 SVal Reg = loc::MemRegionVal(TR); local 231 State = State->bindLoc(Reg, V); 237 Reg = StoreMgr.evalDerivedToBase(Reg, *I); 240 State = State->BindExpr(Result, LC, Reg);
|
H A D | PathDiagnostic.cpp | 1151 if (Optional<loc::MemRegionVal> Reg = SV.getAs<loc::MemRegionVal>()) { 1152 SVal PSV = State->getSVal(Reg->getRegion());
|
H A D | ProgramState.cpp | 699 if (const MemRegion *Reg = V.getAsRegion()) 700 return isTainted(Reg, Kind); 704 bool ProgramState::isTainted(const MemRegion *Reg, TaintTagType K) const { argument 705 if (!Reg) 710 if (const ElementRegion *ER = dyn_cast<ElementRegion>(Reg)) 713 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) 716 if (const SubRegion *ER = dyn_cast<SubRegion>(Reg)) 761 DynamicTypeInfo ProgramState::getDynamicTypeInfo(const MemRegion *Reg) const { 762 Reg = Reg 781 setDynamicTypeInfo(const MemRegion *Reg, DynamicTypeInfo NewTy) const argument [all...] |
/external/compiler-rt/lib/asan/tests/ |
H A D | asan_asm_test.cc | 34 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ 39 : [ptr] "r" (ptr), [val] Reg (val) \ 44 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ 49 : [res] Reg (res) \ 67 #define DECLARE_ASM_WRITE(Type, Size, Mov, Reg) \ 72 : [ptr] "r" (ptr), [val] Reg (val) \ 77 #define DECLARE_ASM_READ(Type, Size, Mov, Reg) \ 82 : [res] Reg (res) \
|
/external/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 258 bool isAllocated(unsigned Reg) const { 259 return UsedRegs[Reg/32] & (1 << (Reg&31)); 310 unsigned AllocateReg(unsigned Reg) { argument 311 if (isAllocated(Reg)) return 0; 312 MarkAllocated(Reg); 313 return Reg; 317 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument 318 if (isAllocated(Reg)) return 0; 319 MarkAllocated(Reg); 333 unsigned Reg = Regs[FirstUnalloc]; local 371 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local [all...] |
H A D | FastISel.h | 344 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
|
H A D | FunctionLoweringInfo.h | 154 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument 155 if (!LiveOutRegInfo.inBounds(Reg)) 158 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg]; 170 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); 173 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument 179 LiveOutRegInfo.grow(Reg); 180 LiveOutInfo &LOI = LiveOutRegInfo[Reg]; 198 unsigned Reg = It->second; local 199 LiveOutRegInfo.grow(Reg); 200 LiveOutRegInfo[Reg] [all...] |
H A D | LiveInterval.h | 535 LiveInterval(unsigned Reg, float Weight) argument 536 : reg(Reg), weight(Weight) {}
|
H A D | LiveIntervalAnalysis.h | 108 LiveInterval &getInterval(unsigned Reg) { argument 109 if (hasInterval(Reg)) 110 return *VirtRegIntervals[Reg]; 112 return createAndComputeVirtRegInterval(Reg); 115 const LiveInterval &getInterval(unsigned Reg) const { 116 return const_cast<LiveIntervals*>(this)->getInterval(Reg); 119 bool hasInterval(unsigned Reg) const { 120 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; 124 LiveInterval &createEmptyInterval(unsigned Reg) { argument 131 createAndComputeVirtRegInterval(unsigned Reg) argument 138 removeInterval(unsigned Reg) argument [all...] |
H A D | LivePhysRegs.h | 74 void addReg(unsigned Reg) { argument 76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 84 void removeReg(unsigned Reg) { argument 86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); 87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 90 for (MCSuperRegIterator SuperRegs(Reg, TRI, /*IncludeSelf=*/false); 98 /// \brief Returns true if register @p Reg is contained in the set. This also 99 /// works if only the super register of @p Reg has been defined, because we 101 bool contains(unsigned Reg) cons [all...] |
H A D | LiveRangeEdit.h | 209 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 211 void eraseVirtReg(unsigned Reg);
|
H A D | LiveVariables.h | 106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through 107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in 110 unsigned Reg, 150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the 153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI); 158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); 159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, 165 MachineInstr *FindLastRefOrPartRef(unsigned Reg); 170 MachineInstr *FindLastPartialDef(unsigned Reg, 281 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument 299 isPHIJoin(unsigned Reg) argument 302 setPHIJoin(unsigned Reg) argument [all...] |
H A D | MachineBasicBlock.h | 320 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } argument 329 void removeLiveIn(unsigned Reg); 333 bool isLiveIn(unsigned Reg) const; 621 /// computeRegisterLiveness - Return whether (physical) register \c Reg 628 /// \c Reg must be a physical register. 630 unsigned Reg, MachineInstr *MI,
|
H A D | MachineFrameInfo.h | 38 unsigned Reg; member in class:llvm::CalleeSavedInfo 43 : Reg(R), FrameIdx(FI) {} 46 unsigned getReg() const { return Reg; }
|