1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32
33
34#include "brw_context.h"
35#include "brw_state.h"
36#include "brw_defines.h"
37#include "main/macros.h"
38
39static void
40brw_upload_vs_unit(struct brw_context *brw)
41{
42   struct intel_context *intel = &brw->intel;
43   struct gl_context *ctx = &intel->ctx;
44   struct brw_vs_unit_state *vs;
45
46   vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
47			sizeof(*vs), 32, &brw->vs.state_offset);
48   memset(vs, 0, sizeof(*vs));
49
50   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
51   vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
52   vs->thread0.kernel_start_pointer =
53      brw_program_reloc(brw,
54			brw->vs.state_offset +
55			offsetof(struct brw_vs_unit_state, thread0),
56			brw->vs.prog_offset +
57			(vs->thread0.grf_reg_count << 1)) >> 6;
58
59   vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
60   /* Choosing multiple program flow means that we may get 2-vertex threads,
61    * which will have the channel mask for dwords 4-7 enabled in the thread,
62    * and those dwords will be written to the second URB handle when we
63    * brw_urb_WRITE() results.
64    */
65   /* Force single program flow on Ironlake.  We cannot reliably get
66    * all applications working without it.  See:
67    * https://bugs.freedesktop.org/show_bug.cgi?id=29172
68    *
69    * The most notable and reliably failing application is the Humus
70    * demo "CelShading"
71   */
72   vs->thread1.single_program_flow = (intel->gen == 5);
73
74   vs->thread1.binding_table_entry_count = 0;
75
76   if (brw->vs.prog_data->total_scratch != 0) {
77      vs->thread2.scratch_space_base_pointer =
78	 brw->vs.scratch_bo->offset >> 10; /* reloc */
79      vs->thread2.per_thread_scratch_space =
80	 ffs(brw->vs.prog_data->total_scratch) - 11;
81   } else {
82      vs->thread2.scratch_space_base_pointer = 0;
83      vs->thread2.per_thread_scratch_space = 0;
84   }
85
86   vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
87   vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
88   vs->thread3.dispatch_grf_start_reg = 1;
89   vs->thread3.urb_entry_read_offset = 0;
90
91   /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */
92   if (ctx->Transform.ClipPlanesEnabled && !brw->vs.prog_data->uses_new_param_layout) {
93      /* Note that we read in the userclip planes as well, hence
94       * clip_start:
95       */
96      vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
97   }
98   else {
99      vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
100   }
101
102
103   /* BRW_NEW_URB_FENCE */
104   if (intel->gen == 5) {
105      switch (brw->urb.nr_vs_entries) {
106      case 8:
107      case 12:
108      case 16:
109      case 32:
110      case 64:
111      case 96:
112      case 128:
113      case 168:
114      case 192:
115      case 224:
116      case 256:
117	 vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
118	 break;
119      default:
120	 assert(0);
121      }
122   } else {
123      switch (brw->urb.nr_vs_entries) {
124      case 8:
125      case 12:
126      case 16:
127      case 32:
128	 break;
129      case 64:
130	 assert(intel->is_g4x);
131	 break;
132      default:
133	 assert(0);
134      }
135      vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
136   }
137
138   vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
139
140   vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
141				   1, brw->max_vs_threads) - 1;
142
143   /* No samplers for ARB_vp programs:
144    */
145   /* It has to be set to 0 for Ironlake
146    */
147   vs->vs5.sampler_count = 0;
148
149   if (unlikely(INTEL_DEBUG & DEBUG_STATS))
150      vs->thread4.stats_enable = 1;
151
152   /* Vertex program always enabled:
153    */
154   vs->vs6.vs_enable = 1;
155
156   /* Emit scratch space relocation */
157   if (brw->vs.prog_data->total_scratch != 0) {
158      drm_intel_bo_emit_reloc(intel->batch.bo,
159			      brw->vs.state_offset +
160			      offsetof(struct brw_vs_unit_state, thread2),
161			      brw->vs.scratch_bo,
162			      vs->thread2.per_thread_scratch_space,
163			      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
164   }
165
166   brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
167}
168
169const struct brw_tracked_state brw_vs_unit = {
170   .dirty = {
171      .mesa  = _NEW_TRANSFORM,
172      .brw   = (BRW_NEW_BATCH |
173		BRW_NEW_PROGRAM_CACHE |
174		BRW_NEW_CURBE_OFFSETS |
175		BRW_NEW_URB_FENCE |
176                BRW_NEW_VERTEX_PROGRAM),
177      .cache = CACHE_NEW_VS_PROG
178   },
179   .emit = brw_upload_vs_unit,
180};
181