1/* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <assert.h> 25 26#include "intel_batchbuffer.h" 27#include "intel_fbo.h" 28#include "intel_mipmap_tree.h" 29 30#include "brw_context.h" 31#include "brw_defines.h" 32#include "brw_state.h" 33 34#include "brw_blorp.h" 35#include "gen7_blorp.h" 36 37 38/* 3DSTATE_URB_VS 39 * 3DSTATE_URB_HS 40 * 3DSTATE_URB_DS 41 * 3DSTATE_URB_GS 42 * 43 * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the 44 * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS: 45 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be 46 * programmed in order for the programming of this state to be 47 * valid. 48 */ 49static void 50gen7_blorp_emit_urb_config(struct brw_context *brw, 51 const brw_blorp_params *params) 52{ 53 /* The minimum valid value is 32. See 3DSTATE_URB_VS, 54 * Dword 1.15:0 "VS Number of URB Entries". 55 */ 56 int num_vs_entries = 32; 57 int vs_size = 2; 58 int vs_start = 2; /* skip over push constants */ 59 60 gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start); 61} 62 63 64/* 3DSTATE_BLEND_STATE_POINTERS */ 65static void 66gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, 67 const brw_blorp_params *params, 68 uint32_t cc_blend_state_offset) 69{ 70 struct intel_context *intel = &brw->intel; 71 72 BEGIN_BATCH(2); 73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); 74 OUT_BATCH(cc_blend_state_offset | 1); 75 ADVANCE_BATCH(); 76} 77 78 79/* 3DSTATE_CC_STATE_POINTERS */ 80static void 81gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, 82 const brw_blorp_params *params, 83 uint32_t cc_state_offset) 84{ 85 struct intel_context *intel = &brw->intel; 86 87 BEGIN_BATCH(2); 88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); 89 OUT_BATCH(cc_state_offset | 1); 90 ADVANCE_BATCH(); 91} 92 93static void 94gen7_blorp_emit_cc_viewport(struct brw_context *brw, 95 const brw_blorp_params *params) 96{ 97 struct intel_context *intel = &brw->intel; 98 struct brw_cc_viewport *ccv; 99 uint32_t cc_vp_offset; 100 101 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE, 102 sizeof(*ccv), 32, 103 &cc_vp_offset); 104 ccv->min_depth = 0.0; 105 ccv->max_depth = 1.0; 106 107 BEGIN_BATCH(2); 108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2)); 109 OUT_BATCH(cc_vp_offset); 110 ADVANCE_BATCH(); 111} 112 113 114/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS 115 * 116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. 117 */ 118static void 119gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, 120 const brw_blorp_params *params, 121 uint32_t depthstencil_offset) 122{ 123 struct intel_context *intel = &brw->intel; 124 125 BEGIN_BATCH(2); 126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); 127 OUT_BATCH(depthstencil_offset | 1); 128 ADVANCE_BATCH(); 129} 130 131 132/* SURFACE_STATE for renderbuffer or texture surface (see 133 * brw_update_renderbuffer_surface and brw_update_texture_surface) 134 */ 135static uint32_t 136gen7_blorp_emit_surface_state(struct brw_context *brw, 137 const brw_blorp_params *params, 138 const brw_blorp_surface_info *surface, 139 uint32_t read_domains, uint32_t write_domain, 140 bool is_render_target) 141{ 142 struct intel_context *intel = &brw->intel; 143 144 uint32_t wm_surf_offset; 145 uint32_t width = surface->width; 146 uint32_t height = surface->height; 147 /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for 148 * color surfaces, width and height are measured in pixels; we don't need 149 * to divide them by 2 as we do for Gen6 (see 150 * gen6_blorp_emit_surface_state). 151 */ 152 struct intel_region *region = surface->mt->region; 153 uint32_t tile_x, tile_y; 154 155 struct gen7_surface_state *surf = (struct gen7_surface_state *) 156 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32, 157 &wm_surf_offset); 158 memset(surf, 0, sizeof(*surf)); 159 160 if (surface->mt->align_h == 4) 161 surf->ss0.vertical_alignment = 1; 162 if (surface->mt->align_w == 8) 163 surf->ss0.horizontal_alignment = 1; 164 165 surf->ss0.surface_format = surface->brw_surfaceformat; 166 surf->ss0.surface_type = BRW_SURFACE_2D; 167 surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ? 168 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL; 169 170 /* reloc */ 171 surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y); 172 surf->ss1.base_addr += region->bo->offset; 173 174 /* Note that the low bits of these fields are missing, so 175 * there's the possibility of getting in trouble. 176 */ 177 assert(tile_x % 4 == 0); 178 assert(tile_y % 2 == 0); 179 surf->ss5.x_offset = tile_x / 4; 180 surf->ss5.y_offset = tile_y / 2; 181 182 surf->ss2.width = width - 1; 183 surf->ss2.height = height - 1; 184 185 uint32_t tiling = surface->map_stencil_as_y_tiled 186 ? I915_TILING_Y : region->tiling; 187 gen7_set_surface_tiling(surf, tiling); 188 189 uint32_t pitch_bytes = region->pitch * region->cpp; 190 if (surface->map_stencil_as_y_tiled) 191 pitch_bytes *= 2; 192 surf->ss3.pitch = pitch_bytes - 1; 193 194 gen7_set_surface_msaa(surf, surface->num_samples, surface->msaa_layout); 195 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { 196 gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, 197 surface->mt->mcs_mt, is_render_target); 198 } 199 200 if (intel->is_haswell) { 201 surf->ss7.shader_channel_select_r = HSW_SCS_RED; 202 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; 203 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; 204 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; 205 } 206 207 /* Emit relocation to surface contents */ 208 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 209 wm_surf_offset + 210 offsetof(struct gen7_surface_state, ss1), 211 region->bo, 212 surf->ss1.base_addr - region->bo->offset, 213 read_domains, write_domain); 214 215 gen7_check_surface_setup(surf, is_render_target); 216 217 return wm_surf_offset; 218} 219 220 221/** 222 * SAMPLER_STATE. See gen7_update_sampler_state(). 223 */ 224static uint32_t 225gen7_blorp_emit_sampler_state(struct brw_context *brw, 226 const brw_blorp_params *params) 227{ 228 uint32_t sampler_offset; 229 230 struct gen7_sampler_state *sampler = (struct gen7_sampler_state *) 231 brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 232 sizeof(struct gen7_sampler_state), 233 32, &sampler_offset); 234 memset(sampler, 0, sizeof(*sampler)); 235 236 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR; 237 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE; 238 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR; 239 240 sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 241 sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 242 sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 243 244 // sampler->ss0.min_mag_neq = 1; 245 246 /* Set LOD bias: 247 */ 248 sampler->ss0.lod_bias = 0; 249 250 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ 251 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ 252 253 /* Set BaseMipLevel, MaxLOD, MinLOD: 254 * 255 * XXX: I don't think that using firstLevel, lastLevel works, 256 * because we always setup the surface state as if firstLevel == 257 * level zero. Probably have to subtract firstLevel from each of 258 * these: 259 */ 260 sampler->ss0.base_level = U_FIXED(0, 1); 261 262 sampler->ss1.max_lod = U_FIXED(0, 8); 263 sampler->ss1.min_lod = U_FIXED(0, 8); 264 265 sampler->ss3.non_normalized_coord = 1; 266 267 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | 268 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | 269 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; 270 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | 271 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | 272 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; 273 274 return sampler_offset; 275} 276 277 278/* 3DSTATE_HS 279 * 280 * Disable the hull shader. 281 */ 282static void 283gen7_blorp_emit_hs_disable(struct brw_context *brw, 284 const brw_blorp_params *params) 285{ 286 struct intel_context *intel = &brw->intel; 287 288 BEGIN_BATCH(7); 289 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); 290 OUT_BATCH(0); 291 OUT_BATCH(0); 292 OUT_BATCH(0); 293 OUT_BATCH(0); 294 OUT_BATCH(0); 295 OUT_BATCH(0); 296 ADVANCE_BATCH(); 297} 298 299 300/* 3DSTATE_TE 301 * 302 * Disable the tesselation engine. 303 */ 304static void 305gen7_blorp_emit_te_disable(struct brw_context *brw, 306 const brw_blorp_params *params) 307{ 308 struct intel_context *intel = &brw->intel; 309 310 BEGIN_BATCH(4); 311 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); 312 OUT_BATCH(0); 313 OUT_BATCH(0); 314 OUT_BATCH(0); 315 ADVANCE_BATCH(); 316} 317 318 319/* 3DSTATE_DS 320 * 321 * Disable the domain shader. 322 */ 323static void 324gen7_blorp_emit_ds_disable(struct brw_context *brw, 325 const brw_blorp_params *params) 326{ 327 struct intel_context *intel = &brw->intel; 328 329 BEGIN_BATCH(6); 330 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); 331 OUT_BATCH(0); 332 OUT_BATCH(0); 333 OUT_BATCH(0); 334 OUT_BATCH(0); 335 OUT_BATCH(0); 336 ADVANCE_BATCH(); 337} 338 339 340/* 3DSTATE_STREAMOUT 341 * 342 * Disable streamout. 343 */ 344static void 345gen7_blorp_emit_streamout_disable(struct brw_context *brw, 346 const brw_blorp_params *params) 347{ 348 struct intel_context *intel = &brw->intel; 349 350 BEGIN_BATCH(3); 351 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); 352 OUT_BATCH(0); 353 OUT_BATCH(0); 354 ADVANCE_BATCH(); 355} 356 357 358static void 359gen7_blorp_emit_sf_config(struct brw_context *brw, 360 const brw_blorp_params *params) 361{ 362 struct intel_context *intel = &brw->intel; 363 364 /* 3DSTATE_SF 365 * 366 * Disable ViewportTransformEnable (dw1.1) 367 * 368 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D 369 * Primitives Overview": 370 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the 371 * use of screen- space coordinates). 372 * 373 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5) 374 * and BackFaceFillMode (dw1.4:3) to SOLID(0). 375 * 376 * From the Sandy Bridge PRM, Volume 2, Part 1, Section 377 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: 378 * SOLID: Any triangle or rectangle object found to be front-facing 379 * is rendered as a solid object. This setting is required when 380 * (rendering rectangle (RECTLIST) objects. 381 */ 382 { 383 BEGIN_BATCH(7); 384 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2)); 385 OUT_BATCH(params->depth_format << 386 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); 387 OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); 388 OUT_BATCH(0); 389 OUT_BATCH(0); 390 OUT_BATCH(0); 391 OUT_BATCH(0); 392 ADVANCE_BATCH(); 393 } 394 395 /* 3DSTATE_SBE */ 396 { 397 BEGIN_BATCH(14); 398 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2)); 399 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */ 400 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | 401 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); 402 for (int i = 0; i < 12; ++i) 403 OUT_BATCH(0); 404 ADVANCE_BATCH(); 405 } 406} 407 408 409/** 410 * Disable thread dispatch (dw5.19) and enable the HiZ op. 411 */ 412static void 413gen7_blorp_emit_wm_config(struct brw_context *brw, 414 const brw_blorp_params *params, 415 brw_blorp_prog_data *prog_data) 416{ 417 struct intel_context *intel = &brw->intel; 418 419 uint32_t dw1 = 0, dw2 = 0; 420 421 switch (params->hiz_op) { 422 case GEN6_HIZ_OP_DEPTH_CLEAR: 423 dw1 |= GEN7_WM_DEPTH_CLEAR; 424 break; 425 case GEN6_HIZ_OP_DEPTH_RESOLVE: 426 dw1 |= GEN7_WM_DEPTH_RESOLVE; 427 break; 428 case GEN6_HIZ_OP_HIZ_RESOLVE: 429 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE; 430 break; 431 case GEN6_HIZ_OP_NONE: 432 break; 433 default: 434 assert(0); 435 break; 436 } 437 dw1 |= GEN7_WM_STATISTICS_ENABLE; 438 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; 439 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; 440 dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ 441 if (params->use_wm_prog) { 442 dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */ 443 dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */ 444 } 445 446 if (params->num_samples > 1) { 447 dw1 |= GEN7_WM_MSRAST_ON_PATTERN; 448 if (prog_data && prog_data->persample_msaa_dispatch) 449 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 450 else 451 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL; 452 } else { 453 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL; 454 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; 455 } 456 457 BEGIN_BATCH(3); 458 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); 459 OUT_BATCH(dw1); 460 OUT_BATCH(dw2); 461 ADVANCE_BATCH(); 462} 463 464 465/** 466 * 3DSTATE_PS 467 * 468 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite 469 * that, thread dispatch info must still be specified. 470 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec 471 * states that the valid range for this field is [0x3, 0x2f]. 472 * - A dispatch mode must be given; that is, at least one of the 473 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was 474 * discovered through simulator error messages. 475 */ 476static void 477gen7_blorp_emit_ps_config(struct brw_context *brw, 478 const brw_blorp_params *params, 479 uint32_t prog_offset, 480 brw_blorp_prog_data *prog_data) 481{ 482 struct intel_context *intel = &brw->intel; 483 uint32_t dw2, dw4, dw5; 484 const int max_threads_shift = brw->intel.is_haswell ? 485 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; 486 487 dw2 = dw4 = dw5 = 0; 488 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift; 489 490 /* If there's a WM program, we need to do 16-pixel dispatch since that's 491 * what the program is compiled for. If there isn't, then it shouldn't 492 * matter because no program is actually being run. However, the hardware 493 * gets angry if we don't enable at least one dispatch mode, so just enable 494 * 16-pixel dispatch unconditionally. 495 */ 496 dw4 |= GEN7_PS_16_DISPATCH_ENABLE; 497 498 if (intel->is_haswell) 499 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ 500 if (params->use_wm_prog) { 501 dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ 502 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; 503 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; 504 } 505 506 BEGIN_BATCH(8); 507 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); 508 OUT_BATCH(params->use_wm_prog ? prog_offset : 0); 509 OUT_BATCH(dw2); 510 OUT_BATCH(0); 511 OUT_BATCH(dw4); 512 OUT_BATCH(dw5); 513 OUT_BATCH(0); 514 OUT_BATCH(0); 515 ADVANCE_BATCH(); 516} 517 518 519static void 520gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, 521 const brw_blorp_params *params, 522 uint32_t wm_bind_bo_offset) 523{ 524 struct intel_context *intel = &brw->intel; 525 526 BEGIN_BATCH(2); 527 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); 528 OUT_BATCH(wm_bind_bo_offset); 529 ADVANCE_BATCH(); 530} 531 532 533static void 534gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, 535 const brw_blorp_params *params, 536 uint32_t sampler_offset) 537{ 538 struct intel_context *intel = &brw->intel; 539 540 BEGIN_BATCH(2); 541 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); 542 OUT_BATCH(sampler_offset); 543 ADVANCE_BATCH(); 544} 545 546 547static void 548gen7_blorp_emit_constant_ps(struct brw_context *brw, 549 const brw_blorp_params *params, 550 uint32_t wm_push_const_offset) 551{ 552 struct intel_context *intel = &brw->intel; 553 554 /* Make sure the push constants fill an exact integer number of 555 * registers. 556 */ 557 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0); 558 559 /* There must be at least one register worth of push constant data. */ 560 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0); 561 562 /* Enable push constant buffer 0. */ 563 BEGIN_BATCH(7); 564 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | 565 (7 - 2)); 566 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS); 567 OUT_BATCH(0); 568 OUT_BATCH(wm_push_const_offset); 569 OUT_BATCH(0); 570 OUT_BATCH(0); 571 OUT_BATCH(0); 572 ADVANCE_BATCH(); 573} 574 575 576static void 577gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, 578 const brw_blorp_params *params) 579{ 580 struct intel_context *intel = &brw->intel; 581 uint32_t draw_x = params->depth.x_offset; 582 uint32_t draw_y = params->depth.y_offset; 583 uint32_t tile_mask_x, tile_mask_y; 584 585 gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); 586 587 /* 3DSTATE_DEPTH_BUFFER */ 588 { 589 uint32_t tile_x = draw_x & tile_mask_x; 590 uint32_t tile_y = draw_y & tile_mask_y; 591 uint32_t offset = 592 intel_region_get_aligned_offset(params->depth.mt->region, 593 draw_x & ~tile_mask_x, 594 draw_y & ~tile_mask_y, false); 595 596 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 597 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth 598 * Coordinate Offset X/Y": 599 * 600 * "The 3 LSBs of both offsets must be zero to ensure correct 601 * alignment" 602 * 603 * We have no guarantee that tile_x and tile_y are correctly aligned, 604 * since they are determined by the mipmap layout, which is only aligned 605 * to multiples of 4. 606 * 607 * So, to avoid hanging the GPU, just smash the low order 3 bits of 608 * tile_x and tile_y to 0. This is a temporary workaround until we come 609 * up with a better solution. 610 */ 611 tile_x &= ~7; 612 tile_y &= ~7; 613 614 intel_emit_depth_stall_flushes(intel); 615 616 BEGIN_BATCH(7); 617 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 618 uint32_t pitch_bytes = 619 params->depth.mt->region->pitch * params->depth.mt->region->cpp; 620 OUT_BATCH((pitch_bytes - 1) | 621 params->depth_format << 18 | 622 1 << 22 | /* hiz enable */ 623 1 << 28 | /* depth write */ 624 BRW_SURFACE_2D << 29); 625 OUT_RELOC(params->depth.mt->region->bo, 626 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 627 offset); 628 OUT_BATCH((params->depth.width + tile_x - 1) << 4 | 629 (params->depth.height + tile_y - 1) << 18); 630 OUT_BATCH(0); 631 OUT_BATCH(tile_x | 632 tile_y << 16); 633 OUT_BATCH(0); 634 ADVANCE_BATCH(); 635 } 636 637 /* 3DSTATE_HIER_DEPTH_BUFFER */ 638 { 639 struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; 640 uint32_t hiz_offset = 641 intel_region_get_aligned_offset(hiz_region, 642 draw_x & ~tile_mask_x, 643 (draw_y & ~tile_mask_y) / 2, false); 644 645 BEGIN_BATCH(3); 646 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 647 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); 648 OUT_RELOC(hiz_region->bo, 649 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 650 hiz_offset); 651 ADVANCE_BATCH(); 652 } 653 654 /* 3DSTATE_STENCIL_BUFFER */ 655 { 656 BEGIN_BATCH(3); 657 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 658 OUT_BATCH(0); 659 OUT_BATCH(0); 660 ADVANCE_BATCH(); 661 } 662} 663 664 665static void 666gen7_blorp_emit_depth_disable(struct brw_context *brw, 667 const brw_blorp_params *params) 668{ 669 struct intel_context *intel = &brw->intel; 670 671 BEGIN_BATCH(7); 672 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 673 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29)); 674 OUT_BATCH(0); 675 OUT_BATCH(0); 676 OUT_BATCH(0); 677 OUT_BATCH(0); 678 OUT_BATCH(0); 679 ADVANCE_BATCH(); 680} 681 682 683/* 3DSTATE_CLEAR_PARAMS 684 * 685 * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2 686 * 3DSTATE_CLEAR_PARAMS: 687 * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along 688 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER, 689 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER). 690 */ 691static void 692gen7_blorp_emit_clear_params(struct brw_context *brw, 693 const brw_blorp_params *params) 694{ 695 struct intel_context *intel = &brw->intel; 696 697 BEGIN_BATCH(3); 698 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); 699 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0); 700 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID); 701 ADVANCE_BATCH(); 702} 703 704 705/* 3DPRIMITIVE */ 706static void 707gen7_blorp_emit_primitive(struct brw_context *brw, 708 const brw_blorp_params *params) 709{ 710 struct intel_context *intel = &brw->intel; 711 712 BEGIN_BATCH(7); 713 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); 714 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL | 715 _3DPRIM_RECTLIST); 716 OUT_BATCH(3); /* vertex count per instance */ 717 OUT_BATCH(0); 718 OUT_BATCH(1); /* instance count */ 719 OUT_BATCH(0); 720 OUT_BATCH(0); 721 ADVANCE_BATCH(); 722} 723 724 725/** 726 * \copydoc gen6_blorp_exec() 727 */ 728void 729gen7_blorp_exec(struct intel_context *intel, 730 const brw_blorp_params *params) 731{ 732 struct gl_context *ctx = &intel->ctx; 733 struct brw_context *brw = brw_context(ctx); 734 brw_blorp_prog_data *prog_data = NULL; 735 uint32_t cc_blend_state_offset = 0; 736 uint32_t cc_state_offset = 0; 737 uint32_t depthstencil_offset; 738 uint32_t wm_push_const_offset = 0; 739 uint32_t wm_bind_bo_offset = 0; 740 uint32_t sampler_offset = 0; 741 742 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); 743 gen6_blorp_emit_batch_head(brw, params); 744 gen7_allocate_push_constants(brw); 745 gen6_emit_3dstate_multisample(brw, params->num_samples); 746 gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); 747 gen6_blorp_emit_state_base_address(brw, params); 748 gen6_blorp_emit_vertices(brw, params); 749 gen7_blorp_emit_urb_config(brw, params); 750 if (params->use_wm_prog) { 751 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); 752 cc_state_offset = gen6_blorp_emit_cc_state(brw, params); 753 gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset); 754 gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset); 755 } 756 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); 757 gen7_blorp_emit_depth_stencil_state_pointers(brw, params, 758 depthstencil_offset); 759 if (params->use_wm_prog) { 760 uint32_t wm_surf_offset_renderbuffer; 761 uint32_t wm_surf_offset_texture; 762 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); 763 wm_surf_offset_renderbuffer = 764 gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, 765 I915_GEM_DOMAIN_RENDER, 766 I915_GEM_DOMAIN_RENDER, 767 true /* is_render_target */); 768 wm_surf_offset_texture = 769 gen7_blorp_emit_surface_state(brw, params, ¶ms->src, 770 I915_GEM_DOMAIN_SAMPLER, 0, 771 false /* is_render_target */); 772 wm_bind_bo_offset = 773 gen6_blorp_emit_binding_table(brw, params, 774 wm_surf_offset_renderbuffer, 775 wm_surf_offset_texture); 776 sampler_offset = gen7_blorp_emit_sampler_state(brw, params); 777 } 778 gen6_blorp_emit_vs_disable(brw, params); 779 gen7_blorp_emit_hs_disable(brw, params); 780 gen7_blorp_emit_te_disable(brw, params); 781 gen7_blorp_emit_ds_disable(brw, params); 782 gen6_blorp_emit_gs_disable(brw, params); 783 gen7_blorp_emit_streamout_disable(brw, params); 784 gen6_blorp_emit_clip_disable(brw, params); 785 gen7_blorp_emit_sf_config(brw, params); 786 gen7_blorp_emit_wm_config(brw, params, prog_data); 787 if (params->use_wm_prog) { 788 gen7_blorp_emit_binding_table_pointers_ps(brw, params, 789 wm_bind_bo_offset); 790 gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset); 791 gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset); 792 } 793 gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data); 794 gen7_blorp_emit_cc_viewport(brw, params); 795 796 if (params->depth.mt) 797 gen7_blorp_emit_depth_stencil_config(brw, params); 798 else 799 gen7_blorp_emit_depth_disable(brw, params); 800 gen7_blorp_emit_clear_params(brw, params); 801 gen6_blorp_emit_drawing_rectangle(brw, params); 802 gen7_blorp_emit_primitive(brw, params); 803 804 /* See comments above at first invocation of intel_flush() in 805 * gen6_blorp_emit_batch_head(). 806 */ 807 intel_flush(ctx); 808 809 /* Be safe. */ 810 brw->state.dirty.brw = ~0; 811 brw->state.dirty.cache = ~0; 812} 813