1[bits 32]
2        svdc    tword [2*eax+esi+12345678h],cs
3        svdc    tword [2*eax+esi+12345678h],ds
4        svdc    [2*eax+esi+12345678h],es
5
6        rsdc    cs,tword [2*eax+esi+12345678h]
7        rsdc    ds,tword [2*eax+esi+12345678h]
8        rsdc    es,[2*eax+esi+12345678h]
9
10        wrshr   eax
11        wrshr   dword [4*edx+esi+12345678h]
12        wrshr   [4*edx+esi+12345678h]
13
14        rdshr   eax
15        rdshr   dword [4*edx+esi+12345678h]
16        rdshr   [4*edx+esi+12345678h]
17
18