MachineRegisterInfo.h revision f0891be8bdbeeadb39da5575273b6645755fa383
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 231213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 3611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers. For each target register class, it keeps a list of 3711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers belonging to the class. 3811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<std::vector<unsigned> > RegClass2VRegMap; 3990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 4090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 41358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 42358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 43358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 44358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 45358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 47358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 4862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 5062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 6684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 716f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 7262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 7362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 81c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool Uses, bool Defs> 82c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 83c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 84c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 86c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,true> reg_iterator; 876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 9200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 9300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 9400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 9500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 96c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 97c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<false,true> def_iterator; 98c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 99c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 100c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 101c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 102c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 10300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 10400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 10500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 10600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 107c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 108c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,false> use_iterator; 109c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 110c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 111c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 112c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 113c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 114ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 115ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 116ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 117ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1186c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 119e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 120e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 121e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 122e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 123e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 12462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 12562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 12662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 12862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 13062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 13162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 13284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1346f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1356c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1366f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1376c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1386c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1391eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1401eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1411eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1421eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1431eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 1441eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1451eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1461eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1471eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 14884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 14984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 15084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 15184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 15284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 15411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1551eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1566f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 15784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 15862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 15984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 160bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 161bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 16211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 16333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 16411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 16584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 16684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 16784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 1682e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 16984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 17184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 17284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 17334cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 17484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 17511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 17611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// getRegClassVirtRegs - Return the list of virtual registers of the given 17711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// target register class. 17811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 17911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng return RegClass2VRegMap[RC->getID()]; 18011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng } 18190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 18290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 18390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 184358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 18590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 18690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 18790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 18890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 18990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 19090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 19190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 19290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 193358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 19490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 19590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 19690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 19790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 19890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 19990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 20084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 20284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 20584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 20684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 20784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 20984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 21084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 21184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 21384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 21484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 21584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 21984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 22084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 22284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 22484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 22584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 22684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 22984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 23084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 23184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 23284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 23384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 23484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 23584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 2396d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 2406d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman bool isLiveIn(unsigned Reg) const { 2416d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2426d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman if (I->first == Reg || I->second == Reg) 2436d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return true; 2446d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return false; 2456d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman } 2466d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 24762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 24862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 2496c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2506c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 251c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 252c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 253c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 254c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 255c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns end(). 256c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool ReturnUses, bool ReturnDefs> 257c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 258f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 2596c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 2601327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 261c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 262c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 263c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 264ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 265ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && op->isDef())) 266c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 267c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 268c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 2696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 2706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 271f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif typedef std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t>::reference reference; 272f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif typedef std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t>::pointer pointer; 2736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 274c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 275c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 2766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 277c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 2786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 2796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 280c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 2816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 2826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2836c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 2856c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 2866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 288c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 2896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 2906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 291c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 292c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 293ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 294ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && Op->isDef()))) 295c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 296c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 2976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 2986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 299c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 300c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3016c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 303e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 3046c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 3056c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 3066c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3076c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 308e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 309e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 310e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 311e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 312e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 313e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 314e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 315e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 316e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 317e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 318e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 319e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 320e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 321e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 322e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 323e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 324e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 3256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 3266c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 32784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 32884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 32984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 33084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 33184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 332