TargetInstrInfo.h revision f7fb31ea33c78f1bc46c23d9edbf9580b7756bbe
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 56fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// This file was developed by the LLVM research group and is distributed under 66fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 18551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 192cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 20be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 21a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 245684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 25f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 265684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Value; 27588668d4681bf928e09534c373b1bcf86757f899Vikram S. Adveclass Type; 285684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Instruction; 292cc214c06cbb94f95928636981c9805d6300cff1Chris Lattnerclass Constant; 30e7506a366e8bd56c97d10beb68e4db953aebaecaChris Lattnerclass Function; 31c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 32ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 33a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 34f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 35f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 36f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 38ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 39c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 40a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 423501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 4300876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4400876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 453501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 46a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 47f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 0; 48f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CALL_FLAG = 1 << 1; 49f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_RET_FLAG = 1 << 2; 50f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BARRIER_FLAG = 1 << 3; 51f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_LOAD_FLAG = 1 << 5; 53f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_STORE_FLAG = 1 << 6; 5415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_2_ADDR_FLAG = 1 << 7; 5715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 6015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 6115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 62f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 6315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 6415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 6515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 66f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_COMMUTABLE = 1 << 9; 67a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 68075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 70075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 71075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 72f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_TERMINATOR_FLAG = 1 << 10; 73075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 7409321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 7509321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// insertion support when the DAG scheduler is inserting it into a machine basic 7609321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// block. 77f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 7809321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner 79ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 80ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 81ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 82ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 83ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 84ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// RegClass - This specifies the register class of the operand if the 85ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// operand is a register. If not, this contains null. 86ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetRegisterClass *RegClass; 87ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 88ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 89ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 90ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 91ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 921fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 931fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 944683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 95c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner int numOperands; // Number of args; -1 if variable #args 9675e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 9775e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 9875e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 99f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 100f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 101ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 102a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 103a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 104a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1053501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 10634695381d626485a560594f162701088079589dfMisha Brukman/// 1073501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 10834695381d626485a560594f162701088079589dfMisha Brukman/// 109075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 110075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 111bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 112075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 11334695381d626485a560594f162701088079589dfMisha Brukman 114075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 115075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 116a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 117bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 118075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 11970535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1204ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 1214ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 1224ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 1234ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner INLINEASM = 1 1244ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner }; 12534695381d626485a560594f162701088079589dfMisha Brukman 126bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 12734695381d626485a560594f162701088079589dfMisha Brukman 128e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 129e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 130e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 1312441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1322441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 1332441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 134a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1354683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 1362441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 1372441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 1384683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 13934695381d626485a560594f162701088079589dfMisha Brukman 1402441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 1412441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 142a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 143450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1442441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 1452441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 146a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 147d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1482441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 1492441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 150d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 151d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1522441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 1532441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 154d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 155d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 156450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 157a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 158a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 159a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 16034695381d626485a560594f162701088079589dfMisha Brukman // 1612441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 1622441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 163a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 164450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1652441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isTwoAddrInstr(MachineOpCode Opcode) const { 1662441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_2_ADDR_FLAG; 1679ada014ec09579a7dd3833f779a1de82bd71bce1Misha Brukman } 168075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner bool isTerminatorInstr(unsigned Opcode) const { 169075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 170075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 1710271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1720271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBranch(MachineOpCode Opcode) const { 1730271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 1740271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1750271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1760271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 1770271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// from executing the instruction immediately following it. Examples include 1780271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// unconditional branches and return instructions. 1790271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBarrier(MachineOpCode Opcode) const { 1800271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 1810271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1820271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1830271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isCall(MachineOpCode Opcode) const { 1840271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_CALL_FLAG; 1850271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1860271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isLoad(MachineOpCode Opcode) const { 1870271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 1880271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1890271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isStore(MachineOpCode Opcode) const { 1900271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_STORE_FLAG; 1910271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1920271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1930271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 1940271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 1950271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// machine basic block. 1960271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 1970271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 1980271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 199d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2000cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 2010cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 2025e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 2035e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 2045e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 2055e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 2065e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 207af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 208af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 209af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 210af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 211af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 212af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 213af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 214af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 215af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 216af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 217af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 218af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 219af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 220af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 221af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 222af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 223af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 224af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 2255e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 22615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 22715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 22815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// may be able to convert a two-address instruction into a true 22915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 23015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 23115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 23215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 23315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 23415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// performed, otherwise it returns the new instruction. 23515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 23615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 23715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 23815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 23915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 240d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 241d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 242d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 243d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 244d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 245d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 246d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 247d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 248d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 249d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 250d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 251d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 252e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos /// Insert a goto (unconditional branch) sequence to TMBB, at the 253e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos /// end of MBB 254e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos virtual void insertGoto(MachineBasicBlock& MBB, 255e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos MachineBasicBlock& TMBB) const { 256905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos assert(0 && "Target didn't implement insertGoto!"); 257905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 258450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 2590cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Reverses the branch condition of the MachineInstr pointed by 2600cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// MI. The instruction is replaced and the new MI is returned. 261905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos virtual MachineBasicBlock::iterator 262096f58b09adb03b5b060e12b327cff57329909f7Alkis Evlogimenos reverseBranchCondition(MachineBasicBlock::iterator MI) const { 263905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos assert(0 && "Target didn't implement reverseBranchCondition!"); 264c2df129da9828406d97f708989b5151ed04dec6bChris Lattner abort(); 265c2df129da9828406d97f708989b5151ed04dec6bChris Lattner return MI; 266905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 2670271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 26865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 26965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 27065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 27165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 27265e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 27365e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 27465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 2750271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 276dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 277dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner /// which must be filled by the code generator. 278dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner bool hasDelaySlot(unsigned Opcode) const { 27949db6fe193168239be2f5aa8b4201614b739e840Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 280dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner } 281a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 282a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 283d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 284d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 285a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 286