TargetInstrInfo.h revision f8c7394781f7cf27ac52ca087e289436d36844da
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#include "llvm/Target/TargetInstrDesc.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 22ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 236c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 24d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Andersonclass CalleeSavedInfo; 2543dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 2643dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 27a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 28f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 29f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 30a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 313501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 3234695381d626485a560594f162701088079589dfMisha Brukman/// 3361e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 3434695381d626485a560594f162701088079589dfMisha Brukman/// 35075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 36749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner unsigned NumOpcodes; // Number of entries in the desc array 3834695381d626485a560594f162701088079589dfMisha Brukman 39075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 42749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 4470535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 454ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 464ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 474ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 481ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 494406604047423576e36657c7ede266ca42e79642Dan Gohman DBG_LABEL = 2, 504406604047423576e36657c7ede266ca42e79642Dan Gohman EH_LABEL = 3, 514406604047423576e36657c7ede266ca42e79642Dan Gohman GC_LABEL = 4, 524406604047423576e36657c7ede266ca42e79642Dan Gohman DECLARE = 5, 5373099b105869f02ece79c2cea982286744635c4aDan Gohman 5473099b105869f02ece79c2cea982286744635c4aDan Gohman /// EXTRACT_SUBREG - This instruction takes two operands: a register 5573099b105869f02ece79c2cea982286744635c4aDan Gohman /// that has subregisters, and a subregister index. It returns the 5673099b105869f02ece79c2cea982286744635c4aDan Gohman /// extracted subregister value. This is commonly used to implement 5773099b105869f02ece79c2cea982286744635c4aDan Gohman /// truncation operations on target architectures which support it. 584406604047423576e36657c7ede266ca42e79642Dan Gohman EXTRACT_SUBREG = 6, 5973099b105869f02ece79c2cea982286744635c4aDan Gohman 6073099b105869f02ece79c2cea982286744635c4aDan Gohman /// INSERT_SUBREG - This instruction takes three operands: a register 6173099b105869f02ece79c2cea982286744635c4aDan Gohman /// that has subregisters, a register providing an insert value, and a 6273099b105869f02ece79c2cea982286744635c4aDan Gohman /// subregister index. It returns the value of the first register with 6373099b105869f02ece79c2cea982286744635c4aDan Gohman /// the value of the second register inserted. The first register is 6473099b105869f02ece79c2cea982286744635c4aDan Gohman /// often defined by an IMPLICIT_DEF, as is commonly used to implement 6573099b105869f02ece79c2cea982286744635c4aDan Gohman /// anyext operations on target architectures which support it. 664406604047423576e36657c7ede266ca42e79642Dan Gohman INSERT_SUBREG = 7, 6773099b105869f02ece79c2cea982286744635c4aDan Gohman 6873099b105869f02ece79c2cea982286744635c4aDan Gohman /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 694406604047423576e36657c7ede266ca42e79642Dan Gohman IMPLICIT_DEF = 8, 7073099b105869f02ece79c2cea982286744635c4aDan Gohman 7173099b105869f02ece79c2cea982286744635c4aDan Gohman /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 7273099b105869f02ece79c2cea982286744635c4aDan Gohman /// that the first operand is an immediate integer constant. This constant 7373099b105869f02ece79c2cea982286744635c4aDan Gohman /// is often zero, as is commonly used to implement zext operations on 7473099b105869f02ece79c2cea982286744635c4aDan Gohman /// target architectures which support it, such as with x86-64 (with 7573099b105869f02ece79c2cea982286744635c4aDan Gohman /// zext from i32 to i64 via implicit zero-extension). 76f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SUBREG_TO_REG = 9, 77f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 78f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// COPY_TO_SUBCLASS - This instruction is a placeholder for a plain 79f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// register-to-register copy into a specific register class. This is only 80f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// used between instruction selection and MachineInstr creation, before 81f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// virtual registers have been created for all the instructions. As with 82f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// normal copies, these may be optimized away by the coalescer. 83f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman COPY_TO_SUBCLASS = 10 846634e26aa11b0e2eabde8b3b463bb943364f8d9dChristopher Lamb }; 8534695381d626485a560594f162701088079589dfMisha Brukman 86bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 8734695381d626485a560594f162701088079589dfMisha Brukman 88e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 89e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 90e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 91749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &get(unsigned Opcode) const { 92749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner assert(Opcode < NumOpcodes && "Invalid opcode!"); 93749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return Descriptors[Opcode]; 94a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 954683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 96041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 97d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 98d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 999f8fea3531f8f8d04d1e183ff570be37d41d13f5Bill Wendling bool isTriviallyReMaterializable(const MachineInstr *MI) const { 100749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return MI->getDesc().isRematerializable() && 101041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling isReallyTriviallyReMaterializable(MI); 102d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 103d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 104d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 105041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 106041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 107041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// instruction itself is actually trivially rematerializable, considering 108041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// its operands. This is used for targets that have instructions that are 109041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// only trivially rematerializable for specific uses. This predicate must 110041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// return false if the instruction has any side effects other than 111041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// producing a value, or if it requres any address registers that are not 112041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// always available. 1139f8fea3531f8f8d04d1e183ff570be37d41d13f5Bill Wendling virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 114d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return true; 115d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 116d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 117d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 11804ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// Return true if the instruction is a register to register move and return 11904ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// the source and dest operands and their sub-register indices by reference. 1205e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 12104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcReg, unsigned& DstReg, 12204ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 1235e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 1245e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 125af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 126af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 127af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 128af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 129af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 130af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 131cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 132cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 133af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 134af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 135af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 136af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 137af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 138af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 139af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 140af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 141cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 142cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 143af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 144af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1455e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 146ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 147ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 148ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 149ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 150ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 151ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const = 0; 152ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 153a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// isInvariantLoad - Return true if the specified instruction (which is 154a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// marked mayLoad) is loading from a location whose value is invariant across 155a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// the function. For example, loading a value from the constant pool or from 156a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// from the argument area of a function if it does not change. This should 157a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// only return true of *all* loads the instruction does are invariant (if it 158a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// does multiple loads). 159cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual bool isInvariantLoad(const MachineInstr *MI) const { 160a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner return false; 161a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner } 162a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner 16315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 16415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1652c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 1666c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 16715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 16815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 16915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 17015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 1716c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 17215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 1736c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 1746c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 175f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 17615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 17715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 17815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 179d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 180d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 181d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 182d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 183d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 184d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 185d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 186d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 187d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 188d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 18958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// If NewMI is true, then a new machine instruction must be created. 19058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// 19158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 19258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const = 0; 193d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 194f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// CommuteChangesDestination - Return true if commuting the specified 195f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// instruction will also changes the destination operand. Also return the 196f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// current operand index of the would be new destination register by 197f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// reference. This can happen when the commutable instruction is also a 198f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// two-address instruction. 199f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng virtual bool CommuteChangesDestination(MachineInstr *MI, 200f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng unsigned &OpIdx) const = 0; 201f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 202b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 203b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 204b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 205b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 206b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 20772dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 20872dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 20972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 210b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 2116c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 212c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// an successor block, it sets TBB to be the branch destination block and 213c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// a list of operands that evaluate the condition. These 2146c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 2156c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 2166c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 4. If this block ends with an conditional branch and an unconditional 217c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// block, it returns the 'true' destination in TBB, the 'false' 218c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// destination in FBB, and a list of operands that evaluate the condition. 219c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// These operands can be passed to other TargetInstrInfo methods to create 220c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// new branches. 221b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 222b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 223b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 224b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 225dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// If AllowModify is true, then this routine is allowed to modify the basic 226dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// block (e.g. delete instructions after the unconditional branch). 227dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// 228b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 229b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 230dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 231dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify = false) const { 232b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 233905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 234b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 235b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2368c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 237b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 238b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 239b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 240b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 241b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 242b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 243b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 244b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 24533644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 24633644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 247b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// null, Cond is empty) needs to be inserted. It returns the number of 248b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// instructions inserted. 249c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// 250c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// It is also invoked by tail merging to add unconditional branches in 251c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// cases where AnalyzeBranch doesn't apply because there was no original 252c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// branch to analyze. At least this much must be implemented, else tail 253c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// merging needs to be disabled. 254b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 255d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 25644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const { 25724321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 258b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 259b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 260b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 261a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// copyRegToReg - Emit instructions to copy between a pair of registers. It 262a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// returns false if the target does not how to copy between the specified 263a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// registers. 264940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 265d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 266d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 267d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 268d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 269d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 270c93457053cfecb24105ee3800c8e53921b950d8fCedric Venet return false; 271d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 272d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 27395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 27495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 27595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 27695a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 27795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 278f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 279f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 280f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 281f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 282f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 283f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 284f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 28595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToAddr - Store the specified register of the given register class 28695a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// to the specified address. The store instruction is to be added to the 28795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// given machine basic block before the specified machine instruction. If 28895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// isKill is true, the register operand is the last use and must be marked 28995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// kill. 290f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 291f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 292f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 293f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 294f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 295f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 296f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 29795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 29895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 29995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 30095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 301f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 302f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 303f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 304f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 305f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 306f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 307f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 30895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromAddr - Load the specified register of the given register class 30995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified address. The load instruction is to be added to 31095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// the given machine basic block before the specified machine instruction. 311f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 312f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 313f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 314f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 315f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 316f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 317f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 318d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 319d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 320d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of store instructions via 321d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// storeRegToStackSlot(). Returns false otherwise. 322d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 323d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 324d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 325d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 326d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 327d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 328d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 329d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 330d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of load instructions via loadRegToStackSlot(). 331d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// Returns false otherwise. 332d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 333d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 334d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 335d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 336d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 337d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 33843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 33943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 34043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 34143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// operand folded, otherwise NULL is returned. The client is responsible for 34243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// removing the old instruction and adding the new one in the instruction 34343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stream. 344c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 345c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 346c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 347c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 34843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 34943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 35043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 35143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 352c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 353c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 354c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 355c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 356c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 357c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 358c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 359c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 360c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 361c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 3625fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 3638e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 364c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 365c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return 0; 366c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 367c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 368c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 369c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 370c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 371c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 372c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 373c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 374c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 37543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 37643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 37743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 378c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 3792b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 38043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 38143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 3828e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 3838e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const { 38443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 38543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 38643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 38743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 38843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 38943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 39043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 39143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 39243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const{ 39343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 39443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 39543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 39643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 39743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 39843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 39943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 40043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 40143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 40243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 40343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 40443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible. 40543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 40643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool UnfoldLoad, bool UnfoldStore) const { 40743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 40843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 40943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 410c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 411c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 412c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 413c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 4148e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 415c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 416c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 417c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 4185f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 4195f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 4205f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 42144eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 42244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4235f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 424905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 4250271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 42665e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 42765e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 42865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 42965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 43065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 43165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 43265e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 43321d03f2de0087d60dbf575d95924404a97852879Evan Cheng 434bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 4354f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 436f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 4374f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4384f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4394f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 440bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 441bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 442318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 443bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 4440402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 44502c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 446f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 447f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 44844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const = 0; 4494f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 450bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 4514f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 452f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 45344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 45444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 4554f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4564f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4570402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 458ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 459ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 460ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 461ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 462ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 463ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 464ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 465ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 4664350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 4674350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 4684350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 46923066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 47023066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 47123066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 47252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Returns the size of the specified Instruction. 47352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 47452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 47552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 47652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 47752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 47852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 47952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 48052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 48152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 482a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 483a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 484641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 485641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 486641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 487641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 488641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 489641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 490749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 491641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 492641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 49358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 49458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const; 495f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng virtual bool CommuteChangesDestination(MachineInstr *MI, 496f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng unsigned &OpIdx) const; 497641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 49844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const; 499ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 500ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 501ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 502ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const; 50352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 504641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 505641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 506d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 507d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 508a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 509