TargetInstrInfo.h revision ffddf97e5dd1fc222cec049c30ca5d9018a741f8
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 56fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// This file was developed by the LLVM research group and is distributed under 66fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 202cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 21be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 22a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 24d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 255684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 26f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 27c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 28ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 296c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 30a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 31f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 32f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 33f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 34a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 35ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 36c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 38a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 393501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 4000876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4100876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 423501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 43a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 44f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 0; 45f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CALL_FLAG = 1 << 1; 46f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_RET_FLAG = 1 << 2; 47f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BARRIER_FLAG = 1 << 3; 48f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_LOAD_FLAG = 1 << 5; 50f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_STORE_FLAG = 1 << 6; 5115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 52a1fd6504aaf62b87530e8230517957bad3facc96Evan Cheng// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 5315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 5415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 5515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 56a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 5715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 60a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_COMMUTABLE = 1 << 8; 61a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 62075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 64075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 65075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 66a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_TERMINATOR_FLAG = 1 << 9; 67075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 6809321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 6909321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// insertion support when the DAG scheduler is inserting it into a machine basic 7009321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// block. 71a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 7209321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner 738d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 748d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// operands in addition to the minimum number operands specified. 75a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_VARIABLE_OPS = 1 << 11; 768d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 771bccb49082a8049d296dcdb2a741929437b6176fEvan Cheng// M_PREDICABLE - Set if this instruction has a predicate operand that 781bccb49082a8049d296dcdb2a741929437b6176fEvan Cheng// controls execution. It may be set to 'always'. 791bccb49082a8049d296dcdb2a741929437b6176fEvan Chengconst unsigned M_PREDICABLE = 1 << 12; 801b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 81d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 82d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman// at any time, e.g. constant generation, load from constant pool. 83d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanconst unsigned M_REMATERIALIZIBLE = 1 << 13; 84d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 854e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 864e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng// (e.g. instructions with unique labels attached). 87ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Chengconst unsigned M_NOT_DUPLICABLE = 1 << 14; 88ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 89ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 90ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng// ARM instructions which can set condition code if 's' bit is set. 91ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Chengconst unsigned M_HAS_OPTIONAL_DEF = 1 << 15; 924e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 9321d03f2de0087d60dbf575d95924404a97852879Evan Cheng// Machine operand flags 9421d03f2de0087d60dbf575d95924404a97852879Evan Cheng// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 9521d03f2de0087d60dbf575d95924404a97852879Evan Cheng// requires a callback to look up its register class. 9621d03f2de0087d60dbf575d95924404a97852879Evan Chengconst unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 9721d03f2de0087d60dbf575d95924404a97852879Evan Cheng 985de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 995de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// predicate operand that controls an M_PREDICATED instruction. 100f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattnerconst unsigned M_PREDICATE_OPERAND = 1 << 1; 101f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 102ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def. 103ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng/// 104ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Chengconst unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2; 105ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 1066c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengnamespace TOI { 1076c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng // Operand constraints: only "tied_to" for now. 1086c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng enum OperandConstraint { 1096c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TIED_TO = 0 // Must be allocated the same register as. 1106c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng }; 1116c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng} 112f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 113ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 114ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 115ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 116ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 117ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 11860f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// RegClass - This specifies the register class enumeration of the operand 11960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// if the operand is a register. If not, this contains 0. 12060f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short RegClass; 12160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short Flags; 122e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// Lower 16 bits are used to specify which constraints are set. The higher 16 123e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// bits are used to specify the value of constraints (4 bits each). 124e2ba8975883874633a1035c245af3b948b940b25Evan Cheng unsigned int Constraints; 125ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 126ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 127ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 128ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 1291fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 1301fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 13133247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng MachineOpCode Opcode; // The opcode. 13233247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng unsigned short numOperands; // Num of args (may be more if variable_ops). 133b5910820ce8608b75cb88e6c4efd2d1a5858159aEvan Cheng unsigned short numDefs; // Num of args that are definitions. 1344683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 13575e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 13675e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 13775e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 138f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 139f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 140ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 1416c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng 1426c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 1436c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// it is set. Returns -1 if it is not set. 1446c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng int getOperandConstraint(unsigned OpNum, 1456c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 146f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 147f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng "Invalid operand # of TargetInstrInfo"); 148f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng if (OpNum < numOperands && 149f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng (OpInfo[OpNum].Constraints & (1 << Constraint))) { 1506c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng unsigned Pos = 16 + Constraint * 4; 1516c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 1526c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 1536c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return -1; 1546c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 155cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng 156cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// findTiedToSrcOperand - Returns the operand that is tied to the specified 157cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// dest operand. Returns -1 if there isn't one. 158cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng int findTiedToSrcOperand(unsigned OpNum) const; 159a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 160a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 161a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1623501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 16334695381d626485a560594f162701088079589dfMisha Brukman/// 1643501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 16534695381d626485a560594f162701088079589dfMisha Brukman/// 166075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 167075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 168bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 169075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 17034695381d626485a560594f162701088079589dfMisha Brukman 171075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 172075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 173a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 174bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 175075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 17670535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1774ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 1784ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 1794ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 1801ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 18108d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb LABEL = 2, 18208d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb EXTRACT_SUBREG = 3, 18308d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb INSERT_SUBREG = 4 1844ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner }; 18534695381d626485a560594f162701088079589dfMisha Brukman 186bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 18734695381d626485a560594f162701088079589dfMisha Brukman 188e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 189e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 190e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 1912441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1922441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 1932441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 194a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1954683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 1962441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 1972441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 1984683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 19934695381d626485a560594f162701088079589dfMisha Brukman 2002441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 2012441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 202a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 203450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 204ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng int getNumDefs(MachineOpCode Opcode) const { 205ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng return get(Opcode).numDefs; 206ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng } 207ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng 2082441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 2092441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 210a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 211d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 2122441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 2132441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 214d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 215d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 2162441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 2172441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 218d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 219d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 220450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 221a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 222a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 223a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 22434695381d626485a560594f162701088079589dfMisha Brukman // 2252441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 2262441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 227a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 228450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 22913d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng bool isCommutableInstr(MachineOpCode Opcode) const { 23013d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng return get(Opcode).Flags & M_COMMUTABLE; 23113d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng } 232d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool isTerminatorInstr(MachineOpCode Opcode) const { 233075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 234075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 2350271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2360271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBranch(MachineOpCode Opcode) const { 2370271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 2380271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2390271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2400271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 2410271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// from executing the instruction immediately following it. Examples include 2420271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// unconditional branches and return instructions. 2430271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBarrier(MachineOpCode Opcode) const { 2440271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 2450271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2460271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2470271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isCall(MachineOpCode Opcode) const { 2480271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_CALL_FLAG; 2490271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2500271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isLoad(MachineOpCode Opcode) const { 2510271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 2520271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2530271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isStore(MachineOpCode Opcode) const { 2540271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_STORE_FLAG; 2550271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2560271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 257b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 258b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// which must be filled by the code generator. 259d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool hasDelaySlot(MachineOpCode Opcode) const { 260b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 261b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 262b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 2630271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 2640271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 2650271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// machine basic block. 266d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 2670271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 2680271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 269d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2708d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng bool hasVariableOperands(MachineOpCode Opcode) const { 2718d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng return get(Opcode).Flags & M_VARIABLE_OPS; 2728d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng } 2738d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 2744e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng bool isPredicable(MachineOpCode Opcode) const { 2754e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng return get(Opcode).Flags & M_PREDICABLE; 2764e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng } 2774e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 2784e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng bool isNotDuplicable(MachineOpCode Opcode) const { 2794e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng return get(Opcode).Flags & M_NOT_DUPLICABLE; 2804e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng } 2814e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 282ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng bool hasOptionalDef(MachineOpCode Opcode) const { 283ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; 284ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 285ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 286d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// isTriviallyReMaterializable - Return true if the instruction is trivially 287d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 288d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 289d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman bool isTriviallyReMaterializable(MachineInstr *MI) const { 290d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && 291d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman isReallyTriviallyReMaterializable(MI); 292d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 293d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 294d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 295d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// isReallyTriviallyReMaterializable - For instructions with opcodes for 296d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 297d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// instruction itself is actually trivially rematerializable, considering 298d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// its operands. This is used for targets that have instructions that are 299d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// only trivially rematerializable for specific uses. This predicate must 300d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// return false if the instruction has any side effects other than 301d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// producing a value, or if it requres any address registers that are not 302d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// always available. 303d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 304d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return true; 305d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 306d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 307d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 308e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 309e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// it is set. Returns -1 if it is not set. 310e2ba8975883874633a1035c245af3b948b940b25Evan Cheng int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 3116c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 3126c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return get(Opcode).getOperandConstraint(OpNum, Constraint); 313e2ba8975883874633a1035c245af3b948b940b25Evan Cheng } 314e2ba8975883874633a1035c245af3b948b940b25Evan Cheng 3150cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 3160cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 3175e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 3185e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 3195e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 3205e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 3215e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 322af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 323af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 324af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 325af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 326af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 327af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 328af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 329af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 330af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 331af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 332af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 333af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 334af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 335af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 336af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 337af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 338af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 339af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 3405e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 34115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 34215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 3432c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 3446c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 34515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 34615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 34715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 34815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 3496c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 35015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 3516c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 3526c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 3536c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 35415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 35515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 35615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 357d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 358d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 359d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 360d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 361d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 362d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 363d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 364d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 365d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 366d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 367d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 368d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 369b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 370b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 371b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 372b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 373b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 37472dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 37572dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 37672dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 377b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 3786c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 3796c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// an successor block, it sets TBB to be the branch destination block and a 3806c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// list of operands that evaluate the condition. These 3816c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 3826c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 3836c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 4. If this block ends with an conditional branch and an unconditional 3846c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// block, it returns the 'true' destination in TBB, the 'false' destination 3856c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// in FBB, and a list of operands that evaluate the condition. These 3866c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 3876c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 388b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 389b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 390b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 391b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 392b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 393b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 394b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner std::vector<MachineOperand> &Cond) const { 395b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 396905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 397b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 398b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 399b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// this is only invoked in cases where AnalyzeBranch returns success. It 400b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 401b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 402b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 403b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 404b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 405b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 406b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 407b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 40833644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 40933644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 410b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// null, Cond is empty) needs to be inserted. It returns the number of 411b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// instructions inserted. 412b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 413d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 414d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner const std::vector<MachineOperand> &Cond) const { 41524321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 416b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 417b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 418b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 419c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 420c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 421c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 422c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 423c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 424c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 425c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 426c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 4275f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 4285f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 4295f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 4305f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 4315f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 432905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 4330271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 43465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 43565e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 43665e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 43765e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 43865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 43965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 44065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 44121d03f2de0087d60dbf575d95924404a97852879Evan Cheng 442bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 4434f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 444f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 4454f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4464f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4474f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 448bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 449bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 450318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 451bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 4520402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 45302c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 454f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 455f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 456f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng const std::vector<MachineOperand> &Pred) const; 4574f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 458bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 4594f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 460f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 461f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 462f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng const std::vector<MachineOperand> &Pred2) const { 4634f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4644f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4650402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 466ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 467ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 468ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 469ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 470ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 471ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 472ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 473ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 47421d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 47521d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// values. 47621d03f2de0087d60dbf575d95924404a97852879Evan Cheng virtual const TargetRegisterClass *getPointerRegClass() const { 47721d03f2de0087d60dbf575d95924404a97852879Evan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 47821d03f2de0087d60dbf575d95924404a97852879Evan Cheng abort(); 479fb062ece96092e70a835c0d462613b07228d60a3Jeff Cohen return 0; // Must return a value in order to compile with VS 2005 48021d03f2de0087d60dbf575d95924404a97852879Evan Cheng } 481a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 482a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 483d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 484d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 485a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 486