TargetRegisterInfo.h revision 845d2c0c776abce551d16f7b1b7dc1f4d4df1a27
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include <cassert> 24#include <functional> 25 26namespace llvm { 27 28class BitVector; 29class MachineFunction; 30class RegScavenger; 31template<class T> class SmallVectorImpl; 32class raw_ostream; 33 34class TargetRegisterClass { 35public: 36 typedef const unsigned* iterator; 37 typedef const unsigned* const_iterator; 38 typedef const EVT* vt_iterator; 39 typedef const TargetRegisterClass* const * sc_iterator; 40private: 41 const MCRegisterClass *MC; 42 const vt_iterator VTs; 43 const unsigned *SubClassMask; 44 const sc_iterator SuperClasses; 45 const sc_iterator SubRegClasses; 46 const sc_iterator SuperRegClasses; 47public: 48 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, 49 const unsigned *subcm, 50 const TargetRegisterClass * const *supcs, 51 const TargetRegisterClass * const *subregcs, 52 const TargetRegisterClass * const *superregcs) 53 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs), 54 SubRegClasses(subregcs), SuperRegClasses(superregcs) {} 55 56 virtual ~TargetRegisterClass() {} // Allow subclasses 57 58 /// getID() - Return the register class ID number. 59 /// 60 unsigned getID() const { return MC->getID(); } 61 62 /// getName() - Return the register class name for debugging. 63 /// 64 const char *getName() const { return MC->getName(); } 65 66 /// begin/end - Return all of the registers in this class. 67 /// 68 iterator begin() const { return MC->begin(); } 69 iterator end() const { return MC->end(); } 70 71 /// getNumRegs - Return the number of registers in this class. 72 /// 73 unsigned getNumRegs() const { return MC->getNumRegs(); } 74 75 /// getRegister - Return the specified register in the class. 76 /// 77 unsigned getRegister(unsigned i) const { 78 return MC->getRegister(i); 79 } 80 81 /// contains - Return true if the specified register is included in this 82 /// register class. This does not include virtual registers. 83 bool contains(unsigned Reg) const { 84 return MC->contains(Reg); 85 } 86 87 /// contains - Return true if both registers are in this class. 88 bool contains(unsigned Reg1, unsigned Reg2) const { 89 return MC->contains(Reg1, Reg2); 90 } 91 92 /// getSize - Return the size of the register in bytes, which is also the size 93 /// of a stack slot allocated to hold a spilled copy of this register. 94 unsigned getSize() const { return MC->getSize(); } 95 96 /// getAlignment - Return the minimum required alignment for a register of 97 /// this class. 98 unsigned getAlignment() const { return MC->getAlignment(); } 99 100 /// getCopyCost - Return the cost of copying a value between two registers in 101 /// this class. A negative number means the register class is very expensive 102 /// to copy e.g. status flag register classes. 103 int getCopyCost() const { return MC->getCopyCost(); } 104 105 /// isAllocatable - Return true if this register class may be used to create 106 /// virtual registers. 107 bool isAllocatable() const { return MC->isAllocatable(); } 108 109 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 110 /// 111 bool hasType(EVT vt) const { 112 for(int i = 0; VTs[i] != MVT::Other; ++i) 113 if (VTs[i] == vt) 114 return true; 115 return false; 116 } 117 118 /// vt_begin / vt_end - Loop over all of the value types that can be 119 /// represented by values in this register class. 120 vt_iterator vt_begin() const { 121 return VTs; 122 } 123 124 vt_iterator vt_end() const { 125 vt_iterator I = VTs; 126 while (*I != MVT::Other) ++I; 127 return I; 128 } 129 130 /// subregclasses_begin / subregclasses_end - Loop over all of 131 /// the subreg register classes of this register class. 132 sc_iterator subregclasses_begin() const { 133 return SubRegClasses; 134 } 135 136 sc_iterator subregclasses_end() const { 137 sc_iterator I = SubRegClasses; 138 while (*I != NULL) ++I; 139 return I; 140 } 141 142 /// getSubRegisterRegClass - Return the register class of subregisters with 143 /// index SubIdx, or NULL if no such class exists. 144 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 145 assert(SubIdx>0 && "Invalid subregister index"); 146 return SubRegClasses[SubIdx-1]; 147 } 148 149 /// superregclasses_begin / superregclasses_end - Loop over all of 150 /// the superreg register classes of this register class. 151 sc_iterator superregclasses_begin() const { 152 return SuperRegClasses; 153 } 154 155 sc_iterator superregclasses_end() const { 156 sc_iterator I = SuperRegClasses; 157 while (*I != NULL) ++I; 158 return I; 159 } 160 161 /// hasSubClass - return true if the specified TargetRegisterClass 162 /// is a proper sub-class of this TargetRegisterClass. 163 bool hasSubClass(const TargetRegisterClass *RC) const { 164 return RC != this && hasSubClassEq(RC); 165 } 166 167 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 168 /// class. 169 bool hasSubClassEq(const TargetRegisterClass *RC) const { 170 unsigned ID = RC->getID(); 171 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 172 } 173 174 /// hasSuperClass - return true if the specified TargetRegisterClass is a 175 /// proper super-class of this TargetRegisterClass. 176 bool hasSuperClass(const TargetRegisterClass *RC) const { 177 return RC->hasSubClass(this); 178 } 179 180 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 181 /// class. 182 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 183 return RC->hasSubClassEq(this); 184 } 185 186 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 187 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 188 /// use it. 189 const unsigned *getSubClassMask() const { 190 return SubClassMask; 191 } 192 193 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 194 /// classes are ordered by ID which is also a topological ordering from large 195 /// to small classes. The list does NOT include the current class. 196 sc_iterator getSuperClasses() const { 197 return SuperClasses; 198 } 199 200 /// isASubClass - return true if this TargetRegisterClass is a subset 201 /// class of at least one other TargetRegisterClass. 202 bool isASubClass() const { 203 return SuperClasses[0] != 0; 204 } 205 206 /// getRawAllocationOrder - Returns the preferred order for allocating 207 /// registers from this register class in MF. The raw order comes directly 208 /// from the .td file and may include reserved registers that are not 209 /// allocatable. Register allocators should also make sure to allocate 210 /// callee-saved registers only after all the volatiles are used. The 211 /// RegisterClassInfo class provides filtered allocation orders with 212 /// callee-saved registers moved to the end. 213 /// 214 /// The MachineFunction argument can be used to tune the allocatable 215 /// registers based on the characteristics of the function, subtarget, or 216 /// other criteria. 217 /// 218 /// By default, this method returns all registers in the class. 219 /// 220 virtual 221 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 222 return makeArrayRef(begin(), getNumRegs()); 223 } 224}; 225 226/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 227/// registers. These are used by codegen, not by MC. 228struct TargetRegisterInfoDesc { 229 unsigned CostPerUse; // Extra cost of instructions using register. 230 bool inAllocatableClass; // Register belongs to an allocatable regclass. 231}; 232 233/// TargetRegisterInfo base class - We assume that the target defines a static 234/// array of TargetRegisterDesc objects that represent all of the machine 235/// registers that the target has. As such, we simply have to track a pointer 236/// to this array so that we can turn register number into a register 237/// descriptor. 238/// 239class TargetRegisterInfo : public MCRegisterInfo { 240public: 241 typedef const TargetRegisterClass * const * regclass_iterator; 242private: 243 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 244 const char *const *SubRegIndexNames; // Names of subreg indexes. 245 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 246 247protected: 248 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 249 regclass_iterator RegClassBegin, 250 regclass_iterator RegClassEnd, 251 const char *const *subregindexnames); 252 virtual ~TargetRegisterInfo(); 253public: 254 255 // Register numbers can represent physical registers, virtual registers, and 256 // sometimes stack slots. The unsigned values are divided into these ranges: 257 // 258 // 0 Not a register, can be used as a sentinel. 259 // [1;2^30) Physical registers assigned by TableGen. 260 // [2^30;2^31) Stack slots. (Rarely used.) 261 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 262 // 263 // Further sentinels can be allocated from the small negative integers. 264 // DenseMapInfo<unsigned> uses -1u and -2u. 265 266 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 267 /// frame index in a variable that normally holds a register. isStackSlot() 268 /// returns true if Reg is in the range used for stack slots. 269 /// 270 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 271 /// slots, so if a variable may contains a stack slot, always check 272 /// isStackSlot() first. 273 /// 274 static bool isStackSlot(unsigned Reg) { 275 return int(Reg) >= (1 << 30); 276 } 277 278 /// stackSlot2Index - Compute the frame index from a register value 279 /// representing a stack slot. 280 static int stackSlot2Index(unsigned Reg) { 281 assert(isStackSlot(Reg) && "Not a stack slot"); 282 return int(Reg - (1u << 30)); 283 } 284 285 /// index2StackSlot - Convert a non-negative frame index to a stack slot 286 /// register value. 287 static unsigned index2StackSlot(int FI) { 288 assert(FI >= 0 && "Cannot hold a negative frame index."); 289 return FI + (1u << 30); 290 } 291 292 /// isPhysicalRegister - Return true if the specified register number is in 293 /// the physical register namespace. 294 static bool isPhysicalRegister(unsigned Reg) { 295 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 296 return int(Reg) > 0; 297 } 298 299 /// isVirtualRegister - Return true if the specified register number is in 300 /// the virtual register namespace. 301 static bool isVirtualRegister(unsigned Reg) { 302 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 303 return int(Reg) < 0; 304 } 305 306 /// virtReg2Index - Convert a virtual register number to a 0-based index. 307 /// The first virtual register in a function will get the index 0. 308 static unsigned virtReg2Index(unsigned Reg) { 309 assert(isVirtualRegister(Reg) && "Not a virtual register"); 310 return Reg & ~(1u << 31); 311 } 312 313 /// index2VirtReg - Convert a 0-based index to a virtual register number. 314 /// This is the inverse operation of VirtReg2IndexFunctor below. 315 static unsigned index2VirtReg(unsigned Index) { 316 return Index | (1u << 31); 317 } 318 319 /// getMinimalPhysRegClass - Returns the Register Class of a physical 320 /// register of the given type, picking the most sub register class of 321 /// the right type that contains this physreg. 322 const TargetRegisterClass * 323 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 324 325 /// getAllocatableSet - Returns a bitset indexed by register number 326 /// indicating if a register is allocatable or not. If a register class is 327 /// specified, returns the subset for the class. 328 BitVector getAllocatableSet(const MachineFunction &MF, 329 const TargetRegisterClass *RC = NULL) const; 330 331 /// getCostPerUse - Return the additional cost of using this register instead 332 /// of other registers in its class. 333 unsigned getCostPerUse(unsigned RegNo) const { 334 return InfoDesc[RegNo].CostPerUse; 335 } 336 337 /// isInAllocatableClass - Return true if the register is in the allocation 338 /// of any register class. 339 bool isInAllocatableClass(unsigned RegNo) const { 340 return InfoDesc[RegNo].inAllocatableClass; 341 } 342 343 /// getSubRegIndexName - Return the human-readable symbolic target-specific 344 /// name for the specified SubRegIndex. 345 const char *getSubRegIndexName(unsigned SubIdx) const { 346 assert(SubIdx && "This is not a subregister index"); 347 return SubRegIndexNames[SubIdx-1]; 348 } 349 350 /// regsOverlap - Returns true if the two registers are equal or alias each 351 /// other. The registers may be virtual register. 352 bool regsOverlap(unsigned regA, unsigned regB) const { 353 if (regA == regB) return true; 354 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 355 return false; 356 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 357 if (*regList == regB) return true; 358 } 359 return false; 360 } 361 362 /// isSubRegister - Returns true if regB is a sub-register of regA. 363 /// 364 bool isSubRegister(unsigned regA, unsigned regB) const { 365 return isSuperRegister(regB, regA); 366 } 367 368 /// isSuperRegister - Returns true if regB is a super-register of regA. 369 /// 370 bool isSuperRegister(unsigned regA, unsigned regB) const { 371 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 372 if (*regList == regB) return true; 373 } 374 return false; 375 } 376 377 /// getCalleeSavedRegs - Return a null-terminated list of all of the 378 /// callee saved registers on this target. The register should be in the 379 /// order of desired callee-save stack frame offset. The first register is 380 /// closed to the incoming stack pointer if stack grows down, and vice versa. 381 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 382 const = 0; 383 384 385 /// getReservedRegs - Returns a bitset indexed by physical register number 386 /// indicating if a register is a special register that has particular uses 387 /// and should be considered unavailable at all times, e.g. SP, RA. This is 388 /// used by register scavenger to determine what registers are free. 389 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 390 391 /// getSubReg - Returns the physical register number of sub-register "Index" 392 /// for physical register RegNo. Return zero if the sub-register does not 393 /// exist. 394 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 395 396 /// getSubRegIndex - For a given register pair, return the sub-register index 397 /// if the second register is a sub-register of the first. Return zero 398 /// otherwise. 399 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 400 401 /// getMatchingSuperReg - Return a super-register of the specified register 402 /// Reg so its sub-register of index SubIdx is Reg. 403 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 404 const TargetRegisterClass *RC) const { 405 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 406 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 407 return SR; 408 return 0; 409 } 410 411 /// canCombineSubRegIndices - Given a register class and a list of 412 /// subregister indices, return true if it's possible to combine the 413 /// subregister indices into one that corresponds to a larger 414 /// subregister. Return the new subregister index by reference. Note the 415 /// new index may be zero if the given subregisters can be combined to 416 /// form the whole register. 417 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 418 SmallVectorImpl<unsigned> &SubIndices, 419 unsigned &NewSubIdx) const { 420 return 0; 421 } 422 423 /// getMatchingSuperRegClass - Return a subclass of the specified register 424 /// class A so that each register in it has a sub-register of the 425 /// specified sub-register index which is in the specified register class B. 426 virtual const TargetRegisterClass * 427 getMatchingSuperRegClass(const TargetRegisterClass *A, 428 const TargetRegisterClass *B, unsigned Idx) const { 429 return 0; 430 } 431 432 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 433 /// supports the sub-register index Idx. 434 /// If no such sub-class exists, return NULL. 435 /// If all registers in RC already have an Idx sub-register, return RC. 436 /// 437 /// TableGen generates a version of this function that is good enough in most 438 /// cases. Targets can override if they have constraints that TableGen 439 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 440 /// supported by the full GR32 register class in 64-bit mode, but only by the 441 /// GR32_ABCD regiister class in 32-bit mode. 442 /// 443 virtual const TargetRegisterClass * 444 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 445 446 /// composeSubRegIndices - Return the subregister index you get from composing 447 /// two subregister indices. 448 /// 449 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 450 /// returns c. Note that composeSubRegIndices does not tell you about illegal 451 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 452 /// b, composeSubRegIndices doesn't tell you. 453 /// 454 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 455 /// ssub_0:S0 - ssub_3:S3 subregs. 456 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 457 /// 458 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 459 // This default implementation is correct for most targets. 460 return b; 461 } 462 463 //===--------------------------------------------------------------------===// 464 // Register Class Information 465 // 466 467 /// Register class iterators 468 /// 469 regclass_iterator regclass_begin() const { return RegClassBegin; } 470 regclass_iterator regclass_end() const { return RegClassEnd; } 471 472 unsigned getNumRegClasses() const { 473 return (unsigned)(regclass_end()-regclass_begin()); 474 } 475 476 /// getRegClass - Returns the register class associated with the enumeration 477 /// value. See class MCOperandInfo. 478 const TargetRegisterClass *getRegClass(unsigned i) const { 479 assert(i < getNumRegClasses() && "Register Class ID out of range"); 480 return RegClassBegin[i]; 481 } 482 483 /// getCommonSubClass - find the largest common subclass of A and B. Return 484 /// NULL if there is no common subclass. 485 const TargetRegisterClass * 486 getCommonSubClass(const TargetRegisterClass *A, 487 const TargetRegisterClass *B) const; 488 489 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 490 /// values. If a target supports multiple different pointer register classes, 491 /// kind specifies which one is indicated. 492 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 493 assert(0 && "Target didn't implement getPointerRegClass!"); 494 return 0; // Must return a value in order to compile with VS 2005 495 } 496 497 /// getCrossCopyRegClass - Returns a legal register class to copy a register 498 /// in the specified class to or from. If it is possible to copy the register 499 /// directly without using a cross register class copy, return the specified 500 /// RC. Returns NULL if it is not possible to copy between a two registers of 501 /// the specified class. 502 virtual const TargetRegisterClass * 503 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 504 return RC; 505 } 506 507 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 508 /// legal to use in the current sub-target and has the same spill size. 509 /// The returned register class can be used to create virtual registers which 510 /// means that all its registers can be copied and spilled. 511 virtual const TargetRegisterClass* 512 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 513 /// The default implementation is very conservative and doesn't allow the 514 /// register allocator to inflate register classes. 515 return RC; 516 } 517 518 /// getRegPressureLimit - Return the register pressure "high water mark" for 519 /// the specific register class. The scheduler is in high register pressure 520 /// mode (for the specific register class) if it goes over the limit. 521 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 522 MachineFunction &MF) const { 523 return 0; 524 } 525 526 /// getRawAllocationOrder - Returns the register allocation order for a 527 /// specified register class with a target-dependent hint. The returned list 528 /// may contain reserved registers that cannot be allocated. 529 /// 530 /// Register allocators need only call this function to resolve 531 /// target-dependent hints, but it should work without hinting as well. 532 virtual ArrayRef<unsigned> 533 getRawAllocationOrder(const TargetRegisterClass *RC, 534 unsigned HintType, unsigned HintReg, 535 const MachineFunction &MF) const { 536 return RC->getRawAllocationOrder(MF); 537 } 538 539 /// ResolveRegAllocHint - Resolves the specified register allocation hint 540 /// to a physical register. Returns the physical register if it is successful. 541 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 542 const MachineFunction &MF) const { 543 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 544 return Reg; 545 return 0; 546 } 547 548 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 549 /// writing a register from RC in two consecutive instructions. 550 /// This can avoid pipeline stalls on certain architectures. 551 /// It does cause increased register pressure, though. 552 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 553 return false; 554 } 555 556 /// UpdateRegAllocHint - A callback to allow target a chance to update 557 /// register allocation hints when a register is "changed" (e.g. coalesced) 558 /// to another register. e.g. On ARM, some virtual registers should target 559 /// register pairs, if one of pair is coalesced to another register, the 560 /// allocation hint of the other half of the pair should be changed to point 561 /// to the new register. 562 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 563 MachineFunction &MF) const { 564 // Do nothing. 565 } 566 567 /// requiresRegisterScavenging - returns true if the target requires (and can 568 /// make use of) the register scavenger. 569 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 570 return false; 571 } 572 573 /// useFPForScavengingIndex - returns true if the target wants to use 574 /// frame pointer based accesses to spill to the scavenger emergency spill 575 /// slot. 576 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 577 return true; 578 } 579 580 /// requiresFrameIndexScavenging - returns true if the target requires post 581 /// PEI scavenging of registers for materializing frame index constants. 582 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 583 return false; 584 } 585 586 /// requiresVirtualBaseRegisters - Returns true if the target wants the 587 /// LocalStackAllocation pass to be run and virtual base registers 588 /// used for more efficient stack access. 589 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 590 return false; 591 } 592 593 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 594 /// the stack frame of the given function for the specified register. e.g. On 595 /// x86, if the frame register is required, the first fixed stack object is 596 /// reserved as its spill slot. This tells PEI not to create a new stack frame 597 /// object for the given register. It should be called only after 598 /// processFunctionBeforeCalleeSavedScan(). 599 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 600 int &FrameIdx) const { 601 return false; 602 } 603 604 /// needsStackRealignment - true if storage within the function requires the 605 /// stack pointer to be aligned more than the normal calling convention calls 606 /// for. 607 virtual bool needsStackRealignment(const MachineFunction &MF) const { 608 return false; 609 } 610 611 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 612 /// index in the instruction, if there is one. 613 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 614 int Idx) const { 615 return 0; 616 } 617 618 /// needsFrameBaseReg - Returns true if the instruction's frame index 619 /// reference would be better served by a base register other than FP 620 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 621 /// references it should create new base registers for. 622 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 623 return false; 624 } 625 626 /// materializeFrameBaseRegister - Insert defining instruction(s) for 627 /// BaseReg to be a pointer to FrameIdx before insertion point I. 628 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 629 unsigned BaseReg, int FrameIdx, 630 int64_t Offset) const { 631 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 632 } 633 634 /// resolveFrameIndex - Resolve a frame index operand of an instruction 635 /// to reference the indicated base register plus offset instead. 636 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 637 unsigned BaseReg, int64_t Offset) const { 638 assert(0 && "resolveFrameIndex does not exist on this target"); 639 } 640 641 /// isFrameOffsetLegal - Determine whether a given offset immediate is 642 /// encodable to resolve a frame index. 643 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 644 int64_t Offset) const { 645 assert(0 && "isFrameOffsetLegal does not exist on this target"); 646 return false; // Must return a value in order to compile with VS 2005 647 } 648 649 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 650 /// code insertion to eliminate call frame setup and destroy pseudo 651 /// instructions (but only if the Target is using them). It is responsible 652 /// for eliminating these instructions, replacing them with concrete 653 /// instructions. This method need only be implemented if using call frame 654 /// setup/destroy pseudo instructions. 655 /// 656 virtual void 657 eliminateCallFramePseudoInstr(MachineFunction &MF, 658 MachineBasicBlock &MBB, 659 MachineBasicBlock::iterator MI) const { 660 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 661 } 662 663 664 /// saveScavengerRegister - Spill the register so it can be used by the 665 /// register scavenger. Return true if the register was spilled, false 666 /// otherwise. If this function does not spill the register, the scavenger 667 /// will instead spill it to the emergency spill slot. 668 /// 669 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 670 MachineBasicBlock::iterator I, 671 MachineBasicBlock::iterator &UseMI, 672 const TargetRegisterClass *RC, 673 unsigned Reg) const { 674 return false; 675 } 676 677 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 678 /// frame indices from instructions which may use them. The instruction 679 /// referenced by the iterator contains an MO_FrameIndex operand which must be 680 /// eliminated by this method. This method may modify or replace the 681 /// specified instruction, as long as it keeps the iterator pointing at the 682 /// finished product. SPAdj is the SP adjustment due to call frame setup 683 /// instruction. 684 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 685 int SPAdj, RegScavenger *RS=NULL) const = 0; 686 687 //===--------------------------------------------------------------------===// 688 /// Debug information queries. 689 690 /// getFrameRegister - This method should return the register used as a base 691 /// for values allocated in the current stack frame. 692 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 693 694 /// getCompactUnwindRegNum - This function maps the register to the number for 695 /// compact unwind encoding. Return -1 if the register isn't valid. 696 virtual int getCompactUnwindRegNum(unsigned, bool) const { 697 return -1; 698 } 699}; 700 701 702// This is useful when building IndexedMaps keyed on virtual registers 703struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 704 unsigned operator()(unsigned Reg) const { 705 return TargetRegisterInfo::virtReg2Index(Reg); 706 } 707}; 708 709/// PrintReg - Helper class for printing registers on a raw_ostream. 710/// Prints virtual and physical registers with or without a TRI instance. 711/// 712/// The format is: 713/// %noreg - NoRegister 714/// %vreg5 - a virtual register. 715/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 716/// %EAX - a physical register 717/// %physreg17 - a physical register when no TRI instance given. 718/// 719/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 720/// 721class PrintReg { 722 const TargetRegisterInfo *TRI; 723 unsigned Reg; 724 unsigned SubIdx; 725public: 726 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 727 : TRI(tri), Reg(reg), SubIdx(subidx) {} 728 void print(raw_ostream&) const; 729}; 730 731static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 732 PR.print(OS); 733 return OS; 734} 735 736} // End llvm namespace 737 738#endif 739