TargetRegisterInfo.h revision c66d36028b21077aa1715331c22347b47b4da94f
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include <cassert> 24#include <functional> 25 26namespace llvm { 27 28class BitVector; 29class MachineFunction; 30class RegScavenger; 31template<class T> class SmallVectorImpl; 32class raw_ostream; 33 34class TargetRegisterClass { 35public: 36 typedef const unsigned* iterator; 37 typedef const unsigned* const_iterator; 38 typedef const EVT* vt_iterator; 39 typedef const TargetRegisterClass* const * sc_iterator; 40private: 41 const MCRegisterClass *MC; 42 const vt_iterator VTs; 43 const sc_iterator SubClasses; 44 const sc_iterator SuperClasses; 45 const sc_iterator SubRegClasses; 46 const sc_iterator SuperRegClasses; 47public: 48 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, 49 const TargetRegisterClass * const *subcs, 50 const TargetRegisterClass * const *supcs, 51 const TargetRegisterClass * const *subregcs, 52 const TargetRegisterClass * const *superregcs) 53 : MC(MC), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 54 SubRegClasses(subregcs), SuperRegClasses(superregcs) {} 55 56 virtual ~TargetRegisterClass() {} // Allow subclasses 57 58 /// getID() - Return the register class ID number. 59 /// 60 unsigned getID() const { return MC->getID(); } 61 62 /// getName() - Return the register class name for debugging. 63 /// 64 const char *getName() const { return MC->getName(); } 65 66 /// begin/end - Return all of the registers in this class. 67 /// 68 iterator begin() const { return MC->begin(); } 69 iterator end() const { return MC->end(); } 70 71 /// getNumRegs - Return the number of registers in this class. 72 /// 73 unsigned getNumRegs() const { return MC->getNumRegs(); } 74 75 /// getRegister - Return the specified register in the class. 76 /// 77 unsigned getRegister(unsigned i) const { 78 return MC->getRegister(i); 79 } 80 81 /// contains - Return true if the specified register is included in this 82 /// register class. This does not include virtual registers. 83 bool contains(unsigned Reg) const { 84 return MC->contains(Reg); 85 } 86 87 /// contains - Return true if both registers are in this class. 88 bool contains(unsigned Reg1, unsigned Reg2) const { 89 return MC->contains(Reg1, Reg2); 90 } 91 92 /// getSize - Return the size of the register in bytes, which is also the size 93 /// of a stack slot allocated to hold a spilled copy of this register. 94 unsigned getSize() const { return MC->getSize(); } 95 96 /// getAlignment - Return the minimum required alignment for a register of 97 /// this class. 98 unsigned getAlignment() const { return MC->getAlignment(); } 99 100 /// getCopyCost - Return the cost of copying a value between two registers in 101 /// this class. A negative number means the register class is very expensive 102 /// to copy e.g. status flag register classes. 103 int getCopyCost() const { return MC->getCopyCost(); } 104 105 /// isAllocatable - Return true if this register class may be used to create 106 /// virtual registers. 107 bool isAllocatable() const { return MC->isAllocatable(); } 108 109 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 110 /// 111 bool hasType(EVT vt) const { 112 for(int i = 0; VTs[i] != MVT::Other; ++i) 113 if (VTs[i] == vt) 114 return true; 115 return false; 116 } 117 118 /// vt_begin / vt_end - Loop over all of the value types that can be 119 /// represented by values in this register class. 120 vt_iterator vt_begin() const { 121 return VTs; 122 } 123 124 vt_iterator vt_end() const { 125 vt_iterator I = VTs; 126 while (*I != MVT::Other) ++I; 127 return I; 128 } 129 130 /// subregclasses_begin / subregclasses_end - Loop over all of 131 /// the subreg register classes of this register class. 132 sc_iterator subregclasses_begin() const { 133 return SubRegClasses; 134 } 135 136 sc_iterator subregclasses_end() const { 137 sc_iterator I = SubRegClasses; 138 while (*I != NULL) ++I; 139 return I; 140 } 141 142 /// getSubRegisterRegClass - Return the register class of subregisters with 143 /// index SubIdx, or NULL if no such class exists. 144 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 145 assert(SubIdx>0 && "Invalid subregister index"); 146 return SubRegClasses[SubIdx-1]; 147 } 148 149 /// superregclasses_begin / superregclasses_end - Loop over all of 150 /// the superreg register classes of this register class. 151 sc_iterator superregclasses_begin() const { 152 return SuperRegClasses; 153 } 154 155 sc_iterator superregclasses_end() const { 156 sc_iterator I = SuperRegClasses; 157 while (*I != NULL) ++I; 158 return I; 159 } 160 161 /// hasSubClass - return true if the specified TargetRegisterClass 162 /// is a proper subset of this TargetRegisterClass. 163 bool hasSubClass(const TargetRegisterClass *cs) const { 164 for (int i = 0; SubClasses[i] != NULL; ++i) 165 if (SubClasses[i] == cs) 166 return true; 167 return false; 168 } 169 170 /// hasSubClassEq - Returns true if RC is a subclass of or equal to this 171 /// class. 172 bool hasSubClassEq(const TargetRegisterClass *RC) const { 173 return RC == this || hasSubClass(RC); 174 } 175 176 /// subclasses_begin / subclasses_end - Loop over all of the classes 177 /// that are proper subsets of this register class. 178 sc_iterator subclasses_begin() const { 179 return SubClasses; 180 } 181 182 sc_iterator subclasses_end() const { 183 sc_iterator I = SubClasses; 184 while (*I != NULL) ++I; 185 return I; 186 } 187 188 /// hasSuperClass - return true if the specified TargetRegisterClass is a 189 /// proper superset of this TargetRegisterClass. 190 bool hasSuperClass(const TargetRegisterClass *cs) const { 191 for (int i = 0; SuperClasses[i] != NULL; ++i) 192 if (SuperClasses[i] == cs) 193 return true; 194 return false; 195 } 196 197 /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this 198 /// class. 199 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 200 return RC == this || hasSuperClass(RC); 201 } 202 203 /// superclasses_begin / superclasses_end - Loop over all of the classes 204 /// that are proper supersets of this register class. 205 sc_iterator superclasses_begin() const { 206 return SuperClasses; 207 } 208 209 sc_iterator superclasses_end() const { 210 sc_iterator I = SuperClasses; 211 while (*I != NULL) ++I; 212 return I; 213 } 214 215 /// isASubClass - return true if this TargetRegisterClass is a subset 216 /// class of at least one other TargetRegisterClass. 217 bool isASubClass() const { 218 return SuperClasses[0] != 0; 219 } 220 221 /// getRawAllocationOrder - Returns the preferred order for allocating 222 /// registers from this register class in MF. The raw order comes directly 223 /// from the .td file and may include reserved registers that are not 224 /// allocatable. Register allocators should also make sure to allocate 225 /// callee-saved registers only after all the volatiles are used. The 226 /// RegisterClassInfo class provides filtered allocation orders with 227 /// callee-saved registers moved to the end. 228 /// 229 /// The MachineFunction argument can be used to tune the allocatable 230 /// registers based on the characteristics of the function, subtarget, or 231 /// other criteria. 232 /// 233 /// By default, this method returns all registers in the class. 234 /// 235 virtual 236 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 237 return makeArrayRef(begin(), getNumRegs()); 238 } 239}; 240 241/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 242/// registers. These are used by codegen, not by MC. 243struct TargetRegisterInfoDesc { 244 unsigned CostPerUse; // Extra cost of instructions using register. 245 bool inAllocatableClass; // Register belongs to an allocatable regclass. 246}; 247 248/// TargetRegisterInfo base class - We assume that the target defines a static 249/// array of TargetRegisterDesc objects that represent all of the machine 250/// registers that the target has. As such, we simply have to track a pointer 251/// to this array so that we can turn register number into a register 252/// descriptor. 253/// 254class TargetRegisterInfo : public MCRegisterInfo { 255public: 256 typedef const TargetRegisterClass * const * regclass_iterator; 257private: 258 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 259 const char *const *SubRegIndexNames; // Names of subreg indexes. 260 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 261 262protected: 263 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 264 regclass_iterator RegClassBegin, 265 regclass_iterator RegClassEnd, 266 const char *const *subregindexnames); 267 virtual ~TargetRegisterInfo(); 268public: 269 270 // Register numbers can represent physical registers, virtual registers, and 271 // sometimes stack slots. The unsigned values are divided into these ranges: 272 // 273 // 0 Not a register, can be used as a sentinel. 274 // [1;2^30) Physical registers assigned by TableGen. 275 // [2^30;2^31) Stack slots. (Rarely used.) 276 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 277 // 278 // Further sentinels can be allocated from the small negative integers. 279 // DenseMapInfo<unsigned> uses -1u and -2u. 280 281 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 282 /// frame index in a variable that normally holds a register. isStackSlot() 283 /// returns true if Reg is in the range used for stack slots. 284 /// 285 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 286 /// slots, so if a variable may contains a stack slot, always check 287 /// isStackSlot() first. 288 /// 289 static bool isStackSlot(unsigned Reg) { 290 return int(Reg) >= (1 << 30); 291 } 292 293 /// stackSlot2Index - Compute the frame index from a register value 294 /// representing a stack slot. 295 static int stackSlot2Index(unsigned Reg) { 296 assert(isStackSlot(Reg) && "Not a stack slot"); 297 return int(Reg - (1u << 30)); 298 } 299 300 /// index2StackSlot - Convert a non-negative frame index to a stack slot 301 /// register value. 302 static unsigned index2StackSlot(int FI) { 303 assert(FI >= 0 && "Cannot hold a negative frame index."); 304 return FI + (1u << 30); 305 } 306 307 /// isPhysicalRegister - Return true if the specified register number is in 308 /// the physical register namespace. 309 static bool isPhysicalRegister(unsigned Reg) { 310 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 311 return int(Reg) > 0; 312 } 313 314 /// isVirtualRegister - Return true if the specified register number is in 315 /// the virtual register namespace. 316 static bool isVirtualRegister(unsigned Reg) { 317 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 318 return int(Reg) < 0; 319 } 320 321 /// virtReg2Index - Convert a virtual register number to a 0-based index. 322 /// The first virtual register in a function will get the index 0. 323 static unsigned virtReg2Index(unsigned Reg) { 324 assert(isVirtualRegister(Reg) && "Not a virtual register"); 325 return Reg & ~(1u << 31); 326 } 327 328 /// index2VirtReg - Convert a 0-based index to a virtual register number. 329 /// This is the inverse operation of VirtReg2IndexFunctor below. 330 static unsigned index2VirtReg(unsigned Index) { 331 return Index | (1u << 31); 332 } 333 334 /// getMinimalPhysRegClass - Returns the Register Class of a physical 335 /// register of the given type, picking the most sub register class of 336 /// the right type that contains this physreg. 337 const TargetRegisterClass * 338 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 339 340 /// getAllocatableSet - Returns a bitset indexed by register number 341 /// indicating if a register is allocatable or not. If a register class is 342 /// specified, returns the subset for the class. 343 BitVector getAllocatableSet(const MachineFunction &MF, 344 const TargetRegisterClass *RC = NULL) const; 345 346 /// getCostPerUse - Return the additional cost of using this register instead 347 /// of other registers in its class. 348 unsigned getCostPerUse(unsigned RegNo) const { 349 return InfoDesc[RegNo].CostPerUse; 350 } 351 352 /// isInAllocatableClass - Return true if the register is in the allocation 353 /// of any register class. 354 bool isInAllocatableClass(unsigned RegNo) const { 355 return InfoDesc[RegNo].inAllocatableClass; 356 } 357 358 /// getSubRegIndexName - Return the human-readable symbolic target-specific 359 /// name for the specified SubRegIndex. 360 const char *getSubRegIndexName(unsigned SubIdx) const { 361 assert(SubIdx && "This is not a subregister index"); 362 return SubRegIndexNames[SubIdx-1]; 363 } 364 365 /// regsOverlap - Returns true if the two registers are equal or alias each 366 /// other. The registers may be virtual register. 367 bool regsOverlap(unsigned regA, unsigned regB) const { 368 if (regA == regB) return true; 369 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 370 return false; 371 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 372 if (*regList == regB) return true; 373 } 374 return false; 375 } 376 377 /// isSubRegister - Returns true if regB is a sub-register of regA. 378 /// 379 bool isSubRegister(unsigned regA, unsigned regB) const { 380 return isSuperRegister(regB, regA); 381 } 382 383 /// isSuperRegister - Returns true if regB is a super-register of regA. 384 /// 385 bool isSuperRegister(unsigned regA, unsigned regB) const { 386 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 387 if (*regList == regB) return true; 388 } 389 return false; 390 } 391 392 /// getCalleeSavedRegs - Return a null-terminated list of all of the 393 /// callee saved registers on this target. The register should be in the 394 /// order of desired callee-save stack frame offset. The first register is 395 /// closed to the incoming stack pointer if stack grows down, and vice versa. 396 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 397 const = 0; 398 399 400 /// getReservedRegs - Returns a bitset indexed by physical register number 401 /// indicating if a register is a special register that has particular uses 402 /// and should be considered unavailable at all times, e.g. SP, RA. This is 403 /// used by register scavenger to determine what registers are free. 404 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 405 406 /// getSubReg - Returns the physical register number of sub-register "Index" 407 /// for physical register RegNo. Return zero if the sub-register does not 408 /// exist. 409 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 410 411 /// getSubRegIndex - For a given register pair, return the sub-register index 412 /// if the second register is a sub-register of the first. Return zero 413 /// otherwise. 414 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 415 416 /// getMatchingSuperReg - Return a super-register of the specified register 417 /// Reg so its sub-register of index SubIdx is Reg. 418 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 419 const TargetRegisterClass *RC) const { 420 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 421 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 422 return SR; 423 return 0; 424 } 425 426 /// canCombineSubRegIndices - Given a register class and a list of 427 /// subregister indices, return true if it's possible to combine the 428 /// subregister indices into one that corresponds to a larger 429 /// subregister. Return the new subregister index by reference. Note the 430 /// new index may be zero if the given subregisters can be combined to 431 /// form the whole register. 432 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 433 SmallVectorImpl<unsigned> &SubIndices, 434 unsigned &NewSubIdx) const { 435 return 0; 436 } 437 438 /// getMatchingSuperRegClass - Return a subclass of the specified register 439 /// class A so that each register in it has a sub-register of the 440 /// specified sub-register index which is in the specified register class B. 441 virtual const TargetRegisterClass * 442 getMatchingSuperRegClass(const TargetRegisterClass *A, 443 const TargetRegisterClass *B, unsigned Idx) const { 444 return 0; 445 } 446 447 /// composeSubRegIndices - Return the subregister index you get from composing 448 /// two subregister indices. 449 /// 450 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 451 /// returns c. Note that composeSubRegIndices does not tell you about illegal 452 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 453 /// b, composeSubRegIndices doesn't tell you. 454 /// 455 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 456 /// ssub_0:S0 - ssub_3:S3 subregs. 457 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 458 /// 459 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 460 // This default implementation is correct for most targets. 461 return b; 462 } 463 464 //===--------------------------------------------------------------------===// 465 // Register Class Information 466 // 467 468 /// Register class iterators 469 /// 470 regclass_iterator regclass_begin() const { return RegClassBegin; } 471 regclass_iterator regclass_end() const { return RegClassEnd; } 472 473 unsigned getNumRegClasses() const { 474 return (unsigned)(regclass_end()-regclass_begin()); 475 } 476 477 /// getRegClass - Returns the register class associated with the enumeration 478 /// value. See class MCOperandInfo. 479 const TargetRegisterClass *getRegClass(unsigned i) const { 480 assert(i < getNumRegClasses() && "Register Class ID out of range"); 481 return RegClassBegin[i]; 482 } 483 484 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 485 /// values. If a target supports multiple different pointer register classes, 486 /// kind specifies which one is indicated. 487 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 488 assert(0 && "Target didn't implement getPointerRegClass!"); 489 return 0; // Must return a value in order to compile with VS 2005 490 } 491 492 /// getCrossCopyRegClass - Returns a legal register class to copy a register 493 /// in the specified class to or from. If it is possible to copy the register 494 /// directly without using a cross register class copy, return the specified 495 /// RC. Returns NULL if it is not possible to copy between a two registers of 496 /// the specified class. 497 virtual const TargetRegisterClass * 498 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 499 return RC; 500 } 501 502 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 503 /// legal to use in the current sub-target and has the same spill size. 504 /// The returned register class can be used to create virtual registers which 505 /// means that all its registers can be copied and spilled. 506 virtual const TargetRegisterClass* 507 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 508 /// The default implementation is very conservative and doesn't allow the 509 /// register allocator to inflate register classes. 510 return RC; 511 } 512 513 /// getRegPressureLimit - Return the register pressure "high water mark" for 514 /// the specific register class. The scheduler is in high register pressure 515 /// mode (for the specific register class) if it goes over the limit. 516 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 517 MachineFunction &MF) const { 518 return 0; 519 } 520 521 /// getRawAllocationOrder - Returns the register allocation order for a 522 /// specified register class with a target-dependent hint. The returned list 523 /// may contain reserved registers that cannot be allocated. 524 /// 525 /// Register allocators need only call this function to resolve 526 /// target-dependent hints, but it should work without hinting as well. 527 virtual ArrayRef<unsigned> 528 getRawAllocationOrder(const TargetRegisterClass *RC, 529 unsigned HintType, unsigned HintReg, 530 const MachineFunction &MF) const { 531 return RC->getRawAllocationOrder(MF); 532 } 533 534 /// ResolveRegAllocHint - Resolves the specified register allocation hint 535 /// to a physical register. Returns the physical register if it is successful. 536 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 537 const MachineFunction &MF) const { 538 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 539 return Reg; 540 return 0; 541 } 542 543 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 544 /// writing a register from RC in two consecutive instructions. 545 /// This can avoid pipeline stalls on certain architectures. 546 /// It does cause increased register pressure, though. 547 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 548 return false; 549 } 550 551 /// UpdateRegAllocHint - A callback to allow target a chance to update 552 /// register allocation hints when a register is "changed" (e.g. coalesced) 553 /// to another register. e.g. On ARM, some virtual registers should target 554 /// register pairs, if one of pair is coalesced to another register, the 555 /// allocation hint of the other half of the pair should be changed to point 556 /// to the new register. 557 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 558 MachineFunction &MF) const { 559 // Do nothing. 560 } 561 562 /// requiresRegisterScavenging - returns true if the target requires (and can 563 /// make use of) the register scavenger. 564 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 565 return false; 566 } 567 568 /// useFPForScavengingIndex - returns true if the target wants to use 569 /// frame pointer based accesses to spill to the scavenger emergency spill 570 /// slot. 571 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 572 return true; 573 } 574 575 /// requiresFrameIndexScavenging - returns true if the target requires post 576 /// PEI scavenging of registers for materializing frame index constants. 577 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 578 return false; 579 } 580 581 /// requiresVirtualBaseRegisters - Returns true if the target wants the 582 /// LocalStackAllocation pass to be run and virtual base registers 583 /// used for more efficient stack access. 584 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 585 return false; 586 } 587 588 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 589 /// the stack frame of the given function for the specified register. e.g. On 590 /// x86, if the frame register is required, the first fixed stack object is 591 /// reserved as its spill slot. This tells PEI not to create a new stack frame 592 /// object for the given register. It should be called only after 593 /// processFunctionBeforeCalleeSavedScan(). 594 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 595 int &FrameIdx) const { 596 return false; 597 } 598 599 /// needsStackRealignment - true if storage within the function requires the 600 /// stack pointer to be aligned more than the normal calling convention calls 601 /// for. 602 virtual bool needsStackRealignment(const MachineFunction &MF) const { 603 return false; 604 } 605 606 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 607 /// index in the instruction, if there is one. 608 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 609 int Idx) const { 610 return 0; 611 } 612 613 /// needsFrameBaseReg - Returns true if the instruction's frame index 614 /// reference would be better served by a base register other than FP 615 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 616 /// references it should create new base registers for. 617 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 618 return false; 619 } 620 621 /// materializeFrameBaseRegister - Insert defining instruction(s) for 622 /// BaseReg to be a pointer to FrameIdx before insertion point I. 623 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 624 unsigned BaseReg, int FrameIdx, 625 int64_t Offset) const { 626 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 627 } 628 629 /// resolveFrameIndex - Resolve a frame index operand of an instruction 630 /// to reference the indicated base register plus offset instead. 631 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 632 unsigned BaseReg, int64_t Offset) const { 633 assert(0 && "resolveFrameIndex does not exist on this target"); 634 } 635 636 /// isFrameOffsetLegal - Determine whether a given offset immediate is 637 /// encodable to resolve a frame index. 638 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 639 int64_t Offset) const { 640 assert(0 && "isFrameOffsetLegal does not exist on this target"); 641 return false; // Must return a value in order to compile with VS 2005 642 } 643 644 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 645 /// code insertion to eliminate call frame setup and destroy pseudo 646 /// instructions (but only if the Target is using them). It is responsible 647 /// for eliminating these instructions, replacing them with concrete 648 /// instructions. This method need only be implemented if using call frame 649 /// setup/destroy pseudo instructions. 650 /// 651 virtual void 652 eliminateCallFramePseudoInstr(MachineFunction &MF, 653 MachineBasicBlock &MBB, 654 MachineBasicBlock::iterator MI) const { 655 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 656 } 657 658 659 /// saveScavengerRegister - Spill the register so it can be used by the 660 /// register scavenger. Return true if the register was spilled, false 661 /// otherwise. If this function does not spill the register, the scavenger 662 /// will instead spill it to the emergency spill slot. 663 /// 664 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 665 MachineBasicBlock::iterator I, 666 MachineBasicBlock::iterator &UseMI, 667 const TargetRegisterClass *RC, 668 unsigned Reg) const { 669 return false; 670 } 671 672 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 673 /// frame indices from instructions which may use them. The instruction 674 /// referenced by the iterator contains an MO_FrameIndex operand which must be 675 /// eliminated by this method. This method may modify or replace the 676 /// specified instruction, as long as it keeps the iterator pointing at the 677 /// finished product. SPAdj is the SP adjustment due to call frame setup 678 /// instruction. 679 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 680 int SPAdj, RegScavenger *RS=NULL) const = 0; 681 682 //===--------------------------------------------------------------------===// 683 /// Debug information queries. 684 685 /// getFrameRegister - This method should return the register used as a base 686 /// for values allocated in the current stack frame. 687 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 688 689 /// getCompactUnwindRegNum - This function maps the register to the number for 690 /// compact unwind encoding. Return -1 if the register isn't valid. 691 virtual int getCompactUnwindRegNum(unsigned, bool) const { 692 return -1; 693 } 694}; 695 696 697// This is useful when building IndexedMaps keyed on virtual registers 698struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 699 unsigned operator()(unsigned Reg) const { 700 return TargetRegisterInfo::virtReg2Index(Reg); 701 } 702}; 703 704/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 705/// if there is no common subclass. 706const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 707 const TargetRegisterClass *B); 708 709/// PrintReg - Helper class for printing registers on a raw_ostream. 710/// Prints virtual and physical registers with or without a TRI instance. 711/// 712/// The format is: 713/// %noreg - NoRegister 714/// %vreg5 - a virtual register. 715/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 716/// %EAX - a physical register 717/// %physreg17 - a physical register when no TRI instance given. 718/// 719/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 720/// 721class PrintReg { 722 const TargetRegisterInfo *TRI; 723 unsigned Reg; 724 unsigned SubIdx; 725public: 726 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 727 : TRI(tri), Reg(reg), SubIdx(subidx) {} 728 void print(raw_ostream&) const; 729}; 730 731static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 732 PR.print(OS); 733 return OS; 734} 735 736} // End llvm namespace 737 738#endif 739