TargetRegisterInfo.h revision e837dead3c8dc3445ef6a0e2322179c57e264a13
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include "llvm/ADT/DenseSet.h" 24#include <cassert> 25#include <functional> 26 27namespace llvm { 28 29class BitVector; 30class MachineFunction; 31class RegScavenger; 32template<class T> class SmallVectorImpl; 33class raw_ostream; 34 35class TargetRegisterClass { 36public: 37 typedef const unsigned* iterator; 38 typedef const unsigned* const_iterator; 39 40 typedef const EVT* vt_iterator; 41 typedef const TargetRegisterClass* const * sc_iterator; 42private: 43 unsigned ID; 44 const char *Name; 45 const vt_iterator VTs; 46 const sc_iterator SubClasses; 47 const sc_iterator SuperClasses; 48 const sc_iterator SubRegClasses; 49 const sc_iterator SuperRegClasses; 50 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 51 const int CopyCost; 52 const bool Allocatable; 53 const iterator RegsBegin, RegsEnd; 54 DenseSet<unsigned> RegSet; 55public: 56 TargetRegisterClass(unsigned id, 57 const char *name, 58 const EVT *vts, 59 const TargetRegisterClass * const *subcs, 60 const TargetRegisterClass * const *supcs, 61 const TargetRegisterClass * const *subregcs, 62 const TargetRegisterClass * const *superregcs, 63 unsigned RS, unsigned Al, int CC, bool Allocable, 64 iterator RB, iterator RE) 65 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 66 SubRegClasses(subregcs), SuperRegClasses(superregcs), 67 RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable), 68 RegsBegin(RB), RegsEnd(RE) { 69 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 70 RegSet.insert(*I); 71 } 72 virtual ~TargetRegisterClass() {} // Allow subclasses 73 74 /// getID() - Return the register class ID number. 75 /// 76 unsigned getID() const { return ID; } 77 78 /// getName() - Return the register class name for debugging. 79 /// 80 const char *getName() const { return Name; } 81 82 /// begin/end - Return all of the registers in this class. 83 /// 84 iterator begin() const { return RegsBegin; } 85 iterator end() const { return RegsEnd; } 86 87 /// getNumRegs - Return the number of registers in this class. 88 /// 89 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 90 91 /// getRegister - Return the specified register in the class. 92 /// 93 unsigned getRegister(unsigned i) const { 94 assert(i < getNumRegs() && "Register number out of range!"); 95 return RegsBegin[i]; 96 } 97 98 /// contains - Return true if the specified register is included in this 99 /// register class. This does not include virtual registers. 100 bool contains(unsigned Reg) const { 101 return RegSet.count(Reg); 102 } 103 104 /// contains - Return true if both registers are in this class. 105 bool contains(unsigned Reg1, unsigned Reg2) const { 106 return contains(Reg1) && contains(Reg2); 107 } 108 109 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 110 /// 111 bool hasType(EVT vt) const { 112 for(int i = 0; VTs[i] != MVT::Other; ++i) 113 if (VTs[i] == vt) 114 return true; 115 return false; 116 } 117 118 /// vt_begin / vt_end - Loop over all of the value types that can be 119 /// represented by values in this register class. 120 vt_iterator vt_begin() const { 121 return VTs; 122 } 123 124 vt_iterator vt_end() const { 125 vt_iterator I = VTs; 126 while (*I != MVT::Other) ++I; 127 return I; 128 } 129 130 /// subregclasses_begin / subregclasses_end - Loop over all of 131 /// the subreg register classes of this register class. 132 sc_iterator subregclasses_begin() const { 133 return SubRegClasses; 134 } 135 136 sc_iterator subregclasses_end() const { 137 sc_iterator I = SubRegClasses; 138 while (*I != NULL) ++I; 139 return I; 140 } 141 142 /// getSubRegisterRegClass - Return the register class of subregisters with 143 /// index SubIdx, or NULL if no such class exists. 144 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 145 assert(SubIdx>0 && "Invalid subregister index"); 146 return SubRegClasses[SubIdx-1]; 147 } 148 149 /// superregclasses_begin / superregclasses_end - Loop over all of 150 /// the superreg register classes of this register class. 151 sc_iterator superregclasses_begin() const { 152 return SuperRegClasses; 153 } 154 155 sc_iterator superregclasses_end() const { 156 sc_iterator I = SuperRegClasses; 157 while (*I != NULL) ++I; 158 return I; 159 } 160 161 /// hasSubClass - return true if the specified TargetRegisterClass 162 /// is a proper subset of this TargetRegisterClass. 163 bool hasSubClass(const TargetRegisterClass *cs) const { 164 for (int i = 0; SubClasses[i] != NULL; ++i) 165 if (SubClasses[i] == cs) 166 return true; 167 return false; 168 } 169 170 /// hasSubClassEq - Returns true if RC is a subclass of or equal to this 171 /// class. 172 bool hasSubClassEq(const TargetRegisterClass *RC) const { 173 return RC == this || hasSubClass(RC); 174 } 175 176 /// subclasses_begin / subclasses_end - Loop over all of the classes 177 /// that are proper subsets of this register class. 178 sc_iterator subclasses_begin() const { 179 return SubClasses; 180 } 181 182 sc_iterator subclasses_end() const { 183 sc_iterator I = SubClasses; 184 while (*I != NULL) ++I; 185 return I; 186 } 187 188 /// hasSuperClass - return true if the specified TargetRegisterClass is a 189 /// proper superset of this TargetRegisterClass. 190 bool hasSuperClass(const TargetRegisterClass *cs) const { 191 for (int i = 0; SuperClasses[i] != NULL; ++i) 192 if (SuperClasses[i] == cs) 193 return true; 194 return false; 195 } 196 197 /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this 198 /// class. 199 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 200 return RC == this || hasSuperClass(RC); 201 } 202 203 /// superclasses_begin / superclasses_end - Loop over all of the classes 204 /// that are proper supersets of this register class. 205 sc_iterator superclasses_begin() const { 206 return SuperClasses; 207 } 208 209 sc_iterator superclasses_end() const { 210 sc_iterator I = SuperClasses; 211 while (*I != NULL) ++I; 212 return I; 213 } 214 215 /// isASubClass - return true if this TargetRegisterClass is a subset 216 /// class of at least one other TargetRegisterClass. 217 bool isASubClass() const { 218 return SuperClasses[0] != 0; 219 } 220 221 /// getRawAllocationOrder - Returns the preferred order for allocating 222 /// registers from this register class in MF. The raw order comes directly 223 /// from the .td file and may include reserved registers that are not 224 /// allocatable. Register allocators should also make sure to allocate 225 /// callee-saved registers only after all the volatiles are used. The 226 /// RegisterClassInfo class provides filtered allocation orders with 227 /// callee-saved registers moved to the end. 228 /// 229 /// The MachineFunction argument can be used to tune the allocatable 230 /// registers based on the characteristics of the function, subtarget, or 231 /// other criteria. 232 /// 233 /// By default, this method returns all registers in the class. 234 /// 235 virtual 236 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 237 return ArrayRef<unsigned>(begin(), getNumRegs()); 238 } 239 240 /// getSize - Return the size of the register in bytes, which is also the size 241 /// of a stack slot allocated to hold a spilled copy of this register. 242 unsigned getSize() const { return RegSize; } 243 244 /// getAlignment - Return the minimum required alignment for a register of 245 /// this class. 246 unsigned getAlignment() const { return Alignment; } 247 248 /// getCopyCost - Return the cost of copying a value between two registers in 249 /// this class. A negative number means the register class is very expensive 250 /// to copy e.g. status flag register classes. 251 int getCopyCost() const { return CopyCost; } 252 253 /// isAllocatable - Return true if this register class may be used to create 254 /// virtual registers. 255 bool isAllocatable() const { return Allocatable; } 256}; 257 258/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 259/// registers. These are used by codegen, not by MC. 260struct TargetRegisterInfoDesc { 261 unsigned CostPerUse; // Extra cost of instructions using register. 262 bool inAllocatableClass; // Register belongs to an allocatable regclass. 263}; 264 265/// TargetRegisterInfo base class - We assume that the target defines a static 266/// array of TargetRegisterDesc objects that represent all of the machine 267/// registers that the target has. As such, we simply have to track a pointer 268/// to this array so that we can turn register number into a register 269/// descriptor. 270/// 271class TargetRegisterInfo : public MCRegisterInfo { 272public: 273 typedef const TargetRegisterClass * const * regclass_iterator; 274private: 275 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 276 const char *const *SubRegIndexNames; // Names of subreg indexes. 277 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 278 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 279 280protected: 281 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 282 regclass_iterator RegClassBegin, 283 regclass_iterator RegClassEnd, 284 const char *const *subregindexnames, 285 int CallFrameSetupOpcode = -1, 286 int CallFrameDestroyOpcode = -1); 287 virtual ~TargetRegisterInfo(); 288public: 289 290 // Register numbers can represent physical registers, virtual registers, and 291 // sometimes stack slots. The unsigned values are divided into these ranges: 292 // 293 // 0 Not a register, can be used as a sentinel. 294 // [1;2^30) Physical registers assigned by TableGen. 295 // [2^30;2^31) Stack slots. (Rarely used.) 296 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 297 // 298 // Further sentinels can be allocated from the small negative integers. 299 // DenseMapInfo<unsigned> uses -1u and -2u. 300 301 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 302 /// frame index in a variable that normally holds a register. isStackSlot() 303 /// returns true if Reg is in the range used for stack slots. 304 /// 305 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 306 /// slots, so if a variable may contains a stack slot, always check 307 /// isStackSlot() first. 308 /// 309 static bool isStackSlot(unsigned Reg) { 310 return int(Reg) >= (1 << 30); 311 } 312 313 /// stackSlot2Index - Compute the frame index from a register value 314 /// representing a stack slot. 315 static int stackSlot2Index(unsigned Reg) { 316 assert(isStackSlot(Reg) && "Not a stack slot"); 317 return int(Reg - (1u << 30)); 318 } 319 320 /// index2StackSlot - Convert a non-negative frame index to a stack slot 321 /// register value. 322 static unsigned index2StackSlot(int FI) { 323 assert(FI >= 0 && "Cannot hold a negative frame index."); 324 return FI + (1u << 30); 325 } 326 327 /// isPhysicalRegister - Return true if the specified register number is in 328 /// the physical register namespace. 329 static bool isPhysicalRegister(unsigned Reg) { 330 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 331 return int(Reg) > 0; 332 } 333 334 /// isVirtualRegister - Return true if the specified register number is in 335 /// the virtual register namespace. 336 static bool isVirtualRegister(unsigned Reg) { 337 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 338 return int(Reg) < 0; 339 } 340 341 /// virtReg2Index - Convert a virtual register number to a 0-based index. 342 /// The first virtual register in a function will get the index 0. 343 static unsigned virtReg2Index(unsigned Reg) { 344 assert(isVirtualRegister(Reg) && "Not a virtual register"); 345 return Reg & ~(1u << 31); 346 } 347 348 /// index2VirtReg - Convert a 0-based index to a virtual register number. 349 /// This is the inverse operation of VirtReg2IndexFunctor below. 350 static unsigned index2VirtReg(unsigned Index) { 351 return Index | (1u << 31); 352 } 353 354 /// getMinimalPhysRegClass - Returns the Register Class of a physical 355 /// register of the given type, picking the most sub register class of 356 /// the right type that contains this physreg. 357 const TargetRegisterClass * 358 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 359 360 /// getAllocatableSet - Returns a bitset indexed by register number 361 /// indicating if a register is allocatable or not. If a register class is 362 /// specified, returns the subset for the class. 363 BitVector getAllocatableSet(const MachineFunction &MF, 364 const TargetRegisterClass *RC = NULL) const; 365 366 /// getCostPerUse - Return the additional cost of using this register instead 367 /// of other registers in its class. 368 unsigned getCostPerUse(unsigned RegNo) const { 369 return InfoDesc[RegNo].CostPerUse; 370 } 371 372 /// isInAllocatableClass - Return true if the register is in the allocation 373 /// of any register class. 374 bool isInAllocatableClass(unsigned RegNo) const { 375 return InfoDesc[RegNo].inAllocatableClass; 376 } 377 378 /// getSubRegIndexName - Return the human-readable symbolic target-specific 379 /// name for the specified SubRegIndex. 380 const char *getSubRegIndexName(unsigned SubIdx) const { 381 assert(SubIdx && "This is not a subregister index"); 382 return SubRegIndexNames[SubIdx-1]; 383 } 384 385 /// regsOverlap - Returns true if the two registers are equal or alias each 386 /// other. The registers may be virtual register. 387 bool regsOverlap(unsigned regA, unsigned regB) const { 388 if (regA == regB) return true; 389 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 390 return false; 391 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 392 if (*regList == regB) return true; 393 } 394 return false; 395 } 396 397 /// isSubRegister - Returns true if regB is a sub-register of regA. 398 /// 399 bool isSubRegister(unsigned regA, unsigned regB) const { 400 return isSuperRegister(regB, regA); 401 } 402 403 /// isSuperRegister - Returns true if regB is a super-register of regA. 404 /// 405 bool isSuperRegister(unsigned regA, unsigned regB) const { 406 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 407 if (*regList == regB) return true; 408 } 409 return false; 410 } 411 412 /// getCalleeSavedRegs - Return a null-terminated list of all of the 413 /// callee saved registers on this target. The register should be in the 414 /// order of desired callee-save stack frame offset. The first register is 415 /// closed to the incoming stack pointer if stack grows down, and vice versa. 416 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 417 const = 0; 418 419 420 /// getReservedRegs - Returns a bitset indexed by physical register number 421 /// indicating if a register is a special register that has particular uses 422 /// and should be considered unavailable at all times, e.g. SP, RA. This is 423 /// used by register scavenger to determine what registers are free. 424 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 425 426 /// getSubReg - Returns the physical register number of sub-register "Index" 427 /// for physical register RegNo. Return zero if the sub-register does not 428 /// exist. 429 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 430 431 /// getSubRegIndex - For a given register pair, return the sub-register index 432 /// if the second register is a sub-register of the first. Return zero 433 /// otherwise. 434 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 435 436 /// getMatchingSuperReg - Return a super-register of the specified register 437 /// Reg so its sub-register of index SubIdx is Reg. 438 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 439 const TargetRegisterClass *RC) const { 440 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 441 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 442 return SR; 443 return 0; 444 } 445 446 /// canCombineSubRegIndices - Given a register class and a list of 447 /// subregister indices, return true if it's possible to combine the 448 /// subregister indices into one that corresponds to a larger 449 /// subregister. Return the new subregister index by reference. Note the 450 /// new index may be zero if the given subregisters can be combined to 451 /// form the whole register. 452 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 453 SmallVectorImpl<unsigned> &SubIndices, 454 unsigned &NewSubIdx) const { 455 return 0; 456 } 457 458 /// getMatchingSuperRegClass - Return a subclass of the specified register 459 /// class A so that each register in it has a sub-register of the 460 /// specified sub-register index which is in the specified register class B. 461 virtual const TargetRegisterClass * 462 getMatchingSuperRegClass(const TargetRegisterClass *A, 463 const TargetRegisterClass *B, unsigned Idx) const { 464 return 0; 465 } 466 467 /// composeSubRegIndices - Return the subregister index you get from composing 468 /// two subregister indices. 469 /// 470 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 471 /// returns c. Note that composeSubRegIndices does not tell you about illegal 472 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 473 /// b, composeSubRegIndices doesn't tell you. 474 /// 475 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 476 /// ssub_0:S0 - ssub_3:S3 subregs. 477 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 478 /// 479 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 480 // This default implementation is correct for most targets. 481 return b; 482 } 483 484 //===--------------------------------------------------------------------===// 485 // Register Class Information 486 // 487 488 /// Register class iterators 489 /// 490 regclass_iterator regclass_begin() const { return RegClassBegin; } 491 regclass_iterator regclass_end() const { return RegClassEnd; } 492 493 unsigned getNumRegClasses() const { 494 return (unsigned)(regclass_end()-regclass_begin()); 495 } 496 497 /// getRegClass - Returns the register class associated with the enumeration 498 /// value. See class MCOperandInfo. 499 const TargetRegisterClass *getRegClass(unsigned i) const { 500 assert(i < getNumRegClasses() && "Register Class ID out of range"); 501 return RegClassBegin[i]; 502 } 503 504 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 505 /// values. If a target supports multiple different pointer register classes, 506 /// kind specifies which one is indicated. 507 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 508 assert(0 && "Target didn't implement getPointerRegClass!"); 509 return 0; // Must return a value in order to compile with VS 2005 510 } 511 512 /// getCrossCopyRegClass - Returns a legal register class to copy a register 513 /// in the specified class to or from. If it is possible to copy the register 514 /// directly without using a cross register class copy, return the specified 515 /// RC. Returns NULL if it is not possible to copy between a two registers of 516 /// the specified class. 517 virtual const TargetRegisterClass * 518 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 519 return RC; 520 } 521 522 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 523 /// legal to use in the current sub-target and has the same spill size. 524 /// The returned register class can be used to create virtual registers which 525 /// means that all its registers can be copied and spilled. 526 virtual const TargetRegisterClass* 527 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 528 /// The default implementation is very conservative and doesn't allow the 529 /// register allocator to inflate register classes. 530 return RC; 531 } 532 533 /// getRegPressureLimit - Return the register pressure "high water mark" for 534 /// the specific register class. The scheduler is in high register pressure 535 /// mode (for the specific register class) if it goes over the limit. 536 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 537 MachineFunction &MF) const { 538 return 0; 539 } 540 541 /// getRawAllocationOrder - Returns the register allocation order for a 542 /// specified register class with a target-dependent hint. The returned list 543 /// may contain reserved registers that cannot be allocated. 544 /// 545 /// Register allocators need only call this function to resolve 546 /// target-dependent hints, but it should work without hinting as well. 547 virtual ArrayRef<unsigned> 548 getRawAllocationOrder(const TargetRegisterClass *RC, 549 unsigned HintType, unsigned HintReg, 550 const MachineFunction &MF) const { 551 return RC->getRawAllocationOrder(MF); 552 } 553 554 /// ResolveRegAllocHint - Resolves the specified register allocation hint 555 /// to a physical register. Returns the physical register if it is successful. 556 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 557 const MachineFunction &MF) const { 558 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 559 return Reg; 560 return 0; 561 } 562 563 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 564 /// writing a register from RC in two consecutive instructions. 565 /// This can avoid pipeline stalls on certain architectures. 566 /// It does cause increased register pressure, though. 567 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 568 return false; 569 } 570 571 /// UpdateRegAllocHint - A callback to allow target a chance to update 572 /// register allocation hints when a register is "changed" (e.g. coalesced) 573 /// to another register. e.g. On ARM, some virtual registers should target 574 /// register pairs, if one of pair is coalesced to another register, the 575 /// allocation hint of the other half of the pair should be changed to point 576 /// to the new register. 577 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 578 MachineFunction &MF) const { 579 // Do nothing. 580 } 581 582 /// requiresRegisterScavenging - returns true if the target requires (and can 583 /// make use of) the register scavenger. 584 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 585 return false; 586 } 587 588 /// useFPForScavengingIndex - returns true if the target wants to use 589 /// frame pointer based accesses to spill to the scavenger emergency spill 590 /// slot. 591 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 592 return true; 593 } 594 595 /// requiresFrameIndexScavenging - returns true if the target requires post 596 /// PEI scavenging of registers for materializing frame index constants. 597 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 598 return false; 599 } 600 601 /// requiresVirtualBaseRegisters - Returns true if the target wants the 602 /// LocalStackAllocation pass to be run and virtual base registers 603 /// used for more efficient stack access. 604 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 605 return false; 606 } 607 608 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 609 /// the stack frame of the given function for the specified register. e.g. On 610 /// x86, if the frame register is required, the first fixed stack object is 611 /// reserved as its spill slot. This tells PEI not to create a new stack frame 612 /// object for the given register. It should be called only after 613 /// processFunctionBeforeCalleeSavedScan(). 614 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 615 int &FrameIdx) const { 616 return false; 617 } 618 619 /// needsStackRealignment - true if storage within the function requires the 620 /// stack pointer to be aligned more than the normal calling convention calls 621 /// for. 622 virtual bool needsStackRealignment(const MachineFunction &MF) const { 623 return false; 624 } 625 626 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 627 /// index in the instruction, if there is one. 628 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 629 int Idx) const { 630 return 0; 631 } 632 633 /// needsFrameBaseReg - Returns true if the instruction's frame index 634 /// reference would be better served by a base register other than FP 635 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 636 /// references it should create new base registers for. 637 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 638 return false; 639 } 640 641 /// materializeFrameBaseRegister - Insert defining instruction(s) for 642 /// BaseReg to be a pointer to FrameIdx before insertion point I. 643 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 644 unsigned BaseReg, int FrameIdx, 645 int64_t Offset) const { 646 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 647 } 648 649 /// resolveFrameIndex - Resolve a frame index operand of an instruction 650 /// to reference the indicated base register plus offset instead. 651 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 652 unsigned BaseReg, int64_t Offset) const { 653 assert(0 && "resolveFrameIndex does not exist on this target"); 654 } 655 656 /// isFrameOffsetLegal - Determine whether a given offset immediate is 657 /// encodable to resolve a frame index. 658 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 659 int64_t Offset) const { 660 assert(0 && "isFrameOffsetLegal does not exist on this target"); 661 return false; // Must return a value in order to compile with VS 2005 662 } 663 664 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 665 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 666 /// targets use pseudo instructions in order to abstract away the difference 667 /// between operating with a frame pointer and operating without, through the 668 /// use of these two instructions. 669 /// 670 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 671 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 672 673 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 674 /// code insertion to eliminate call frame setup and destroy pseudo 675 /// instructions (but only if the Target is using them). It is responsible 676 /// for eliminating these instructions, replacing them with concrete 677 /// instructions. This method need only be implemented if using call frame 678 /// setup/destroy pseudo instructions. 679 /// 680 virtual void 681 eliminateCallFramePseudoInstr(MachineFunction &MF, 682 MachineBasicBlock &MBB, 683 MachineBasicBlock::iterator MI) const { 684 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 685 "eliminateCallFramePseudoInstr must be implemented if using" 686 " call frame setup/destroy pseudo instructions!"); 687 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 688 } 689 690 691 /// saveScavengerRegister - Spill the register so it can be used by the 692 /// register scavenger. Return true if the register was spilled, false 693 /// otherwise. If this function does not spill the register, the scavenger 694 /// will instead spill it to the emergency spill slot. 695 /// 696 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 697 MachineBasicBlock::iterator I, 698 MachineBasicBlock::iterator &UseMI, 699 const TargetRegisterClass *RC, 700 unsigned Reg) const { 701 return false; 702 } 703 704 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 705 /// frame indices from instructions which may use them. The instruction 706 /// referenced by the iterator contains an MO_FrameIndex operand which must be 707 /// eliminated by this method. This method may modify or replace the 708 /// specified instruction, as long as it keeps the iterator pointing at the 709 /// finished product. SPAdj is the SP adjustment due to call frame setup 710 /// instruction. 711 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 712 int SPAdj, RegScavenger *RS=NULL) const = 0; 713 714 //===--------------------------------------------------------------------===// 715 /// Debug information queries. 716 717 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 718 /// number. Returns -1 if there is no equivalent value. The second 719 /// parameter allows targets to use different numberings for EH info and 720 /// debugging info. 721 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 722 723 virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0; 724 725 /// getFrameRegister - This method should return the register used as a base 726 /// for values allocated in the current stack frame. 727 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 728 729 /// getRARegister - This method should return the register where the return 730 /// address can be found. 731 virtual unsigned getRARegister() const = 0; 732 733 /// getSEHRegNum - Map a target register to an equivalent SEH register 734 /// number. Returns -1 if there is no equivalent value. 735 virtual int getSEHRegNum(unsigned i) const { 736 return i; 737 } 738}; 739 740 741// This is useful when building IndexedMaps keyed on virtual registers 742struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 743 unsigned operator()(unsigned Reg) const { 744 return TargetRegisterInfo::virtReg2Index(Reg); 745 } 746}; 747 748/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 749/// if there is no common subclass. 750const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 751 const TargetRegisterClass *B); 752 753/// PrintReg - Helper class for printing registers on a raw_ostream. 754/// Prints virtual and physical registers with or without a TRI instance. 755/// 756/// The format is: 757/// %noreg - NoRegister 758/// %vreg5 - a virtual register. 759/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 760/// %EAX - a physical register 761/// %physreg17 - a physical register when no TRI instance given. 762/// 763/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 764/// 765class PrintReg { 766 const TargetRegisterInfo *TRI; 767 unsigned Reg; 768 unsigned SubIdx; 769public: 770 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 771 : TRI(tri), Reg(reg), SubIdx(subidx) {} 772 void print(raw_ostream&) const; 773}; 774 775static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 776 PR.print(OS); 777 return OS; 778} 779 780} // End llvm namespace 781 782#endif 783