DeadMachineInstructionElim.cpp revision 00a99a35840451a291eb61a192a750908a4073ae 
1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is an extremely simple MachineInstr-level dead-code-elimination pass.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "codegen-dce"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/Pass.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/ADT/Statistic.h"
24using namespace llvm;
25
26STATISTIC(NumDeletes,          "Number of dead instructions deleted");
27
28namespace {
29  class DeadMachineInstructionElim : public MachineFunctionPass {
30    virtual bool runOnMachineFunction(MachineFunction &MF);
31
32    const TargetRegisterInfo *TRI;
33    const MachineRegisterInfo *MRI;
34    const TargetInstrInfo *TII;
35    BitVector LivePhysRegs;
36
37  public:
38    static char ID; // Pass identification, replacement for typeid
39    DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
40
41  private:
42    bool isDead(const MachineInstr *MI) const;
43  };
44}
45char DeadMachineInstructionElim::ID = 0;
46
47static RegisterPass<DeadMachineInstructionElim>
48Y("dead-mi-elimination",
49  "Remove dead machine instructions");
50
51FunctionPass *llvm::createDeadMachineInstructionElimPass() {
52  return new DeadMachineInstructionElim();
53}
54
55bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
56  // Don't delete instructions with side effects.
57  bool SawStore = false;
58  if (!MI->isSafeToMove(TII, SawStore, 0))
59    return false;
60
61  // Examine each operand.
62  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
63    const MachineOperand &MO = MI->getOperand(i);
64    if (MO.isReg() && MO.isDef()) {
65      unsigned Reg = MO.getReg();
66      if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
67          LivePhysRegs[Reg] : !MRI->use_empty(Reg)) {
68        // This def has a use. Don't delete the instruction!
69        return false;
70      }
71    }
72  }
73
74  // If there are no defs with uses, the instruction is dead.
75  return true;
76}
77
78bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
79  bool AnyChanges = false;
80  MRI = &MF.getRegInfo();
81  TRI = MF.getTarget().getRegisterInfo();
82  TII = MF.getTarget().getInstrInfo();
83
84  // Compute a bitvector to represent all non-allocatable physregs.
85  BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
86  NonAllocatableRegs.flip();
87
88  // Loop over all instructions in all blocks, from bottom to top, so that it's
89  // more likely that chains of dependent but ultimately dead instructions will
90  // be cleaned up.
91  for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
92       I != E; ++I) {
93    MachineBasicBlock *MBB = &*I;
94
95    // Start out assuming that all non-allocatable registers are live
96    // out of this block.
97    LivePhysRegs = NonAllocatableRegs;
98
99    // Also add any explicit live-out physregs for this block.
100    if (!MBB->empty() && MBB->back().getDesc().isReturn())
101      for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
102           LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
103        unsigned Reg = *LOI;
104        if (TargetRegisterInfo::isPhysicalRegister(Reg))
105          LivePhysRegs.set(Reg);
106      }
107
108    // Now scan the instructions and delete dead ones, tracking physreg
109    // liveness as we go.
110    for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
111         MIE = MBB->rend(); MII != MIE; ) {
112      MachineInstr *MI = &*MII;
113
114      if (MI->getOpcode()==TargetInstrInfo::DEBUG_VALUE) {
115        // Don't delete the DEBUG_VALUE itself, but if its Value operand is
116        // a vreg and this is the only use, substitute an undef operand;
117        // the former operand will then be deleted normally.
118        if (MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
119          unsigned Reg = MI->getOperand(0).getReg();
120          MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
121          assert(I != MRI->use_end());
122          if (++I == MRI->use_end())
123            // only one use, which must be this DEBUG_VALUE.
124            MI->getOperand(0).setReg(0U);
125        }
126      }
127
128      // If the instruction is dead, delete it!
129      if (isDead(MI)) {
130        DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
131        AnyChanges = true;
132        MI->eraseFromParent();
133        ++NumDeletes;
134        MIE = MBB->rend();
135        // MII is now pointing to the next instruction to process,
136        // so don't increment it.
137        continue;
138      }
139
140      // Record the physreg defs.
141      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
142        const MachineOperand &MO = MI->getOperand(i);
143        if (MO.isReg() && MO.isDef()) {
144          unsigned Reg = MO.getReg();
145          if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
146            LivePhysRegs.reset(Reg);
147            // Check the subreg set, not the alias set, because a def
148            // of a super-register may still be partially live after
149            // this def.
150            for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
151                 *SubRegs; ++SubRegs)
152              LivePhysRegs.reset(*SubRegs);
153          }
154        }
155      }
156      // Record the physreg uses, after the defs, in case a physreg is
157      // both defined and used in the same instruction.
158      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
159        const MachineOperand &MO = MI->getOperand(i);
160        if (MO.isReg() && MO.isUse()) {
161          unsigned Reg = MO.getReg();
162          if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
163            LivePhysRegs.set(Reg);
164            for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
165                 *AliasSet; ++AliasSet)
166              LivePhysRegs.set(*AliasSet);
167          }
168        }
169      }
170
171      // We didn't delete the current instruction, so increment MII to
172      // the next one.
173      ++MII;
174    }
175  }
176
177  LivePhysRegs.clear();
178  return AnyChanges;
179}
180