DeadMachineInstructionElim.cpp revision 478a8a02bc0f2e739ed8f4240152e99837e480b9 
1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is an extremely simple MachineInstr-level dead-code-elimination pass.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "codegen-dce"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/Pass.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/ADT/Statistic.h"
24using namespace llvm;
25
26STATISTIC(NumDeletes,          "Number of dead instructions deleted");
27
28namespace {
29  class DeadMachineInstructionElim : public MachineFunctionPass {
30    virtual bool runOnMachineFunction(MachineFunction &MF);
31
32    const TargetRegisterInfo *TRI;
33    const MachineRegisterInfo *MRI;
34    const TargetInstrInfo *TII;
35    BitVector LivePhysRegs;
36
37  public:
38    static char ID; // Pass identification, replacement for typeid
39    DeadMachineInstructionElim() : MachineFunctionPass(ID) {
40     initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
41    }
42
43  private:
44    bool isDead(const MachineInstr *MI) const;
45  };
46}
47char DeadMachineInstructionElim::ID = 0;
48
49INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
50                "Remove dead machine instructions", false, false)
51
52FunctionPass *llvm::createDeadMachineInstructionElimPass() {
53  return new DeadMachineInstructionElim();
54}
55
56bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
57  // Technically speaking inline asm without side effects and no defs can still
58  // be deleted. But there is so much bad inline asm code out there, we should
59  // let them be.
60  if (MI->isInlineAsm())
61    return false;
62
63  // Don't delete instructions with side effects.
64  bool SawStore = false;
65  if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
66    return false;
67
68  // Examine each operand.
69  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
70    const MachineOperand &MO = MI->getOperand(i);
71    if (MO.isReg() && MO.isDef()) {
72      unsigned Reg = MO.getReg();
73      if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
74          LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
75        // This def has a non-debug use. Don't delete the instruction!
76        return false;
77      }
78    }
79  }
80
81  // If there are no defs with uses, the instruction is dead.
82  return true;
83}
84
85bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
86  bool AnyChanges = false;
87  MRI = &MF.getRegInfo();
88  TRI = MF.getTarget().getRegisterInfo();
89  TII = MF.getTarget().getInstrInfo();
90
91  // Treat reserved registers as always live.
92  BitVector ReservedRegs = TRI->getReservedRegs(MF);
93
94  // Loop over all instructions in all blocks, from bottom to top, so that it's
95  // more likely that chains of dependent but ultimately dead instructions will
96  // be cleaned up.
97  for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
98       I != E; ++I) {
99    MachineBasicBlock *MBB = &*I;
100
101    // Start out assuming that reserved registers are live out of this block.
102    LivePhysRegs = ReservedRegs;
103
104    // Also add any explicit live-out physregs for this block.
105    if (!MBB->empty() && MBB->back().isReturn())
106      for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
107           LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
108        unsigned Reg = *LOI;
109        if (TargetRegisterInfo::isPhysicalRegister(Reg))
110          LivePhysRegs.set(Reg);
111      }
112
113    // Add live-ins from sucessors to LivePhysRegs. Normally, physregs are not
114    // live across blocks, but some targets (x86) can have flags live out of a
115    // block.
116    for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(),
117           E = MBB->succ_end(); S != E; S++)
118      for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
119           LI != (*S)->livein_end(); LI++)
120        LivePhysRegs.set(*LI);
121
122    // Now scan the instructions and delete dead ones, tracking physreg
123    // liveness as we go.
124    for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
125         MIE = MBB->rend(); MII != MIE; ) {
126      MachineInstr *MI = &*MII;
127
128      // If the instruction is dead, delete it!
129      if (isDead(MI)) {
130        DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
131        // It is possible that some DBG_VALUE instructions refer to this
132        // instruction.  Examine each def operand for such references;
133        // if found, mark the DBG_VALUE as undef (but don't delete it).
134        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
135          const MachineOperand &MO = MI->getOperand(i);
136          if (!MO.isReg() || !MO.isDef())
137            continue;
138          unsigned Reg = MO.getReg();
139          if (!TargetRegisterInfo::isVirtualRegister(Reg))
140            continue;
141          MachineRegisterInfo::use_iterator nextI;
142          for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
143               E = MRI->use_end(); I!=E; I=nextI) {
144            nextI = llvm::next(I);  // I is invalidated by the setReg
145            MachineOperand& Use = I.getOperand();
146            MachineInstr *UseMI = Use.getParent();
147            if (UseMI==MI)
148              continue;
149            assert(Use.isDebug());
150            UseMI->getOperand(0).setReg(0U);
151          }
152        }
153        AnyChanges = true;
154        MI->eraseFromParent();
155        ++NumDeletes;
156        MIE = MBB->rend();
157        // MII is now pointing to the next instruction to process,
158        // so don't increment it.
159        continue;
160      }
161
162      // Record the physreg defs.
163      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
164        const MachineOperand &MO = MI->getOperand(i);
165        if (MO.isReg() && MO.isDef()) {
166          unsigned Reg = MO.getReg();
167          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
168            LivePhysRegs.reset(Reg);
169            // Check the subreg set, not the alias set, because a def
170            // of a super-register may still be partially live after
171            // this def.
172            for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
173                 *SubRegs; ++SubRegs)
174              LivePhysRegs.reset(*SubRegs);
175          }
176        } else if (MO.isRegMask()) {
177          // Register mask of preserved registers. All clobbers are dead.
178          LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
179          LivePhysRegs |= ReservedRegs;
180        }
181      }
182      // Record the physreg uses, after the defs, in case a physreg is
183      // both defined and used in the same instruction.
184      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
185        const MachineOperand &MO = MI->getOperand(i);
186        if (MO.isReg() && MO.isUse()) {
187          unsigned Reg = MO.getReg();
188          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
189            LivePhysRegs.set(Reg);
190            for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
191                 *AliasSet; ++AliasSet)
192              LivePhysRegs.set(*AliasSet);
193          }
194        }
195      }
196
197      // We didn't delete the current instruction, so increment MII to
198      // the next one.
199      ++MII;
200    }
201  }
202
203  LivePhysRegs.clear();
204  return AnyChanges;
205}
206