LiveStackAnalysis.cpp revision 86f6afb2fcf72c987aa2cfc01f5b4044dda349bd 
1//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "livestacks"
17#include "llvm/CodeGen/LiveStackAnalysis.h"
18#include "llvm/CodeGen/LiveIntervalAnalysis.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/ADT/Statistic.h"
23#include <limits>
24using namespace llvm;
25
26char LiveStacks::ID = 0;
27static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
28
29void LiveStacks::scaleNumbering(int factor) {
30  // Scale the intervals.
31  for (iterator LI = begin(), LE = end(); LI != LE; ++LI) {
32    LI->second.scaleNumbering(factor);
33  }
34}
35
36void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
37  AU.setPreservesAll();
38  MachineFunctionPass::getAnalysisUsage(AU);
39}
40
41void LiveStacks::releaseMemory() {
42  // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
43  VNInfoAllocator.Reset();
44  S2IMap.clear();
45  S2RCMap.clear();
46}
47
48bool LiveStacks::runOnMachineFunction(MachineFunction &) {
49  // FIXME: No analysis is being done right now. We are relying on the
50  // register allocators to provide the information.
51  return false;
52}
53
54/// print - Implement the dump method.
55void LiveStacks::print(std::ostream &O, const Module*) const {
56  O << "********** INTERVALS **********\n";
57  for (const_iterator I = begin(), E = end(); I != E; ++I) {
58    I->second.print(O);
59    int Slot = I->first;
60    const TargetRegisterClass *RC = getIntervalRegClass(Slot);
61    if (RC)
62      O << " [" << RC->getName() << "]\n";
63    else
64      O << " [Unknown]\n";
65  }
66}
67