LiveStackAnalysis.cpp revision 991de14dd62dcbab4b31357ae22dc5b053ba50a0 
1//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "livestacks"
17#include "llvm/CodeGen/LiveStackAnalysis.h"
18#include "llvm/CodeGen/LiveIntervalAnalysis.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/ADT/Statistic.h"
24#include <limits>
25using namespace llvm;
26
27char LiveStacks::ID = 0;
28static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
29
30void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
31  AU.setPreservesAll();
32  AU.addPreserved<SlotIndexes>();
33  AU.addRequiredTransitive<SlotIndexes>();
34  MachineFunctionPass::getAnalysisUsage(AU);
35}
36
37void LiveStacks::releaseMemory() {
38  // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
39  VNInfoAllocator.DestroyAll();
40  S2IMap.clear();
41  S2RCMap.clear();
42}
43
44bool LiveStacks::runOnMachineFunction(MachineFunction &) {
45  // FIXME: No analysis is being done right now. We are relying on the
46  // register allocators to provide the information.
47  return false;
48}
49
50/// print - Implement the dump method.
51void LiveStacks::print(raw_ostream &OS, const Module*) const {
52
53  OS << "********** INTERVALS **********\n";
54  for (const_iterator I = begin(), E = end(); I != E; ++I) {
55    I->second.print(OS);
56    int Slot = I->first;
57    const TargetRegisterClass *RC = getIntervalRegClass(Slot);
58    if (RC)
59      OS << " [" << RC->getName() << "]\n";
60    else
61      OS << " [Unknown]\n";
62  }
63}
64