LiveStackAnalysis.cpp revision ce665bd2e2b581ab0858d1afe359192bac96b868 
1//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "livestacks"
17#include "llvm/CodeGen/LiveStackAnalysis.h"
18#include "llvm/CodeGen/LiveIntervalAnalysis.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/ADT/Statistic.h"
24#include <limits>
25using namespace llvm;
26
27char LiveStacks::ID = 0;
28INITIALIZE_PASS(LiveStacks, "livestacks",
29                "Live Stack Slot Analysis", false, false)
30
31void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
32  AU.setPreservesAll();
33  AU.addPreserved<SlotIndexes>();
34  AU.addRequiredTransitive<SlotIndexes>();
35  MachineFunctionPass::getAnalysisUsage(AU);
36}
37
38void LiveStacks::releaseMemory() {
39  // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
40  VNInfoAllocator.Reset();
41  S2IMap.clear();
42  S2RCMap.clear();
43}
44
45bool LiveStacks::runOnMachineFunction(MachineFunction &) {
46  // FIXME: No analysis is being done right now. We are relying on the
47  // register allocators to provide the information.
48  return false;
49}
50
51/// print - Implement the dump method.
52void LiveStacks::print(raw_ostream &OS, const Module*) const {
53
54  OS << "********** INTERVALS **********\n";
55  for (const_iterator I = begin(), E = end(); I != E; ++I) {
56    I->second.print(OS);
57    int Slot = I->first;
58    const TargetRegisterClass *RC = getIntervalRegClass(Slot);
59    if (RC)
60      OS << " [" << RC->getName() << "]\n";
61    else
62      OS << " [Unknown]\n";
63  }
64}
65