MachineRegisterInfo.cpp revision fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cd
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 17f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/Support/CommandLine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 206f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 23a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()]; 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 3503bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4071f095b20a2b1710d35b81fced4ae8b2ca1a6f61Dan Gohman delete [] RegClass2VRegMap; 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman unsigned VR = Reg; 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman assert(Reg < VRegInfo.size() && "Invalid vreg!"); 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 5133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 5233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Remove from old register class's vregs list. This may be slow but 5433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // fortunately this operation is rarely needed. 5533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 56a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR); 5733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegs.erase(I); 5833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Add to new register class's vregs list. 6033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman RegClass2VRegMap[RC->getID()].push_back(VR); 6133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 6233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 632e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 642e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 652e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 662e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 672e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 682e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 692e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 702e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 712e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 72358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng RegAllocHints.push_back(std::make_pair(0, 0)); 732e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 742e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 752e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 762e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 772e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned VR = getLastVirtReg(); 782e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman RegClass2VRegMap[RegClass->getID()].push_back(VR); 792e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman return VR; 802e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 812e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 8462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 8562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 8662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 8762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 8862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 8962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *List = VRegInfo[i].second; 9062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 9162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 9262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner List->Contents.Reg.Prev = &VRegInfo[i].second; 9362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 9484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 95a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 96e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 97e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 98e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 99e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 100e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 101e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 102e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 103e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 104e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 105e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 106e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 107e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 108e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 109e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 110a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 111a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 112a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 113a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 114a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1156f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 116a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner "Invalid vreg!"); 1172bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 1182bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman if (!def_empty(Reg)) 1192bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman return &*def_begin(Reg); 120a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 121a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1221eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1231423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1241423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_iterator UI = use_begin(RegNo); 1251423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_end()) 1261423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1271423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_end(); 1281423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1291423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 1301423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 1311423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1321423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 1331423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1341423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 1351423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1361eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 13749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 13849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 13949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 14049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 14149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 14249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 14349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 14449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 14549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 14613e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 14713e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 14813e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 14913e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 15013e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 15113e73f483ef2ba630962dad3125393292533b756Dan Gohman} 15213e73f483ef2ba630962dad3125393292533b756Dan Gohman 15313e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 15413e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 15513e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 15613e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 15713e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 15813e73f483ef2ba630962dad3125393292533b756Dan Gohman} 15913e73f483ef2ba630962dad3125393292533b756Dan Gohman 1602ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 1612ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 1622ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 1632ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1642ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 1652ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 1662ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 1672ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 1682ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 1693946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 1703946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 1713946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 1723946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1733946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 1743946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 1753946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 1763946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 1773946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 17898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 17998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 18098708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 18198708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 18298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 18398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 184701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 185fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 186fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 187fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 188fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 189fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 190fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 191fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 192fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 193fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 194fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 195fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 196fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 197fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman const TargetRegisterClass *RC = getRegClass(LiveIns[i].second); 198fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 199fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns[i].second, LiveIns[i].first, 200fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman RC, RC, DebugLoc()); 201fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 202fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman (void) Emitted; 203fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 204fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 205fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 206fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 207fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 208fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 209fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 210701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 21198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 21298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 21382b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesenvoid MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 21482b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (int i = UsedPhysRegs.find_first(); i >= 0; 21582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen i = UsedPhysRegs.find_next(i)) 21682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (const unsigned *SS = TRI.getSubRegisters(i); 21782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen unsigned SubReg = *SS; ++SS) 2188e8b3cb9371e60b22d1f401ec63a774c6115e98dJakob Stoklund Olesen if (SubReg > unsigned(i)) 21982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen UsedPhysRegs.set(SubReg); 22082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen} 22182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 2221eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2231eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2241eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2251eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 2261eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 2271eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 228