MachineVerifier.cpp revision 005975c04c5ffc4ee07107ad60dd7d465464e6f7
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Pass to verify generated machine code. The following is checked: 11// 12// Operand counts: All explicit operands must be present. 13// 14// Register classes: All physical and virtual register operands must be 15// compatible with the register class required by the instruction descriptor. 16// 17// Register live intervals: Registers must be defined only once, and must be 18// defined before use. 19// 20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21// command-line option -verify-machineinstrs, or by defining the environment 22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23// the verifier errors. 24//===----------------------------------------------------------------------===// 25 26#include "llvm/ADT/DenseSet.h" 27#include "llvm/ADT/SetOperations.h" 28#include "llvm/ADT/SmallVector.h" 29#include "llvm/Function.h" 30#include "llvm/CodeGen/LiveVariables.h" 31#include "llvm/CodeGen/MachineFunctionPass.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/Target/TargetMachine.h" 35#include "llvm/Target/TargetRegisterInfo.h" 36#include "llvm/Target/TargetInstrInfo.h" 37#include "llvm/Support/Compiler.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/ErrorHandling.h" 40#include "llvm/Support/raw_ostream.h" 41#include <fstream> 42 43using namespace llvm; 44 45namespace { 46 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass { 47 static char ID; // Pass ID, replacement for typeid 48 49 MachineVerifier(bool allowDoubleDefs = false) : 50 MachineFunctionPass(&ID), 51 allowVirtDoubleDefs(allowDoubleDefs), 52 allowPhysDoubleDefs(allowDoubleDefs), 53 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 54 {} 55 56 void getAnalysisUsage(AnalysisUsage &AU) const { 57 AU.setPreservesAll(); 58 } 59 60 bool runOnMachineFunction(MachineFunction &MF); 61 62 const bool allowVirtDoubleDefs; 63 const bool allowPhysDoubleDefs; 64 65 const char *const OutFileName; 66 std::ostream *OS; 67 const MachineFunction *MF; 68 const TargetMachine *TM; 69 const TargetRegisterInfo *TRI; 70 const MachineRegisterInfo *MRI; 71 72 unsigned foundErrors; 73 74 typedef SmallVector<unsigned, 16> RegVector; 75 typedef DenseSet<unsigned> RegSet; 76 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 77 78 BitVector regsReserved; 79 RegSet regsLive; 80 RegVector regsDefined, regsImpDefined, regsDead, regsKilled; 81 82 // Add Reg and any sub-registers to RV 83 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 84 RV.push_back(Reg); 85 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 86 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) 87 RV.push_back(*R); 88 } 89 90 // Does RS contain any super-registers of Reg? 91 bool anySuperRegisters(const RegSet &RS, unsigned Reg) { 92 for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++) 93 if (RS.count(*R)) 94 return true; 95 return false; 96 } 97 98 struct BBInfo { 99 // Is this MBB reachable from the MF entry point? 100 bool reachable; 101 102 // Vregs that must be live in because they are used without being 103 // defined. Map value is the user. 104 RegMap vregsLiveIn; 105 106 // Vregs that must be dead in because they are defined without being 107 // killed first. Map value is the defining instruction. 108 RegMap vregsDeadIn; 109 110 // Regs killed in MBB. They may be defined again, and will then be in both 111 // regsKilled and regsLiveOut. 112 RegSet regsKilled; 113 114 // Regs defined in MBB and live out. Note that vregs passing through may 115 // be live out without being mentioned here. 116 RegSet regsLiveOut; 117 118 // Vregs that pass through MBB untouched. This set is disjoint from 119 // regsKilled and regsLiveOut. 120 RegSet vregsPassed; 121 122 BBInfo() : reachable(false) {} 123 124 // Add register to vregsPassed if it belongs there. Return true if 125 // anything changed. 126 bool addPassed(unsigned Reg) { 127 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 128 return false; 129 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 130 return false; 131 return vregsPassed.insert(Reg).second; 132 } 133 134 // Same for a full set. 135 bool addPassed(const RegSet &RS) { 136 bool changed = false; 137 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 138 if (addPassed(*I)) 139 changed = true; 140 return changed; 141 } 142 143 // Live-out registers are either in regsLiveOut or vregsPassed. 144 bool isLiveOut(unsigned Reg) const { 145 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 146 } 147 }; 148 149 // Extra register info per MBB. 150 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 151 152 bool isReserved(unsigned Reg) { 153 return Reg < regsReserved.size() && regsReserved[Reg]; 154 } 155 156 void visitMachineFunctionBefore(); 157 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 158 void visitMachineInstrBefore(const MachineInstr *MI); 159 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 160 void visitMachineInstrAfter(const MachineInstr *MI); 161 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 162 void visitMachineFunctionAfter(); 163 164 void report(const char *msg, const MachineFunction *MF); 165 void report(const char *msg, const MachineBasicBlock *MBB); 166 void report(const char *msg, const MachineInstr *MI); 167 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 168 169 void markReachable(const MachineBasicBlock *MBB); 170 void calcMaxRegsPassed(); 171 void calcMinRegsPassed(); 172 void checkPHIOps(const MachineBasicBlock *MBB); 173 }; 174} 175 176char MachineVerifier::ID = 0; 177static RegisterPass<MachineVerifier> 178MachineVer("machineverifier", "Verify generated machine code"); 179static const PassInfo *const MachineVerifyID = &MachineVer; 180 181FunctionPass * 182llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) 183{ 184 return new MachineVerifier(allowPhysDoubleDefs); 185} 186 187bool 188MachineVerifier::runOnMachineFunction(MachineFunction &MF) 189{ 190 std::ofstream OutFile; 191 if (OutFileName) { 192 OutFile.open(OutFileName, std::ios::out | std::ios::app); 193 OS = &OutFile; 194 } else { 195 OS = cerr.stream(); 196 } 197 198 foundErrors = 0; 199 200 this->MF = &MF; 201 TM = &MF.getTarget(); 202 TRI = TM->getRegisterInfo(); 203 MRI = &MF.getRegInfo(); 204 205 visitMachineFunctionBefore(); 206 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 207 MFI!=MFE; ++MFI) { 208 visitMachineBasicBlockBefore(MFI); 209 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(), 210 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) { 211 visitMachineInstrBefore(MBBI); 212 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 213 visitMachineOperand(&MBBI->getOperand(I), I); 214 visitMachineInstrAfter(MBBI); 215 } 216 visitMachineBasicBlockAfter(MFI); 217 } 218 visitMachineFunctionAfter(); 219 220 if (OutFileName) 221 OutFile.close(); 222 else if (foundErrors) { 223 std::string msg; 224 raw_string_ostream Msg(msg); 225 Msg << "Found " << foundErrors << " machine code errors."; 226 llvm_report_error(Msg.str()); 227 } 228 229 return false; // no changes 230} 231 232void 233MachineVerifier::report(const char *msg, const MachineFunction *MF) 234{ 235 assert(MF); 236 *OS << "\n"; 237 if (!foundErrors++) 238 MF->print(OS); 239 *OS << "*** Bad machine code: " << msg << " ***\n" 240 << "- function: " << MF->getFunction()->getNameStr() << "\n"; 241} 242 243void 244MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) 245{ 246 assert(MBB); 247 report(msg, MBB->getParent()); 248 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr() 249 << " " << (void*)MBB 250 << " (#" << MBB->getNumber() << ")\n"; 251} 252 253void 254MachineVerifier::report(const char *msg, const MachineInstr *MI) 255{ 256 assert(MI); 257 report(msg, MI->getParent()); 258 *OS << "- instruction: "; 259 MI->print(OS, TM); 260} 261 262void 263MachineVerifier::report(const char *msg, 264 const MachineOperand *MO, unsigned MONum) 265{ 266 assert(MO); 267 report(msg, MO->getParent()); 268 *OS << "- operand " << MONum << ": "; 269 MO->print(*OS, TM); 270 *OS << "\n"; 271} 272 273void 274MachineVerifier::markReachable(const MachineBasicBlock *MBB) 275{ 276 BBInfo &MInfo = MBBInfoMap[MBB]; 277 if (!MInfo.reachable) { 278 MInfo.reachable = true; 279 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 280 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 281 markReachable(*SuI); 282 } 283} 284 285void 286MachineVerifier::visitMachineFunctionBefore() 287{ 288 regsReserved = TRI->getReservedRegs(*MF); 289 markReachable(&MF->front()); 290} 291 292void 293MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) 294{ 295 regsLive.clear(); 296 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), 297 E = MBB->livein_end(); I != E; ++I) { 298 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 299 report("MBB live-in list contains non-physical register", MBB); 300 continue; 301 } 302 regsLive.insert(*I); 303 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++) 304 regsLive.insert(*R); 305 } 306 regsKilled.clear(); 307 regsDefined.clear(); 308 regsImpDefined.clear(); 309} 310 311void 312MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) 313{ 314 const TargetInstrDesc &TI = MI->getDesc(); 315 if (MI->getNumExplicitOperands() < TI.getNumOperands()) { 316 report("Too few operands", MI); 317 *OS << TI.getNumOperands() << " operands expected, but " 318 << MI->getNumExplicitOperands() << " given.\n"; 319 } 320 if (!TI.isVariadic()) { 321 if (MI->getNumExplicitOperands() > TI.getNumOperands()) { 322 report("Too many operands", MI); 323 *OS << TI.getNumOperands() << " operands expected, but " 324 << MI->getNumExplicitOperands() << " given.\n"; 325 } 326 } 327} 328 329void 330MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) 331{ 332 const MachineInstr *MI = MO->getParent(); 333 const TargetInstrDesc &TI = MI->getDesc(); 334 335 // The first TI.NumDefs operands must be explicit register defines 336 if (MONum < TI.getNumDefs()) { 337 if (!MO->isReg()) 338 report("Explicit definition must be a register", MO, MONum); 339 else if (!MO->isDef()) 340 report("Explicit definition marked as use", MO, MONum); 341 else if (MO->isImplicit()) 342 report("Explicit definition marked as implicit", MO, MONum); 343 } 344 345 switch (MO->getType()) { 346 case MachineOperand::MO_Register: { 347 const unsigned Reg = MO->getReg(); 348 if (!Reg) 349 return; 350 351 // Check Live Variables. 352 if (MO->isUse()) { 353 if (MO->isKill()) { 354 addRegWithSubRegs(regsKilled, Reg); 355 // Tied operands on two-address instuctions MUST NOT have a <kill> flag. 356 if (MI->isRegTiedToDefOperand(MONum)) 357 report("Illegal kill flag on two-address instruction operand", 358 MO, MONum); 359 } else { 360 // TwoAddress instr modifying a reg is treated as kill+def. 361 unsigned defIdx; 362 if (MI->isRegTiedToDefOperand(MONum, &defIdx) && 363 MI->getOperand(defIdx).getReg() == Reg) 364 addRegWithSubRegs(regsKilled, Reg); 365 } 366 // Explicit use of a dead register. 367 if (!MO->isImplicit() && !regsLive.count(Reg)) { 368 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 369 // Reserved registers may be used even when 'dead'. 370 if (!isReserved(Reg)) 371 report("Using an undefined physical register", MO, MONum); 372 } else { 373 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 374 // We don't know which virtual registers are live in, so only complain 375 // if vreg was killed in this MBB. Otherwise keep track of vregs that 376 // must be live in. PHI instructions are handled separately. 377 if (MInfo.regsKilled.count(Reg)) 378 report("Using a killed virtual register", MO, MONum); 379 else if (MI->getOpcode() != TargetInstrInfo::PHI) 380 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 381 } 382 } 383 } else { 384 // Register defined. 385 // TODO: verify that earlyclobber ops are not used. 386 if (MO->isImplicit()) 387 addRegWithSubRegs(regsImpDefined, Reg); 388 else 389 addRegWithSubRegs(regsDefined, Reg); 390 391 if (MO->isDead()) 392 addRegWithSubRegs(regsDead, Reg); 393 } 394 395 // Check register classes. 396 if (MONum < TI.getNumOperands() && !MO->isImplicit()) { 397 const TargetOperandInfo &TOI = TI.OpInfo[MONum]; 398 unsigned SubIdx = MO->getSubReg(); 399 400 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 401 unsigned sr = Reg; 402 if (SubIdx) { 403 unsigned s = TRI->getSubReg(Reg, SubIdx); 404 if (!s) { 405 report("Invalid subregister index for physical register", 406 MO, MONum); 407 return; 408 } 409 sr = s; 410 } 411 if (TOI.RegClass) { 412 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass); 413 if (!DRC->contains(sr)) { 414 report("Illegal physical register for instruction", MO, MONum); 415 *OS << TRI->getName(sr) << " is not a " 416 << DRC->getName() << " register.\n"; 417 } 418 } 419 } else { 420 // Virtual register. 421 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 422 if (SubIdx) { 423 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) { 424 report("Invalid subregister index for virtual register", MO, MONum); 425 return; 426 } 427 RC = *(RC->subregclasses_begin()+SubIdx); 428 } 429 if (TOI.RegClass) { 430 const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass); 431 if (RC != DRC && !RC->hasSuperClass(DRC)) { 432 report("Illegal virtual register for instruction", MO, MONum); 433 *OS << "Expected a " << DRC->getName() << " register, but got a " 434 << RC->getName() << " register\n"; 435 } 436 } 437 } 438 } 439 break; 440 } 441 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do. 442 // case MachineOperand::MO_MachineBasicBlock: 443 // if (MI->getOpcode() == TargetInstrInfo::PHI) { 444 // if (!MO->getMBB()->isSuccessor(MI->getParent())) 445 // report("PHI operand is not in the CFG", MO, MONum); 446 // } 447 // break; 448 default: 449 break; 450 } 451} 452 453void 454MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) 455{ 456 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 457 set_union(MInfo.regsKilled, regsKilled); 458 set_subtract(regsLive, regsKilled); 459 regsKilled.clear(); 460 461 for (RegVector::const_iterator I = regsDefined.begin(), 462 E = regsDefined.end(); I != E; ++I) { 463 if (regsLive.count(*I)) { 464 if (TargetRegisterInfo::isPhysicalRegister(*I)) { 465 // We allow double defines to physical registers with live 466 // super-registers. 467 if (!allowPhysDoubleDefs && !isReserved(*I) && 468 !anySuperRegisters(regsLive, *I)) { 469 report("Redefining a live physical register", MI); 470 *OS << "Register " << TRI->getName(*I) 471 << " was defined but already live.\n"; 472 } 473 } else { 474 if (!allowVirtDoubleDefs) { 475 report("Redefining a live virtual register", MI); 476 *OS << "Virtual register %reg" << *I 477 << " was defined but already live.\n"; 478 } 479 } 480 } else if (TargetRegisterInfo::isVirtualRegister(*I) && 481 !MInfo.regsKilled.count(*I)) { 482 // Virtual register defined without being killed first must be dead on 483 // entry. 484 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI)); 485 } 486 } 487 488 set_union(regsLive, regsDefined); regsDefined.clear(); 489 set_union(regsLive, regsImpDefined); regsImpDefined.clear(); 490 set_subtract(regsLive, regsDead); regsDead.clear(); 491} 492 493void 494MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) 495{ 496 MBBInfoMap[MBB].regsLiveOut = regsLive; 497 regsLive.clear(); 498} 499 500// Calculate the largest possible vregsPassed sets. These are the registers that 501// can pass through an MBB live, but may not be live every time. It is assumed 502// that all vregsPassed sets are empty before the call. 503void 504MachineVerifier::calcMaxRegsPassed() 505{ 506 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 507 // have any vregsPassed. 508 DenseSet<const MachineBasicBlock*> todo; 509 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 510 MFI != MFE; ++MFI) { 511 const MachineBasicBlock &MBB(*MFI); 512 BBInfo &MInfo = MBBInfoMap[&MBB]; 513 if (!MInfo.reachable) 514 continue; 515 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 516 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 517 BBInfo &SInfo = MBBInfoMap[*SuI]; 518 if (SInfo.addPassed(MInfo.regsLiveOut)) 519 todo.insert(*SuI); 520 } 521 } 522 523 // Iteratively push vregsPassed to successors. This will converge to the same 524 // final state regardless of DenseSet iteration order. 525 while (!todo.empty()) { 526 const MachineBasicBlock *MBB = *todo.begin(); 527 todo.erase(MBB); 528 BBInfo &MInfo = MBBInfoMap[MBB]; 529 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 530 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 531 if (*SuI == MBB) 532 continue; 533 BBInfo &SInfo = MBBInfoMap[*SuI]; 534 if (SInfo.addPassed(MInfo.vregsPassed)) 535 todo.insert(*SuI); 536 } 537 } 538} 539 540// Calculate the minimum vregsPassed set. These are the registers that always 541// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has 542// been called earlier. 543void 544MachineVerifier::calcMinRegsPassed() 545{ 546 DenseSet<const MachineBasicBlock*> todo; 547 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 548 MFI != MFE; ++MFI) 549 todo.insert(MFI); 550 551 while (!todo.empty()) { 552 const MachineBasicBlock *MBB = *todo.begin(); 553 todo.erase(MBB); 554 BBInfo &MInfo = MBBInfoMap[MBB]; 555 556 // Remove entries from vRegsPassed that are not live out from all 557 // reachable predecessors. 558 RegSet dead; 559 for (RegSet::iterator I = MInfo.vregsPassed.begin(), 560 E = MInfo.vregsPassed.end(); I != E; ++I) { 561 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 562 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 563 BBInfo &PrInfo = MBBInfoMap[*PrI]; 564 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) { 565 dead.insert(*I); 566 break; 567 } 568 } 569 } 570 // If any regs removed, we need to recheck successors. 571 if (!dead.empty()) { 572 set_subtract(MInfo.vregsPassed, dead); 573 todo.insert(MBB->succ_begin(), MBB->succ_end()); 574 } 575 } 576} 577 578// Check PHI instructions at the beginning of MBB. It is assumed that 579// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid. 580void 581MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) 582{ 583 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 584 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { 585 DenseSet<const MachineBasicBlock*> seen; 586 587 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 588 unsigned Reg = BBI->getOperand(i).getReg(); 589 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 590 if (!Pre->isSuccessor(MBB)) 591 continue; 592 seen.insert(Pre); 593 BBInfo &PrInfo = MBBInfoMap[Pre]; 594 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 595 report("PHI operand is not live-out from predecessor", 596 &BBI->getOperand(i), i); 597 } 598 599 // Did we see all predecessors? 600 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 601 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 602 if (!seen.count(*PrI)) { 603 report("Missing PHI operand", BBI); 604 *OS << "MBB #" << (*PrI)->getNumber() 605 << " is a predecessor according to the CFG.\n"; 606 } 607 } 608 } 609} 610 611void 612MachineVerifier::visitMachineFunctionAfter() 613{ 614 calcMaxRegsPassed(); 615 616 // With the maximal set of vregsPassed we can verify dead-in registers. 617 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 618 MFI != MFE; ++MFI) { 619 BBInfo &MInfo = MBBInfoMap[MFI]; 620 621 // Skip unreachable MBBs. 622 if (!MInfo.reachable) 623 continue; 624 625 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 626 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 627 BBInfo &PrInfo = MBBInfoMap[*PrI]; 628 if (!PrInfo.reachable) 629 continue; 630 631 // Verify physical live-ins. EH landing pads have magic live-ins so we 632 // ignore them. 633 if (!MFI->isLandingPad()) { 634 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(), 635 E = MFI->livein_end(); I != E; ++I) { 636 if (TargetRegisterInfo::isPhysicalRegister(*I) && 637 !isReserved (*I) && !PrInfo.isLiveOut(*I)) { 638 report("Live-in physical register is not live-out from predecessor", 639 MFI); 640 *OS << "Register " << TRI->getName(*I) 641 << " is not live-out from MBB #" << (*PrI)->getNumber() 642 << ".\n"; 643 } 644 } 645 } 646 647 648 // Verify dead-in virtual registers. 649 if (!allowVirtDoubleDefs) { 650 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(), 651 E = MInfo.vregsDeadIn.end(); I != E; ++I) { 652 // DeadIn register must be in neither regsLiveOut or vregsPassed of 653 // any predecessor. 654 if (PrInfo.isLiveOut(I->first)) { 655 report("Live-in virtual register redefined", I->second); 656 *OS << "Register %reg" << I->first 657 << " was live-out from predecessor MBB #" 658 << (*PrI)->getNumber() << ".\n"; 659 } 660 } 661 } 662 } 663 } 664 665 calcMinRegsPassed(); 666 667 // With the minimal set of vregsPassed we can verify live-in virtual 668 // registers, including PHI instructions. 669 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 670 MFI != MFE; ++MFI) { 671 BBInfo &MInfo = MBBInfoMap[MFI]; 672 673 // Skip unreachable MBBs. 674 if (!MInfo.reachable) 675 continue; 676 677 checkPHIOps(MFI); 678 679 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 680 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 681 BBInfo &PrInfo = MBBInfoMap[*PrI]; 682 if (!PrInfo.reachable) 683 continue; 684 685 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(), 686 E = MInfo.vregsLiveIn.end(); I != E; ++I) { 687 if (!PrInfo.isLiveOut(I->first)) { 688 report("Used virtual register is not live-in", I->second); 689 *OS << "Register %reg" << I->first 690 << " is not live-out from predecessor MBB #" 691 << (*PrI)->getNumber() 692 << ".\n"; 693 } 694 } 695 } 696 } 697} 698