MachineVerifier.cpp revision 18ea3a1551214f1ff3f123f2d67443d5f19baea5 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/Function.h"
27#include "llvm/CodeGen/LiveVariables.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/ADT/DenseSet.h"
37#include "llvm/ADT/SetOperations.h"
38#include "llvm/ADT/SmallVector.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/raw_ostream.h"
42using namespace llvm;
43
44namespace {
45  struct MachineVerifier {
46
47    MachineVerifier(Pass *pass, bool allowDoubleDefs) :
48      PASS(pass),
49      allowVirtDoubleDefs(allowDoubleDefs),
50      allowPhysDoubleDefs(allowDoubleDefs),
51      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
52      {}
53
54    bool runOnMachineFunction(MachineFunction &MF);
55
56    Pass *const PASS;
57    const bool allowVirtDoubleDefs;
58    const bool allowPhysDoubleDefs;
59
60    const char *const OutFileName;
61    raw_ostream *OS;
62    const MachineFunction *MF;
63    const TargetMachine *TM;
64    const TargetRegisterInfo *TRI;
65    const MachineRegisterInfo *MRI;
66
67    unsigned foundErrors;
68
69    typedef SmallVector<unsigned, 16> RegVector;
70    typedef DenseSet<unsigned> RegSet;
71    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
72
73    BitVector regsReserved;
74    RegSet regsLive;
75    RegVector regsDefined, regsDead, regsKilled;
76    RegSet regsLiveInButUnused;
77
78    // Add Reg and any sub-registers to RV
79    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
80      RV.push_back(Reg);
81      if (TargetRegisterInfo::isPhysicalRegister(Reg))
82        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
83          RV.push_back(*R);
84    }
85
86    struct BBInfo {
87      // Is this MBB reachable from the MF entry point?
88      bool reachable;
89
90      // Vregs that must be live in because they are used without being
91      // defined. Map value is the user.
92      RegMap vregsLiveIn;
93
94      // Vregs that must be dead in because they are defined without being
95      // killed first. Map value is the defining instruction.
96      RegMap vregsDeadIn;
97
98      // Regs killed in MBB. They may be defined again, and will then be in both
99      // regsKilled and regsLiveOut.
100      RegSet regsKilled;
101
102      // Regs defined in MBB and live out. Note that vregs passing through may
103      // be live out without being mentioned here.
104      RegSet regsLiveOut;
105
106      // Vregs that pass through MBB untouched. This set is disjoint from
107      // regsKilled and regsLiveOut.
108      RegSet vregsPassed;
109
110      // Vregs that must pass through MBB because they are needed by a successor
111      // block. This set is disjoint from regsLiveOut.
112      RegSet vregsRequired;
113
114      BBInfo() : reachable(false) {}
115
116      // Add register to vregsPassed if it belongs there. Return true if
117      // anything changed.
118      bool addPassed(unsigned Reg) {
119        if (!TargetRegisterInfo::isVirtualRegister(Reg))
120          return false;
121        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
122          return false;
123        return vregsPassed.insert(Reg).second;
124      }
125
126      // Same for a full set.
127      bool addPassed(const RegSet &RS) {
128        bool changed = false;
129        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
130          if (addPassed(*I))
131            changed = true;
132        return changed;
133      }
134
135      // Add register to vregsRequired if it belongs there. Return true if
136      // anything changed.
137      bool addRequired(unsigned Reg) {
138        if (!TargetRegisterInfo::isVirtualRegister(Reg))
139          return false;
140        if (regsLiveOut.count(Reg))
141          return false;
142        return vregsRequired.insert(Reg).second;
143      }
144
145      // Same for a full set.
146      bool addRequired(const RegSet &RS) {
147        bool changed = false;
148        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
149          if (addRequired(*I))
150            changed = true;
151        return changed;
152      }
153
154      // Same for a full map.
155      bool addRequired(const RegMap &RM) {
156        bool changed = false;
157        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
158          if (addRequired(I->first))
159            changed = true;
160        return changed;
161      }
162
163      // Live-out registers are either in regsLiveOut or vregsPassed.
164      bool isLiveOut(unsigned Reg) const {
165        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
166      }
167    };
168
169    // Extra register info per MBB.
170    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
171
172    bool isReserved(unsigned Reg) {
173      return Reg < regsReserved.size() && regsReserved.test(Reg);
174    }
175
176    // Analysis information if available
177    LiveVariables *LiveVars;
178
179    void visitMachineFunctionBefore();
180    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
181    void visitMachineInstrBefore(const MachineInstr *MI);
182    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
183    void visitMachineInstrAfter(const MachineInstr *MI);
184    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
185    void visitMachineFunctionAfter();
186
187    void report(const char *msg, const MachineFunction *MF);
188    void report(const char *msg, const MachineBasicBlock *MBB);
189    void report(const char *msg, const MachineInstr *MI);
190    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
191
192    void markReachable(const MachineBasicBlock *MBB);
193    void calcMaxRegsPassed();
194    void calcMinRegsPassed();
195    void checkPHIOps(const MachineBasicBlock *MBB);
196
197    void calcRegsRequired();
198    void verifyLiveVariables();
199  };
200
201  struct MachineVerifierPass : public MachineFunctionPass {
202    static char ID; // Pass ID, replacement for typeid
203    bool AllowDoubleDefs;
204
205    explicit MachineVerifierPass(bool allowDoubleDefs = false)
206      : MachineFunctionPass(&ID),
207        AllowDoubleDefs(allowDoubleDefs) {}
208
209    void getAnalysisUsage(AnalysisUsage &AU) const {
210      AU.setPreservesAll();
211      MachineFunctionPass::getAnalysisUsage(AU);
212    }
213
214    bool runOnMachineFunction(MachineFunction &MF) {
215      MF.verify(this, AllowDoubleDefs);
216      return false;
217    }
218  };
219
220}
221
222char MachineVerifierPass::ID = 0;
223static RegisterPass<MachineVerifierPass>
224MachineVer("machineverifier", "Verify generated machine code");
225static const PassInfo *const MachineVerifyID = &MachineVer;
226
227FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
228  return new MachineVerifierPass(allowPhysDoubleDefs);
229}
230
231void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
232  MachineVerifier(p, allowDoubleDefs)
233    .runOnMachineFunction(const_cast<MachineFunction&>(*this));
234}
235
236bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
237  raw_ostream *OutFile = 0;
238  if (OutFileName) {
239    std::string ErrorInfo;
240    OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
241                                 raw_fd_ostream::F_Append);
242    if (!ErrorInfo.empty()) {
243      errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
244      exit(1);
245    }
246
247    OS = OutFile;
248  } else {
249    OS = &errs();
250  }
251
252  foundErrors = 0;
253
254  this->MF = &MF;
255  TM = &MF.getTarget();
256  TRI = TM->getRegisterInfo();
257  MRI = &MF.getRegInfo();
258
259  if (PASS) {
260    LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
261  } else {
262    LiveVars = NULL;
263  }
264
265  visitMachineFunctionBefore();
266  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
267       MFI!=MFE; ++MFI) {
268    visitMachineBasicBlockBefore(MFI);
269    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
270           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
271      visitMachineInstrBefore(MBBI);
272      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
273        visitMachineOperand(&MBBI->getOperand(I), I);
274      visitMachineInstrAfter(MBBI);
275    }
276    visitMachineBasicBlockAfter(MFI);
277  }
278  visitMachineFunctionAfter();
279
280  if (OutFile)
281    delete OutFile;
282  else if (foundErrors)
283    llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
284
285  // Clean up.
286  regsLive.clear();
287  regsDefined.clear();
288  regsDead.clear();
289  regsKilled.clear();
290  regsLiveInButUnused.clear();
291  MBBInfoMap.clear();
292
293  return false;                 // no changes
294}
295
296void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
297  assert(MF);
298  *OS << '\n';
299  if (!foundErrors++)
300    MF->print(*OS);
301  *OS << "*** Bad machine code: " << msg << " ***\n"
302      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
303}
304
305void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
306  assert(MBB);
307  report(msg, MBB->getParent());
308  *OS << "- basic block: " << MBB->getName()
309      << " " << (void*)MBB
310      << " (BB#" << MBB->getNumber() << ")\n";
311}
312
313void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
314  assert(MI);
315  report(msg, MI->getParent());
316  *OS << "- instruction: ";
317  MI->print(*OS, TM);
318}
319
320void MachineVerifier::report(const char *msg,
321                             const MachineOperand *MO, unsigned MONum) {
322  assert(MO);
323  report(msg, MO->getParent());
324  *OS << "- operand " << MONum << ":   ";
325  MO->print(*OS, TM);
326  *OS << "\n";
327}
328
329void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
330  BBInfo &MInfo = MBBInfoMap[MBB];
331  if (!MInfo.reachable) {
332    MInfo.reachable = true;
333    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
334           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
335      markReachable(*SuI);
336  }
337}
338
339void MachineVerifier::visitMachineFunctionBefore() {
340  regsReserved = TRI->getReservedRegs(*MF);
341
342  // A sub-register of a reserved register is also reserved
343  for (int Reg = regsReserved.find_first(); Reg>=0;
344       Reg = regsReserved.find_next(Reg)) {
345    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
346      // FIXME: This should probably be:
347      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
348      regsReserved.set(*Sub);
349    }
350  }
351  markReachable(&MF->front());
352}
353
354// Does iterator point to a and b as the first two elements?
355bool matchPair(MachineBasicBlock::const_succ_iterator i,
356               const MachineBasicBlock *a, const MachineBasicBlock *b) {
357  if (*i == a)
358    return *++i == b;
359  if (*i == b)
360    return *++i == a;
361  return false;
362}
363
364void
365MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
366  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
367
368  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
369  MachineBasicBlock *TBB = 0, *FBB = 0;
370  SmallVector<MachineOperand, 4> Cond;
371  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
372                          TBB, FBB, Cond)) {
373    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
374    // check whether its answers match up with reality.
375    if (!TBB && !FBB) {
376      // Block falls through to its successor.
377      MachineFunction::const_iterator MBBI = MBB;
378      ++MBBI;
379      if (MBBI == MF->end()) {
380        // It's possible that the block legitimately ends with a noreturn
381        // call or an unreachable, in which case it won't actually fall
382        // out the bottom of the function.
383      } else if (MBB->succ_empty()) {
384        // It's possible that the block legitimately ends with a noreturn
385        // call or an unreachable, in which case it won't actuall fall
386        // out of the block.
387      } else if (MBB->succ_size() != 1) {
388        report("MBB exits via unconditional fall-through but doesn't have "
389               "exactly one CFG successor!", MBB);
390      } else if (MBB->succ_begin()[0] != MBBI) {
391        report("MBB exits via unconditional fall-through but its successor "
392               "differs from its CFG successor!", MBB);
393      }
394      if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
395        report("MBB exits via unconditional fall-through but ends with a "
396               "barrier instruction!", MBB);
397      }
398      if (!Cond.empty()) {
399        report("MBB exits via unconditional fall-through but has a condition!",
400               MBB);
401      }
402    } else if (TBB && !FBB && Cond.empty()) {
403      // Block unconditionally branches somewhere.
404      if (MBB->succ_size() != 1) {
405        report("MBB exits via unconditional branch but doesn't have "
406               "exactly one CFG successor!", MBB);
407      } else if (MBB->succ_begin()[0] != TBB) {
408        report("MBB exits via unconditional branch but the CFG "
409               "successor doesn't match the actual successor!", MBB);
410      }
411      if (MBB->empty()) {
412        report("MBB exits via unconditional branch but doesn't contain "
413               "any instructions!", MBB);
414      } else if (!MBB->back().getDesc().isBarrier()) {
415        report("MBB exits via unconditional branch but doesn't end with a "
416               "barrier instruction!", MBB);
417      } else if (!MBB->back().getDesc().isTerminator()) {
418        report("MBB exits via unconditional branch but the branch isn't a "
419               "terminator instruction!", MBB);
420      }
421    } else if (TBB && !FBB && !Cond.empty()) {
422      // Block conditionally branches somewhere, otherwise falls through.
423      MachineFunction::const_iterator MBBI = MBB;
424      ++MBBI;
425      if (MBBI == MF->end()) {
426        report("MBB conditionally falls through out of function!", MBB);
427      } if (MBB->succ_size() != 2) {
428        report("MBB exits via conditional branch/fall-through but doesn't have "
429               "exactly two CFG successors!", MBB);
430      } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
431        report("MBB exits via conditional branch/fall-through but the CFG "
432               "successors don't match the actual successors!", MBB);
433      }
434      if (MBB->empty()) {
435        report("MBB exits via conditional branch/fall-through but doesn't "
436               "contain any instructions!", MBB);
437      } else if (MBB->back().getDesc().isBarrier()) {
438        report("MBB exits via conditional branch/fall-through but ends with a "
439               "barrier instruction!", MBB);
440      } else if (!MBB->back().getDesc().isTerminator()) {
441        report("MBB exits via conditional branch/fall-through but the branch "
442               "isn't a terminator instruction!", MBB);
443      }
444    } else if (TBB && FBB) {
445      // Block conditionally branches somewhere, otherwise branches
446      // somewhere else.
447      if (MBB->succ_size() != 2) {
448        report("MBB exits via conditional branch/branch but doesn't have "
449               "exactly two CFG successors!", MBB);
450      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
451        report("MBB exits via conditional branch/branch but the CFG "
452               "successors don't match the actual successors!", MBB);
453      }
454      if (MBB->empty()) {
455        report("MBB exits via conditional branch/branch but doesn't "
456               "contain any instructions!", MBB);
457      } else if (!MBB->back().getDesc().isBarrier()) {
458        report("MBB exits via conditional branch/branch but doesn't end with a "
459               "barrier instruction!", MBB);
460      } else if (!MBB->back().getDesc().isTerminator()) {
461        report("MBB exits via conditional branch/branch but the branch "
462               "isn't a terminator instruction!", MBB);
463      }
464      if (Cond.empty()) {
465        report("MBB exits via conditinal branch/branch but there's no "
466               "condition!", MBB);
467      }
468    } else {
469      report("AnalyzeBranch returned invalid data!", MBB);
470    }
471  }
472
473  regsLive.clear();
474  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
475         E = MBB->livein_end(); I != E; ++I) {
476    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
477      report("MBB live-in list contains non-physical register", MBB);
478      continue;
479    }
480    regsLive.insert(*I);
481    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
482      regsLive.insert(*R);
483  }
484  regsLiveInButUnused = regsLive;
485
486  const MachineFrameInfo *MFI = MF->getFrameInfo();
487  assert(MFI && "Function has no frame info");
488  BitVector PR = MFI->getPristineRegs(MBB);
489  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
490    regsLive.insert(I);
491    for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
492      regsLive.insert(*R);
493  }
494
495  regsKilled.clear();
496  regsDefined.clear();
497}
498
499void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
500  const TargetInstrDesc &TI = MI->getDesc();
501  if (MI->getNumOperands() < TI.getNumOperands()) {
502    report("Too few operands", MI);
503    *OS << TI.getNumOperands() << " operands expected, but "
504        << MI->getNumExplicitOperands() << " given.\n";
505  }
506
507  // Check the MachineMemOperands for basic consistency.
508  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
509       E = MI->memoperands_end(); I != E; ++I) {
510    if ((*I)->isLoad() && !TI.mayLoad())
511      report("Missing mayLoad flag", MI);
512    if ((*I)->isStore() && !TI.mayStore())
513      report("Missing mayStore flag", MI);
514  }
515}
516
517void
518MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
519  const MachineInstr *MI = MO->getParent();
520  const TargetInstrDesc &TI = MI->getDesc();
521
522  // The first TI.NumDefs operands must be explicit register defines
523  if (MONum < TI.getNumDefs()) {
524    if (!MO->isReg())
525      report("Explicit definition must be a register", MO, MONum);
526    else if (!MO->isDef())
527      report("Explicit definition marked as use", MO, MONum);
528    else if (MO->isImplicit())
529      report("Explicit definition marked as implicit", MO, MONum);
530  } else if (MONum < TI.getNumOperands()) {
531    if (MO->isReg()) {
532      if (MO->isDef())
533        report("Explicit operand marked as def", MO, MONum);
534      if (MO->isImplicit())
535        report("Explicit operand marked as implicit", MO, MONum);
536    }
537  } else {
538    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
539    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
540      report("Extra explicit operand on non-variadic instruction", MO, MONum);
541  }
542
543  switch (MO->getType()) {
544  case MachineOperand::MO_Register: {
545    const unsigned Reg = MO->getReg();
546    if (!Reg)
547      return;
548
549    // Check Live Variables.
550    if (MO->isUndef()) {
551      // An <undef> doesn't refer to any register, so just skip it.
552    } else if (MO->isUse()) {
553      regsLiveInButUnused.erase(Reg);
554
555      bool isKill = false;
556      if (MO->isKill()) {
557        isKill = true;
558        // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
559        if (MI->isRegTiedToDefOperand(MONum))
560            report("Illegal kill flag on two-address instruction operand",
561                   MO, MONum);
562      } else {
563        // TwoAddress instr modifying a reg is treated as kill+def.
564        unsigned defIdx;
565        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
566            MI->getOperand(defIdx).getReg() == Reg)
567          isKill = true;
568      }
569      if (isKill) {
570        addRegWithSubRegs(regsKilled, Reg);
571
572        // Check that LiveVars knows this kill
573        if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
574          LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
575          if (std::find(VI.Kills.begin(),
576                        VI.Kills.end(), MI) == VI.Kills.end())
577            report("Kill missing from LiveVariables", MO, MONum);
578        }
579      }
580
581      // Use of a dead register.
582      if (!regsLive.count(Reg)) {
583        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
584          // Reserved registers may be used even when 'dead'.
585          if (!isReserved(Reg))
586            report("Using an undefined physical register", MO, MONum);
587        } else {
588          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
589          // We don't know which virtual registers are live in, so only complain
590          // if vreg was killed in this MBB. Otherwise keep track of vregs that
591          // must be live in. PHI instructions are handled separately.
592          if (MInfo.regsKilled.count(Reg))
593            report("Using a killed virtual register", MO, MONum);
594          else if (MI->getOpcode() != TargetInstrInfo::PHI)
595            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
596        }
597      }
598    } else {
599      assert(MO->isDef());
600      // Register defined.
601      // TODO: verify that earlyclobber ops are not used.
602      if (MO->isDead())
603        addRegWithSubRegs(regsDead, Reg);
604      else
605        addRegWithSubRegs(regsDefined, Reg);
606    }
607
608    // Check register classes.
609    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
610      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
611      unsigned SubIdx = MO->getSubReg();
612
613      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
614        unsigned sr = Reg;
615        if (SubIdx) {
616          unsigned s = TRI->getSubReg(Reg, SubIdx);
617          if (!s) {
618            report("Invalid subregister index for physical register",
619                   MO, MONum);
620            return;
621          }
622          sr = s;
623        }
624        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
625          if (!DRC->contains(sr)) {
626            report("Illegal physical register for instruction", MO, MONum);
627            *OS << TRI->getName(sr) << " is not a "
628                << DRC->getName() << " register.\n";
629          }
630        }
631      } else {
632        // Virtual register.
633        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
634        if (SubIdx) {
635          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
636            report("Invalid subregister index for virtual register", MO, MONum);
637            return;
638          }
639          RC = *(RC->subregclasses_begin()+SubIdx);
640        }
641        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
642          if (RC != DRC && !RC->hasSuperClass(DRC)) {
643            report("Illegal virtual register for instruction", MO, MONum);
644            *OS << "Expected a " << DRC->getName() << " register, but got a "
645                << RC->getName() << " register\n";
646          }
647        }
648      }
649    }
650    break;
651  }
652
653  case MachineOperand::MO_MachineBasicBlock:
654    if (MI->getOpcode() == TargetInstrInfo::PHI) {
655      if (!MO->getMBB()->isSuccessor(MI->getParent()))
656        report("PHI operand is not in the CFG", MO, MONum);
657    }
658    break;
659
660  default:
661    break;
662  }
663}
664
665void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
666  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
667  set_union(MInfo.regsKilled, regsKilled);
668  set_subtract(regsLive, regsKilled);
669  regsKilled.clear();
670
671  // Verify that both <def> and <def,dead> operands refer to dead registers.
672  RegVector defs(regsDefined);
673  defs.append(regsDead.begin(), regsDead.end());
674
675  for (RegVector::const_iterator I = defs.begin(), E = defs.end();
676       I != E; ++I) {
677    if (regsLive.count(*I)) {
678      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
679        if (!allowPhysDoubleDefs && !isReserved(*I) &&
680            !regsLiveInButUnused.count(*I)) {
681          report("Redefining a live physical register", MI);
682          *OS << "Register " << TRI->getName(*I)
683              << " was defined but already live.\n";
684        }
685      } else {
686        if (!allowVirtDoubleDefs) {
687          report("Redefining a live virtual register", MI);
688          *OS << "Virtual register %reg" << *I
689              << " was defined but already live.\n";
690        }
691      }
692    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
693               !MInfo.regsKilled.count(*I)) {
694      // Virtual register defined without being killed first must be dead on
695      // entry.
696      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
697    }
698  }
699
700  set_subtract(regsLive, regsDead); regsDead.clear();
701  set_union(regsLive, regsDefined); regsDefined.clear();
702}
703
704void
705MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
706  MBBInfoMap[MBB].regsLiveOut = regsLive;
707  regsLive.clear();
708}
709
710// Calculate the largest possible vregsPassed sets. These are the registers that
711// can pass through an MBB live, but may not be live every time. It is assumed
712// that all vregsPassed sets are empty before the call.
713void MachineVerifier::calcMaxRegsPassed() {
714  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
715  // have any vregsPassed.
716  DenseSet<const MachineBasicBlock*> todo;
717  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
718       MFI != MFE; ++MFI) {
719    const MachineBasicBlock &MBB(*MFI);
720    BBInfo &MInfo = MBBInfoMap[&MBB];
721    if (!MInfo.reachable)
722      continue;
723    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
724           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
725      BBInfo &SInfo = MBBInfoMap[*SuI];
726      if (SInfo.addPassed(MInfo.regsLiveOut))
727        todo.insert(*SuI);
728    }
729  }
730
731  // Iteratively push vregsPassed to successors. This will converge to the same
732  // final state regardless of DenseSet iteration order.
733  while (!todo.empty()) {
734    const MachineBasicBlock *MBB = *todo.begin();
735    todo.erase(MBB);
736    BBInfo &MInfo = MBBInfoMap[MBB];
737    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
738           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
739      if (*SuI == MBB)
740        continue;
741      BBInfo &SInfo = MBBInfoMap[*SuI];
742      if (SInfo.addPassed(MInfo.vregsPassed))
743        todo.insert(*SuI);
744    }
745  }
746}
747
748// Calculate the minimum vregsPassed set. These are the registers that always
749// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
750// been called earlier.
751void MachineVerifier::calcMinRegsPassed() {
752  DenseSet<const MachineBasicBlock*> todo;
753  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
754       MFI != MFE; ++MFI)
755    todo.insert(MFI);
756
757  while (!todo.empty()) {
758    const MachineBasicBlock *MBB = *todo.begin();
759    todo.erase(MBB);
760    BBInfo &MInfo = MBBInfoMap[MBB];
761
762    // Remove entries from vRegsPassed that are not live out from all
763    // reachable predecessors.
764    RegSet dead;
765    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
766           E = MInfo.vregsPassed.end(); I != E; ++I) {
767      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
768             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
769        BBInfo &PrInfo = MBBInfoMap[*PrI];
770        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
771          dead.insert(*I);
772          break;
773        }
774      }
775    }
776    // If any regs removed, we need to recheck successors.
777    if (!dead.empty()) {
778      set_subtract(MInfo.vregsPassed, dead);
779      todo.insert(MBB->succ_begin(), MBB->succ_end());
780    }
781  }
782}
783
784// Calculate the set of virtual registers that must be passed through each basic
785// block in order to satisfy the requirements of successor blocks. This is very
786// similar to calcMaxRegsPassed, only backwards.
787void MachineVerifier::calcRegsRequired() {
788  // First push live-in regs to predecessors' vregsRequired.
789  DenseSet<const MachineBasicBlock*> todo;
790  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
791       MFI != MFE; ++MFI) {
792    const MachineBasicBlock &MBB(*MFI);
793    BBInfo &MInfo = MBBInfoMap[&MBB];
794    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
795           PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
796      BBInfo &PInfo = MBBInfoMap[*PrI];
797      if (PInfo.addRequired(MInfo.vregsLiveIn))
798        todo.insert(*PrI);
799    }
800  }
801
802  // Iteratively push vregsRequired to predecessors. This will converge to the
803  // same final state regardless of DenseSet iteration order.
804  while (!todo.empty()) {
805    const MachineBasicBlock *MBB = *todo.begin();
806    todo.erase(MBB);
807    BBInfo &MInfo = MBBInfoMap[MBB];
808    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
809           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
810      if (*PrI == MBB)
811        continue;
812      BBInfo &SInfo = MBBInfoMap[*PrI];
813      if (SInfo.addRequired(MInfo.vregsRequired))
814        todo.insert(*PrI);
815    }
816  }
817}
818
819// Check PHI instructions at the beginning of MBB. It is assumed that
820// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
821void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
822  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
823       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
824    DenseSet<const MachineBasicBlock*> seen;
825
826    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
827      unsigned Reg = BBI->getOperand(i).getReg();
828      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
829      if (!Pre->isSuccessor(MBB))
830        continue;
831      seen.insert(Pre);
832      BBInfo &PrInfo = MBBInfoMap[Pre];
833      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
834        report("PHI operand is not live-out from predecessor",
835               &BBI->getOperand(i), i);
836    }
837
838    // Did we see all predecessors?
839    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
840           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
841      if (!seen.count(*PrI)) {
842        report("Missing PHI operand", BBI);
843        *OS << "BB#" << (*PrI)->getNumber()
844            << " is a predecessor according to the CFG.\n";
845      }
846    }
847  }
848}
849
850void MachineVerifier::visitMachineFunctionAfter() {
851  calcMaxRegsPassed();
852
853  // With the maximal set of vregsPassed we can verify dead-in registers.
854  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
855       MFI != MFE; ++MFI) {
856    BBInfo &MInfo = MBBInfoMap[MFI];
857
858    // Skip unreachable MBBs.
859    if (!MInfo.reachable)
860      continue;
861
862    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
863           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
864      BBInfo &PrInfo = MBBInfoMap[*PrI];
865      if (!PrInfo.reachable)
866        continue;
867
868      // Verify physical live-ins. EH landing pads have magic live-ins so we
869      // ignore them.
870      if (!MFI->isLandingPad()) {
871        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
872               E = MFI->livein_end(); I != E; ++I) {
873          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
874              !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
875            report("Live-in physical register is not live-out from predecessor",
876                   MFI);
877            *OS << "Register " << TRI->getName(*I)
878                << " is not live-out from BB#" << (*PrI)->getNumber()
879                << ".\n";
880          }
881        }
882      }
883
884
885      // Verify dead-in virtual registers.
886      if (!allowVirtDoubleDefs) {
887        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
888               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
889          // DeadIn register must be in neither regsLiveOut or vregsPassed of
890          // any predecessor.
891          if (PrInfo.isLiveOut(I->first)) {
892            report("Live-in virtual register redefined", I->second);
893            *OS << "Register %reg" << I->first
894                << " was live-out from predecessor MBB #"
895                << (*PrI)->getNumber() << ".\n";
896          }
897        }
898      }
899    }
900  }
901
902  calcMinRegsPassed();
903
904  // With the minimal set of vregsPassed we can verify live-in virtual
905  // registers, including PHI instructions.
906  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
907       MFI != MFE; ++MFI) {
908    BBInfo &MInfo = MBBInfoMap[MFI];
909
910    // Skip unreachable MBBs.
911    if (!MInfo.reachable)
912      continue;
913
914    checkPHIOps(MFI);
915
916    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
917           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
918      BBInfo &PrInfo = MBBInfoMap[*PrI];
919      if (!PrInfo.reachable)
920        continue;
921
922      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
923             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
924        if (!PrInfo.isLiveOut(I->first)) {
925          report("Used virtual register is not live-in", I->second);
926          *OS << "Register %reg" << I->first
927              << " is not live-out from predecessor MBB #"
928              << (*PrI)->getNumber()
929              << ".\n";
930        }
931      }
932    }
933  }
934
935  // Now check LiveVariables info if available
936  if (LiveVars) {
937    calcRegsRequired();
938    verifyLiveVariables();
939  }
940}
941
942void MachineVerifier::verifyLiveVariables() {
943  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
944  for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
945         RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
946    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
947    for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
948         MFI != MFE; ++MFI) {
949      BBInfo &MInfo = MBBInfoMap[MFI];
950
951      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
952      if (MInfo.vregsRequired.count(Reg)) {
953        if (!VI.AliveBlocks.test(MFI->getNumber())) {
954          report("LiveVariables: Block missing from AliveBlocks", MFI);
955          *OS << "Virtual register %reg" << Reg
956              << " must be live through the block.\n";
957        }
958      } else {
959        if (VI.AliveBlocks.test(MFI->getNumber())) {
960          report("LiveVariables: Block should not be in AliveBlocks", MFI);
961          *OS << "Virtual register %reg" << Reg
962              << " is not needed live through the block.\n";
963        }
964      }
965    }
966  }
967}
968
969
970