MachineVerifier.cpp revision 22d67cf6ac84c06867681a2fe72f78d5d2b9444d 
1//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/Function.h"
27#include "llvm/CodeGen/LiveIntervalAnalysis.h"
28#include "llvm/CodeGen/LiveVariables.h"
29#include "llvm/CodeGen/LiveStackAnalysis.h"
30#include "llvm/CodeGen/MachineFunctionPass.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/Passes.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include "llvm/Target/TargetInstrInfo.h"
38#include "llvm/ADT/DenseSet.h"
39#include "llvm/ADT/SetOperations.h"
40#include "llvm/ADT/SmallVector.h"
41#include "llvm/Support/Debug.h"
42#include "llvm/Support/ErrorHandling.h"
43#include "llvm/Support/raw_ostream.h"
44using namespace llvm;
45
46namespace {
47  struct MachineVerifier {
48
49    MachineVerifier(Pass *pass, const char *b) :
50      PASS(pass),
51      Banner(b),
52      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
53      {}
54
55    bool runOnMachineFunction(MachineFunction &MF);
56
57    Pass *const PASS;
58    const char *Banner;
59    const char *const OutFileName;
60    raw_ostream *OS;
61    const MachineFunction *MF;
62    const TargetMachine *TM;
63    const TargetRegisterInfo *TRI;
64    const MachineRegisterInfo *MRI;
65
66    unsigned foundErrors;
67
68    typedef SmallVector<unsigned, 16> RegVector;
69    typedef DenseSet<unsigned> RegSet;
70    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
71
72    BitVector regsReserved;
73    RegSet regsLive;
74    RegVector regsDefined, regsDead, regsKilled;
75    RegSet regsLiveInButUnused;
76
77    // Add Reg and any sub-registers to RV
78    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
79      RV.push_back(Reg);
80      if (TargetRegisterInfo::isPhysicalRegister(Reg))
81        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
82          RV.push_back(*R);
83    }
84
85    struct BBInfo {
86      // Is this MBB reachable from the MF entry point?
87      bool reachable;
88
89      // Vregs that must be live in because they are used without being
90      // defined. Map value is the user.
91      RegMap vregsLiveIn;
92
93      // Regs killed in MBB. They may be defined again, and will then be in both
94      // regsKilled and regsLiveOut.
95      RegSet regsKilled;
96
97      // Regs defined in MBB and live out. Note that vregs passing through may
98      // be live out without being mentioned here.
99      RegSet regsLiveOut;
100
101      // Vregs that pass through MBB untouched. This set is disjoint from
102      // regsKilled and regsLiveOut.
103      RegSet vregsPassed;
104
105      // Vregs that must pass through MBB because they are needed by a successor
106      // block. This set is disjoint from regsLiveOut.
107      RegSet vregsRequired;
108
109      BBInfo() : reachable(false) {}
110
111      // Add register to vregsPassed if it belongs there. Return true if
112      // anything changed.
113      bool addPassed(unsigned Reg) {
114        if (!TargetRegisterInfo::isVirtualRegister(Reg))
115          return false;
116        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
117          return false;
118        return vregsPassed.insert(Reg).second;
119      }
120
121      // Same for a full set.
122      bool addPassed(const RegSet &RS) {
123        bool changed = false;
124        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
125          if (addPassed(*I))
126            changed = true;
127        return changed;
128      }
129
130      // Add register to vregsRequired if it belongs there. Return true if
131      // anything changed.
132      bool addRequired(unsigned Reg) {
133        if (!TargetRegisterInfo::isVirtualRegister(Reg))
134          return false;
135        if (regsLiveOut.count(Reg))
136          return false;
137        return vregsRequired.insert(Reg).second;
138      }
139
140      // Same for a full set.
141      bool addRequired(const RegSet &RS) {
142        bool changed = false;
143        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
144          if (addRequired(*I))
145            changed = true;
146        return changed;
147      }
148
149      // Same for a full map.
150      bool addRequired(const RegMap &RM) {
151        bool changed = false;
152        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
153          if (addRequired(I->first))
154            changed = true;
155        return changed;
156      }
157
158      // Live-out registers are either in regsLiveOut or vregsPassed.
159      bool isLiveOut(unsigned Reg) const {
160        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
161      }
162    };
163
164    // Extra register info per MBB.
165    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
166
167    bool isReserved(unsigned Reg) {
168      return Reg < regsReserved.size() && regsReserved.test(Reg);
169    }
170
171    // Analysis information if available
172    LiveVariables *LiveVars;
173    LiveIntervals *LiveInts;
174    LiveStacks *LiveStks;
175    SlotIndexes *Indexes;
176
177    void visitMachineFunctionBefore();
178    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
179    void visitMachineInstrBefore(const MachineInstr *MI);
180    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
181    void visitMachineInstrAfter(const MachineInstr *MI);
182    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
183    void visitMachineFunctionAfter();
184
185    void report(const char *msg, const MachineFunction *MF);
186    void report(const char *msg, const MachineBasicBlock *MBB);
187    void report(const char *msg, const MachineInstr *MI);
188    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
189
190    void markReachable(const MachineBasicBlock *MBB);
191    void calcRegsPassed();
192    void checkPHIOps(const MachineBasicBlock *MBB);
193
194    void calcRegsRequired();
195    void verifyLiveVariables();
196    void verifyLiveIntervals();
197  };
198
199  struct MachineVerifierPass : public MachineFunctionPass {
200    static char ID; // Pass ID, replacement for typeid
201    const char *const Banner;
202
203    MachineVerifierPass(const char *b = 0)
204      : MachineFunctionPass(ID), Banner(b) {
205        initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
206      }
207
208    void getAnalysisUsage(AnalysisUsage &AU) const {
209      AU.setPreservesAll();
210      MachineFunctionPass::getAnalysisUsage(AU);
211    }
212
213    bool runOnMachineFunction(MachineFunction &MF) {
214      MF.verify(this, Banner);
215      return false;
216    }
217  };
218
219}
220
221char MachineVerifierPass::ID = 0;
222INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
223                "Verify generated machine code", false, false)
224
225FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
226  return new MachineVerifierPass(Banner);
227}
228
229void MachineFunction::verify(Pass *p, const char *Banner) const {
230  MachineVerifier(p, Banner)
231    .runOnMachineFunction(const_cast<MachineFunction&>(*this));
232}
233
234bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
235  raw_ostream *OutFile = 0;
236  if (OutFileName) {
237    std::string ErrorInfo;
238    OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
239                                 raw_fd_ostream::F_Append);
240    if (!ErrorInfo.empty()) {
241      errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
242      exit(1);
243    }
244
245    OS = OutFile;
246  } else {
247    OS = &errs();
248  }
249
250  foundErrors = 0;
251
252  this->MF = &MF;
253  TM = &MF.getTarget();
254  TRI = TM->getRegisterInfo();
255  MRI = &MF.getRegInfo();
256
257  LiveVars = NULL;
258  LiveInts = NULL;
259  LiveStks = NULL;
260  Indexes = NULL;
261  if (PASS) {
262    LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
263    // We don't want to verify LiveVariables if LiveIntervals is available.
264    if (!LiveInts)
265      LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
266    LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
267    Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
268  }
269
270  visitMachineFunctionBefore();
271  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
272       MFI!=MFE; ++MFI) {
273    visitMachineBasicBlockBefore(MFI);
274    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
275           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
276      visitMachineInstrBefore(MBBI);
277      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
278        visitMachineOperand(&MBBI->getOperand(I), I);
279      visitMachineInstrAfter(MBBI);
280    }
281    visitMachineBasicBlockAfter(MFI);
282  }
283  visitMachineFunctionAfter();
284
285  if (OutFile)
286    delete OutFile;
287  else if (foundErrors)
288    report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
289
290  // Clean up.
291  regsLive.clear();
292  regsDefined.clear();
293  regsDead.clear();
294  regsKilled.clear();
295  regsLiveInButUnused.clear();
296  MBBInfoMap.clear();
297
298  return false;                 // no changes
299}
300
301void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
302  assert(MF);
303  *OS << '\n';
304  if (!foundErrors++) {
305    if (Banner)
306      *OS << "# " << Banner << '\n';
307    MF->print(*OS, Indexes);
308  }
309  *OS << "*** Bad machine code: " << msg << " ***\n"
310      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
311}
312
313void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
314  assert(MBB);
315  report(msg, MBB->getParent());
316  *OS << "- basic block: " << MBB->getName()
317      << " " << (void*)MBB
318      << " (BB#" << MBB->getNumber() << ")";
319  if (Indexes)
320    *OS << " [" << Indexes->getMBBStartIdx(MBB)
321        << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
322  *OS << '\n';
323}
324
325void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
326  assert(MI);
327  report(msg, MI->getParent());
328  *OS << "- instruction: ";
329  if (Indexes && Indexes->hasIndex(MI))
330    *OS << Indexes->getInstructionIndex(MI) << '\t';
331  MI->print(*OS, TM);
332}
333
334void MachineVerifier::report(const char *msg,
335                             const MachineOperand *MO, unsigned MONum) {
336  assert(MO);
337  report(msg, MO->getParent());
338  *OS << "- operand " << MONum << ":   ";
339  MO->print(*OS, TM);
340  *OS << "\n";
341}
342
343void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
344  BBInfo &MInfo = MBBInfoMap[MBB];
345  if (!MInfo.reachable) {
346    MInfo.reachable = true;
347    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
348           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
349      markReachable(*SuI);
350  }
351}
352
353void MachineVerifier::visitMachineFunctionBefore() {
354  regsReserved = TRI->getReservedRegs(*MF);
355
356  // A sub-register of a reserved register is also reserved
357  for (int Reg = regsReserved.find_first(); Reg>=0;
358       Reg = regsReserved.find_next(Reg)) {
359    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
360      // FIXME: This should probably be:
361      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
362      regsReserved.set(*Sub);
363    }
364  }
365  markReachable(&MF->front());
366}
367
368// Does iterator point to a and b as the first two elements?
369static bool matchPair(MachineBasicBlock::const_succ_iterator i,
370                      const MachineBasicBlock *a, const MachineBasicBlock *b) {
371  if (*i == a)
372    return *++i == b;
373  if (*i == b)
374    return *++i == a;
375  return false;
376}
377
378void
379MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
380  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
381
382  // Count the number of landing pad successors.
383  unsigned LandingPadSuccs = 0;
384  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
385       E = MBB->succ_end(); I != E; ++I)
386    LandingPadSuccs += (*I)->isLandingPad();
387  if (LandingPadSuccs > 1)
388    report("MBB has more than one landing pad successor", MBB);
389
390  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
391  MachineBasicBlock *TBB = 0, *FBB = 0;
392  SmallVector<MachineOperand, 4> Cond;
393  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
394                          TBB, FBB, Cond)) {
395    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
396    // check whether its answers match up with reality.
397    if (!TBB && !FBB) {
398      // Block falls through to its successor.
399      MachineFunction::const_iterator MBBI = MBB;
400      ++MBBI;
401      if (MBBI == MF->end()) {
402        // It's possible that the block legitimately ends with a noreturn
403        // call or an unreachable, in which case it won't actually fall
404        // out the bottom of the function.
405      } else if (MBB->succ_size() == LandingPadSuccs) {
406        // It's possible that the block legitimately ends with a noreturn
407        // call or an unreachable, in which case it won't actuall fall
408        // out of the block.
409      } else if (MBB->succ_size() != 1+LandingPadSuccs) {
410        report("MBB exits via unconditional fall-through but doesn't have "
411               "exactly one CFG successor!", MBB);
412      } else if (!MBB->isSuccessor(MBBI)) {
413        report("MBB exits via unconditional fall-through but its successor "
414               "differs from its CFG successor!", MBB);
415      }
416      if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
417          !TII->isPredicated(&MBB->back())) {
418        report("MBB exits via unconditional fall-through but ends with a "
419               "barrier instruction!", MBB);
420      }
421      if (!Cond.empty()) {
422        report("MBB exits via unconditional fall-through but has a condition!",
423               MBB);
424      }
425    } else if (TBB && !FBB && Cond.empty()) {
426      // Block unconditionally branches somewhere.
427      if (MBB->succ_size() != 1+LandingPadSuccs) {
428        report("MBB exits via unconditional branch but doesn't have "
429               "exactly one CFG successor!", MBB);
430      } else if (!MBB->isSuccessor(TBB)) {
431        report("MBB exits via unconditional branch but the CFG "
432               "successor doesn't match the actual successor!", MBB);
433      }
434      if (MBB->empty()) {
435        report("MBB exits via unconditional branch but doesn't contain "
436               "any instructions!", MBB);
437      } else if (!MBB->back().getDesc().isBarrier()) {
438        report("MBB exits via unconditional branch but doesn't end with a "
439               "barrier instruction!", MBB);
440      } else if (!MBB->back().getDesc().isTerminator()) {
441        report("MBB exits via unconditional branch but the branch isn't a "
442               "terminator instruction!", MBB);
443      }
444    } else if (TBB && !FBB && !Cond.empty()) {
445      // Block conditionally branches somewhere, otherwise falls through.
446      MachineFunction::const_iterator MBBI = MBB;
447      ++MBBI;
448      if (MBBI == MF->end()) {
449        report("MBB conditionally falls through out of function!", MBB);
450      } if (MBB->succ_size() != 2) {
451        report("MBB exits via conditional branch/fall-through but doesn't have "
452               "exactly two CFG successors!", MBB);
453      } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
454        report("MBB exits via conditional branch/fall-through but the CFG "
455               "successors don't match the actual successors!", MBB);
456      }
457      if (MBB->empty()) {
458        report("MBB exits via conditional branch/fall-through but doesn't "
459               "contain any instructions!", MBB);
460      } else if (MBB->back().getDesc().isBarrier()) {
461        report("MBB exits via conditional branch/fall-through but ends with a "
462               "barrier instruction!", MBB);
463      } else if (!MBB->back().getDesc().isTerminator()) {
464        report("MBB exits via conditional branch/fall-through but the branch "
465               "isn't a terminator instruction!", MBB);
466      }
467    } else if (TBB && FBB) {
468      // Block conditionally branches somewhere, otherwise branches
469      // somewhere else.
470      if (MBB->succ_size() != 2) {
471        report("MBB exits via conditional branch/branch but doesn't have "
472               "exactly two CFG successors!", MBB);
473      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
474        report("MBB exits via conditional branch/branch but the CFG "
475               "successors don't match the actual successors!", MBB);
476      }
477      if (MBB->empty()) {
478        report("MBB exits via conditional branch/branch but doesn't "
479               "contain any instructions!", MBB);
480      } else if (!MBB->back().getDesc().isBarrier()) {
481        report("MBB exits via conditional branch/branch but doesn't end with a "
482               "barrier instruction!", MBB);
483      } else if (!MBB->back().getDesc().isTerminator()) {
484        report("MBB exits via conditional branch/branch but the branch "
485               "isn't a terminator instruction!", MBB);
486      }
487      if (Cond.empty()) {
488        report("MBB exits via conditinal branch/branch but there's no "
489               "condition!", MBB);
490      }
491    } else {
492      report("AnalyzeBranch returned invalid data!", MBB);
493    }
494  }
495
496  regsLive.clear();
497  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
498         E = MBB->livein_end(); I != E; ++I) {
499    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
500      report("MBB live-in list contains non-physical register", MBB);
501      continue;
502    }
503    regsLive.insert(*I);
504    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
505      regsLive.insert(*R);
506  }
507  regsLiveInButUnused = regsLive;
508
509  const MachineFrameInfo *MFI = MF->getFrameInfo();
510  assert(MFI && "Function has no frame info");
511  BitVector PR = MFI->getPristineRegs(MBB);
512  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
513    regsLive.insert(I);
514    for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
515      regsLive.insert(*R);
516  }
517
518  regsKilled.clear();
519  regsDefined.clear();
520}
521
522void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
523  const TargetInstrDesc &TI = MI->getDesc();
524  if (MI->getNumOperands() < TI.getNumOperands()) {
525    report("Too few operands", MI);
526    *OS << TI.getNumOperands() << " operands expected, but "
527        << MI->getNumExplicitOperands() << " given.\n";
528  }
529
530  // Check the MachineMemOperands for basic consistency.
531  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
532       E = MI->memoperands_end(); I != E; ++I) {
533    if ((*I)->isLoad() && !TI.mayLoad())
534      report("Missing mayLoad flag", MI);
535    if ((*I)->isStore() && !TI.mayStore())
536      report("Missing mayStore flag", MI);
537  }
538
539  // Debug values must not have a slot index.
540  // Other instructions must have one.
541  if (LiveInts) {
542    bool mapped = !LiveInts->isNotInMIMap(MI);
543    if (MI->isDebugValue()) {
544      if (mapped)
545        report("Debug instruction has a slot index", MI);
546    } else {
547      if (!mapped)
548        report("Missing slot index", MI);
549    }
550  }
551
552}
553
554void
555MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
556  const MachineInstr *MI = MO->getParent();
557  const TargetInstrDesc &TI = MI->getDesc();
558  const TargetOperandInfo &TOI = TI.OpInfo[MONum];
559
560  // The first TI.NumDefs operands must be explicit register defines
561  if (MONum < TI.getNumDefs()) {
562    if (!MO->isReg())
563      report("Explicit definition must be a register", MO, MONum);
564    else if (!MO->isDef())
565      report("Explicit definition marked as use", MO, MONum);
566    else if (MO->isImplicit())
567      report("Explicit definition marked as implicit", MO, MONum);
568  } else if (MONum < TI.getNumOperands()) {
569    // Don't check if it's the last operand in a variadic instruction. See,
570    // e.g., LDM_RET in the arm back end.
571    if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
572      if (MO->isDef() && !TOI.isOptionalDef())
573          report("Explicit operand marked as def", MO, MONum);
574      if (MO->isImplicit())
575        report("Explicit operand marked as implicit", MO, MONum);
576    }
577  } else {
578    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
579    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
580      report("Extra explicit operand on non-variadic instruction", MO, MONum);
581  }
582
583  switch (MO->getType()) {
584  case MachineOperand::MO_Register: {
585    const unsigned Reg = MO->getReg();
586    if (!Reg)
587      return;
588
589    // Check Live Variables.
590    if (MO->isUndef()) {
591      // An <undef> doesn't refer to any register, so just skip it.
592    } else if (MO->isUse()) {
593      regsLiveInButUnused.erase(Reg);
594
595      bool isKill = false;
596      unsigned defIdx;
597      if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
598        // A two-addr use counts as a kill if use and def are the same.
599        unsigned DefReg = MI->getOperand(defIdx).getReg();
600        if (Reg == DefReg) {
601          isKill = true;
602          // And in that case an explicit kill flag is not allowed.
603          if (MO->isKill())
604            report("Illegal kill flag on two-address instruction operand",
605                   MO, MONum);
606        } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
607          report("Two-address instruction operands must be identical",
608                 MO, MONum);
609        }
610      } else
611        isKill = MO->isKill();
612
613      if (isKill)
614        addRegWithSubRegs(regsKilled, Reg);
615
616      // Check that LiveVars knows this kill.
617      if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
618          MO->isKill()) {
619        LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
620        if (std::find(VI.Kills.begin(),
621                      VI.Kills.end(), MI) == VI.Kills.end())
622          report("Kill missing from LiveVariables", MO, MONum);
623      }
624
625      // Check LiveInts liveness and kill.
626      if (TargetRegisterInfo::isVirtualRegister(Reg) &&
627          LiveInts && !LiveInts->isNotInMIMap(MI)) {
628        SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getUseIndex();
629        if (LiveInts->hasInterval(Reg)) {
630          const LiveInterval &LI = LiveInts->getInterval(Reg);
631          if (!LI.liveAt(UseIdx)) {
632            report("No live range at use", MO, MONum);
633            *OS << UseIdx << " is not live in " << LI << '\n';
634          }
635          // Verify isKill == LI.killedAt.
636          // Two-address instrs don't have kill flags on the tied operands, and
637          // we even allow
638          //   %r1 = add %r1, %r1
639          // without a kill flag on the untied operand.
640          // MI->findRegisterUseOperandIdx finds the first operand using reg.
641          if (!MI->isRegTiedToDefOperand(MI->findRegisterUseOperandIdx(Reg))) {
642            // MI could kill register without a kill flag on MO.
643            bool miKill = MI->killsRegister(Reg);
644            bool liKill = LI.killedAt(UseIdx.getDefIndex());
645            if (miKill && !liKill) {
646              report("Live range continues after kill flag", MO, MONum);
647              *OS << "Live range: " << LI << '\n';
648            }
649            if (!miKill && liKill) {
650              report("Live range ends without kill flag", MO, MONum);
651              *OS << "Live range: " << LI << '\n';
652            }
653          }
654        } else {
655          report("Virtual register has no Live interval", MO, MONum);
656        }
657      }
658
659      // Use of a dead register.
660      if (!regsLive.count(Reg)) {
661        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
662          // Reserved registers may be used even when 'dead'.
663          if (!isReserved(Reg))
664            report("Using an undefined physical register", MO, MONum);
665        } else {
666          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
667          // We don't know which virtual registers are live in, so only complain
668          // if vreg was killed in this MBB. Otherwise keep track of vregs that
669          // must be live in. PHI instructions are handled separately.
670          if (MInfo.regsKilled.count(Reg))
671            report("Using a killed virtual register", MO, MONum);
672          else if (!MI->isPHI())
673            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
674        }
675      }
676    } else {
677      assert(MO->isDef());
678      // Register defined.
679      // TODO: verify that earlyclobber ops are not used.
680      if (MO->isDead())
681        addRegWithSubRegs(regsDead, Reg);
682      else
683        addRegWithSubRegs(regsDefined, Reg);
684
685      // Check LiveInts for a live range, but only for virtual registers.
686      if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
687          !LiveInts->isNotInMIMap(MI)) {
688        SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getDefIndex();
689        if (LiveInts->hasInterval(Reg)) {
690          const LiveInterval &LI = LiveInts->getInterval(Reg);
691          if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
692            assert(VNI && "NULL valno is not allowed");
693            if (VNI->def != DefIdx) {
694              report("Inconsistent valno->def", MO, MONum);
695              *OS << "Valno " << VNI->id << " is not defined at "
696                  << DefIdx << " in " << LI << '\n';
697            }
698          } else {
699            report("No live range at def", MO, MONum);
700            *OS << DefIdx << " is not live in " << LI << '\n';
701          }
702        } else {
703          report("Virtual register has no Live interval", MO, MONum);
704        }
705      }
706    }
707
708    // Check register classes.
709    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
710      unsigned SubIdx = MO->getSubReg();
711
712      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
713        unsigned sr = Reg;
714        if (SubIdx) {
715          unsigned s = TRI->getSubReg(Reg, SubIdx);
716          if (!s) {
717            report("Invalid subregister index for physical register",
718                   MO, MONum);
719            return;
720          }
721          sr = s;
722        }
723        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
724          if (!DRC->contains(sr)) {
725            report("Illegal physical register for instruction", MO, MONum);
726            *OS << TRI->getName(sr) << " is not a "
727                << DRC->getName() << " register.\n";
728          }
729        }
730      } else {
731        // Virtual register.
732        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
733        if (SubIdx) {
734          const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
735          if (!SRC) {
736            report("Invalid subregister index for virtual register", MO, MONum);
737            *OS << "Register class " << RC->getName()
738                << " does not support subreg index " << SubIdx << "\n";
739            return;
740          }
741          RC = SRC;
742        }
743        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
744          if (RC != DRC && !RC->hasSuperClass(DRC)) {
745            report("Illegal virtual register for instruction", MO, MONum);
746            *OS << "Expected a " << DRC->getName() << " register, but got a "
747                << RC->getName() << " register\n";
748          }
749        }
750      }
751    }
752    break;
753  }
754
755  case MachineOperand::MO_MachineBasicBlock:
756    if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
757      report("PHI operand is not in the CFG", MO, MONum);
758    break;
759
760  case MachineOperand::MO_FrameIndex:
761    if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
762        LiveInts && !LiveInts->isNotInMIMap(MI)) {
763      LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
764      SlotIndex Idx = LiveInts->getInstructionIndex(MI);
765      if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) {
766        report("Instruction loads from dead spill slot", MO, MONum);
767        *OS << "Live stack: " << LI << '\n';
768      }
769      if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) {
770        report("Instruction stores to dead spill slot", MO, MONum);
771        *OS << "Live stack: " << LI << '\n';
772      }
773    }
774    break;
775
776  default:
777    break;
778  }
779}
780
781void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
782  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
783  set_union(MInfo.regsKilled, regsKilled);
784  set_subtract(regsLive, regsKilled); regsKilled.clear();
785  set_subtract(regsLive, regsDead);   regsDead.clear();
786  set_union(regsLive, regsDefined);   regsDefined.clear();
787}
788
789void
790MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
791  MBBInfoMap[MBB].regsLiveOut = regsLive;
792  regsLive.clear();
793}
794
795// Calculate the largest possible vregsPassed sets. These are the registers that
796// can pass through an MBB live, but may not be live every time. It is assumed
797// that all vregsPassed sets are empty before the call.
798void MachineVerifier::calcRegsPassed() {
799  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
800  // have any vregsPassed.
801  DenseSet<const MachineBasicBlock*> todo;
802  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
803       MFI != MFE; ++MFI) {
804    const MachineBasicBlock &MBB(*MFI);
805    BBInfo &MInfo = MBBInfoMap[&MBB];
806    if (!MInfo.reachable)
807      continue;
808    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
809           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
810      BBInfo &SInfo = MBBInfoMap[*SuI];
811      if (SInfo.addPassed(MInfo.regsLiveOut))
812        todo.insert(*SuI);
813    }
814  }
815
816  // Iteratively push vregsPassed to successors. This will converge to the same
817  // final state regardless of DenseSet iteration order.
818  while (!todo.empty()) {
819    const MachineBasicBlock *MBB = *todo.begin();
820    todo.erase(MBB);
821    BBInfo &MInfo = MBBInfoMap[MBB];
822    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
823           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
824      if (*SuI == MBB)
825        continue;
826      BBInfo &SInfo = MBBInfoMap[*SuI];
827      if (SInfo.addPassed(MInfo.vregsPassed))
828        todo.insert(*SuI);
829    }
830  }
831}
832
833// Calculate the set of virtual registers that must be passed through each basic
834// block in order to satisfy the requirements of successor blocks. This is very
835// similar to calcRegsPassed, only backwards.
836void MachineVerifier::calcRegsRequired() {
837  // First push live-in regs to predecessors' vregsRequired.
838  DenseSet<const MachineBasicBlock*> todo;
839  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
840       MFI != MFE; ++MFI) {
841    const MachineBasicBlock &MBB(*MFI);
842    BBInfo &MInfo = MBBInfoMap[&MBB];
843    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
844           PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
845      BBInfo &PInfo = MBBInfoMap[*PrI];
846      if (PInfo.addRequired(MInfo.vregsLiveIn))
847        todo.insert(*PrI);
848    }
849  }
850
851  // Iteratively push vregsRequired to predecessors. This will converge to the
852  // same final state regardless of DenseSet iteration order.
853  while (!todo.empty()) {
854    const MachineBasicBlock *MBB = *todo.begin();
855    todo.erase(MBB);
856    BBInfo &MInfo = MBBInfoMap[MBB];
857    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
858           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
859      if (*PrI == MBB)
860        continue;
861      BBInfo &SInfo = MBBInfoMap[*PrI];
862      if (SInfo.addRequired(MInfo.vregsRequired))
863        todo.insert(*PrI);
864    }
865  }
866}
867
868// Check PHI instructions at the beginning of MBB. It is assumed that
869// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
870void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
871  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
872       BBI != BBE && BBI->isPHI(); ++BBI) {
873    DenseSet<const MachineBasicBlock*> seen;
874
875    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
876      unsigned Reg = BBI->getOperand(i).getReg();
877      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
878      if (!Pre->isSuccessor(MBB))
879        continue;
880      seen.insert(Pre);
881      BBInfo &PrInfo = MBBInfoMap[Pre];
882      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
883        report("PHI operand is not live-out from predecessor",
884               &BBI->getOperand(i), i);
885    }
886
887    // Did we see all predecessors?
888    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
889           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
890      if (!seen.count(*PrI)) {
891        report("Missing PHI operand", BBI);
892        *OS << "BB#" << (*PrI)->getNumber()
893            << " is a predecessor according to the CFG.\n";
894      }
895    }
896  }
897}
898
899void MachineVerifier::visitMachineFunctionAfter() {
900  calcRegsPassed();
901
902  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
903       MFI != MFE; ++MFI) {
904    BBInfo &MInfo = MBBInfoMap[MFI];
905
906    // Skip unreachable MBBs.
907    if (!MInfo.reachable)
908      continue;
909
910    checkPHIOps(MFI);
911  }
912
913  // Now check liveness info if available
914  if (LiveVars || LiveInts)
915    calcRegsRequired();
916  if (LiveVars)
917    verifyLiveVariables();
918  if (LiveInts)
919    verifyLiveIntervals();
920}
921
922void MachineVerifier::verifyLiveVariables() {
923  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
924  for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
925         RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
926    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
927    for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
928         MFI != MFE; ++MFI) {
929      BBInfo &MInfo = MBBInfoMap[MFI];
930
931      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
932      if (MInfo.vregsRequired.count(Reg)) {
933        if (!VI.AliveBlocks.test(MFI->getNumber())) {
934          report("LiveVariables: Block missing from AliveBlocks", MFI);
935          *OS << "Virtual register %reg" << Reg
936              << " must be live through the block.\n";
937        }
938      } else {
939        if (VI.AliveBlocks.test(MFI->getNumber())) {
940          report("LiveVariables: Block should not be in AliveBlocks", MFI);
941          *OS << "Virtual register %reg" << Reg
942              << " is not needed live through the block.\n";
943        }
944      }
945    }
946  }
947}
948
949void MachineVerifier::verifyLiveIntervals() {
950  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
951  for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
952       LVE = LiveInts->end(); LVI != LVE; ++LVI) {
953    const LiveInterval &LI = *LVI->second;
954
955    // Spilling and splitting may leave unused registers around. Skip them.
956    if (MRI->use_empty(LI.reg))
957      continue;
958
959    // Physical registers have much weirdness going on, mostly from coalescing.
960    // We should probably fix it, but for now just ignore them.
961    if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
962      continue;
963
964    assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
965
966    for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
967         I!=E; ++I) {
968      VNInfo *VNI = *I;
969      const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
970
971      if (!DefVNI) {
972        if (!VNI->isUnused()) {
973          report("Valno not live at def and not marked unused", MF);
974          *OS << "Valno #" << VNI->id << " in " << LI << '\n';
975        }
976        continue;
977      }
978
979      if (VNI->isUnused())
980        continue;
981
982      if (DefVNI != VNI) {
983        report("Live range at def has different valno", MF);
984        *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
985            << " where valno #" << DefVNI->id << " is live in " << LI << '\n';
986        continue;
987      }
988
989      const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
990      if (!MBB) {
991        report("Invalid definition index", MF);
992        *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
993            << " in " << LI << '\n';
994        continue;
995      }
996
997      if (VNI->isPHIDef()) {
998        if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
999          report("PHIDef value is not defined at MBB start", MF);
1000          *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1001              << ", not at the beginning of BB#" << MBB->getNumber()
1002              << " in " << LI << '\n';
1003        }
1004      } else {
1005        // Non-PHI def.
1006        if (!VNI->def.isDef()) {
1007          report("Non-PHI def must be at a DEF slot", MF);
1008          *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1009              << " in " << LI << '\n';
1010        }
1011        const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1012        if (!MI) {
1013          report("No instruction at def index", MF);
1014          *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1015              << " in " << LI << '\n';
1016        } else if (!MI->modifiesRegister(LI.reg, TRI)) {
1017          report("Defining instruction does not modify register", MI);
1018          *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1019        }
1020      }
1021    }
1022
1023    for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
1024      const VNInfo *VNI = I->valno;
1025      assert(VNI && "Live range has no valno");
1026
1027      if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1028        report("Foreign valno in live range", MF);
1029        I->print(*OS);
1030        *OS << " has a valno not in " << LI << '\n';
1031      }
1032
1033      if (VNI->isUnused()) {
1034        report("Live range valno is marked unused", MF);
1035        I->print(*OS);
1036        *OS << " in " << LI << '\n';
1037      }
1038
1039      const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
1040      if (!MBB) {
1041        report("Bad start of live segment, no basic block", MF);
1042        I->print(*OS);
1043        *OS << " in " << LI << '\n';
1044        continue;
1045      }
1046      SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1047      if (I->start != MBBStartIdx && I->start != VNI->def) {
1048        report("Live segment must begin at MBB entry or valno def", MBB);
1049        I->print(*OS);
1050        *OS << " in " << LI << '\n' << "Basic block starts at "
1051            << MBBStartIdx << '\n';
1052      }
1053
1054      const MachineBasicBlock *EndMBB =
1055                                LiveInts->getMBBFromIndex(I->end.getPrevSlot());
1056      if (!EndMBB) {
1057        report("Bad end of live segment, no basic block", MF);
1058        I->print(*OS);
1059        *OS << " in " << LI << '\n';
1060        continue;
1061      }
1062      if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
1063        // The live segment is ending inside EndMBB
1064        const MachineInstr *MI =
1065                        LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
1066        if (!MI) {
1067          report("Live segment doesn't end at a valid instruction", EndMBB);
1068        I->print(*OS);
1069        *OS << " in " << LI << '\n' << "Basic block starts at "
1070            << MBBStartIdx << '\n';
1071        } else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1072                   !MI->readsVirtualRegister(LI.reg)) {
1073          // FIXME: Should we require a kill flag?
1074          report("Instruction killing live segment doesn't read register", MI);
1075          I->print(*OS);
1076          *OS << " in " << LI << '\n';
1077        }
1078      }
1079
1080      // Now check all the basic blocks in this live segment.
1081      MachineFunction::const_iterator MFI = MBB;
1082      // Is LI live-in to MBB and not a PHIDef?
1083      if (I->start == VNI->def) {
1084        // Not live-in to any blocks.
1085        if (MBB == EndMBB)
1086          continue;
1087        // Skip this block.
1088        ++MFI;
1089      }
1090      for (;;) {
1091        assert(LiveInts->isLiveInToMBB(LI, MFI));
1092        // We don't know how to track physregs into a landing pad.
1093        if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
1094            MFI->isLandingPad()) {
1095          if (&*MFI == EndMBB)
1096            break;
1097          ++MFI;
1098          continue;
1099        }
1100        // Check that VNI is live-out of all predecessors.
1101        for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1102             PE = MFI->pred_end(); PI != PE; ++PI) {
1103          SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
1104          const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
1105          if (!PVNI) {
1106            report("Register not marked live out of predecessor", *PI);
1107            *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1108                << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
1109                << PEnd << " in " << LI << '\n';
1110          } else if (PVNI != VNI) {
1111            report("Different value live out of predecessor", *PI);
1112            *OS << "Valno #" << PVNI->id << " live out of BB#"
1113                << (*PI)->getNumber() << '@' << PEnd
1114                << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1115                << '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
1116          }
1117        }
1118        if (&*MFI == EndMBB)
1119          break;
1120        ++MFI;
1121      }
1122    }
1123
1124    // Check the LI only has one connected component.
1125    if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1126      ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1127      unsigned NumComp = ConEQ.Classify(&LI);
1128      if (NumComp > 1) {
1129        report("Multiple connected components in live interval", MF);
1130        *OS << NumComp << " components in " << LI << '\n';
1131        for (unsigned comp = 0; comp != NumComp; ++comp) {
1132          *OS << comp << ": valnos";
1133          for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1134               E = LI.vni_end(); I!=E; ++I)
1135            if (comp == ConEQ.getEqClass(*I))
1136              *OS << ' ' << (*I)->id;
1137          *OS << '\n';
1138        }
1139      }
1140    }
1141  }
1142}
1143
1144