MachineVerifier.cpp revision 24ff056654cd4eae6c6403b81dfceaa46605f395 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/Function.h"
27#include "llvm/CodeGen/LiveVariables.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/ADT/DenseSet.h"
37#include "llvm/ADT/SetOperations.h"
38#include "llvm/ADT/SmallVector.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/raw_ostream.h"
42using namespace llvm;
43
44namespace {
45  struct MachineVerifier {
46
47    MachineVerifier(Pass *pass, bool allowDoubleDefs) :
48      PASS(pass),
49      allowVirtDoubleDefs(allowDoubleDefs),
50      allowPhysDoubleDefs(true),
51      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
52      {}
53
54    bool runOnMachineFunction(MachineFunction &MF);
55
56    Pass *const PASS;
57    const bool allowVirtDoubleDefs;
58    const bool allowPhysDoubleDefs;
59
60    const char *const OutFileName;
61    raw_ostream *OS;
62    const MachineFunction *MF;
63    const TargetMachine *TM;
64    const TargetRegisterInfo *TRI;
65    const MachineRegisterInfo *MRI;
66
67    unsigned foundErrors;
68
69    typedef SmallVector<unsigned, 16> RegVector;
70    typedef DenseSet<unsigned> RegSet;
71    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
72
73    BitVector regsReserved;
74    RegSet regsLive;
75    RegVector regsDefined, regsDead, regsKilled;
76    RegSet regsLiveInButUnused;
77
78    // Add Reg and any sub-registers to RV
79    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
80      RV.push_back(Reg);
81      if (TargetRegisterInfo::isPhysicalRegister(Reg))
82        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
83          RV.push_back(*R);
84    }
85
86    struct BBInfo {
87      // Is this MBB reachable from the MF entry point?
88      bool reachable;
89
90      // Vregs that must be live in because they are used without being
91      // defined. Map value is the user.
92      RegMap vregsLiveIn;
93
94      // Vregs that must be dead in because they are defined without being
95      // killed first. Map value is the defining instruction.
96      RegMap vregsDeadIn;
97
98      // Regs killed in MBB. They may be defined again, and will then be in both
99      // regsKilled and regsLiveOut.
100      RegSet regsKilled;
101
102      // Regs defined in MBB and live out. Note that vregs passing through may
103      // be live out without being mentioned here.
104      RegSet regsLiveOut;
105
106      // Vregs that pass through MBB untouched. This set is disjoint from
107      // regsKilled and regsLiveOut.
108      RegSet vregsPassed;
109
110      // Vregs that must pass through MBB because they are needed by a successor
111      // block. This set is disjoint from regsLiveOut.
112      RegSet vregsRequired;
113
114      BBInfo() : reachable(false) {}
115
116      // Add register to vregsPassed if it belongs there. Return true if
117      // anything changed.
118      bool addPassed(unsigned Reg) {
119        if (!TargetRegisterInfo::isVirtualRegister(Reg))
120          return false;
121        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
122          return false;
123        return vregsPassed.insert(Reg).second;
124      }
125
126      // Same for a full set.
127      bool addPassed(const RegSet &RS) {
128        bool changed = false;
129        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
130          if (addPassed(*I))
131            changed = true;
132        return changed;
133      }
134
135      // Add register to vregsRequired if it belongs there. Return true if
136      // anything changed.
137      bool addRequired(unsigned Reg) {
138        if (!TargetRegisterInfo::isVirtualRegister(Reg))
139          return false;
140        if (regsLiveOut.count(Reg))
141          return false;
142        return vregsRequired.insert(Reg).second;
143      }
144
145      // Same for a full set.
146      bool addRequired(const RegSet &RS) {
147        bool changed = false;
148        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
149          if (addRequired(*I))
150            changed = true;
151        return changed;
152      }
153
154      // Same for a full map.
155      bool addRequired(const RegMap &RM) {
156        bool changed = false;
157        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
158          if (addRequired(I->first))
159            changed = true;
160        return changed;
161      }
162
163      // Live-out registers are either in regsLiveOut or vregsPassed.
164      bool isLiveOut(unsigned Reg) const {
165        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
166      }
167    };
168
169    // Extra register info per MBB.
170    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
171
172    bool isReserved(unsigned Reg) {
173      return Reg < regsReserved.size() && regsReserved.test(Reg);
174    }
175
176    // Analysis information if available
177    LiveVariables *LiveVars;
178
179    void visitMachineFunctionBefore();
180    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
181    void visitMachineInstrBefore(const MachineInstr *MI);
182    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
183    void visitMachineInstrAfter(const MachineInstr *MI);
184    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
185    void visitMachineFunctionAfter();
186
187    void report(const char *msg, const MachineFunction *MF);
188    void report(const char *msg, const MachineBasicBlock *MBB);
189    void report(const char *msg, const MachineInstr *MI);
190    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
191
192    void markReachable(const MachineBasicBlock *MBB);
193    void calcRegsPassed();
194    void checkPHIOps(const MachineBasicBlock *MBB);
195
196    void calcRegsRequired();
197    void verifyLiveVariables();
198  };
199
200  struct MachineVerifierPass : public MachineFunctionPass {
201    static char ID; // Pass ID, replacement for typeid
202    bool AllowDoubleDefs;
203
204    explicit MachineVerifierPass(bool allowDoubleDefs = false)
205      : MachineFunctionPass(&ID),
206        AllowDoubleDefs(allowDoubleDefs) {}
207
208    void getAnalysisUsage(AnalysisUsage &AU) const {
209      AU.setPreservesAll();
210      MachineFunctionPass::getAnalysisUsage(AU);
211    }
212
213    bool runOnMachineFunction(MachineFunction &MF) {
214      MF.verify(this, AllowDoubleDefs);
215      return false;
216    }
217  };
218
219}
220
221char MachineVerifierPass::ID = 0;
222static RegisterPass<MachineVerifierPass>
223MachineVer("machineverifier", "Verify generated machine code");
224static const PassInfo *const MachineVerifyID = &MachineVer;
225
226FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
227  return new MachineVerifierPass(allowPhysDoubleDefs);
228}
229
230void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
231  MachineVerifier(p, allowDoubleDefs)
232    .runOnMachineFunction(const_cast<MachineFunction&>(*this));
233}
234
235bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
236  raw_ostream *OutFile = 0;
237  if (OutFileName) {
238    std::string ErrorInfo;
239    OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
240                                 raw_fd_ostream::F_Append);
241    if (!ErrorInfo.empty()) {
242      errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
243      exit(1);
244    }
245
246    OS = OutFile;
247  } else {
248    OS = &errs();
249  }
250
251  foundErrors = 0;
252
253  this->MF = &MF;
254  TM = &MF.getTarget();
255  TRI = TM->getRegisterInfo();
256  MRI = &MF.getRegInfo();
257
258  if (PASS) {
259    LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
260  } else {
261    LiveVars = NULL;
262  }
263
264  visitMachineFunctionBefore();
265  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
266       MFI!=MFE; ++MFI) {
267    visitMachineBasicBlockBefore(MFI);
268    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
269           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
270      visitMachineInstrBefore(MBBI);
271      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
272        visitMachineOperand(&MBBI->getOperand(I), I);
273      visitMachineInstrAfter(MBBI);
274    }
275    visitMachineBasicBlockAfter(MFI);
276  }
277  visitMachineFunctionAfter();
278
279  if (OutFile)
280    delete OutFile;
281  else if (foundErrors)
282    report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
283
284  // Clean up.
285  regsLive.clear();
286  regsDefined.clear();
287  regsDead.clear();
288  regsKilled.clear();
289  regsLiveInButUnused.clear();
290  MBBInfoMap.clear();
291
292  return false;                 // no changes
293}
294
295void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
296  assert(MF);
297  *OS << '\n';
298  if (!foundErrors++)
299    MF->print(*OS);
300  *OS << "*** Bad machine code: " << msg << " ***\n"
301      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
302}
303
304void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
305  assert(MBB);
306  report(msg, MBB->getParent());
307  *OS << "- basic block: " << MBB->getName()
308      << " " << (void*)MBB
309      << " (BB#" << MBB->getNumber() << ")\n";
310}
311
312void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
313  assert(MI);
314  report(msg, MI->getParent());
315  *OS << "- instruction: ";
316  MI->print(*OS, TM);
317}
318
319void MachineVerifier::report(const char *msg,
320                             const MachineOperand *MO, unsigned MONum) {
321  assert(MO);
322  report(msg, MO->getParent());
323  *OS << "- operand " << MONum << ":   ";
324  MO->print(*OS, TM);
325  *OS << "\n";
326}
327
328void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
329  BBInfo &MInfo = MBBInfoMap[MBB];
330  if (!MInfo.reachable) {
331    MInfo.reachable = true;
332    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
333           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
334      markReachable(*SuI);
335  }
336}
337
338void MachineVerifier::visitMachineFunctionBefore() {
339  regsReserved = TRI->getReservedRegs(*MF);
340
341  // A sub-register of a reserved register is also reserved
342  for (int Reg = regsReserved.find_first(); Reg>=0;
343       Reg = regsReserved.find_next(Reg)) {
344    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
345      // FIXME: This should probably be:
346      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
347      regsReserved.set(*Sub);
348    }
349  }
350  markReachable(&MF->front());
351}
352
353// Does iterator point to a and b as the first two elements?
354static bool matchPair(MachineBasicBlock::const_succ_iterator i,
355                      const MachineBasicBlock *a, const MachineBasicBlock *b) {
356  if (*i == a)
357    return *++i == b;
358  if (*i == b)
359    return *++i == a;
360  return false;
361}
362
363void
364MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
365  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
366
367  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
368  MachineBasicBlock *TBB = 0, *FBB = 0;
369  SmallVector<MachineOperand, 4> Cond;
370  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
371                          TBB, FBB, Cond)) {
372    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
373    // check whether its answers match up with reality.
374    if (!TBB && !FBB) {
375      // Block falls through to its successor.
376      MachineFunction::const_iterator MBBI = MBB;
377      ++MBBI;
378      if (MBBI == MF->end()) {
379        // It's possible that the block legitimately ends with a noreturn
380        // call or an unreachable, in which case it won't actually fall
381        // out the bottom of the function.
382      } else if (MBB->succ_empty()) {
383        // It's possible that the block legitimately ends with a noreturn
384        // call or an unreachable, in which case it won't actuall fall
385        // out of the block.
386      } else if (MBB->succ_size() != 1) {
387        report("MBB exits via unconditional fall-through but doesn't have "
388               "exactly one CFG successor!", MBB);
389      } else if (MBB->succ_begin()[0] != MBBI) {
390        report("MBB exits via unconditional fall-through but its successor "
391               "differs from its CFG successor!", MBB);
392      }
393      if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
394          !TII->isPredicated(&MBB->back())) {
395        report("MBB exits via unconditional fall-through but ends with a "
396               "barrier instruction!", MBB);
397      }
398      if (!Cond.empty()) {
399        report("MBB exits via unconditional fall-through but has a condition!",
400               MBB);
401      }
402    } else if (TBB && !FBB && Cond.empty()) {
403      // Block unconditionally branches somewhere.
404      if (MBB->succ_size() != 1) {
405        report("MBB exits via unconditional branch but doesn't have "
406               "exactly one CFG successor!", MBB);
407      } else if (MBB->succ_begin()[0] != TBB) {
408        report("MBB exits via unconditional branch but the CFG "
409               "successor doesn't match the actual successor!", MBB);
410      }
411      if (MBB->empty()) {
412        report("MBB exits via unconditional branch but doesn't contain "
413               "any instructions!", MBB);
414      } else if (!MBB->back().getDesc().isBarrier()) {
415        report("MBB exits via unconditional branch but doesn't end with a "
416               "barrier instruction!", MBB);
417      } else if (!MBB->back().getDesc().isTerminator()) {
418        report("MBB exits via unconditional branch but the branch isn't a "
419               "terminator instruction!", MBB);
420      }
421    } else if (TBB && !FBB && !Cond.empty()) {
422      // Block conditionally branches somewhere, otherwise falls through.
423      MachineFunction::const_iterator MBBI = MBB;
424      ++MBBI;
425      if (MBBI == MF->end()) {
426        report("MBB conditionally falls through out of function!", MBB);
427      } if (MBB->succ_size() != 2) {
428        report("MBB exits via conditional branch/fall-through but doesn't have "
429               "exactly two CFG successors!", MBB);
430      } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
431        report("MBB exits via conditional branch/fall-through but the CFG "
432               "successors don't match the actual successors!", MBB);
433      }
434      if (MBB->empty()) {
435        report("MBB exits via conditional branch/fall-through but doesn't "
436               "contain any instructions!", MBB);
437      } else if (MBB->back().getDesc().isBarrier()) {
438        report("MBB exits via conditional branch/fall-through but ends with a "
439               "barrier instruction!", MBB);
440      } else if (!MBB->back().getDesc().isTerminator()) {
441        report("MBB exits via conditional branch/fall-through but the branch "
442               "isn't a terminator instruction!", MBB);
443      }
444    } else if (TBB && FBB) {
445      // Block conditionally branches somewhere, otherwise branches
446      // somewhere else.
447      if (MBB->succ_size() != 2) {
448        report("MBB exits via conditional branch/branch but doesn't have "
449               "exactly two CFG successors!", MBB);
450      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
451        report("MBB exits via conditional branch/branch but the CFG "
452               "successors don't match the actual successors!", MBB);
453      }
454      if (MBB->empty()) {
455        report("MBB exits via conditional branch/branch but doesn't "
456               "contain any instructions!", MBB);
457      } else if (!MBB->back().getDesc().isBarrier()) {
458        report("MBB exits via conditional branch/branch but doesn't end with a "
459               "barrier instruction!", MBB);
460      } else if (!MBB->back().getDesc().isTerminator()) {
461        report("MBB exits via conditional branch/branch but the branch "
462               "isn't a terminator instruction!", MBB);
463      }
464      if (Cond.empty()) {
465        report("MBB exits via conditinal branch/branch but there's no "
466               "condition!", MBB);
467      }
468    } else {
469      report("AnalyzeBranch returned invalid data!", MBB);
470    }
471  }
472
473  regsLive.clear();
474  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
475         E = MBB->livein_end(); I != E; ++I) {
476    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
477      report("MBB live-in list contains non-physical register", MBB);
478      continue;
479    }
480    regsLive.insert(*I);
481    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
482      regsLive.insert(*R);
483  }
484  regsLiveInButUnused = regsLive;
485
486  const MachineFrameInfo *MFI = MF->getFrameInfo();
487  assert(MFI && "Function has no frame info");
488  BitVector PR = MFI->getPristineRegs(MBB);
489  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
490    regsLive.insert(I);
491    for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
492      regsLive.insert(*R);
493  }
494
495  regsKilled.clear();
496  regsDefined.clear();
497}
498
499void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
500  const TargetInstrDesc &TI = MI->getDesc();
501  if (MI->getNumOperands() < TI.getNumOperands()) {
502    report("Too few operands", MI);
503    *OS << TI.getNumOperands() << " operands expected, but "
504        << MI->getNumExplicitOperands() << " given.\n";
505  }
506
507  // Check the MachineMemOperands for basic consistency.
508  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
509       E = MI->memoperands_end(); I != E; ++I) {
510    if ((*I)->isLoad() && !TI.mayLoad())
511      report("Missing mayLoad flag", MI);
512    if ((*I)->isStore() && !TI.mayStore())
513      report("Missing mayStore flag", MI);
514  }
515}
516
517void
518MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
519  const MachineInstr *MI = MO->getParent();
520  const TargetInstrDesc &TI = MI->getDesc();
521
522  // The first TI.NumDefs operands must be explicit register defines
523  if (MONum < TI.getNumDefs()) {
524    if (!MO->isReg())
525      report("Explicit definition must be a register", MO, MONum);
526    else if (!MO->isDef())
527      report("Explicit definition marked as use", MO, MONum);
528    else if (MO->isImplicit())
529      report("Explicit definition marked as implicit", MO, MONum);
530  } else if (MONum < TI.getNumOperands()) {
531    if (MO->isReg()) {
532      if (MO->isDef())
533        report("Explicit operand marked as def", MO, MONum);
534      if (MO->isImplicit())
535        report("Explicit operand marked as implicit", MO, MONum);
536    }
537  } else {
538    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
539    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
540      report("Extra explicit operand on non-variadic instruction", MO, MONum);
541  }
542
543  switch (MO->getType()) {
544  case MachineOperand::MO_Register: {
545    const unsigned Reg = MO->getReg();
546    if (!Reg)
547      return;
548
549    // Check Live Variables.
550    if (MO->isUndef()) {
551      // An <undef> doesn't refer to any register, so just skip it.
552    } else if (MO->isUse()) {
553      regsLiveInButUnused.erase(Reg);
554
555      bool isKill = false;
556      unsigned defIdx;
557      if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
558        // A two-addr use counts as a kill if use and def are the same.
559        unsigned DefReg = MI->getOperand(defIdx).getReg();
560        if (Reg == DefReg) {
561          isKill = true;
562          // ANd in that case an explicit kill flag is not allowed.
563          if (MO->isKill())
564            report("Illegal kill flag on two-address instruction operand",
565                   MO, MONum);
566        } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
567          report("Two-address instruction operands must be identical",
568                 MO, MONum);
569        }
570      } else
571        isKill = MO->isKill();
572
573      if (isKill) {
574        addRegWithSubRegs(regsKilled, Reg);
575
576        // Check that LiveVars knows this kill
577        if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
578          LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
579          if (std::find(VI.Kills.begin(),
580                        VI.Kills.end(), MI) == VI.Kills.end())
581            report("Kill missing from LiveVariables", MO, MONum);
582        }
583      }
584
585      // Use of a dead register.
586      if (!regsLive.count(Reg)) {
587        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
588          // Reserved registers may be used even when 'dead'.
589          if (!isReserved(Reg))
590            report("Using an undefined physical register", MO, MONum);
591        } else {
592          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
593          // We don't know which virtual registers are live in, so only complain
594          // if vreg was killed in this MBB. Otherwise keep track of vregs that
595          // must be live in. PHI instructions are handled separately.
596          if (MInfo.regsKilled.count(Reg))
597            report("Using a killed virtual register", MO, MONum);
598          else if (!MI->isPHI())
599            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
600        }
601      }
602    } else {
603      assert(MO->isDef());
604      // Register defined.
605      // TODO: verify that earlyclobber ops are not used.
606      if (MO->isDead())
607        addRegWithSubRegs(regsDead, Reg);
608      else
609        addRegWithSubRegs(regsDefined, Reg);
610    }
611
612    // Check register classes.
613    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
614      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
615      unsigned SubIdx = MO->getSubReg();
616
617      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
618        unsigned sr = Reg;
619        if (SubIdx) {
620          unsigned s = TRI->getSubReg(Reg, SubIdx);
621          if (!s) {
622            report("Invalid subregister index for physical register",
623                   MO, MONum);
624            return;
625          }
626          sr = s;
627        }
628        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
629          if (!DRC->contains(sr)) {
630            report("Illegal physical register for instruction", MO, MONum);
631            *OS << TRI->getName(sr) << " is not a "
632                << DRC->getName() << " register.\n";
633          }
634        }
635      } else {
636        // Virtual register.
637        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
638        if (SubIdx) {
639          const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
640          if (!SRC) {
641            report("Invalid subregister index for virtual register", MO, MONum);
642            *OS << "Register class " << RC->getName()
643                << " does not support subreg index " << SubIdx << "\n";
644            return;
645          }
646          RC = SRC;
647        }
648        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
649          if (RC != DRC && !RC->hasSuperClass(DRC)) {
650            report("Illegal virtual register for instruction", MO, MONum);
651            *OS << "Expected a " << DRC->getName() << " register, but got a "
652                << RC->getName() << " register\n";
653          }
654        }
655      }
656    }
657    break;
658  }
659
660  case MachineOperand::MO_MachineBasicBlock:
661    if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
662      report("PHI operand is not in the CFG", MO, MONum);
663    break;
664
665  default:
666    break;
667  }
668}
669
670void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
671  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
672  set_union(MInfo.regsKilled, regsKilled);
673  set_subtract(regsLive, regsKilled);
674  regsKilled.clear();
675
676  // Verify that both <def> and <def,dead> operands refer to dead registers.
677  RegVector defs(regsDefined);
678  defs.append(regsDead.begin(), regsDead.end());
679
680  for (RegVector::const_iterator I = defs.begin(), E = defs.end();
681       I != E; ++I) {
682    if (regsLive.count(*I)) {
683      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
684        if (!allowPhysDoubleDefs && !isReserved(*I) &&
685            !regsLiveInButUnused.count(*I)) {
686          report("Redefining a live physical register", MI);
687          *OS << "Register " << TRI->getName(*I)
688              << " was defined but already live.\n";
689        }
690      } else {
691        if (!allowVirtDoubleDefs) {
692          report("Redefining a live virtual register", MI);
693          *OS << "Virtual register %reg" << *I
694              << " was defined but already live.\n";
695        }
696      }
697    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
698               !MInfo.regsKilled.count(*I)) {
699      // Virtual register defined without being killed first must be dead on
700      // entry.
701      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
702    }
703  }
704
705  set_subtract(regsLive, regsDead); regsDead.clear();
706  set_union(regsLive, regsDefined); regsDefined.clear();
707}
708
709void
710MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
711  MBBInfoMap[MBB].regsLiveOut = regsLive;
712  regsLive.clear();
713}
714
715// Calculate the largest possible vregsPassed sets. These are the registers that
716// can pass through an MBB live, but may not be live every time. It is assumed
717// that all vregsPassed sets are empty before the call.
718void MachineVerifier::calcRegsPassed() {
719  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
720  // have any vregsPassed.
721  DenseSet<const MachineBasicBlock*> todo;
722  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
723       MFI != MFE; ++MFI) {
724    const MachineBasicBlock &MBB(*MFI);
725    BBInfo &MInfo = MBBInfoMap[&MBB];
726    if (!MInfo.reachable)
727      continue;
728    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
729           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
730      BBInfo &SInfo = MBBInfoMap[*SuI];
731      if (SInfo.addPassed(MInfo.regsLiveOut))
732        todo.insert(*SuI);
733    }
734  }
735
736  // Iteratively push vregsPassed to successors. This will converge to the same
737  // final state regardless of DenseSet iteration order.
738  while (!todo.empty()) {
739    const MachineBasicBlock *MBB = *todo.begin();
740    todo.erase(MBB);
741    BBInfo &MInfo = MBBInfoMap[MBB];
742    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
743           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
744      if (*SuI == MBB)
745        continue;
746      BBInfo &SInfo = MBBInfoMap[*SuI];
747      if (SInfo.addPassed(MInfo.vregsPassed))
748        todo.insert(*SuI);
749    }
750  }
751}
752
753// Calculate the set of virtual registers that must be passed through each basic
754// block in order to satisfy the requirements of successor blocks. This is very
755// similar to calcRegsPassed, only backwards.
756void MachineVerifier::calcRegsRequired() {
757  // First push live-in regs to predecessors' vregsRequired.
758  DenseSet<const MachineBasicBlock*> todo;
759  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
760       MFI != MFE; ++MFI) {
761    const MachineBasicBlock &MBB(*MFI);
762    BBInfo &MInfo = MBBInfoMap[&MBB];
763    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
764           PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
765      BBInfo &PInfo = MBBInfoMap[*PrI];
766      if (PInfo.addRequired(MInfo.vregsLiveIn))
767        todo.insert(*PrI);
768    }
769  }
770
771  // Iteratively push vregsRequired to predecessors. This will converge to the
772  // same final state regardless of DenseSet iteration order.
773  while (!todo.empty()) {
774    const MachineBasicBlock *MBB = *todo.begin();
775    todo.erase(MBB);
776    BBInfo &MInfo = MBBInfoMap[MBB];
777    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
778           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
779      if (*PrI == MBB)
780        continue;
781      BBInfo &SInfo = MBBInfoMap[*PrI];
782      if (SInfo.addRequired(MInfo.vregsRequired))
783        todo.insert(*PrI);
784    }
785  }
786}
787
788// Check PHI instructions at the beginning of MBB. It is assumed that
789// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
790void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
791  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
792       BBI != BBE && BBI->isPHI(); ++BBI) {
793    DenseSet<const MachineBasicBlock*> seen;
794
795    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
796      unsigned Reg = BBI->getOperand(i).getReg();
797      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
798      if (!Pre->isSuccessor(MBB))
799        continue;
800      seen.insert(Pre);
801      BBInfo &PrInfo = MBBInfoMap[Pre];
802      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
803        report("PHI operand is not live-out from predecessor",
804               &BBI->getOperand(i), i);
805    }
806
807    // Did we see all predecessors?
808    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
809           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
810      if (!seen.count(*PrI)) {
811        report("Missing PHI operand", BBI);
812        *OS << "BB#" << (*PrI)->getNumber()
813            << " is a predecessor according to the CFG.\n";
814      }
815    }
816  }
817}
818
819void MachineVerifier::visitMachineFunctionAfter() {
820  calcRegsPassed();
821
822  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
823       MFI != MFE; ++MFI) {
824    BBInfo &MInfo = MBBInfoMap[MFI];
825
826    // Skip unreachable MBBs.
827    if (!MInfo.reachable)
828      continue;
829
830    checkPHIOps(MFI);
831
832    // Verify dead-in virtual registers.
833    if (!allowVirtDoubleDefs) {
834      for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
835             PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
836        BBInfo &PrInfo = MBBInfoMap[*PrI];
837        if (!PrInfo.reachable)
838          continue;
839
840        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
841               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
842          // DeadIn register must be in neither regsLiveOut or vregsPassed of
843          // any predecessor.
844          if (PrInfo.isLiveOut(I->first)) {
845            report("Live-in virtual register redefined", I->second);
846            *OS << "Register %reg" << I->first
847                << " was live-out from predecessor MBB #"
848                << (*PrI)->getNumber() << ".\n";
849          }
850        }
851      }
852    }
853  }
854
855  // Now check LiveVariables info if available
856  if (LiveVars) {
857    calcRegsRequired();
858    verifyLiveVariables();
859  }
860}
861
862void MachineVerifier::verifyLiveVariables() {
863  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
864  for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
865         RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
866    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
867    for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
868         MFI != MFE; ++MFI) {
869      BBInfo &MInfo = MBBInfoMap[MFI];
870
871      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
872      if (MInfo.vregsRequired.count(Reg)) {
873        if (!VI.AliveBlocks.test(MFI->getNumber())) {
874          report("LiveVariables: Block missing from AliveBlocks", MFI);
875          *OS << "Virtual register %reg" << Reg
876              << " must be live through the block.\n";
877        }
878      } else {
879        if (VI.AliveBlocks.test(MFI->getNumber())) {
880          report("LiveVariables: Block should not be in AliveBlocks", MFI);
881          *OS << "Virtual register %reg" << Reg
882              << " is not needed live through the block.\n";
883        }
884      }
885    }
886  }
887}
888
889
890