MachineVerifier.cpp revision 803e6ca25b44a8bf77d2debb39e024aabafea05b 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/ADT/DenseSet.h"
27#include "llvm/ADT/SetOperations.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/Function.h"
30#include "llvm/CodeGen/LiveVariables.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Target/TargetInstrInfo.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include <fstream>
42
43using namespace llvm;
44
45namespace {
46  struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47    static char ID; // Pass ID, replacement for typeid
48
49    MachineVerifier(bool allowDoubleDefs = false) :
50      MachineFunctionPass(&ID),
51      allowVirtDoubleDefs(allowDoubleDefs),
52      allowPhysDoubleDefs(allowDoubleDefs),
53      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54        {}
55
56    void getAnalysisUsage(AnalysisUsage &AU) const {
57      AU.setPreservesAll();
58      MachineFunctionPass::getAnalysisUsage(AU);
59    }
60
61    bool runOnMachineFunction(MachineFunction &MF);
62
63    const bool allowVirtDoubleDefs;
64    const bool allowPhysDoubleDefs;
65
66    const char *const OutFileName;
67    std::ostream *OS;
68    const MachineFunction *MF;
69    const TargetMachine *TM;
70    const TargetRegisterInfo *TRI;
71    const MachineRegisterInfo *MRI;
72
73    unsigned foundErrors;
74
75    typedef SmallVector<unsigned, 16> RegVector;
76    typedef DenseSet<unsigned> RegSet;
77    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78
79    BitVector regsReserved;
80    RegSet regsLive;
81    RegVector regsDefined, regsDead, regsKilled;
82    RegSet regsLiveInButUnused;
83
84    // Add Reg and any sub-registers to RV
85    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86      RV.push_back(Reg);
87      if (TargetRegisterInfo::isPhysicalRegister(Reg))
88        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
89          RV.push_back(*R);
90    }
91
92    struct BBInfo {
93      // Is this MBB reachable from the MF entry point?
94      bool reachable;
95
96      // Vregs that must be live in because they are used without being
97      // defined. Map value is the user.
98      RegMap vregsLiveIn;
99
100      // Vregs that must be dead in because they are defined without being
101      // killed first. Map value is the defining instruction.
102      RegMap vregsDeadIn;
103
104      // Regs killed in MBB. They may be defined again, and will then be in both
105      // regsKilled and regsLiveOut.
106      RegSet regsKilled;
107
108      // Regs defined in MBB and live out. Note that vregs passing through may
109      // be live out without being mentioned here.
110      RegSet regsLiveOut;
111
112      // Vregs that pass through MBB untouched. This set is disjoint from
113      // regsKilled and regsLiveOut.
114      RegSet vregsPassed;
115
116      BBInfo() : reachable(false) {}
117
118      // Add register to vregsPassed if it belongs there. Return true if
119      // anything changed.
120      bool addPassed(unsigned Reg) {
121        if (!TargetRegisterInfo::isVirtualRegister(Reg))
122          return false;
123        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
124          return false;
125        return vregsPassed.insert(Reg).second;
126      }
127
128      // Same for a full set.
129      bool addPassed(const RegSet &RS) {
130        bool changed = false;
131        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
132          if (addPassed(*I))
133            changed = true;
134        return changed;
135      }
136
137      // Live-out registers are either in regsLiveOut or vregsPassed.
138      bool isLiveOut(unsigned Reg) const {
139        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
140      }
141    };
142
143    // Extra register info per MBB.
144    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
145
146    bool isReserved(unsigned Reg) {
147      return Reg < regsReserved.size() && regsReserved.test(Reg);
148    }
149
150    void visitMachineFunctionBefore();
151    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
152    void visitMachineInstrBefore(const MachineInstr *MI);
153    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
154    void visitMachineInstrAfter(const MachineInstr *MI);
155    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
156    void visitMachineFunctionAfter();
157
158    void report(const char *msg, const MachineFunction *MF);
159    void report(const char *msg, const MachineBasicBlock *MBB);
160    void report(const char *msg, const MachineInstr *MI);
161    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
162
163    void markReachable(const MachineBasicBlock *MBB);
164    void calcMaxRegsPassed();
165    void calcMinRegsPassed();
166    void checkPHIOps(const MachineBasicBlock *MBB);
167  };
168}
169
170char MachineVerifier::ID = 0;
171static RegisterPass<MachineVerifier>
172MachineVer("machineverifier", "Verify generated machine code");
173static const PassInfo *const MachineVerifyID = &MachineVer;
174
175FunctionPass *
176llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
177{
178  return new MachineVerifier(allowPhysDoubleDefs);
179}
180
181bool
182MachineVerifier::runOnMachineFunction(MachineFunction &MF)
183{
184  std::ofstream OutFile;
185  if (OutFileName) {
186    OutFile.open(OutFileName, std::ios::out | std::ios::app);
187    OS = &OutFile;
188  } else {
189    OS = cerr.stream();
190  }
191
192  foundErrors = 0;
193
194  this->MF = &MF;
195  TM = &MF.getTarget();
196  TRI = TM->getRegisterInfo();
197  MRI = &MF.getRegInfo();
198
199  visitMachineFunctionBefore();
200  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
201       MFI!=MFE; ++MFI) {
202    visitMachineBasicBlockBefore(MFI);
203    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
204           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
205      visitMachineInstrBefore(MBBI);
206      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
207        visitMachineOperand(&MBBI->getOperand(I), I);
208      visitMachineInstrAfter(MBBI);
209    }
210    visitMachineBasicBlockAfter(MFI);
211  }
212  visitMachineFunctionAfter();
213
214  if (OutFileName)
215    OutFile.close();
216  else if (foundErrors) {
217    std::string msg;
218    raw_string_ostream Msg(msg);
219    Msg << "Found " << foundErrors << " machine code errors.";
220    llvm_report_error(Msg.str());
221  }
222
223  // Clean up.
224  regsLive.clear();
225  regsDefined.clear();
226  regsDead.clear();
227  regsKilled.clear();
228  regsLiveInButUnused.clear();
229  MBBInfoMap.clear();
230
231  return false;                 // no changes
232}
233
234void
235MachineVerifier::report(const char *msg, const MachineFunction *MF)
236{
237  assert(MF);
238  *OS << "\n";
239  if (!foundErrors++)
240    MF->print(OS);
241  *OS << "*** Bad machine code: " << msg << " ***\n"
242      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
243}
244
245void
246MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
247{
248  assert(MBB);
249  report(msg, MBB->getParent());
250  *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
251      << " " << (void*)MBB
252      << " (#" << MBB->getNumber() << ")\n";
253}
254
255void
256MachineVerifier::report(const char *msg, const MachineInstr *MI)
257{
258  assert(MI);
259  report(msg, MI->getParent());
260  *OS << "- instruction: ";
261  MI->print(OS, TM);
262}
263
264void
265MachineVerifier::report(const char *msg,
266                        const MachineOperand *MO, unsigned MONum)
267{
268  assert(MO);
269  report(msg, MO->getParent());
270  *OS << "- operand " << MONum << ":   ";
271  MO->print(*OS, TM);
272  *OS << "\n";
273}
274
275void
276MachineVerifier::markReachable(const MachineBasicBlock *MBB)
277{
278  BBInfo &MInfo = MBBInfoMap[MBB];
279  if (!MInfo.reachable) {
280    MInfo.reachable = true;
281    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
282           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
283      markReachable(*SuI);
284  }
285}
286
287void
288MachineVerifier::visitMachineFunctionBefore()
289{
290  regsReserved = TRI->getReservedRegs(*MF);
291
292  // A sub-register of a reserved register is also reserved
293  for (int Reg = regsReserved.find_first(); Reg>=0;
294       Reg = regsReserved.find_next(Reg)) {
295    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
296      // FIXME: This should probably be:
297      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
298      regsReserved.set(*Sub);
299    }
300  }
301  markReachable(&MF->front());
302}
303
304void
305MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
306{
307  regsLive.clear();
308  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
309         E = MBB->livein_end(); I != E; ++I) {
310    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
311      report("MBB live-in list contains non-physical register", MBB);
312      continue;
313    }
314    regsLive.insert(*I);
315    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
316      regsLive.insert(*R);
317  }
318  regsLiveInButUnused = regsLive;
319  regsKilled.clear();
320  regsDefined.clear();
321}
322
323void
324MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
325{
326  const TargetInstrDesc &TI = MI->getDesc();
327  if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
328    report("Too few operands", MI);
329    *OS << TI.getNumOperands() << " operands expected, but "
330        << MI->getNumExplicitOperands() << " given.\n";
331  }
332  if (!TI.isVariadic()) {
333    if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
334      report("Too many operands", MI);
335      *OS << TI.getNumOperands() << " operands expected, but "
336          << MI->getNumExplicitOperands() << " given.\n";
337    }
338  }
339}
340
341void
342MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
343{
344  const MachineInstr *MI = MO->getParent();
345  const TargetInstrDesc &TI = MI->getDesc();
346
347  // The first TI.NumDefs operands must be explicit register defines
348  if (MONum < TI.getNumDefs()) {
349    if (!MO->isReg())
350      report("Explicit definition must be a register", MO, MONum);
351    else if (!MO->isDef())
352      report("Explicit definition marked as use", MO, MONum);
353    else if (MO->isImplicit())
354      report("Explicit definition marked as implicit", MO, MONum);
355  }
356
357  switch (MO->getType()) {
358  case MachineOperand::MO_Register: {
359    const unsigned Reg = MO->getReg();
360    if (!Reg)
361      return;
362
363    // Check Live Variables.
364    if (MO->isUndef()) {
365      // An <undef> doesn't refer to any register, so just skip it.
366    } else if (MO->isUse()) {
367      regsLiveInButUnused.erase(Reg);
368
369      if (MO->isKill()) {
370        addRegWithSubRegs(regsKilled, Reg);
371        // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
372        if (MI->isRegTiedToDefOperand(MONum))
373            report("Illegal kill flag on two-address instruction operand",
374                   MO, MONum);
375      } else {
376        // TwoAddress instr modifying a reg is treated as kill+def.
377        unsigned defIdx;
378        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
379            MI->getOperand(defIdx).getReg() == Reg)
380          addRegWithSubRegs(regsKilled, Reg);
381      }
382      // Use of a dead register.
383      if (!regsLive.count(Reg)) {
384        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
385          // Reserved registers may be used even when 'dead'.
386          if (!isReserved(Reg))
387            report("Using an undefined physical register", MO, MONum);
388        } else {
389          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
390          // We don't know which virtual registers are live in, so only complain
391          // if vreg was killed in this MBB. Otherwise keep track of vregs that
392          // must be live in. PHI instructions are handled separately.
393          if (MInfo.regsKilled.count(Reg))
394            report("Using a killed virtual register", MO, MONum);
395          else if (MI->getOpcode() != TargetInstrInfo::PHI)
396            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
397        }
398      }
399    } else {
400      assert(MO->isDef());
401      // Register defined.
402      // TODO: verify that earlyclobber ops are not used.
403      if (MO->isDead())
404        addRegWithSubRegs(regsDead, Reg);
405      else
406        addRegWithSubRegs(regsDefined, Reg);
407    }
408
409    // Check register classes.
410    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
411      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
412      unsigned SubIdx = MO->getSubReg();
413
414      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
415        unsigned sr = Reg;
416        if (SubIdx) {
417          unsigned s = TRI->getSubReg(Reg, SubIdx);
418          if (!s) {
419            report("Invalid subregister index for physical register",
420                   MO, MONum);
421            return;
422          }
423          sr = s;
424        }
425        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
426          if (!DRC->contains(sr)) {
427            report("Illegal physical register for instruction", MO, MONum);
428            *OS << TRI->getName(sr) << " is not a "
429                << DRC->getName() << " register.\n";
430          }
431        }
432      } else {
433        // Virtual register.
434        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
435        if (SubIdx) {
436          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
437            report("Invalid subregister index for virtual register", MO, MONum);
438            return;
439          }
440          RC = *(RC->subregclasses_begin()+SubIdx);
441        }
442        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
443          if (RC != DRC && !RC->hasSuperClass(DRC)) {
444            report("Illegal virtual register for instruction", MO, MONum);
445            *OS << "Expected a " << DRC->getName() << " register, but got a "
446                << RC->getName() << " register\n";
447          }
448        }
449      }
450    }
451    break;
452  }
453    // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
454    // case MachineOperand::MO_MachineBasicBlock:
455    //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
456    //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
457    //       report("PHI operand is not in the CFG", MO, MONum);
458    //   }
459    //   break;
460  default:
461    break;
462  }
463}
464
465void
466MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
467{
468  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
469  set_union(MInfo.regsKilled, regsKilled);
470  set_subtract(regsLive, regsKilled);
471  regsKilled.clear();
472
473  // Verify that both <def> and <def,dead> operands refer to dead registers.
474  RegVector defs(regsDefined);
475  defs.append(regsDead.begin(), regsDead.end());
476
477  for (RegVector::const_iterator I = defs.begin(), E = defs.end();
478       I != E; ++I) {
479    if (regsLive.count(*I)) {
480      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
481        if (!allowPhysDoubleDefs && !isReserved(*I) &&
482            !regsLiveInButUnused.count(*I)) {
483          report("Redefining a live physical register", MI);
484          *OS << "Register " << TRI->getName(*I)
485              << " was defined but already live.\n";
486        }
487      } else {
488        if (!allowVirtDoubleDefs) {
489          report("Redefining a live virtual register", MI);
490          *OS << "Virtual register %reg" << *I
491              << " was defined but already live.\n";
492        }
493      }
494    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
495               !MInfo.regsKilled.count(*I)) {
496      // Virtual register defined without being killed first must be dead on
497      // entry.
498      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
499    }
500  }
501
502  set_subtract(regsLive, regsDead); regsDead.clear();
503  set_union(regsLive, regsDefined); regsDefined.clear();
504}
505
506void
507MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
508{
509  MBBInfoMap[MBB].regsLiveOut = regsLive;
510  regsLive.clear();
511}
512
513// Calculate the largest possible vregsPassed sets. These are the registers that
514// can pass through an MBB live, but may not be live every time. It is assumed
515// that all vregsPassed sets are empty before the call.
516void
517MachineVerifier::calcMaxRegsPassed()
518{
519  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
520  // have any vregsPassed.
521  DenseSet<const MachineBasicBlock*> todo;
522  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
523       MFI != MFE; ++MFI) {
524    const MachineBasicBlock &MBB(*MFI);
525    BBInfo &MInfo = MBBInfoMap[&MBB];
526    if (!MInfo.reachable)
527      continue;
528    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
529           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
530      BBInfo &SInfo = MBBInfoMap[*SuI];
531      if (SInfo.addPassed(MInfo.regsLiveOut))
532        todo.insert(*SuI);
533    }
534  }
535
536  // Iteratively push vregsPassed to successors. This will converge to the same
537  // final state regardless of DenseSet iteration order.
538  while (!todo.empty()) {
539    const MachineBasicBlock *MBB = *todo.begin();
540    todo.erase(MBB);
541    BBInfo &MInfo = MBBInfoMap[MBB];
542    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
543           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
544      if (*SuI == MBB)
545        continue;
546      BBInfo &SInfo = MBBInfoMap[*SuI];
547      if (SInfo.addPassed(MInfo.vregsPassed))
548        todo.insert(*SuI);
549    }
550  }
551}
552
553// Calculate the minimum vregsPassed set. These are the registers that always
554// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
555// been called earlier.
556void
557MachineVerifier::calcMinRegsPassed()
558{
559  DenseSet<const MachineBasicBlock*> todo;
560  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
561       MFI != MFE; ++MFI)
562    todo.insert(MFI);
563
564  while (!todo.empty()) {
565    const MachineBasicBlock *MBB = *todo.begin();
566    todo.erase(MBB);
567    BBInfo &MInfo = MBBInfoMap[MBB];
568
569    // Remove entries from vRegsPassed that are not live out from all
570    // reachable predecessors.
571    RegSet dead;
572    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
573           E = MInfo.vregsPassed.end(); I != E; ++I) {
574      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
575             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
576        BBInfo &PrInfo = MBBInfoMap[*PrI];
577        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
578          dead.insert(*I);
579          break;
580        }
581      }
582    }
583    // If any regs removed, we need to recheck successors.
584    if (!dead.empty()) {
585      set_subtract(MInfo.vregsPassed, dead);
586      todo.insert(MBB->succ_begin(), MBB->succ_end());
587    }
588  }
589}
590
591// Check PHI instructions at the beginning of MBB. It is assumed that
592// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
593void
594MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
595{
596  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
597       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
598    DenseSet<const MachineBasicBlock*> seen;
599
600    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
601      unsigned Reg = BBI->getOperand(i).getReg();
602      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
603      if (!Pre->isSuccessor(MBB))
604        continue;
605      seen.insert(Pre);
606      BBInfo &PrInfo = MBBInfoMap[Pre];
607      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
608        report("PHI operand is not live-out from predecessor",
609               &BBI->getOperand(i), i);
610    }
611
612    // Did we see all predecessors?
613    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
614           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
615      if (!seen.count(*PrI)) {
616        report("Missing PHI operand", BBI);
617        *OS << "MBB #" << (*PrI)->getNumber()
618            << " is a predecessor according to the CFG.\n";
619      }
620    }
621  }
622}
623
624void
625MachineVerifier::visitMachineFunctionAfter()
626{
627  calcMaxRegsPassed();
628
629  // With the maximal set of vregsPassed we can verify dead-in registers.
630  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
631       MFI != MFE; ++MFI) {
632    BBInfo &MInfo = MBBInfoMap[MFI];
633
634    // Skip unreachable MBBs.
635    if (!MInfo.reachable)
636      continue;
637
638    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
639           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
640      BBInfo &PrInfo = MBBInfoMap[*PrI];
641      if (!PrInfo.reachable)
642        continue;
643
644      // Verify physical live-ins. EH landing pads have magic live-ins so we
645      // ignore them.
646      if (!MFI->isLandingPad()) {
647        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
648               E = MFI->livein_end(); I != E; ++I) {
649          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
650              !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
651            report("Live-in physical register is not live-out from predecessor",
652                   MFI);
653            *OS << "Register " << TRI->getName(*I)
654                << " is not live-out from MBB #" << (*PrI)->getNumber()
655                << ".\n";
656          }
657        }
658      }
659
660
661      // Verify dead-in virtual registers.
662      if (!allowVirtDoubleDefs) {
663        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
664               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
665          // DeadIn register must be in neither regsLiveOut or vregsPassed of
666          // any predecessor.
667          if (PrInfo.isLiveOut(I->first)) {
668            report("Live-in virtual register redefined", I->second);
669            *OS << "Register %reg" << I->first
670                << " was live-out from predecessor MBB #"
671                << (*PrI)->getNumber() << ".\n";
672          }
673        }
674      }
675    }
676  }
677
678  calcMinRegsPassed();
679
680  // With the minimal set of vregsPassed we can verify live-in virtual
681  // registers, including PHI instructions.
682  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
683       MFI != MFE; ++MFI) {
684    BBInfo &MInfo = MBBInfoMap[MFI];
685
686    // Skip unreachable MBBs.
687    if (!MInfo.reachable)
688      continue;
689
690    checkPHIOps(MFI);
691
692    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
693           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
694      BBInfo &PrInfo = MBBInfoMap[*PrI];
695      if (!PrInfo.reachable)
696        continue;
697
698      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
699             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
700        if (!PrInfo.isLiveOut(I->first)) {
701          report("Used virtual register is not live-in", I->second);
702          *OS << "Register %reg" << I->first
703              << " is not live-out from predecessor MBB #"
704              << (*PrI)->getNumber()
705              << ".\n";
706        }
707      }
708    }
709  }
710}
711