MachineVerifier.cpp revision 933c762371fe8cc6e2ef5d00d6866f4924852fed 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/ADT/DenseSet.h"
27#include "llvm/ADT/SetOperations.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/Function.h"
30#include "llvm/CodeGen/LiveVariables.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Target/TargetInstrInfo.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include <fstream>
42
43using namespace llvm;
44
45namespace {
46  struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47    static char ID; // Pass ID, replacement for typeid
48
49    MachineVerifier(bool allowDoubleDefs = false) :
50      MachineFunctionPass(&ID),
51      allowVirtDoubleDefs(allowDoubleDefs),
52      allowPhysDoubleDefs(allowDoubleDefs),
53      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54        {}
55
56    void getAnalysisUsage(AnalysisUsage &AU) const {
57      AU.setPreservesAll();
58      MachineFunctionPass::getAnalysisUsage(AU);
59    }
60
61    bool runOnMachineFunction(MachineFunction &MF);
62
63    const bool allowVirtDoubleDefs;
64    const bool allowPhysDoubleDefs;
65
66    const char *const OutFileName;
67    std::ostream *OS;
68    const MachineFunction *MF;
69    const TargetMachine *TM;
70    const TargetRegisterInfo *TRI;
71    const MachineRegisterInfo *MRI;
72
73    unsigned foundErrors;
74
75    typedef SmallVector<unsigned, 16> RegVector;
76    typedef DenseSet<unsigned> RegSet;
77    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78
79    BitVector regsReserved;
80    RegSet regsLive;
81    RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
82
83    // Add Reg and any sub-registers to RV
84    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
85      RV.push_back(Reg);
86      if (TargetRegisterInfo::isPhysicalRegister(Reg))
87        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
88          RV.push_back(*R);
89    }
90
91    // Does RS contain any super-registers of Reg?
92    bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
93      for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
94        if (RS.count(*R))
95          return true;
96      return false;
97    }
98
99    struct BBInfo {
100      // Is this MBB reachable from the MF entry point?
101      bool reachable;
102
103      // Vregs that must be live in because they are used without being
104      // defined. Map value is the user.
105      RegMap vregsLiveIn;
106
107      // Vregs that must be dead in because they are defined without being
108      // killed first. Map value is the defining instruction.
109      RegMap vregsDeadIn;
110
111      // Regs killed in MBB. They may be defined again, and will then be in both
112      // regsKilled and regsLiveOut.
113      RegSet regsKilled;
114
115      // Regs defined in MBB and live out. Note that vregs passing through may
116      // be live out without being mentioned here.
117      RegSet regsLiveOut;
118
119      // Vregs that pass through MBB untouched. This set is disjoint from
120      // regsKilled and regsLiveOut.
121      RegSet vregsPassed;
122
123      BBInfo() : reachable(false) {}
124
125      // Add register to vregsPassed if it belongs there. Return true if
126      // anything changed.
127      bool addPassed(unsigned Reg) {
128        if (!TargetRegisterInfo::isVirtualRegister(Reg))
129          return false;
130        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
131          return false;
132        return vregsPassed.insert(Reg).second;
133      }
134
135      // Same for a full set.
136      bool addPassed(const RegSet &RS) {
137        bool changed = false;
138        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
139          if (addPassed(*I))
140            changed = true;
141        return changed;
142      }
143
144      // Live-out registers are either in regsLiveOut or vregsPassed.
145      bool isLiveOut(unsigned Reg) const {
146        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
147      }
148    };
149
150    // Extra register info per MBB.
151    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
152
153    bool isReserved(unsigned Reg) {
154      return Reg < regsReserved.size() && regsReserved[Reg];
155    }
156
157    void visitMachineFunctionBefore();
158    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
159    void visitMachineInstrBefore(const MachineInstr *MI);
160    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
161    void visitMachineInstrAfter(const MachineInstr *MI);
162    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
163    void visitMachineFunctionAfter();
164
165    void report(const char *msg, const MachineFunction *MF);
166    void report(const char *msg, const MachineBasicBlock *MBB);
167    void report(const char *msg, const MachineInstr *MI);
168    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
169
170    void markReachable(const MachineBasicBlock *MBB);
171    void calcMaxRegsPassed();
172    void calcMinRegsPassed();
173    void checkPHIOps(const MachineBasicBlock *MBB);
174  };
175}
176
177char MachineVerifier::ID = 0;
178static RegisterPass<MachineVerifier>
179MachineVer("machineverifier", "Verify generated machine code");
180static const PassInfo *const MachineVerifyID = &MachineVer;
181
182FunctionPass *
183llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
184{
185  return new MachineVerifier(allowPhysDoubleDefs);
186}
187
188bool
189MachineVerifier::runOnMachineFunction(MachineFunction &MF)
190{
191  std::ofstream OutFile;
192  if (OutFileName) {
193    OutFile.open(OutFileName, std::ios::out | std::ios::app);
194    OS = &OutFile;
195  } else {
196    OS = cerr.stream();
197  }
198
199  foundErrors = 0;
200
201  this->MF = &MF;
202  TM = &MF.getTarget();
203  TRI = TM->getRegisterInfo();
204  MRI = &MF.getRegInfo();
205
206  visitMachineFunctionBefore();
207  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
208       MFI!=MFE; ++MFI) {
209    visitMachineBasicBlockBefore(MFI);
210    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
211           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
212      visitMachineInstrBefore(MBBI);
213      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
214        visitMachineOperand(&MBBI->getOperand(I), I);
215      visitMachineInstrAfter(MBBI);
216    }
217    visitMachineBasicBlockAfter(MFI);
218  }
219  visitMachineFunctionAfter();
220
221  if (OutFileName)
222    OutFile.close();
223  else if (foundErrors) {
224    std::string msg;
225    raw_string_ostream Msg(msg);
226    Msg << "Found " << foundErrors << " machine code errors.";
227    llvm_report_error(Msg.str());
228  }
229
230  return false;                 // no changes
231}
232
233void
234MachineVerifier::report(const char *msg, const MachineFunction *MF)
235{
236  assert(MF);
237  *OS << "\n";
238  if (!foundErrors++)
239    MF->print(OS);
240  *OS << "*** Bad machine code: " << msg << " ***\n"
241      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
242}
243
244void
245MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
246{
247  assert(MBB);
248  report(msg, MBB->getParent());
249  *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
250      << " " << (void*)MBB
251      << " (#" << MBB->getNumber() << ")\n";
252}
253
254void
255MachineVerifier::report(const char *msg, const MachineInstr *MI)
256{
257  assert(MI);
258  report(msg, MI->getParent());
259  *OS << "- instruction: ";
260  MI->print(OS, TM);
261}
262
263void
264MachineVerifier::report(const char *msg,
265                        const MachineOperand *MO, unsigned MONum)
266{
267  assert(MO);
268  report(msg, MO->getParent());
269  *OS << "- operand " << MONum << ":   ";
270  MO->print(*OS, TM);
271  *OS << "\n";
272}
273
274void
275MachineVerifier::markReachable(const MachineBasicBlock *MBB)
276{
277  BBInfo &MInfo = MBBInfoMap[MBB];
278  if (!MInfo.reachable) {
279    MInfo.reachable = true;
280    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
281           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
282      markReachable(*SuI);
283  }
284}
285
286void
287MachineVerifier::visitMachineFunctionBefore()
288{
289  regsReserved = TRI->getReservedRegs(*MF);
290  markReachable(&MF->front());
291}
292
293void
294MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
295{
296  regsLive.clear();
297  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
298         E = MBB->livein_end(); I != E; ++I) {
299    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
300      report("MBB live-in list contains non-physical register", MBB);
301      continue;
302    }
303    regsLive.insert(*I);
304    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
305      regsLive.insert(*R);
306  }
307  regsKilled.clear();
308  regsDefined.clear();
309  regsImpDefined.clear();
310}
311
312void
313MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
314{
315  const TargetInstrDesc &TI = MI->getDesc();
316  if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
317    report("Too few operands", MI);
318    *OS << TI.getNumOperands() << " operands expected, but "
319        << MI->getNumExplicitOperands() << " given.\n";
320  }
321  if (!TI.isVariadic()) {
322    if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
323      report("Too many operands", MI);
324      *OS << TI.getNumOperands() << " operands expected, but "
325          << MI->getNumExplicitOperands() << " given.\n";
326    }
327  }
328}
329
330void
331MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
332{
333  const MachineInstr *MI = MO->getParent();
334  const TargetInstrDesc &TI = MI->getDesc();
335
336  // The first TI.NumDefs operands must be explicit register defines
337  if (MONum < TI.getNumDefs()) {
338    if (!MO->isReg())
339      report("Explicit definition must be a register", MO, MONum);
340    else if (!MO->isDef())
341      report("Explicit definition marked as use", MO, MONum);
342    else if (MO->isImplicit())
343      report("Explicit definition marked as implicit", MO, MONum);
344  }
345
346  switch (MO->getType()) {
347  case MachineOperand::MO_Register: {
348    const unsigned Reg = MO->getReg();
349    if (!Reg)
350      return;
351
352    // Check Live Variables.
353    if (MO->isUse()) {
354      if (MO->isKill()) {
355        addRegWithSubRegs(regsKilled, Reg);
356        // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
357        if (MI->isRegTiedToDefOperand(MONum))
358            report("Illegal kill flag on two-address instruction operand",
359                   MO, MONum);
360      } else {
361        // TwoAddress instr modifying a reg is treated as kill+def.
362        unsigned defIdx;
363        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
364            MI->getOperand(defIdx).getReg() == Reg)
365          addRegWithSubRegs(regsKilled, Reg);
366      }
367      // Explicit use of a dead register.
368      if (!MO->isImplicit() && !regsLive.count(Reg)) {
369        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
370          // Reserved registers may be used even when 'dead'.
371          if (!isReserved(Reg))
372            report("Using an undefined physical register", MO, MONum);
373        } else {
374          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
375          // We don't know which virtual registers are live in, so only complain
376          // if vreg was killed in this MBB. Otherwise keep track of vregs that
377          // must be live in. PHI instructions are handled separately.
378          if (MInfo.regsKilled.count(Reg))
379            report("Using a killed virtual register", MO, MONum);
380          else if (MI->getOpcode() != TargetInstrInfo::PHI)
381            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
382        }
383      }
384    } else {
385      // Register defined.
386      // TODO: verify that earlyclobber ops are not used.
387      if (MO->isImplicit())
388        addRegWithSubRegs(regsImpDefined, Reg);
389      else
390        addRegWithSubRegs(regsDefined, Reg);
391
392      if (MO->isDead())
393        addRegWithSubRegs(regsDead, Reg);
394    }
395
396    // Check register classes.
397    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
398      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
399      unsigned SubIdx = MO->getSubReg();
400
401      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
402        unsigned sr = Reg;
403        if (SubIdx) {
404          unsigned s = TRI->getSubReg(Reg, SubIdx);
405          if (!s) {
406            report("Invalid subregister index for physical register",
407                   MO, MONum);
408            return;
409          }
410          sr = s;
411        }
412        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
413          if (!DRC->contains(sr)) {
414            report("Illegal physical register for instruction", MO, MONum);
415            *OS << TRI->getName(sr) << " is not a "
416                << DRC->getName() << " register.\n";
417          }
418        }
419      } else {
420        // Virtual register.
421        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
422        if (SubIdx) {
423          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
424            report("Invalid subregister index for virtual register", MO, MONum);
425            return;
426          }
427          RC = *(RC->subregclasses_begin()+SubIdx);
428        }
429        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
430          if (RC != DRC && !RC->hasSuperClass(DRC)) {
431            report("Illegal virtual register for instruction", MO, MONum);
432            *OS << "Expected a " << DRC->getName() << " register, but got a "
433                << RC->getName() << " register\n";
434          }
435        }
436      }
437    }
438    break;
439  }
440    // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
441    // case MachineOperand::MO_MachineBasicBlock:
442    //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
443    //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
444    //       report("PHI operand is not in the CFG", MO, MONum);
445    //   }
446    //   break;
447  default:
448    break;
449  }
450}
451
452void
453MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
454{
455  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
456  set_union(MInfo.regsKilled, regsKilled);
457  set_subtract(regsLive, regsKilled);
458  regsKilled.clear();
459
460  for (RegVector::const_iterator I = regsDefined.begin(),
461         E = regsDefined.end(); I != E; ++I) {
462    if (regsLive.count(*I)) {
463      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
464        // We allow double defines to physical registers with live
465        // super-registers.
466        if (!allowPhysDoubleDefs && !isReserved(*I) &&
467            !anySuperRegisters(regsLive, *I)) {
468          report("Redefining a live physical register", MI);
469          *OS << "Register " << TRI->getName(*I)
470              << " was defined but already live.\n";
471        }
472      } else {
473        if (!allowVirtDoubleDefs) {
474          report("Redefining a live virtual register", MI);
475          *OS << "Virtual register %reg" << *I
476              << " was defined but already live.\n";
477        }
478      }
479    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
480               !MInfo.regsKilled.count(*I)) {
481      // Virtual register defined without being killed first must be dead on
482      // entry.
483      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
484    }
485  }
486
487  set_union(regsLive, regsDefined); regsDefined.clear();
488  set_union(regsLive, regsImpDefined); regsImpDefined.clear();
489  set_subtract(regsLive, regsDead); regsDead.clear();
490}
491
492void
493MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
494{
495  MBBInfoMap[MBB].regsLiveOut = regsLive;
496  regsLive.clear();
497}
498
499// Calculate the largest possible vregsPassed sets. These are the registers that
500// can pass through an MBB live, but may not be live every time. It is assumed
501// that all vregsPassed sets are empty before the call.
502void
503MachineVerifier::calcMaxRegsPassed()
504{
505  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
506  // have any vregsPassed.
507  DenseSet<const MachineBasicBlock*> todo;
508  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
509       MFI != MFE; ++MFI) {
510    const MachineBasicBlock &MBB(*MFI);
511    BBInfo &MInfo = MBBInfoMap[&MBB];
512    if (!MInfo.reachable)
513      continue;
514    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
515           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
516      BBInfo &SInfo = MBBInfoMap[*SuI];
517      if (SInfo.addPassed(MInfo.regsLiveOut))
518        todo.insert(*SuI);
519    }
520  }
521
522  // Iteratively push vregsPassed to successors. This will converge to the same
523  // final state regardless of DenseSet iteration order.
524  while (!todo.empty()) {
525    const MachineBasicBlock *MBB = *todo.begin();
526    todo.erase(MBB);
527    BBInfo &MInfo = MBBInfoMap[MBB];
528    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
529           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
530      if (*SuI == MBB)
531        continue;
532      BBInfo &SInfo = MBBInfoMap[*SuI];
533      if (SInfo.addPassed(MInfo.vregsPassed))
534        todo.insert(*SuI);
535    }
536  }
537}
538
539// Calculate the minimum vregsPassed set. These are the registers that always
540// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
541// been called earlier.
542void
543MachineVerifier::calcMinRegsPassed()
544{
545  DenseSet<const MachineBasicBlock*> todo;
546  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
547       MFI != MFE; ++MFI)
548    todo.insert(MFI);
549
550  while (!todo.empty()) {
551    const MachineBasicBlock *MBB = *todo.begin();
552    todo.erase(MBB);
553    BBInfo &MInfo = MBBInfoMap[MBB];
554
555    // Remove entries from vRegsPassed that are not live out from all
556    // reachable predecessors.
557    RegSet dead;
558    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
559           E = MInfo.vregsPassed.end(); I != E; ++I) {
560      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
561             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
562        BBInfo &PrInfo = MBBInfoMap[*PrI];
563        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
564          dead.insert(*I);
565          break;
566        }
567      }
568    }
569    // If any regs removed, we need to recheck successors.
570    if (!dead.empty()) {
571      set_subtract(MInfo.vregsPassed, dead);
572      todo.insert(MBB->succ_begin(), MBB->succ_end());
573    }
574  }
575}
576
577// Check PHI instructions at the beginning of MBB. It is assumed that
578// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
579void
580MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
581{
582  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
583       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
584    DenseSet<const MachineBasicBlock*> seen;
585
586    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
587      unsigned Reg = BBI->getOperand(i).getReg();
588      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
589      if (!Pre->isSuccessor(MBB))
590        continue;
591      seen.insert(Pre);
592      BBInfo &PrInfo = MBBInfoMap[Pre];
593      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
594        report("PHI operand is not live-out from predecessor",
595               &BBI->getOperand(i), i);
596    }
597
598    // Did we see all predecessors?
599    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
600           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
601      if (!seen.count(*PrI)) {
602        report("Missing PHI operand", BBI);
603        *OS << "MBB #" << (*PrI)->getNumber()
604            << " is a predecessor according to the CFG.\n";
605      }
606    }
607  }
608}
609
610void
611MachineVerifier::visitMachineFunctionAfter()
612{
613  calcMaxRegsPassed();
614
615  // With the maximal set of vregsPassed we can verify dead-in registers.
616  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
617       MFI != MFE; ++MFI) {
618    BBInfo &MInfo = MBBInfoMap[MFI];
619
620    // Skip unreachable MBBs.
621    if (!MInfo.reachable)
622      continue;
623
624    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
625           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
626      BBInfo &PrInfo = MBBInfoMap[*PrI];
627      if (!PrInfo.reachable)
628        continue;
629
630      // Verify physical live-ins. EH landing pads have magic live-ins so we
631      // ignore them.
632      if (!MFI->isLandingPad()) {
633        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
634               E = MFI->livein_end(); I != E; ++I) {
635          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
636              !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
637            report("Live-in physical register is not live-out from predecessor",
638                   MFI);
639            *OS << "Register " << TRI->getName(*I)
640                << " is not live-out from MBB #" << (*PrI)->getNumber()
641                << ".\n";
642          }
643        }
644      }
645
646
647      // Verify dead-in virtual registers.
648      if (!allowVirtDoubleDefs) {
649        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
650               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
651          // DeadIn register must be in neither regsLiveOut or vregsPassed of
652          // any predecessor.
653          if (PrInfo.isLiveOut(I->first)) {
654            report("Live-in virtual register redefined", I->second);
655            *OS << "Register %reg" << I->first
656                << " was live-out from predecessor MBB #"
657                << (*PrI)->getNumber() << ".\n";
658          }
659        }
660      }
661    }
662  }
663
664  calcMinRegsPassed();
665
666  // With the minimal set of vregsPassed we can verify live-in virtual
667  // registers, including PHI instructions.
668  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
669       MFI != MFE; ++MFI) {
670    BBInfo &MInfo = MBBInfoMap[MFI];
671
672    // Skip unreachable MBBs.
673    if (!MInfo.reachable)
674      continue;
675
676    checkPHIOps(MFI);
677
678    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
679           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
680      BBInfo &PrInfo = MBBInfoMap[*PrI];
681      if (!PrInfo.reachable)
682        continue;
683
684      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
685             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
686        if (!PrInfo.isLiveOut(I->first)) {
687          report("Used virtual register is not live-in", I->second);
688          *OS << "Register %reg" << I->first
689              << " is not live-out from predecessor MBB #"
690              << (*PrI)->getNumber()
691              << ".\n";
692        }
693      }
694    }
695  }
696}
697