MachineVerifier.cpp revision e693fe774d2f52f9affea558e88d7d43169af112 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/ADT/DenseSet.h"
27#include "llvm/ADT/SetOperations.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/Function.h"
30#include "llvm/CodeGen/LiveVariables.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Target/TargetInstrInfo.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#include <fstream>
42
43using namespace llvm;
44
45namespace {
46  struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47    static char ID; // Pass ID, replacement for typeid
48
49    MachineVerifier(bool allowDoubleDefs = false) :
50      MachineFunctionPass(&ID),
51      allowVirtDoubleDefs(allowDoubleDefs),
52      allowPhysDoubleDefs(allowDoubleDefs),
53      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
54        {}
55
56    void getAnalysisUsage(AnalysisUsage &AU) const {
57      AU.setPreservesAll();
58      MachineFunctionPass::getAnalysisUsage(AU);
59    }
60
61    bool runOnMachineFunction(MachineFunction &MF);
62
63    const bool allowVirtDoubleDefs;
64    const bool allowPhysDoubleDefs;
65
66    const char *const OutFileName;
67    std::ostream *OS;
68    const MachineFunction *MF;
69    const TargetMachine *TM;
70    const TargetRegisterInfo *TRI;
71    const MachineRegisterInfo *MRI;
72
73    unsigned foundErrors;
74
75    typedef SmallVector<unsigned, 16> RegVector;
76    typedef DenseSet<unsigned> RegSet;
77    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78
79    BitVector regsReserved;
80    RegSet regsLive;
81    RegVector regsDefined, regsDead, regsKilled;
82    RegSet regsLiveInButUnused;
83
84    // Add Reg and any sub-registers to RV
85    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86      RV.push_back(Reg);
87      if (TargetRegisterInfo::isPhysicalRegister(Reg))
88        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
89          RV.push_back(*R);
90    }
91
92    struct BBInfo {
93      // Is this MBB reachable from the MF entry point?
94      bool reachable;
95
96      // Vregs that must be live in because they are used without being
97      // defined. Map value is the user.
98      RegMap vregsLiveIn;
99
100      // Vregs that must be dead in because they are defined without being
101      // killed first. Map value is the defining instruction.
102      RegMap vregsDeadIn;
103
104      // Regs killed in MBB. They may be defined again, and will then be in both
105      // regsKilled and regsLiveOut.
106      RegSet regsKilled;
107
108      // Regs defined in MBB and live out. Note that vregs passing through may
109      // be live out without being mentioned here.
110      RegSet regsLiveOut;
111
112      // Vregs that pass through MBB untouched. This set is disjoint from
113      // regsKilled and regsLiveOut.
114      RegSet vregsPassed;
115
116      BBInfo() : reachable(false) {}
117
118      // Add register to vregsPassed if it belongs there. Return true if
119      // anything changed.
120      bool addPassed(unsigned Reg) {
121        if (!TargetRegisterInfo::isVirtualRegister(Reg))
122          return false;
123        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
124          return false;
125        return vregsPassed.insert(Reg).second;
126      }
127
128      // Same for a full set.
129      bool addPassed(const RegSet &RS) {
130        bool changed = false;
131        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
132          if (addPassed(*I))
133            changed = true;
134        return changed;
135      }
136
137      // Live-out registers are either in regsLiveOut or vregsPassed.
138      bool isLiveOut(unsigned Reg) const {
139        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
140      }
141    };
142
143    // Extra register info per MBB.
144    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
145
146    bool isReserved(unsigned Reg) {
147      return Reg < regsReserved.size() && regsReserved.test(Reg);
148    }
149
150    void visitMachineFunctionBefore();
151    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
152    void visitMachineInstrBefore(const MachineInstr *MI);
153    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
154    void visitMachineInstrAfter(const MachineInstr *MI);
155    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
156    void visitMachineFunctionAfter();
157
158    void report(const char *msg, const MachineFunction *MF);
159    void report(const char *msg, const MachineBasicBlock *MBB);
160    void report(const char *msg, const MachineInstr *MI);
161    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
162
163    void markReachable(const MachineBasicBlock *MBB);
164    void calcMaxRegsPassed();
165    void calcMinRegsPassed();
166    void checkPHIOps(const MachineBasicBlock *MBB);
167  };
168}
169
170char MachineVerifier::ID = 0;
171static RegisterPass<MachineVerifier>
172MachineVer("machineverifier", "Verify generated machine code");
173static const PassInfo *const MachineVerifyID = &MachineVer;
174
175FunctionPass *
176llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
177{
178  return new MachineVerifier(allowPhysDoubleDefs);
179}
180
181bool
182MachineVerifier::runOnMachineFunction(MachineFunction &MF)
183{
184  std::ofstream OutFile;
185  if (OutFileName) {
186    OutFile.open(OutFileName, std::ios::out | std::ios::app);
187    OS = &OutFile;
188  } else {
189    OS = cerr.stream();
190  }
191
192  foundErrors = 0;
193
194  this->MF = &MF;
195  TM = &MF.getTarget();
196  TRI = TM->getRegisterInfo();
197  MRI = &MF.getRegInfo();
198
199  visitMachineFunctionBefore();
200  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
201       MFI!=MFE; ++MFI) {
202    visitMachineBasicBlockBefore(MFI);
203    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
204           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
205      visitMachineInstrBefore(MBBI);
206      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
207        visitMachineOperand(&MBBI->getOperand(I), I);
208      visitMachineInstrAfter(MBBI);
209    }
210    visitMachineBasicBlockAfter(MFI);
211  }
212  visitMachineFunctionAfter();
213
214  if (OutFileName)
215    OutFile.close();
216  else if (foundErrors) {
217    std::string msg;
218    raw_string_ostream Msg(msg);
219    Msg << "Found " << foundErrors << " machine code errors.";
220    llvm_report_error(Msg.str());
221  }
222
223  return false;                 // no changes
224}
225
226void
227MachineVerifier::report(const char *msg, const MachineFunction *MF)
228{
229  assert(MF);
230  *OS << "\n";
231  if (!foundErrors++)
232    MF->print(OS);
233  *OS << "*** Bad machine code: " << msg << " ***\n"
234      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
235}
236
237void
238MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
239{
240  assert(MBB);
241  report(msg, MBB->getParent());
242  *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
243      << " " << (void*)MBB
244      << " (#" << MBB->getNumber() << ")\n";
245}
246
247void
248MachineVerifier::report(const char *msg, const MachineInstr *MI)
249{
250  assert(MI);
251  report(msg, MI->getParent());
252  *OS << "- instruction: ";
253  MI->print(OS, TM);
254}
255
256void
257MachineVerifier::report(const char *msg,
258                        const MachineOperand *MO, unsigned MONum)
259{
260  assert(MO);
261  report(msg, MO->getParent());
262  *OS << "- operand " << MONum << ":   ";
263  MO->print(*OS, TM);
264  *OS << "\n";
265}
266
267void
268MachineVerifier::markReachable(const MachineBasicBlock *MBB)
269{
270  BBInfo &MInfo = MBBInfoMap[MBB];
271  if (!MInfo.reachable) {
272    MInfo.reachable = true;
273    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
274           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
275      markReachable(*SuI);
276  }
277}
278
279void
280MachineVerifier::visitMachineFunctionBefore()
281{
282  regsReserved = TRI->getReservedRegs(*MF);
283
284  // A sub-register of a reserved register is also reserved
285  for (int Reg = regsReserved.find_first(); Reg>=0;
286       Reg = regsReserved.find_next(Reg)) {
287    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
288      // FIXME: This should probably be:
289      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
290      regsReserved.set(*Sub);
291    }
292  }
293  markReachable(&MF->front());
294}
295
296void
297MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
298{
299  regsLive.clear();
300  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
301         E = MBB->livein_end(); I != E; ++I) {
302    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
303      report("MBB live-in list contains non-physical register", MBB);
304      continue;
305    }
306    regsLive.insert(*I);
307    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
308      regsLive.insert(*R);
309  }
310  regsLiveInButUnused = regsLive;
311  regsKilled.clear();
312  regsDefined.clear();
313}
314
315void
316MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
317{
318  const TargetInstrDesc &TI = MI->getDesc();
319  if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
320    report("Too few operands", MI);
321    *OS << TI.getNumOperands() << " operands expected, but "
322        << MI->getNumExplicitOperands() << " given.\n";
323  }
324  if (!TI.isVariadic()) {
325    if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
326      report("Too many operands", MI);
327      *OS << TI.getNumOperands() << " operands expected, but "
328          << MI->getNumExplicitOperands() << " given.\n";
329    }
330  }
331}
332
333void
334MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
335{
336  const MachineInstr *MI = MO->getParent();
337  const TargetInstrDesc &TI = MI->getDesc();
338
339  // The first TI.NumDefs operands must be explicit register defines
340  if (MONum < TI.getNumDefs()) {
341    if (!MO->isReg())
342      report("Explicit definition must be a register", MO, MONum);
343    else if (!MO->isDef())
344      report("Explicit definition marked as use", MO, MONum);
345    else if (MO->isImplicit())
346      report("Explicit definition marked as implicit", MO, MONum);
347  }
348
349  switch (MO->getType()) {
350  case MachineOperand::MO_Register: {
351    const unsigned Reg = MO->getReg();
352    if (!Reg)
353      return;
354
355    // Check Live Variables.
356    if (MO->isUndef()) {
357      // An <undef> doesn't refer to any register, so just skip it.
358    } else if (MO->isUse()) {
359      regsLiveInButUnused.erase(Reg);
360
361      if (MO->isKill()) {
362        addRegWithSubRegs(regsKilled, Reg);
363        // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
364        if (MI->isRegTiedToDefOperand(MONum))
365            report("Illegal kill flag on two-address instruction operand",
366                   MO, MONum);
367      } else {
368        // TwoAddress instr modifying a reg is treated as kill+def.
369        unsigned defIdx;
370        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
371            MI->getOperand(defIdx).getReg() == Reg)
372          addRegWithSubRegs(regsKilled, Reg);
373      }
374      // Use of a dead register.
375      if (!regsLive.count(Reg)) {
376        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
377          // Reserved registers may be used even when 'dead'.
378          if (!isReserved(Reg))
379            report("Using an undefined physical register", MO, MONum);
380        } else {
381          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
382          // We don't know which virtual registers are live in, so only complain
383          // if vreg was killed in this MBB. Otherwise keep track of vregs that
384          // must be live in. PHI instructions are handled separately.
385          if (MInfo.regsKilled.count(Reg))
386            report("Using a killed virtual register", MO, MONum);
387          else if (MI->getOpcode() != TargetInstrInfo::PHI)
388            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
389        }
390      }
391    } else {
392      assert(MO->isDef());
393      // Register defined.
394      // TODO: verify that earlyclobber ops are not used.
395      if (MO->isDead())
396        addRegWithSubRegs(regsDead, Reg);
397      else
398        addRegWithSubRegs(regsDefined, Reg);
399    }
400
401    // Check register classes.
402    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
403      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
404      unsigned SubIdx = MO->getSubReg();
405
406      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
407        unsigned sr = Reg;
408        if (SubIdx) {
409          unsigned s = TRI->getSubReg(Reg, SubIdx);
410          if (!s) {
411            report("Invalid subregister index for physical register",
412                   MO, MONum);
413            return;
414          }
415          sr = s;
416        }
417        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
418          if (!DRC->contains(sr)) {
419            report("Illegal physical register for instruction", MO, MONum);
420            *OS << TRI->getName(sr) << " is not a "
421                << DRC->getName() << " register.\n";
422          }
423        }
424      } else {
425        // Virtual register.
426        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
427        if (SubIdx) {
428          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
429            report("Invalid subregister index for virtual register", MO, MONum);
430            return;
431          }
432          RC = *(RC->subregclasses_begin()+SubIdx);
433        }
434        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
435          if (RC != DRC && !RC->hasSuperClass(DRC)) {
436            report("Illegal virtual register for instruction", MO, MONum);
437            *OS << "Expected a " << DRC->getName() << " register, but got a "
438                << RC->getName() << " register\n";
439          }
440        }
441      }
442    }
443    break;
444  }
445    // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
446    // case MachineOperand::MO_MachineBasicBlock:
447    //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
448    //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
449    //       report("PHI operand is not in the CFG", MO, MONum);
450    //   }
451    //   break;
452  default:
453    break;
454  }
455}
456
457void
458MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
459{
460  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
461  set_union(MInfo.regsKilled, regsKilled);
462  set_subtract(regsLive, regsKilled);
463  regsKilled.clear();
464
465  // Verify that both <def> and <def,dead> operands refer to dead registers.
466  RegVector defs(regsDefined);
467  defs.append(regsDead.begin(), regsDead.end());
468
469  for (RegVector::const_iterator I = defs.begin(), E = defs.end();
470       I != E; ++I) {
471    if (regsLive.count(*I)) {
472      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
473        if (!allowPhysDoubleDefs && !isReserved(*I) &&
474            !regsLiveInButUnused.count(*I)) {
475          report("Redefining a live physical register", MI);
476          *OS << "Register " << TRI->getName(*I)
477              << " was defined but already live.\n";
478        }
479      } else {
480        if (!allowVirtDoubleDefs) {
481          report("Redefining a live virtual register", MI);
482          *OS << "Virtual register %reg" << *I
483              << " was defined but already live.\n";
484        }
485      }
486    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
487               !MInfo.regsKilled.count(*I)) {
488      // Virtual register defined without being killed first must be dead on
489      // entry.
490      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
491    }
492  }
493
494  set_subtract(regsLive, regsDead); regsDead.clear();
495  set_union(regsLive, regsDefined); regsDefined.clear();
496}
497
498void
499MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
500{
501  MBBInfoMap[MBB].regsLiveOut = regsLive;
502  regsLive.clear();
503}
504
505// Calculate the largest possible vregsPassed sets. These are the registers that
506// can pass through an MBB live, but may not be live every time. It is assumed
507// that all vregsPassed sets are empty before the call.
508void
509MachineVerifier::calcMaxRegsPassed()
510{
511  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
512  // have any vregsPassed.
513  DenseSet<const MachineBasicBlock*> todo;
514  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
515       MFI != MFE; ++MFI) {
516    const MachineBasicBlock &MBB(*MFI);
517    BBInfo &MInfo = MBBInfoMap[&MBB];
518    if (!MInfo.reachable)
519      continue;
520    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
521           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
522      BBInfo &SInfo = MBBInfoMap[*SuI];
523      if (SInfo.addPassed(MInfo.regsLiveOut))
524        todo.insert(*SuI);
525    }
526  }
527
528  // Iteratively push vregsPassed to successors. This will converge to the same
529  // final state regardless of DenseSet iteration order.
530  while (!todo.empty()) {
531    const MachineBasicBlock *MBB = *todo.begin();
532    todo.erase(MBB);
533    BBInfo &MInfo = MBBInfoMap[MBB];
534    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
535           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
536      if (*SuI == MBB)
537        continue;
538      BBInfo &SInfo = MBBInfoMap[*SuI];
539      if (SInfo.addPassed(MInfo.vregsPassed))
540        todo.insert(*SuI);
541    }
542  }
543}
544
545// Calculate the minimum vregsPassed set. These are the registers that always
546// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
547// been called earlier.
548void
549MachineVerifier::calcMinRegsPassed()
550{
551  DenseSet<const MachineBasicBlock*> todo;
552  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
553       MFI != MFE; ++MFI)
554    todo.insert(MFI);
555
556  while (!todo.empty()) {
557    const MachineBasicBlock *MBB = *todo.begin();
558    todo.erase(MBB);
559    BBInfo &MInfo = MBBInfoMap[MBB];
560
561    // Remove entries from vRegsPassed that are not live out from all
562    // reachable predecessors.
563    RegSet dead;
564    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
565           E = MInfo.vregsPassed.end(); I != E; ++I) {
566      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
567             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
568        BBInfo &PrInfo = MBBInfoMap[*PrI];
569        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
570          dead.insert(*I);
571          break;
572        }
573      }
574    }
575    // If any regs removed, we need to recheck successors.
576    if (!dead.empty()) {
577      set_subtract(MInfo.vregsPassed, dead);
578      todo.insert(MBB->succ_begin(), MBB->succ_end());
579    }
580  }
581}
582
583// Check PHI instructions at the beginning of MBB. It is assumed that
584// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
585void
586MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
587{
588  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
589       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
590    DenseSet<const MachineBasicBlock*> seen;
591
592    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
593      unsigned Reg = BBI->getOperand(i).getReg();
594      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
595      if (!Pre->isSuccessor(MBB))
596        continue;
597      seen.insert(Pre);
598      BBInfo &PrInfo = MBBInfoMap[Pre];
599      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
600        report("PHI operand is not live-out from predecessor",
601               &BBI->getOperand(i), i);
602    }
603
604    // Did we see all predecessors?
605    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
606           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
607      if (!seen.count(*PrI)) {
608        report("Missing PHI operand", BBI);
609        *OS << "MBB #" << (*PrI)->getNumber()
610            << " is a predecessor according to the CFG.\n";
611      }
612    }
613  }
614}
615
616void
617MachineVerifier::visitMachineFunctionAfter()
618{
619  calcMaxRegsPassed();
620
621  // With the maximal set of vregsPassed we can verify dead-in registers.
622  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
623       MFI != MFE; ++MFI) {
624    BBInfo &MInfo = MBBInfoMap[MFI];
625
626    // Skip unreachable MBBs.
627    if (!MInfo.reachable)
628      continue;
629
630    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
631           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
632      BBInfo &PrInfo = MBBInfoMap[*PrI];
633      if (!PrInfo.reachable)
634        continue;
635
636      // Verify physical live-ins. EH landing pads have magic live-ins so we
637      // ignore them.
638      if (!MFI->isLandingPad()) {
639        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
640               E = MFI->livein_end(); I != E; ++I) {
641          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
642              !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
643            report("Live-in physical register is not live-out from predecessor",
644                   MFI);
645            *OS << "Register " << TRI->getName(*I)
646                << " is not live-out from MBB #" << (*PrI)->getNumber()
647                << ".\n";
648          }
649        }
650      }
651
652
653      // Verify dead-in virtual registers.
654      if (!allowVirtDoubleDefs) {
655        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
656               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
657          // DeadIn register must be in neither regsLiveOut or vregsPassed of
658          // any predecessor.
659          if (PrInfo.isLiveOut(I->first)) {
660            report("Live-in virtual register redefined", I->second);
661            *OS << "Register %reg" << I->first
662                << " was live-out from predecessor MBB #"
663                << (*PrI)->getNumber() << ".\n";
664          }
665        }
666      }
667    }
668  }
669
670  calcMinRegsPassed();
671
672  // With the minimal set of vregsPassed we can verify live-in virtual
673  // registers, including PHI instructions.
674  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
675       MFI != MFE; ++MFI) {
676    BBInfo &MInfo = MBBInfoMap[MFI];
677
678    // Skip unreachable MBBs.
679    if (!MInfo.reachable)
680      continue;
681
682    checkPHIOps(MFI);
683
684    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
685           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
686      BBInfo &PrInfo = MBBInfoMap[*PrI];
687      if (!PrInfo.reachable)
688        continue;
689
690      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
691             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
692        if (!PrInfo.isLiveOut(I->first)) {
693          report("Used virtual register is not live-in", I->second);
694          *OS << "Register %reg" << I->first
695              << " is not live-out from predecessor MBB #"
696              << (*PrI)->getNumber()
697              << ".\n";
698        }
699      }
700    }
701  }
702}
703