MachineVerifier.cpp revision f1172bbd107d5b180d7986d2517af246c64c5139 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/Function.h"
27#include "llvm/CodeGen/LiveVariables.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/ADT/DenseSet.h"
37#include "llvm/ADT/SetOperations.h"
38#include "llvm/ADT/SmallVector.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/ErrorHandling.h"
41#include "llvm/Support/raw_ostream.h"
42using namespace llvm;
43
44namespace {
45  struct MachineVerifier {
46
47    MachineVerifier(Pass *pass) :
48      PASS(pass),
49      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
50      {}
51
52    bool runOnMachineFunction(MachineFunction &MF);
53
54    Pass *const PASS;
55    const char *const OutFileName;
56    raw_ostream *OS;
57    const MachineFunction *MF;
58    const TargetMachine *TM;
59    const TargetRegisterInfo *TRI;
60    const MachineRegisterInfo *MRI;
61
62    unsigned foundErrors;
63
64    typedef SmallVector<unsigned, 16> RegVector;
65    typedef DenseSet<unsigned> RegSet;
66    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
67
68    BitVector regsReserved;
69    RegSet regsLive;
70    RegVector regsDefined, regsDead, regsKilled;
71    RegSet regsLiveInButUnused;
72
73    // Add Reg and any sub-registers to RV
74    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
75      RV.push_back(Reg);
76      if (TargetRegisterInfo::isPhysicalRegister(Reg))
77        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
78          RV.push_back(*R);
79    }
80
81    struct BBInfo {
82      // Is this MBB reachable from the MF entry point?
83      bool reachable;
84
85      // Vregs that must be live in because they are used without being
86      // defined. Map value is the user.
87      RegMap vregsLiveIn;
88
89      // Regs killed in MBB. They may be defined again, and will then be in both
90      // regsKilled and regsLiveOut.
91      RegSet regsKilled;
92
93      // Regs defined in MBB and live out. Note that vregs passing through may
94      // be live out without being mentioned here.
95      RegSet regsLiveOut;
96
97      // Vregs that pass through MBB untouched. This set is disjoint from
98      // regsKilled and regsLiveOut.
99      RegSet vregsPassed;
100
101      // Vregs that must pass through MBB because they are needed by a successor
102      // block. This set is disjoint from regsLiveOut.
103      RegSet vregsRequired;
104
105      BBInfo() : reachable(false) {}
106
107      // Add register to vregsPassed if it belongs there. Return true if
108      // anything changed.
109      bool addPassed(unsigned Reg) {
110        if (!TargetRegisterInfo::isVirtualRegister(Reg))
111          return false;
112        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
113          return false;
114        return vregsPassed.insert(Reg).second;
115      }
116
117      // Same for a full set.
118      bool addPassed(const RegSet &RS) {
119        bool changed = false;
120        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
121          if (addPassed(*I))
122            changed = true;
123        return changed;
124      }
125
126      // Add register to vregsRequired if it belongs there. Return true if
127      // anything changed.
128      bool addRequired(unsigned Reg) {
129        if (!TargetRegisterInfo::isVirtualRegister(Reg))
130          return false;
131        if (regsLiveOut.count(Reg))
132          return false;
133        return vregsRequired.insert(Reg).second;
134      }
135
136      // Same for a full set.
137      bool addRequired(const RegSet &RS) {
138        bool changed = false;
139        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
140          if (addRequired(*I))
141            changed = true;
142        return changed;
143      }
144
145      // Same for a full map.
146      bool addRequired(const RegMap &RM) {
147        bool changed = false;
148        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
149          if (addRequired(I->first))
150            changed = true;
151        return changed;
152      }
153
154      // Live-out registers are either in regsLiveOut or vregsPassed.
155      bool isLiveOut(unsigned Reg) const {
156        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
157      }
158    };
159
160    // Extra register info per MBB.
161    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
162
163    bool isReserved(unsigned Reg) {
164      return Reg < regsReserved.size() && regsReserved.test(Reg);
165    }
166
167    // Analysis information if available
168    LiveVariables *LiveVars;
169
170    void visitMachineFunctionBefore();
171    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
172    void visitMachineInstrBefore(const MachineInstr *MI);
173    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
174    void visitMachineInstrAfter(const MachineInstr *MI);
175    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
176    void visitMachineFunctionAfter();
177
178    void report(const char *msg, const MachineFunction *MF);
179    void report(const char *msg, const MachineBasicBlock *MBB);
180    void report(const char *msg, const MachineInstr *MI);
181    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
182
183    void markReachable(const MachineBasicBlock *MBB);
184    void calcRegsPassed();
185    void checkPHIOps(const MachineBasicBlock *MBB);
186
187    void calcRegsRequired();
188    void verifyLiveVariables();
189  };
190
191  struct MachineVerifierPass : public MachineFunctionPass {
192    static char ID; // Pass ID, replacement for typeid
193
194    MachineVerifierPass()
195      : MachineFunctionPass(&ID) {}
196
197    void getAnalysisUsage(AnalysisUsage &AU) const {
198      AU.setPreservesAll();
199      MachineFunctionPass::getAnalysisUsage(AU);
200    }
201
202    bool runOnMachineFunction(MachineFunction &MF) {
203      MF.verify(this);
204      return false;
205    }
206  };
207
208}
209
210char MachineVerifierPass::ID = 0;
211static RegisterPass<MachineVerifierPass>
212MachineVer("machineverifier", "Verify generated machine code");
213static const PassInfo *const MachineVerifyID = &MachineVer;
214
215FunctionPass *llvm::createMachineVerifierPass() {
216  return new MachineVerifierPass();
217}
218
219void MachineFunction::verify(Pass *p) const {
220  MachineVerifier(p).runOnMachineFunction(const_cast<MachineFunction&>(*this));
221}
222
223bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
224  raw_ostream *OutFile = 0;
225  if (OutFileName) {
226    std::string ErrorInfo;
227    OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
228                                 raw_fd_ostream::F_Append);
229    if (!ErrorInfo.empty()) {
230      errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
231      exit(1);
232    }
233
234    OS = OutFile;
235  } else {
236    OS = &errs();
237  }
238
239  foundErrors = 0;
240
241  this->MF = &MF;
242  TM = &MF.getTarget();
243  TRI = TM->getRegisterInfo();
244  MRI = &MF.getRegInfo();
245
246  if (PASS) {
247    LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
248  } else {
249    LiveVars = NULL;
250  }
251
252  visitMachineFunctionBefore();
253  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
254       MFI!=MFE; ++MFI) {
255    visitMachineBasicBlockBefore(MFI);
256    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
257           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
258      visitMachineInstrBefore(MBBI);
259      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
260        visitMachineOperand(&MBBI->getOperand(I), I);
261      visitMachineInstrAfter(MBBI);
262    }
263    visitMachineBasicBlockAfter(MFI);
264  }
265  visitMachineFunctionAfter();
266
267  if (OutFile)
268    delete OutFile;
269  else if (foundErrors)
270    report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
271
272  // Clean up.
273  regsLive.clear();
274  regsDefined.clear();
275  regsDead.clear();
276  regsKilled.clear();
277  regsLiveInButUnused.clear();
278  MBBInfoMap.clear();
279
280  return false;                 // no changes
281}
282
283void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
284  assert(MF);
285  *OS << '\n';
286  if (!foundErrors++)
287    MF->print(*OS);
288  *OS << "*** Bad machine code: " << msg << " ***\n"
289      << "- function:    " << MF->getFunction()->getNameStr() << "\n";
290}
291
292void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
293  assert(MBB);
294  report(msg, MBB->getParent());
295  *OS << "- basic block: " << MBB->getName()
296      << " " << (void*)MBB
297      << " (BB#" << MBB->getNumber() << ")\n";
298}
299
300void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
301  assert(MI);
302  report(msg, MI->getParent());
303  *OS << "- instruction: ";
304  MI->print(*OS, TM);
305}
306
307void MachineVerifier::report(const char *msg,
308                             const MachineOperand *MO, unsigned MONum) {
309  assert(MO);
310  report(msg, MO->getParent());
311  *OS << "- operand " << MONum << ":   ";
312  MO->print(*OS, TM);
313  *OS << "\n";
314}
315
316void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
317  BBInfo &MInfo = MBBInfoMap[MBB];
318  if (!MInfo.reachable) {
319    MInfo.reachable = true;
320    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
321           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
322      markReachable(*SuI);
323  }
324}
325
326void MachineVerifier::visitMachineFunctionBefore() {
327  regsReserved = TRI->getReservedRegs(*MF);
328
329  // A sub-register of a reserved register is also reserved
330  for (int Reg = regsReserved.find_first(); Reg>=0;
331       Reg = regsReserved.find_next(Reg)) {
332    for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
333      // FIXME: This should probably be:
334      // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
335      regsReserved.set(*Sub);
336    }
337  }
338  markReachable(&MF->front());
339}
340
341// Does iterator point to a and b as the first two elements?
342static bool matchPair(MachineBasicBlock::const_succ_iterator i,
343                      const MachineBasicBlock *a, const MachineBasicBlock *b) {
344  if (*i == a)
345    return *++i == b;
346  if (*i == b)
347    return *++i == a;
348  return false;
349}
350
351void
352MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
353  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
354
355  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
356  MachineBasicBlock *TBB = 0, *FBB = 0;
357  SmallVector<MachineOperand, 4> Cond;
358  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
359                          TBB, FBB, Cond)) {
360    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
361    // check whether its answers match up with reality.
362    if (!TBB && !FBB) {
363      // Block falls through to its successor.
364      MachineFunction::const_iterator MBBI = MBB;
365      ++MBBI;
366      if (MBBI == MF->end()) {
367        // It's possible that the block legitimately ends with a noreturn
368        // call or an unreachable, in which case it won't actually fall
369        // out the bottom of the function.
370      } else if (MBB->succ_empty()) {
371        // It's possible that the block legitimately ends with a noreturn
372        // call or an unreachable, in which case it won't actuall fall
373        // out of the block.
374      } else if (MBB->succ_size() != 1) {
375        report("MBB exits via unconditional fall-through but doesn't have "
376               "exactly one CFG successor!", MBB);
377      } else if (MBB->succ_begin()[0] != MBBI) {
378        report("MBB exits via unconditional fall-through but its successor "
379               "differs from its CFG successor!", MBB);
380      }
381      if (!MBB->empty() && MBB->back().getDesc().isBarrier() &&
382          !TII->isPredicated(&MBB->back())) {
383        report("MBB exits via unconditional fall-through but ends with a "
384               "barrier instruction!", MBB);
385      }
386      if (!Cond.empty()) {
387        report("MBB exits via unconditional fall-through but has a condition!",
388               MBB);
389      }
390    } else if (TBB && !FBB && Cond.empty()) {
391      // Block unconditionally branches somewhere.
392      if (MBB->succ_size() != 1) {
393        report("MBB exits via unconditional branch but doesn't have "
394               "exactly one CFG successor!", MBB);
395      } else if (MBB->succ_begin()[0] != TBB) {
396        report("MBB exits via unconditional branch but the CFG "
397               "successor doesn't match the actual successor!", MBB);
398      }
399      if (MBB->empty()) {
400        report("MBB exits via unconditional branch but doesn't contain "
401               "any instructions!", MBB);
402      } else if (!MBB->back().getDesc().isBarrier()) {
403        report("MBB exits via unconditional branch but doesn't end with a "
404               "barrier instruction!", MBB);
405      } else if (!MBB->back().getDesc().isTerminator()) {
406        report("MBB exits via unconditional branch but the branch isn't a "
407               "terminator instruction!", MBB);
408      }
409    } else if (TBB && !FBB && !Cond.empty()) {
410      // Block conditionally branches somewhere, otherwise falls through.
411      MachineFunction::const_iterator MBBI = MBB;
412      ++MBBI;
413      if (MBBI == MF->end()) {
414        report("MBB conditionally falls through out of function!", MBB);
415      } if (MBB->succ_size() != 2) {
416        report("MBB exits via conditional branch/fall-through but doesn't have "
417               "exactly two CFG successors!", MBB);
418      } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
419        report("MBB exits via conditional branch/fall-through but the CFG "
420               "successors don't match the actual successors!", MBB);
421      }
422      if (MBB->empty()) {
423        report("MBB exits via conditional branch/fall-through but doesn't "
424               "contain any instructions!", MBB);
425      } else if (MBB->back().getDesc().isBarrier()) {
426        report("MBB exits via conditional branch/fall-through but ends with a "
427               "barrier instruction!", MBB);
428      } else if (!MBB->back().getDesc().isTerminator()) {
429        report("MBB exits via conditional branch/fall-through but the branch "
430               "isn't a terminator instruction!", MBB);
431      }
432    } else if (TBB && FBB) {
433      // Block conditionally branches somewhere, otherwise branches
434      // somewhere else.
435      if (MBB->succ_size() != 2) {
436        report("MBB exits via conditional branch/branch but doesn't have "
437               "exactly two CFG successors!", MBB);
438      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
439        report("MBB exits via conditional branch/branch but the CFG "
440               "successors don't match the actual successors!", MBB);
441      }
442      if (MBB->empty()) {
443        report("MBB exits via conditional branch/branch but doesn't "
444               "contain any instructions!", MBB);
445      } else if (!MBB->back().getDesc().isBarrier()) {
446        report("MBB exits via conditional branch/branch but doesn't end with a "
447               "barrier instruction!", MBB);
448      } else if (!MBB->back().getDesc().isTerminator()) {
449        report("MBB exits via conditional branch/branch but the branch "
450               "isn't a terminator instruction!", MBB);
451      }
452      if (Cond.empty()) {
453        report("MBB exits via conditinal branch/branch but there's no "
454               "condition!", MBB);
455      }
456    } else {
457      report("AnalyzeBranch returned invalid data!", MBB);
458    }
459  }
460
461  regsLive.clear();
462  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
463         E = MBB->livein_end(); I != E; ++I) {
464    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
465      report("MBB live-in list contains non-physical register", MBB);
466      continue;
467    }
468    regsLive.insert(*I);
469    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
470      regsLive.insert(*R);
471  }
472  regsLiveInButUnused = regsLive;
473
474  const MachineFrameInfo *MFI = MF->getFrameInfo();
475  assert(MFI && "Function has no frame info");
476  BitVector PR = MFI->getPristineRegs(MBB);
477  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
478    regsLive.insert(I);
479    for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
480      regsLive.insert(*R);
481  }
482
483  regsKilled.clear();
484  regsDefined.clear();
485}
486
487void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
488  const TargetInstrDesc &TI = MI->getDesc();
489  if (MI->getNumOperands() < TI.getNumOperands()) {
490    report("Too few operands", MI);
491    *OS << TI.getNumOperands() << " operands expected, but "
492        << MI->getNumExplicitOperands() << " given.\n";
493  }
494
495  // Check the MachineMemOperands for basic consistency.
496  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
497       E = MI->memoperands_end(); I != E; ++I) {
498    if ((*I)->isLoad() && !TI.mayLoad())
499      report("Missing mayLoad flag", MI);
500    if ((*I)->isStore() && !TI.mayStore())
501      report("Missing mayStore flag", MI);
502  }
503}
504
505void
506MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
507  const MachineInstr *MI = MO->getParent();
508  const TargetInstrDesc &TI = MI->getDesc();
509
510  // The first TI.NumDefs operands must be explicit register defines
511  if (MONum < TI.getNumDefs()) {
512    if (!MO->isReg())
513      report("Explicit definition must be a register", MO, MONum);
514    else if (!MO->isDef())
515      report("Explicit definition marked as use", MO, MONum);
516    else if (MO->isImplicit())
517      report("Explicit definition marked as implicit", MO, MONum);
518  } else if (MONum < TI.getNumOperands()) {
519    if (MO->isReg()) {
520      if (MO->isDef())
521        report("Explicit operand marked as def", MO, MONum);
522      if (MO->isImplicit())
523        report("Explicit operand marked as implicit", MO, MONum);
524    }
525  } else {
526    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
527    if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg())
528      report("Extra explicit operand on non-variadic instruction", MO, MONum);
529  }
530
531  switch (MO->getType()) {
532  case MachineOperand::MO_Register: {
533    const unsigned Reg = MO->getReg();
534    if (!Reg)
535      return;
536
537    // Check Live Variables.
538    if (MO->isUndef()) {
539      // An <undef> doesn't refer to any register, so just skip it.
540    } else if (MO->isUse()) {
541      regsLiveInButUnused.erase(Reg);
542
543      bool isKill = false;
544      unsigned defIdx;
545      if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
546        // A two-addr use counts as a kill if use and def are the same.
547        unsigned DefReg = MI->getOperand(defIdx).getReg();
548        if (Reg == DefReg) {
549          isKill = true;
550          // ANd in that case an explicit kill flag is not allowed.
551          if (MO->isKill())
552            report("Illegal kill flag on two-address instruction operand",
553                   MO, MONum);
554        } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
555          report("Two-address instruction operands must be identical",
556                 MO, MONum);
557        }
558      } else
559        isKill = MO->isKill();
560
561      if (isKill) {
562        addRegWithSubRegs(regsKilled, Reg);
563
564        // Check that LiveVars knows this kill
565        if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
566          LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
567          if (std::find(VI.Kills.begin(),
568                        VI.Kills.end(), MI) == VI.Kills.end())
569            report("Kill missing from LiveVariables", MO, MONum);
570        }
571      }
572
573      // Use of a dead register.
574      if (!regsLive.count(Reg)) {
575        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
576          // Reserved registers may be used even when 'dead'.
577          if (!isReserved(Reg))
578            report("Using an undefined physical register", MO, MONum);
579        } else {
580          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
581          // We don't know which virtual registers are live in, so only complain
582          // if vreg was killed in this MBB. Otherwise keep track of vregs that
583          // must be live in. PHI instructions are handled separately.
584          if (MInfo.regsKilled.count(Reg))
585            report("Using a killed virtual register", MO, MONum);
586          else if (!MI->isPHI())
587            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
588        }
589      }
590    } else {
591      assert(MO->isDef());
592      // Register defined.
593      // TODO: verify that earlyclobber ops are not used.
594      if (MO->isDead())
595        addRegWithSubRegs(regsDead, Reg);
596      else
597        addRegWithSubRegs(regsDefined, Reg);
598    }
599
600    // Check register classes.
601    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
602      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
603      unsigned SubIdx = MO->getSubReg();
604
605      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
606        unsigned sr = Reg;
607        if (SubIdx) {
608          unsigned s = TRI->getSubReg(Reg, SubIdx);
609          if (!s) {
610            report("Invalid subregister index for physical register",
611                   MO, MONum);
612            return;
613          }
614          sr = s;
615        }
616        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
617          if (!DRC->contains(sr)) {
618            report("Illegal physical register for instruction", MO, MONum);
619            *OS << TRI->getName(sr) << " is not a "
620                << DRC->getName() << " register.\n";
621          }
622        }
623      } else {
624        // Virtual register.
625        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
626        if (SubIdx) {
627          const TargetRegisterClass *SRC = RC->getSubRegisterRegClass(SubIdx);
628          if (!SRC) {
629            report("Invalid subregister index for virtual register", MO, MONum);
630            *OS << "Register class " << RC->getName()
631                << " does not support subreg index " << SubIdx << "\n";
632            return;
633          }
634          RC = SRC;
635        }
636        if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
637          if (RC != DRC && !RC->hasSuperClass(DRC)) {
638            report("Illegal virtual register for instruction", MO, MONum);
639            *OS << "Expected a " << DRC->getName() << " register, but got a "
640                << RC->getName() << " register\n";
641          }
642        }
643      }
644    }
645    break;
646  }
647
648  case MachineOperand::MO_MachineBasicBlock:
649    if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
650      report("PHI operand is not in the CFG", MO, MONum);
651    break;
652
653  default:
654    break;
655  }
656}
657
658void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
659  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
660  set_union(MInfo.regsKilled, regsKilled);
661  set_subtract(regsLive, regsKilled); regsKilled.clear();
662  set_subtract(regsLive, regsDead);   regsDead.clear();
663  set_union(regsLive, regsDefined);   regsDefined.clear();
664}
665
666void
667MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
668  MBBInfoMap[MBB].regsLiveOut = regsLive;
669  regsLive.clear();
670}
671
672// Calculate the largest possible vregsPassed sets. These are the registers that
673// can pass through an MBB live, but may not be live every time. It is assumed
674// that all vregsPassed sets are empty before the call.
675void MachineVerifier::calcRegsPassed() {
676  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
677  // have any vregsPassed.
678  DenseSet<const MachineBasicBlock*> todo;
679  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
680       MFI != MFE; ++MFI) {
681    const MachineBasicBlock &MBB(*MFI);
682    BBInfo &MInfo = MBBInfoMap[&MBB];
683    if (!MInfo.reachable)
684      continue;
685    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
686           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
687      BBInfo &SInfo = MBBInfoMap[*SuI];
688      if (SInfo.addPassed(MInfo.regsLiveOut))
689        todo.insert(*SuI);
690    }
691  }
692
693  // Iteratively push vregsPassed to successors. This will converge to the same
694  // final state regardless of DenseSet iteration order.
695  while (!todo.empty()) {
696    const MachineBasicBlock *MBB = *todo.begin();
697    todo.erase(MBB);
698    BBInfo &MInfo = MBBInfoMap[MBB];
699    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
700           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
701      if (*SuI == MBB)
702        continue;
703      BBInfo &SInfo = MBBInfoMap[*SuI];
704      if (SInfo.addPassed(MInfo.vregsPassed))
705        todo.insert(*SuI);
706    }
707  }
708}
709
710// Calculate the set of virtual registers that must be passed through each basic
711// block in order to satisfy the requirements of successor blocks. This is very
712// similar to calcRegsPassed, only backwards.
713void MachineVerifier::calcRegsRequired() {
714  // First push live-in regs to predecessors' vregsRequired.
715  DenseSet<const MachineBasicBlock*> todo;
716  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
717       MFI != MFE; ++MFI) {
718    const MachineBasicBlock &MBB(*MFI);
719    BBInfo &MInfo = MBBInfoMap[&MBB];
720    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
721           PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
722      BBInfo &PInfo = MBBInfoMap[*PrI];
723      if (PInfo.addRequired(MInfo.vregsLiveIn))
724        todo.insert(*PrI);
725    }
726  }
727
728  // Iteratively push vregsRequired to predecessors. This will converge to the
729  // same final state regardless of DenseSet iteration order.
730  while (!todo.empty()) {
731    const MachineBasicBlock *MBB = *todo.begin();
732    todo.erase(MBB);
733    BBInfo &MInfo = MBBInfoMap[MBB];
734    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
735           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
736      if (*PrI == MBB)
737        continue;
738      BBInfo &SInfo = MBBInfoMap[*PrI];
739      if (SInfo.addRequired(MInfo.vregsRequired))
740        todo.insert(*PrI);
741    }
742  }
743}
744
745// Check PHI instructions at the beginning of MBB. It is assumed that
746// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
747void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
748  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
749       BBI != BBE && BBI->isPHI(); ++BBI) {
750    DenseSet<const MachineBasicBlock*> seen;
751
752    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
753      unsigned Reg = BBI->getOperand(i).getReg();
754      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
755      if (!Pre->isSuccessor(MBB))
756        continue;
757      seen.insert(Pre);
758      BBInfo &PrInfo = MBBInfoMap[Pre];
759      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
760        report("PHI operand is not live-out from predecessor",
761               &BBI->getOperand(i), i);
762    }
763
764    // Did we see all predecessors?
765    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
766           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
767      if (!seen.count(*PrI)) {
768        report("Missing PHI operand", BBI);
769        *OS << "BB#" << (*PrI)->getNumber()
770            << " is a predecessor according to the CFG.\n";
771      }
772    }
773  }
774}
775
776void MachineVerifier::visitMachineFunctionAfter() {
777  calcRegsPassed();
778
779  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
780       MFI != MFE; ++MFI) {
781    BBInfo &MInfo = MBBInfoMap[MFI];
782
783    // Skip unreachable MBBs.
784    if (!MInfo.reachable)
785      continue;
786
787    checkPHIOps(MFI);
788  }
789
790  // Now check LiveVariables info if available
791  if (LiveVars) {
792    calcRegsRequired();
793    verifyLiveVariables();
794  }
795}
796
797void MachineVerifier::verifyLiveVariables() {
798  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
799  for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
800         RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
801    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
802    for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
803         MFI != MFE; ++MFI) {
804      BBInfo &MInfo = MBBInfoMap[MFI];
805
806      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
807      if (MInfo.vregsRequired.count(Reg)) {
808        if (!VI.AliveBlocks.test(MFI->getNumber())) {
809          report("LiveVariables: Block missing from AliveBlocks", MFI);
810          *OS << "Virtual register %reg" << Reg
811              << " must be live through the block.\n";
812        }
813      } else {
814        if (VI.AliveBlocks.test(MFI->getNumber())) {
815          report("LiveVariables: Block should not be in AliveBlocks", MFI);
816          *OS << "Virtual register %reg" << Reg
817              << " is not needed live through the block.\n";
818        }
819      }
820    }
821  }
822}
823
824
825