PHIElimination.cpp revision 4930e7266b7643410cfbbed5ef6e4d3b19178918
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "llvm/CodeGen/Passes.h" 18#include "PHIEliminationUtils.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/SmallPtrSet.h" 21#include "llvm/ADT/Statistic.h" 22#include "llvm/CodeGen/LiveIntervalAnalysis.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineDominators.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineLoopInfo.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/IR/Function.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Compiler.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Target/TargetInstrInfo.h" 34#include "llvm/Target/TargetMachine.h" 35#include <algorithm> 36using namespace llvm; 37 38static cl::opt<bool> 39DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), 40 cl::Hidden, cl::desc("Disable critical edge splitting " 41 "during PHI elimination")); 42 43static cl::opt<bool> 44SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false), 45 cl::Hidden, cl::desc("Split all critical edges during " 46 "PHI elimination")); 47 48namespace { 49 class PHIElimination : public MachineFunctionPass { 50 MachineRegisterInfo *MRI; // Machine register information 51 LiveVariables *LV; 52 LiveIntervals *LIS; 53 54 public: 55 static char ID; // Pass identification, replacement for typeid 56 PHIElimination() : MachineFunctionPass(ID) { 57 initializePHIEliminationPass(*PassRegistry::getPassRegistry()); 58 } 59 60 virtual bool runOnMachineFunction(MachineFunction &Fn); 61 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 62 63 private: 64 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions 65 /// in predecessor basic blocks. 66 /// 67 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); 68 void LowerPHINode(MachineBasicBlock &MBB, 69 MachineBasicBlock::iterator AfterPHIsIt); 70 71 /// analyzePHINodes - Gather information about the PHI nodes in 72 /// here. In particular, we want to map the number of uses of a virtual 73 /// register which is used in a PHI node. We map that to the BB the 74 /// vreg is coming from. This is used later to determine when the vreg 75 /// is killed in the BB. 76 /// 77 void analyzePHINodes(const MachineFunction& Fn); 78 79 /// Split critical edges where necessary for good coalescer performance. 80 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, 81 MachineLoopInfo *MLI); 82 83 // These functions are temporary abstractions around LiveVariables and 84 // LiveIntervals, so they can go away when LiveVariables does. 85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB); 86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB); 87 88 typedef std::pair<unsigned, unsigned> BBVRegPair; 89 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse; 90 91 VRegPHIUse VRegPHIUseCount; 92 93 // Defs of PHI sources which are implicit_def. 94 SmallPtrSet<MachineInstr*, 4> ImpDefs; 95 96 // Map reusable lowered PHI node -> incoming join register. 97 typedef DenseMap<MachineInstr*, unsigned, 98 MachineInstrExpressionTrait> LoweredPHIMap; 99 LoweredPHIMap LoweredPHIs; 100 }; 101} 102 103STATISTIC(NumLowered, "Number of phis lowered"); 104STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split"); 105STATISTIC(NumReused, "Number of reused lowered phis"); 106 107char PHIElimination::ID = 0; 108char& llvm::PHIEliminationID = PHIElimination::ID; 109 110INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination", 111 "Eliminate PHI nodes for register allocation", 112 false, false) 113INITIALIZE_PASS_DEPENDENCY(LiveVariables) 114INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination", 115 "Eliminate PHI nodes for register allocation", false, false) 116 117void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { 118 AU.addPreserved<LiveVariables>(); 119 AU.addPreserved<LiveIntervals>(); 120 AU.addPreserved<MachineDominatorTree>(); 121 AU.addPreserved<MachineLoopInfo>(); 122 MachineFunctionPass::getAnalysisUsage(AU); 123} 124 125bool PHIElimination::runOnMachineFunction(MachineFunction &MF) { 126 MRI = &MF.getRegInfo(); 127 LV = getAnalysisIfAvailable<LiveVariables>(); 128 LIS = getAnalysisIfAvailable<LiveIntervals>(); 129 130 bool Changed = false; 131 132 // This pass takes the function out of SSA form. 133 MRI->leaveSSA(); 134 135 // Split critical edges to help the coalescer. This does not yet support 136 // updating LiveIntervals, so we disable it. 137 if (!DisableEdgeSplitting && (LV || LIS)) { 138 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>(); 139 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 140 Changed |= SplitPHIEdges(MF, *I, MLI); 141 } 142 143 // Populate VRegPHIUseCount 144 analyzePHINodes(MF); 145 146 // Eliminate PHI instructions by inserting copies into predecessor blocks. 147 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 148 Changed |= EliminatePHINodes(MF, *I); 149 150 // Remove dead IMPLICIT_DEF instructions. 151 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(), 152 E = ImpDefs.end(); I != E; ++I) { 153 MachineInstr *DefMI = *I; 154 unsigned DefReg = DefMI->getOperand(0).getReg(); 155 if (MRI->use_nodbg_empty(DefReg)) { 156 if (LIS) 157 LIS->RemoveMachineInstrFromMaps(DefMI); 158 DefMI->eraseFromParent(); 159 } 160 } 161 162 // Clean up the lowered PHI instructions. 163 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end(); 164 I != E; ++I) { 165 if (LIS) 166 LIS->RemoveMachineInstrFromMaps(I->first); 167 MF.DeleteMachineInstr(I->first); 168 } 169 170 LoweredPHIs.clear(); 171 ImpDefs.clear(); 172 VRegPHIUseCount.clear(); 173 174 if (LIS) 175 MF.verify(this, "After PHI elimination"); 176 177 return Changed; 178} 179 180/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 181/// predecessor basic blocks. 182/// 183bool PHIElimination::EliminatePHINodes(MachineFunction &MF, 184 MachineBasicBlock &MBB) { 185 if (MBB.empty() || !MBB.front().isPHI()) 186 return false; // Quick exit for basic blocks without PHIs. 187 188 // Get an iterator to the first instruction after the last PHI node (this may 189 // also be the end of the basic block). 190 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin()); 191 192 while (MBB.front().isPHI()) 193 LowerPHINode(MBB, AfterPHIsIt); 194 195 return true; 196} 197 198/// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs. 199/// This includes registers with no defs. 200static bool isImplicitlyDefined(unsigned VirtReg, 201 const MachineRegisterInfo *MRI) { 202 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg), 203 DE = MRI->def_end(); DI != DE; ++DI) 204 if (!DI->isImplicitDef()) 205 return false; 206 return true; 207} 208 209/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node 210/// are implicit_def's. 211static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 212 const MachineRegisterInfo *MRI) { 213 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 214 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI)) 215 return false; 216 return true; 217} 218 219 220/// LowerPHINode - Lower the PHI node at the top of the specified block, 221/// 222void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, 223 MachineBasicBlock::iterator AfterPHIsIt) { 224 ++NumLowered; 225 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 226 MachineInstr *MPhi = MBB.remove(MBB.begin()); 227 228 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 229 unsigned DestReg = MPhi->getOperand(0).getReg(); 230 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); 231 bool isDead = MPhi->getOperand(0).isDead(); 232 233 // Create a new register for the incoming PHI arguments. 234 MachineFunction &MF = *MBB.getParent(); 235 unsigned IncomingReg = 0; 236 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI? 237 238 // Insert a register to register copy at the top of the current block (but 239 // after any remaining phi nodes) which copies the new incoming register 240 // into the phi node destination. 241 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 242 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 243 // If all sources of a PHI node are implicit_def, just emit an 244 // implicit_def instead of a copy. 245 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 246 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 247 else { 248 // Can we reuse an earlier PHI node? This only happens for critical edges, 249 // typically those created by tail duplication. 250 unsigned &entry = LoweredPHIs[MPhi]; 251 if (entry) { 252 // An identical PHI node was already lowered. Reuse the incoming register. 253 IncomingReg = entry; 254 reusedIncoming = true; 255 ++NumReused; 256 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); 257 } else { 258 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 259 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 260 } 261 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 262 TII->get(TargetOpcode::COPY), DestReg) 263 .addReg(IncomingReg); 264 } 265 266 // Update live variable information if there is any. 267 if (LV) { 268 MachineInstr *PHICopy = prior(AfterPHIsIt); 269 270 if (IncomingReg) { 271 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg); 272 273 // Increment use count of the newly created virtual register. 274 LV->setPHIJoin(IncomingReg); 275 276 // When we are reusing the incoming register, it may already have been 277 // killed in this block. The old kill will also have been inserted at 278 // AfterPHIsIt, so it appears before the current PHICopy. 279 if (reusedIncoming) 280 if (MachineInstr *OldKill = VI.findKill(&MBB)) { 281 DEBUG(dbgs() << "Remove old kill from " << *OldKill); 282 LV->removeVirtualRegisterKilled(IncomingReg, OldKill); 283 DEBUG(MBB.dump()); 284 } 285 286 // Add information to LiveVariables to know that the incoming value is 287 // killed. Note that because the value is defined in several places (once 288 // each for each incoming block), the "def" block and instruction fields 289 // for the VarInfo is not filled in. 290 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 291 } 292 293 // Since we are going to be deleting the PHI node, if it is the last use of 294 // any registers, or if the value itself is dead, we need to move this 295 // information over to the new copy we just inserted. 296 LV->removeVirtualRegistersKilled(MPhi); 297 298 // If the result is dead, update LV. 299 if (isDead) { 300 LV->addVirtualRegisterDead(DestReg, PHICopy); 301 LV->removeVirtualRegisterDead(DestReg, MPhi); 302 } 303 } 304 305 // Update LiveIntervals for the new copy or implicit def. 306 if (LIS) { 307 MachineInstr *NewInstr = prior(AfterPHIsIt); 308 LIS->InsertMachineInstrInMaps(NewInstr); 309 310 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB); 311 SlotIndex DestCopyIndex = LIS->getInstructionIndex(NewInstr); 312 if (IncomingReg) { 313 // Add the region from the beginning of MBB to the copy instruction to 314 // IncomingReg's live interval. 315 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg); 316 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex); 317 if (!IncomingVNI) 318 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex, 319 LIS->getVNInfoAllocator()); 320 IncomingLI.addRange(LiveRange(MBBStartIndex, 321 DestCopyIndex.getRegSlot(), 322 IncomingVNI)); 323 } 324 325 LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg); 326 if (NewInstr->getOperand(0).isDead()) { 327 // A dead PHI's live range begins and ends at the start of the MBB, but 328 // the lowered copy, which will still be dead, needs to begin and end at 329 // the copy instruction. 330 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex); 331 assert(OrigDestVNI && "PHI destination should be live at block entry."); 332 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot()); 333 DestLI.createDeadDef(DestCopyIndex.getRegSlot(), 334 LIS->getVNInfoAllocator()); 335 DestLI.removeValNo(OrigDestVNI); 336 } else { 337 // Otherwise, remove the region from the beginning of MBB to the copy 338 // instruction from DestReg's live interval. 339 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot()); 340 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot()); 341 assert(DestVNI && "PHI destination should be live at its definition."); 342 DestVNI->def = DestCopyIndex.getRegSlot(); 343 } 344 } 345 346 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 347 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 348 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(), 349 MPhi->getOperand(i).getReg())]; 350 351 // Now loop over all of the incoming arguments, changing them to copy into the 352 // IncomingReg register in the corresponding predecessor basic block. 353 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 354 for (int i = NumSrcs - 1; i >= 0; --i) { 355 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 356 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); 357 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() || 358 isImplicitlyDefined(SrcReg, MRI); 359 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 360 "Machine PHI Operands must all be virtual registers!"); 361 362 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 363 // path the PHI. 364 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 365 366 // Check to make sure we haven't already emitted the copy for this block. 367 // This can happen because PHI nodes may have multiple entries for the same 368 // basic block. 369 if (!MBBsInsertedInto.insert(&opBlock)) 370 continue; // If the copy has already been emitted, we're done. 371 372 // Find a safe location to insert the copy, this may be the first terminator 373 // in the block (or end()). 374 MachineBasicBlock::iterator InsertPos = 375 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); 376 377 // Insert the copy. 378 MachineInstr *NewSrcInstr = 0; 379 if (!reusedIncoming && IncomingReg) { 380 if (SrcUndef) { 381 // The source register is undefined, so there is no need for a real 382 // COPY, but we still need to ensure joint dominance by defs. 383 // Insert an IMPLICIT_DEF instruction. 384 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), 385 TII->get(TargetOpcode::IMPLICIT_DEF), 386 IncomingReg); 387 388 // Clean up the old implicit-def, if there even was one. 389 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 390 if (DefMI->isImplicitDef()) 391 ImpDefs.insert(DefMI); 392 } else { 393 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), 394 TII->get(TargetOpcode::COPY), IncomingReg) 395 .addReg(SrcReg, 0, SrcSubReg); 396 } 397 } 398 399 // We only need to update the LiveVariables kill of SrcReg if this was the 400 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live 401 // out of the predecessor. We can also ignore undef sources. 402 if (LV && !SrcUndef && 403 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && 404 !LV->isLiveOut(SrcReg, opBlock)) { 405 // We want to be able to insert a kill of the register if this PHI (aka, 406 // the copy we just inserted) is the last use of the source value. Live 407 // variable analysis conservatively handles this by saying that the value 408 // is live until the end of the block the PHI entry lives in. If the value 409 // really is dead at the PHI copy, there will be no successor blocks which 410 // have the value live-in. 411 412 // Okay, if we now know that the value is not live out of the block, we 413 // can add a kill marker in this block saying that it kills the incoming 414 // value! 415 416 // In our final twist, we have to decide which instruction kills the 417 // register. In most cases this is the copy, however, terminator 418 // instructions at the end of the block may also use the value. In this 419 // case, we should mark the last such terminator as being the killing 420 // block, not the copy. 421 MachineBasicBlock::iterator KillInst = opBlock.end(); 422 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); 423 for (MachineBasicBlock::iterator Term = FirstTerm; 424 Term != opBlock.end(); ++Term) { 425 if (Term->readsRegister(SrcReg)) 426 KillInst = Term; 427 } 428 429 if (KillInst == opBlock.end()) { 430 // No terminator uses the register. 431 432 if (reusedIncoming || !IncomingReg) { 433 // We may have to rewind a bit if we didn't insert a copy this time. 434 KillInst = FirstTerm; 435 while (KillInst != opBlock.begin()) { 436 --KillInst; 437 if (KillInst->isDebugValue()) 438 continue; 439 if (KillInst->readsRegister(SrcReg)) 440 break; 441 } 442 } else { 443 // We just inserted this copy. 444 KillInst = prior(InsertPos); 445 } 446 } 447 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); 448 449 // Finally, mark it killed. 450 LV->addVirtualRegisterKilled(SrcReg, KillInst); 451 452 // This vreg no longer lives all of the way through opBlock. 453 unsigned opBlockNum = opBlock.getNumber(); 454 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); 455 } 456 457 if (LIS) { 458 if (NewSrcInstr) { 459 LIS->InsertMachineInstrInMaps(NewSrcInstr); 460 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr); 461 } 462 463 if (!SrcUndef && 464 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) { 465 LiveInterval &SrcLI = LIS->getInterval(SrcReg); 466 467 bool isLiveOut = false; 468 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), 469 SE = opBlock.succ_end(); SI != SE; ++SI) { 470 SlotIndex startIdx = LIS->getMBBStartIdx(*SI); 471 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx); 472 473 // Definitions by other PHIs are not truly live-in for our purposes. 474 if (VNI && VNI->def != startIdx) { 475 isLiveOut = true; 476 break; 477 } 478 } 479 480 if (!isLiveOut) { 481 MachineBasicBlock::iterator KillInst = opBlock.end(); 482 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); 483 for (MachineBasicBlock::iterator Term = FirstTerm; 484 Term != opBlock.end(); ++Term) { 485 if (Term->readsRegister(SrcReg)) 486 KillInst = Term; 487 } 488 489 if (KillInst == opBlock.end()) { 490 // No terminator uses the register. 491 492 if (reusedIncoming || !IncomingReg) { 493 // We may have to rewind a bit if we didn't just insert a copy. 494 KillInst = FirstTerm; 495 while (KillInst != opBlock.begin()) { 496 --KillInst; 497 if (KillInst->isDebugValue()) 498 continue; 499 if (KillInst->readsRegister(SrcReg)) 500 break; 501 } 502 } else { 503 // We just inserted this copy. 504 KillInst = prior(InsertPos); 505 } 506 } 507 assert(KillInst->readsRegister(SrcReg) && 508 "Cannot find kill instruction"); 509 510 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst); 511 SrcLI.removeRange(LastUseIndex.getRegSlot(), 512 LIS->getMBBEndIdx(&opBlock)); 513 } 514 } 515 } 516 } 517 518 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map. 519 if (reusedIncoming || !IncomingReg) { 520 if (LIS) 521 LIS->RemoveMachineInstrFromMaps(MPhi); 522 MF.DeleteMachineInstr(MPhi); 523 } 524} 525 526/// analyzePHINodes - Gather information about the PHI nodes in here. In 527/// particular, we want to map the number of uses of a virtual register which is 528/// used in a PHI node. We map that to the BB the vreg is coming from. This is 529/// used later to determine when the vreg is killed in the BB. 530/// 531void PHIElimination::analyzePHINodes(const MachineFunction& MF) { 532 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 533 I != E; ++I) 534 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 535 BBI != BBE && BBI->isPHI(); ++BBI) 536 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 537 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(), 538 BBI->getOperand(i).getReg())]; 539} 540 541bool PHIElimination::SplitPHIEdges(MachineFunction &MF, 542 MachineBasicBlock &MBB, 543 MachineLoopInfo *MLI) { 544 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad()) 545 return false; // Quick exit for basic blocks without PHIs. 546 547 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0; 548 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader(); 549 550 bool Changed = false; 551 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end(); 552 BBI != BBE && BBI->isPHI(); ++BBI) { 553 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 554 unsigned Reg = BBI->getOperand(i).getReg(); 555 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB(); 556 // Is there a critical edge from PreMBB to MBB? 557 if (PreMBB->succ_size() == 1) 558 continue; 559 560 // Avoid splitting backedges of loops. It would introduce small 561 // out-of-line blocks into the loop which is very bad for code placement. 562 if (PreMBB == &MBB && !SplitAllCriticalEdges) 563 continue; 564 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0; 565 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges) 566 continue; 567 568 // LV doesn't consider a phi use live-out, so isLiveOut only returns true 569 // when the source register is live-out for some other reason than a phi 570 // use. That means the copy we will insert in PreMBB won't be a kill, and 571 // there is a risk it may not be coalesced away. 572 // 573 // If the copy would be a kill, there is no need to split the edge. 574 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges) 575 continue; 576 577 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" 578 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber() 579 << ": " << *BBI); 580 581 // If Reg is not live-in to MBB, it means it must be live-in to some 582 // other PreMBB successor, and we can avoid the interference by splitting 583 // the edge. 584 // 585 // If Reg *is* live-in to MBB, the interference is inevitable and a copy 586 // is likely to be left after coalescing. If we are looking at a loop 587 // exiting edge, split it so we won't insert code in the loop, otherwise 588 // don't bother. 589 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges; 590 591 // Check for a loop exiting edge. 592 if (!ShouldSplit && CurLoop != PreLoop) { 593 DEBUG({ 594 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n"; 595 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop; 596 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop; 597 }); 598 // This edge could be entering a loop, exiting a loop, or it could be 599 // both: Jumping directly form one loop to the header of a sibling 600 // loop. 601 // Split unless this edge is entering CurLoop from an outer loop. 602 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop); 603 } 604 if (!ShouldSplit) 605 continue; 606 if (!PreMBB->SplitCriticalEdge(&MBB, this)) { 607 DEBUG(dbgs() << "Failed to split ciritcal edge.\n"); 608 continue; 609 } 610 Changed = true; 611 ++NumCriticalEdgesSplit; 612 } 613 } 614 return Changed; 615} 616 617bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) { 618 assert((LV || LIS) && 619 "isLiveIn() requires either LiveVariables or LiveIntervals"); 620 if (LIS) 621 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB); 622 else 623 return LV->isLiveIn(Reg, *MBB); 624} 625 626bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) { 627 assert((LV || LIS) && 628 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals"); 629 // LiveVariables considers uses in PHIs to be in the predecessor basic block, 630 // so that a register used only in a PHI is not live out of the block. In 631 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than 632 // in the predecessor basic block, so that a register used only in a PHI is live 633 // out of the block. 634 if (LIS) { 635 const LiveInterval &LI = LIS->getInterval(Reg); 636 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 637 SE = MBB->succ_end(); SI != SE; ++SI) { 638 if (LI.liveAt(LIS->getMBBStartIdx(*SI))) 639 return true; 640 } 641 return false; 642 } else { 643 return LV->isLiveOut(Reg, *MBB); 644 } 645} 646