PHIElimination.cpp revision 4f659eccafe34efea2a4ba6e57ad09977e9157c2
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "llvm/CodeGen/Passes.h" 18#include "PHIEliminationUtils.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/SmallPtrSet.h" 21#include "llvm/ADT/Statistic.h" 22#include "llvm/CodeGen/LiveIntervalAnalysis.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineDominators.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineLoopInfo.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/IR/Function.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Compiler.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Target/TargetInstrInfo.h" 34#include "llvm/Target/TargetMachine.h" 35#include <algorithm> 36using namespace llvm; 37 38static cl::opt<bool> 39DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), 40 cl::Hidden, cl::desc("Disable critical edge splitting " 41 "during PHI elimination")); 42 43static cl::opt<bool> 44SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false), 45 cl::Hidden, cl::desc("Split all critical edges during " 46 "PHI elimination")); 47 48namespace { 49 class PHIElimination : public MachineFunctionPass { 50 MachineRegisterInfo *MRI; // Machine register information 51 LiveVariables *LV; 52 LiveIntervals *LIS; 53 54 public: 55 static char ID; // Pass identification, replacement for typeid 56 PHIElimination() : MachineFunctionPass(ID) { 57 initializePHIEliminationPass(*PassRegistry::getPassRegistry()); 58 } 59 60 virtual bool runOnMachineFunction(MachineFunction &Fn); 61 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 62 63 private: 64 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions 65 /// in predecessor basic blocks. 66 /// 67 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); 68 void LowerPHINode(MachineBasicBlock &MBB, 69 MachineBasicBlock::iterator AfterPHIsIt); 70 71 /// analyzePHINodes - Gather information about the PHI nodes in 72 /// here. In particular, we want to map the number of uses of a virtual 73 /// register which is used in a PHI node. We map that to the BB the 74 /// vreg is coming from. This is used later to determine when the vreg 75 /// is killed in the BB. 76 /// 77 void analyzePHINodes(const MachineFunction& Fn); 78 79 /// Split critical edges where necessary for good coalescer performance. 80 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB, 81 MachineLoopInfo *MLI); 82 83 // These functions are temporary abstractions around LiveVariables and 84 // LiveIntervals, so they can go away when LiveVariables does. 85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB); 86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB); 87 88 typedef std::pair<unsigned, unsigned> BBVRegPair; 89 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse; 90 91 VRegPHIUse VRegPHIUseCount; 92 93 // Defs of PHI sources which are implicit_def. 94 SmallPtrSet<MachineInstr*, 4> ImpDefs; 95 96 // Map reusable lowered PHI node -> incoming join register. 97 typedef DenseMap<MachineInstr*, unsigned, 98 MachineInstrExpressionTrait> LoweredPHIMap; 99 LoweredPHIMap LoweredPHIs; 100 }; 101} 102 103STATISTIC(NumLowered, "Number of phis lowered"); 104STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split"); 105STATISTIC(NumReused, "Number of reused lowered phis"); 106 107char PHIElimination::ID = 0; 108char& llvm::PHIEliminationID = PHIElimination::ID; 109 110INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination", 111 "Eliminate PHI nodes for register allocation", 112 false, false) 113INITIALIZE_PASS_DEPENDENCY(LiveVariables) 114INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination", 115 "Eliminate PHI nodes for register allocation", false, false) 116 117void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { 118 AU.addPreserved<LiveVariables>(); 119 AU.addPreserved<SlotIndexes>(); 120 AU.addPreserved<LiveIntervals>(); 121 AU.addPreserved<MachineDominatorTree>(); 122 AU.addPreserved<MachineLoopInfo>(); 123 MachineFunctionPass::getAnalysisUsage(AU); 124} 125 126bool PHIElimination::runOnMachineFunction(MachineFunction &MF) { 127 MRI = &MF.getRegInfo(); 128 LV = getAnalysisIfAvailable<LiveVariables>(); 129 LIS = getAnalysisIfAvailable<LiveIntervals>(); 130 131 bool Changed = false; 132 133 // This pass takes the function out of SSA form. 134 MRI->leaveSSA(); 135 136 // Split critical edges to help the coalescer. This does not yet support 137 // updating LiveIntervals, so we disable it. 138 if (!DisableEdgeSplitting && (LV || LIS)) { 139 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>(); 140 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 141 Changed |= SplitPHIEdges(MF, *I, MLI); 142 } 143 144 // Populate VRegPHIUseCount 145 analyzePHINodes(MF); 146 147 // Eliminate PHI instructions by inserting copies into predecessor blocks. 148 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 149 Changed |= EliminatePHINodes(MF, *I); 150 151 // Remove dead IMPLICIT_DEF instructions. 152 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(), 153 E = ImpDefs.end(); I != E; ++I) { 154 MachineInstr *DefMI = *I; 155 unsigned DefReg = DefMI->getOperand(0).getReg(); 156 if (MRI->use_nodbg_empty(DefReg)) { 157 if (LIS) 158 LIS->RemoveMachineInstrFromMaps(DefMI); 159 DefMI->eraseFromParent(); 160 } 161 } 162 163 // Clean up the lowered PHI instructions. 164 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end(); 165 I != E; ++I) { 166 if (LIS) 167 LIS->RemoveMachineInstrFromMaps(I->first); 168 MF.DeleteMachineInstr(I->first); 169 } 170 171 LoweredPHIs.clear(); 172 ImpDefs.clear(); 173 VRegPHIUseCount.clear(); 174 175 if (LIS) 176 MF.verify(this, "After PHI elimination"); 177 178 return Changed; 179} 180 181/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 182/// predecessor basic blocks. 183/// 184bool PHIElimination::EliminatePHINodes(MachineFunction &MF, 185 MachineBasicBlock &MBB) { 186 if (MBB.empty() || !MBB.front().isPHI()) 187 return false; // Quick exit for basic blocks without PHIs. 188 189 // Get an iterator to the first instruction after the last PHI node (this may 190 // also be the end of the basic block). 191 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin()); 192 193 while (MBB.front().isPHI()) 194 LowerPHINode(MBB, AfterPHIsIt); 195 196 return true; 197} 198 199/// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs. 200/// This includes registers with no defs. 201static bool isImplicitlyDefined(unsigned VirtReg, 202 const MachineRegisterInfo *MRI) { 203 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg), 204 DE = MRI->def_end(); DI != DE; ++DI) 205 if (!DI->isImplicitDef()) 206 return false; 207 return true; 208} 209 210/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node 211/// are implicit_def's. 212static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 213 const MachineRegisterInfo *MRI) { 214 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 215 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI)) 216 return false; 217 return true; 218} 219 220 221/// LowerPHINode - Lower the PHI node at the top of the specified block, 222/// 223void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, 224 MachineBasicBlock::iterator AfterPHIsIt) { 225 ++NumLowered; 226 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 227 MachineInstr *MPhi = MBB.remove(MBB.begin()); 228 229 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 230 unsigned DestReg = MPhi->getOperand(0).getReg(); 231 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); 232 bool isDead = MPhi->getOperand(0).isDead(); 233 234 // Create a new register for the incoming PHI arguments. 235 MachineFunction &MF = *MBB.getParent(); 236 unsigned IncomingReg = 0; 237 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI? 238 239 // Insert a register to register copy at the top of the current block (but 240 // after any remaining phi nodes) which copies the new incoming register 241 // into the phi node destination. 242 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 243 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 244 // If all sources of a PHI node are implicit_def, just emit an 245 // implicit_def instead of a copy. 246 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 247 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 248 else { 249 // Can we reuse an earlier PHI node? This only happens for critical edges, 250 // typically those created by tail duplication. 251 unsigned &entry = LoweredPHIs[MPhi]; 252 if (entry) { 253 // An identical PHI node was already lowered. Reuse the incoming register. 254 IncomingReg = entry; 255 reusedIncoming = true; 256 ++NumReused; 257 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); 258 } else { 259 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 260 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 261 } 262 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 263 TII->get(TargetOpcode::COPY), DestReg) 264 .addReg(IncomingReg); 265 } 266 267 // Update live variable information if there is any. 268 if (LV) { 269 MachineInstr *PHICopy = prior(AfterPHIsIt); 270 271 if (IncomingReg) { 272 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg); 273 274 // Increment use count of the newly created virtual register. 275 LV->setPHIJoin(IncomingReg); 276 277 // When we are reusing the incoming register, it may already have been 278 // killed in this block. The old kill will also have been inserted at 279 // AfterPHIsIt, so it appears before the current PHICopy. 280 if (reusedIncoming) 281 if (MachineInstr *OldKill = VI.findKill(&MBB)) { 282 DEBUG(dbgs() << "Remove old kill from " << *OldKill); 283 LV->removeVirtualRegisterKilled(IncomingReg, OldKill); 284 DEBUG(MBB.dump()); 285 } 286 287 // Add information to LiveVariables to know that the incoming value is 288 // killed. Note that because the value is defined in several places (once 289 // each for each incoming block), the "def" block and instruction fields 290 // for the VarInfo is not filled in. 291 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 292 } 293 294 // Since we are going to be deleting the PHI node, if it is the last use of 295 // any registers, or if the value itself is dead, we need to move this 296 // information over to the new copy we just inserted. 297 LV->removeVirtualRegistersKilled(MPhi); 298 299 // If the result is dead, update LV. 300 if (isDead) { 301 LV->addVirtualRegisterDead(DestReg, PHICopy); 302 LV->removeVirtualRegisterDead(DestReg, MPhi); 303 } 304 } 305 306 // Update LiveIntervals for the new copy or implicit def. 307 if (LIS) { 308 MachineInstr *NewInstr = prior(AfterPHIsIt); 309 LIS->InsertMachineInstrInMaps(NewInstr); 310 311 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB); 312 SlotIndex DestCopyIndex = LIS->getInstructionIndex(NewInstr); 313 if (IncomingReg) { 314 // Add the region from the beginning of MBB to the copy instruction to 315 // IncomingReg's live interval. 316 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg); 317 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex); 318 if (!IncomingVNI) 319 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex, 320 LIS->getVNInfoAllocator()); 321 IncomingLI.addRange(LiveRange(MBBStartIndex, 322 DestCopyIndex.getRegSlot(), 323 IncomingVNI)); 324 } 325 326 LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg); 327 if (NewInstr->getOperand(0).isDead()) { 328 // A dead PHI's live range begins and ends at the start of the MBB, but 329 // the lowered copy, which will still be dead, needs to begin and end at 330 // the copy instruction. 331 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex); 332 assert(OrigDestVNI && "PHI destination should be live at block entry."); 333 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot()); 334 DestLI.createDeadDef(DestCopyIndex.getRegSlot(), 335 LIS->getVNInfoAllocator()); 336 DestLI.removeValNo(OrigDestVNI); 337 } else { 338 // Otherwise, remove the region from the beginning of MBB to the copy 339 // instruction from DestReg's live interval. 340 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot()); 341 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot()); 342 assert(DestVNI && "PHI destination should be live at its definition."); 343 DestVNI->def = DestCopyIndex.getRegSlot(); 344 } 345 } 346 347 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 348 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 349 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(), 350 MPhi->getOperand(i).getReg())]; 351 352 // Now loop over all of the incoming arguments, changing them to copy into the 353 // IncomingReg register in the corresponding predecessor basic block. 354 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 355 for (int i = NumSrcs - 1; i >= 0; --i) { 356 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 357 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); 358 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() || 359 isImplicitlyDefined(SrcReg, MRI); 360 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 361 "Machine PHI Operands must all be virtual registers!"); 362 363 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 364 // path the PHI. 365 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 366 367 // Check to make sure we haven't already emitted the copy for this block. 368 // This can happen because PHI nodes may have multiple entries for the same 369 // basic block. 370 if (!MBBsInsertedInto.insert(&opBlock)) 371 continue; // If the copy has already been emitted, we're done. 372 373 // Find a safe location to insert the copy, this may be the first terminator 374 // in the block (or end()). 375 MachineBasicBlock::iterator InsertPos = 376 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); 377 378 // Insert the copy. 379 MachineInstr *NewSrcInstr = 0; 380 if (!reusedIncoming && IncomingReg) { 381 if (SrcUndef) { 382 // The source register is undefined, so there is no need for a real 383 // COPY, but we still need to ensure joint dominance by defs. 384 // Insert an IMPLICIT_DEF instruction. 385 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), 386 TII->get(TargetOpcode::IMPLICIT_DEF), 387 IncomingReg); 388 389 // Clean up the old implicit-def, if there even was one. 390 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 391 if (DefMI->isImplicitDef()) 392 ImpDefs.insert(DefMI); 393 } else { 394 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(), 395 TII->get(TargetOpcode::COPY), IncomingReg) 396 .addReg(SrcReg, 0, SrcSubReg); 397 } 398 } 399 400 // We only need to update the LiveVariables kill of SrcReg if this was the 401 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live 402 // out of the predecessor. We can also ignore undef sources. 403 if (LV && !SrcUndef && 404 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && 405 !LV->isLiveOut(SrcReg, opBlock)) { 406 // We want to be able to insert a kill of the register if this PHI (aka, 407 // the copy we just inserted) is the last use of the source value. Live 408 // variable analysis conservatively handles this by saying that the value 409 // is live until the end of the block the PHI entry lives in. If the value 410 // really is dead at the PHI copy, there will be no successor blocks which 411 // have the value live-in. 412 413 // Okay, if we now know that the value is not live out of the block, we 414 // can add a kill marker in this block saying that it kills the incoming 415 // value! 416 417 // In our final twist, we have to decide which instruction kills the 418 // register. In most cases this is the copy, however, terminator 419 // instructions at the end of the block may also use the value. In this 420 // case, we should mark the last such terminator as being the killing 421 // block, not the copy. 422 MachineBasicBlock::iterator KillInst = opBlock.end(); 423 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); 424 for (MachineBasicBlock::iterator Term = FirstTerm; 425 Term != opBlock.end(); ++Term) { 426 if (Term->readsRegister(SrcReg)) 427 KillInst = Term; 428 } 429 430 if (KillInst == opBlock.end()) { 431 // No terminator uses the register. 432 433 if (reusedIncoming || !IncomingReg) { 434 // We may have to rewind a bit if we didn't insert a copy this time. 435 KillInst = FirstTerm; 436 while (KillInst != opBlock.begin()) { 437 --KillInst; 438 if (KillInst->isDebugValue()) 439 continue; 440 if (KillInst->readsRegister(SrcReg)) 441 break; 442 } 443 } else { 444 // We just inserted this copy. 445 KillInst = prior(InsertPos); 446 } 447 } 448 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); 449 450 // Finally, mark it killed. 451 LV->addVirtualRegisterKilled(SrcReg, KillInst); 452 453 // This vreg no longer lives all of the way through opBlock. 454 unsigned opBlockNum = opBlock.getNumber(); 455 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); 456 } 457 458 if (LIS) { 459 if (NewSrcInstr) { 460 LIS->InsertMachineInstrInMaps(NewSrcInstr); 461 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr); 462 } 463 464 if (!SrcUndef && 465 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) { 466 LiveInterval &SrcLI = LIS->getInterval(SrcReg); 467 468 bool isLiveOut = false; 469 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), 470 SE = opBlock.succ_end(); SI != SE; ++SI) { 471 SlotIndex startIdx = LIS->getMBBStartIdx(*SI); 472 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx); 473 474 // Definitions by other PHIs are not truly live-in for our purposes. 475 if (VNI && VNI->def != startIdx) { 476 isLiveOut = true; 477 break; 478 } 479 } 480 481 if (!isLiveOut) { 482 MachineBasicBlock::iterator KillInst = opBlock.end(); 483 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator(); 484 for (MachineBasicBlock::iterator Term = FirstTerm; 485 Term != opBlock.end(); ++Term) { 486 if (Term->readsRegister(SrcReg)) 487 KillInst = Term; 488 } 489 490 if (KillInst == opBlock.end()) { 491 // No terminator uses the register. 492 493 if (reusedIncoming || !IncomingReg) { 494 // We may have to rewind a bit if we didn't just insert a copy. 495 KillInst = FirstTerm; 496 while (KillInst != opBlock.begin()) { 497 --KillInst; 498 if (KillInst->isDebugValue()) 499 continue; 500 if (KillInst->readsRegister(SrcReg)) 501 break; 502 } 503 } else { 504 // We just inserted this copy. 505 KillInst = prior(InsertPos); 506 } 507 } 508 assert(KillInst->readsRegister(SrcReg) && 509 "Cannot find kill instruction"); 510 511 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst); 512 SrcLI.removeRange(LastUseIndex.getRegSlot(), 513 LIS->getMBBEndIdx(&opBlock)); 514 } 515 } 516 } 517 } 518 519 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map. 520 if (reusedIncoming || !IncomingReg) { 521 if (LIS) 522 LIS->RemoveMachineInstrFromMaps(MPhi); 523 MF.DeleteMachineInstr(MPhi); 524 } 525} 526 527/// analyzePHINodes - Gather information about the PHI nodes in here. In 528/// particular, we want to map the number of uses of a virtual register which is 529/// used in a PHI node. We map that to the BB the vreg is coming from. This is 530/// used later to determine when the vreg is killed in the BB. 531/// 532void PHIElimination::analyzePHINodes(const MachineFunction& MF) { 533 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 534 I != E; ++I) 535 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 536 BBI != BBE && BBI->isPHI(); ++BBI) 537 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 538 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(), 539 BBI->getOperand(i).getReg())]; 540} 541 542bool PHIElimination::SplitPHIEdges(MachineFunction &MF, 543 MachineBasicBlock &MBB, 544 MachineLoopInfo *MLI) { 545 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad()) 546 return false; // Quick exit for basic blocks without PHIs. 547 548 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0; 549 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader(); 550 551 bool Changed = false; 552 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end(); 553 BBI != BBE && BBI->isPHI(); ++BBI) { 554 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 555 unsigned Reg = BBI->getOperand(i).getReg(); 556 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB(); 557 // Is there a critical edge from PreMBB to MBB? 558 if (PreMBB->succ_size() == 1) 559 continue; 560 561 // Avoid splitting backedges of loops. It would introduce small 562 // out-of-line blocks into the loop which is very bad for code placement. 563 if (PreMBB == &MBB && !SplitAllCriticalEdges) 564 continue; 565 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0; 566 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges) 567 continue; 568 569 // LV doesn't consider a phi use live-out, so isLiveOut only returns true 570 // when the source register is live-out for some other reason than a phi 571 // use. That means the copy we will insert in PreMBB won't be a kill, and 572 // there is a risk it may not be coalesced away. 573 // 574 // If the copy would be a kill, there is no need to split the edge. 575 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges) 576 continue; 577 578 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" 579 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber() 580 << ": " << *BBI); 581 582 // If Reg is not live-in to MBB, it means it must be live-in to some 583 // other PreMBB successor, and we can avoid the interference by splitting 584 // the edge. 585 // 586 // If Reg *is* live-in to MBB, the interference is inevitable and a copy 587 // is likely to be left after coalescing. If we are looking at a loop 588 // exiting edge, split it so we won't insert code in the loop, otherwise 589 // don't bother. 590 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges; 591 592 // Check for a loop exiting edge. 593 if (!ShouldSplit && CurLoop != PreLoop) { 594 DEBUG({ 595 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n"; 596 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop; 597 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop; 598 }); 599 // This edge could be entering a loop, exiting a loop, or it could be 600 // both: Jumping directly form one loop to the header of a sibling 601 // loop. 602 // Split unless this edge is entering CurLoop from an outer loop. 603 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop); 604 } 605 if (!ShouldSplit) 606 continue; 607 if (!PreMBB->SplitCriticalEdge(&MBB, this)) { 608 DEBUG(dbgs() << "Failed to split ciritcal edge.\n"); 609 continue; 610 } 611 Changed = true; 612 ++NumCriticalEdgesSplit; 613 } 614 } 615 return Changed; 616} 617 618bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) { 619 assert((LV || LIS) && 620 "isLiveIn() requires either LiveVariables or LiveIntervals"); 621 if (LIS) 622 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB); 623 else 624 return LV->isLiveIn(Reg, *MBB); 625} 626 627bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) { 628 assert((LV || LIS) && 629 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals"); 630 // LiveVariables considers uses in PHIs to be in the predecessor basic block, 631 // so that a register used only in a PHI is not live out of the block. In 632 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than 633 // in the predecessor basic block, so that a register used only in a PHI is live 634 // out of the block. 635 if (LIS) { 636 const LiveInterval &LI = LIS->getInterval(Reg); 637 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 638 SE = MBB->succ_end(); SI != SE; ++SI) { 639 if (LI.liveAt(LIS->getMBBStartIdx(*SI))) 640 return true; 641 } 642 return false; 643 } else { 644 return LV->isLiveOut(Reg, *MBB); 645 } 646} 647