RegAllocPBQP.cpp revision 2a835f947a114142071456d7586118a0949499a0
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30// Author: Lang Hames 31// Email: lhames@gmail.com 32// 33//===----------------------------------------------------------------------===// 34 35#define DEBUG_TYPE "regalloc" 36 37#include "PBQP.h" 38#include "VirtRegMap.h" 39#include "llvm/CodeGen/LiveIntervalAnalysis.h" 40#include "llvm/CodeGen/LiveStackAnalysis.h" 41#include "llvm/CodeGen/MachineFunctionPass.h" 42#include "llvm/CodeGen/MachineLoopInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/RegAllocRegistry.h" 45#include "llvm/CodeGen/RegisterCoalescer.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Target/TargetInstrInfo.h" 48#include "llvm/Target/TargetMachine.h" 49#include <limits> 50#include <map> 51#include <memory> 52#include <set> 53#include <vector> 54 55using namespace llvm; 56 57static RegisterRegAlloc 58registerPBQPRepAlloc("pbqp", "PBQP register allocator", 59 createPBQPRegisterAllocator); 60 61namespace { 62 63 //! 64 //! PBQP based allocators solve the register allocation problem by mapping 65 //! register allocation problems to Partitioned Boolean Quadratic 66 //! Programming problems. 67 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass { 68 public: 69 70 static char ID; 71 72 //! Construct a PBQP register allocator. 73 PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {} 74 75 //! Return the pass name. 76 virtual const char* getPassName() const throw() { 77 return "PBQP Register Allocator"; 78 } 79 80 //! PBQP analysis usage. 81 virtual void getAnalysisUsage(AnalysisUsage &au) const { 82 au.addRequired<LiveIntervals>(); 83 au.addRequiredTransitive<RegisterCoalescer>(); 84 au.addRequired<LiveStacks>(); 85 au.addPreserved<LiveStacks>(); 86 au.addRequired<MachineLoopInfo>(); 87 au.addPreserved<MachineLoopInfo>(); 88 MachineFunctionPass::getAnalysisUsage(au); 89 } 90 91 //! Perform register allocation 92 virtual bool runOnMachineFunction(MachineFunction &MF); 93 94 private: 95 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 96 typedef std::vector<const LiveInterval*> Node2LIMap; 97 typedef std::vector<unsigned> AllowedSet; 98 typedef std::vector<AllowedSet> AllowedSetMap; 99 typedef std::set<unsigned> RegSet; 100 typedef std::pair<unsigned, unsigned> RegPair; 101 typedef std::map<RegPair, PBQPNum> CoalesceMap; 102 103 typedef std::set<LiveInterval*> LiveIntervalSet; 104 105 MachineFunction *mf; 106 const TargetMachine *tm; 107 const TargetRegisterInfo *tri; 108 const TargetInstrInfo *tii; 109 const MachineLoopInfo *loopInfo; 110 MachineRegisterInfo *mri; 111 112 LiveIntervals *lis; 113 LiveStacks *lss; 114 VirtRegMap *vrm; 115 116 LI2NodeMap li2Node; 117 Node2LIMap node2LI; 118 AllowedSetMap allowedSets; 119 LiveIntervalSet vregIntervalsToAlloc, 120 emptyVRegIntervals; 121 122 123 //! Builds a PBQP cost vector. 124 template <typename RegContainer> 125 PBQPVector* buildCostVector(unsigned vReg, 126 const RegContainer &allowed, 127 const CoalesceMap &cealesces, 128 PBQPNum spillCost) const; 129 130 //! \brief Builds a PBQP interference matrix. 131 //! 132 //! @return Either a pointer to a non-zero PBQP matrix representing the 133 //! allocation option costs, or a null pointer for a zero matrix. 134 //! 135 //! Expects allowed sets for two interfering LiveIntervals. These allowed 136 //! sets should contain only allocable registers from the LiveInterval's 137 //! register class, with any interfering pre-colored registers removed. 138 template <typename RegContainer> 139 PBQPMatrix* buildInterferenceMatrix(const RegContainer &allowed1, 140 const RegContainer &allowed2) const; 141 142 //! 143 //! Expects allowed sets for two potentially coalescable LiveIntervals, 144 //! and an estimated benefit due to coalescing. The allowed sets should 145 //! contain only allocable registers from the LiveInterval's register 146 //! classes, with any interfering pre-colored registers removed. 147 template <typename RegContainer> 148 PBQPMatrix* buildCoalescingMatrix(const RegContainer &allowed1, 149 const RegContainer &allowed2, 150 PBQPNum cBenefit) const; 151 152 //! \brief Finds coalescing opportunities and returns them as a map. 153 //! 154 //! Any entries in the map are guaranteed coalescable, even if their 155 //! corresponding live intervals overlap. 156 CoalesceMap findCoalesces(); 157 158 //! \brief Finds the initial set of vreg intervals to allocate. 159 void findVRegIntervalsToAlloc(); 160 161 //! \brief Constructs a PBQP problem representation of the register 162 //! allocation problem for this function. 163 //! 164 //! @return a PBQP solver object for the register allocation problem. 165 pbqp* constructPBQPProblem(); 166 167 //! \brief Adds a stack interval if the given live interval has been 168 //! spilled. Used to support stack slot coloring. 169 void addStackInterval(const LiveInterval *spilled, float &weight); 170 171 //! \brief Given a solved PBQP problem maps this solution back to a register 172 //! assignment. 173 bool mapPBQPToRegAlloc(pbqp *problem); 174 175 //! \brief Postprocessing before final spilling. Sets basic block "live in" 176 //! variables. 177 void finalizeAlloc() const; 178 179 }; 180 181 char PBQPRegAlloc::ID = 0; 182} 183 184 185template <typename RegContainer> 186PBQPVector* PBQPRegAlloc::buildCostVector(unsigned vReg, 187 const RegContainer &allowed, 188 const CoalesceMap &coalesces, 189 PBQPNum spillCost) const { 190 191 typedef typename RegContainer::const_iterator AllowedItr; 192 193 // Allocate vector. Additional element (0th) used for spill option 194 PBQPVector *v = new PBQPVector(allowed.size() + 1); 195 196 (*v)[0] = spillCost; 197 198 // Iterate over the allowed registers inserting coalesce benefits if there 199 // are any. 200 unsigned ai = 0; 201 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 202 itr != end; ++itr, ++ai) { 203 204 unsigned pReg = *itr; 205 206 CoalesceMap::const_iterator cmItr = 207 coalesces.find(RegPair(vReg, pReg)); 208 209 // No coalesce - on to the next preg. 210 if (cmItr == coalesces.end()) 211 continue; 212 213 // We have a coalesce - insert the benefit. 214 (*v)[ai + 1] = -cmItr->second; 215 } 216 217 return v; 218} 219 220template <typename RegContainer> 221PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix( 222 const RegContainer &allowed1, const RegContainer &allowed2) const { 223 224 typedef typename RegContainer::const_iterator RegContainerIterator; 225 226 // Construct a PBQP matrix representing the cost of allocation options. The 227 // rows and columns correspond to the allocation options for the two live 228 // intervals. Elements will be infinite where corresponding registers alias, 229 // since we cannot allocate aliasing registers to interfering live intervals. 230 // All other elements (non-aliasing combinations) will have zero cost. Note 231 // that the spill option (element 0,0) has zero cost, since we can allocate 232 // both intervals to memory safely (the cost for each individual allocation 233 // to memory is accounted for by the cost vectors for each live interval). 234 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1); 235 236 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 237 // between interfering live ranges with non-overlapping register sets (e.g. 238 // non-overlapping reg classes, or disjoint sets of allowed regs within the 239 // same class). The term "overlapping" is used advisedly: sets which do not 240 // intersect, but contain registers which alias, will have non-zero matrices. 241 // We optimize zero matrices away to improve solver speed. 242 bool isZeroMatrix = true; 243 244 245 // Row index. Starts at 1, since the 0th row is for the spill option, which 246 // is always zero. 247 unsigned ri = 1; 248 249 // Iterate over allowed sets, insert infinities where required. 250 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 251 a1Itr != a1End; ++a1Itr) { 252 253 // Column index, starts at 1 as for row index. 254 unsigned ci = 1; 255 unsigned reg1 = *a1Itr; 256 257 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 258 a2Itr != a2End; ++a2Itr) { 259 260 unsigned reg2 = *a2Itr; 261 262 // If the row/column regs are identical or alias insert an infinity. 263 if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) { 264 (*m)[ri][ci] = std::numeric_limits<PBQPNum>::infinity(); 265 isZeroMatrix = false; 266 } 267 268 ++ci; 269 } 270 271 ++ri; 272 } 273 274 // If this turns out to be a zero matrix... 275 if (isZeroMatrix) { 276 // free it and return null. 277 delete m; 278 return 0; 279 } 280 281 // ...otherwise return the cost matrix. 282 return m; 283} 284 285template <typename RegContainer> 286PBQPMatrix* PBQPRegAlloc::buildCoalescingMatrix( 287 const RegContainer &allowed1, const RegContainer &allowed2, 288 PBQPNum cBenefit) const { 289 290 typedef typename RegContainer::const_iterator RegContainerIterator; 291 292 // Construct a PBQP Matrix representing the benefits of coalescing. As with 293 // interference matrices the rows and columns represent allowed registers 294 // for the LiveIntervals which are (potentially) to be coalesced. The amount 295 // -cBenefit will be placed in any element representing the same register 296 // for both intervals. 297 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1); 298 299 // Reset costs to zero. 300 m->reset(0); 301 302 // Assume the matrix is zero till proven otherwise. Zero matrices will be 303 // optimized away as in the interference case. 304 bool isZeroMatrix = true; 305 306 // Row index. Starts at 1, since the 0th row is for the spill option, which 307 // is always zero. 308 unsigned ri = 1; 309 310 // Iterate over the allowed sets, insert coalescing benefits where 311 // appropriate. 312 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 313 a1Itr != a1End; ++a1Itr) { 314 315 // Column index, starts at 1 as for row index. 316 unsigned ci = 1; 317 unsigned reg1 = *a1Itr; 318 319 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 320 a2Itr != a2End; ++a2Itr) { 321 322 // If the row and column represent the same register insert a beneficial 323 // cost to preference this allocation - it would allow us to eliminate a 324 // move instruction. 325 if (reg1 == *a2Itr) { 326 (*m)[ri][ci] = -cBenefit; 327 isZeroMatrix = false; 328 } 329 330 ++ci; 331 } 332 333 ++ri; 334 } 335 336 // If this turns out to be a zero matrix... 337 if (isZeroMatrix) { 338 // ...free it and return null. 339 delete m; 340 return 0; 341 } 342 343 return m; 344} 345 346PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 347 348 typedef MachineFunction::const_iterator MFIterator; 349 typedef MachineBasicBlock::const_iterator MBBIterator; 350 typedef LiveInterval::const_vni_iterator VNIIterator; 351 352 CoalesceMap coalescesFound; 353 354 // To find coalesces we need to iterate over the function looking for 355 // copy instructions. 356 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 357 bbItr != bbEnd; ++bbItr) { 358 359 const MachineBasicBlock *mbb = &*bbItr; 360 361 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 362 iItr != iEnd; ++iItr) { 363 364 const MachineInstr *instr = &*iItr; 365 unsigned srcReg, dstReg; 366 367 // If this isn't a copy then continue to the next instruction. 368 if (!tii->isMoveInstr(*instr, srcReg, dstReg)) 369 continue; 370 371 // If the registers are already the same our job is nice and easy. 372 if (dstReg == srcReg) 373 continue; 374 375 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 376 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 377 378 // If both registers are physical then we can't coalesce. 379 if (srcRegIsPhysical && dstRegIsPhysical) 380 continue; 381 382 // If it's a copy that includes a virtual register but the source and 383 // destination classes differ then we can't coalesce, so continue with 384 // the next instruction. 385 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? 386 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg); 387 388 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? 389 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg); 390 391 if (srcRegClass != dstRegClass) 392 continue; 393 394 // We also need any physical regs to be allocable, coalescing with 395 // a non-allocable register is invalid. 396 if (srcRegIsPhysical) { 397 if (std::find(srcRegClass->allocation_order_begin(*mf), 398 srcRegClass->allocation_order_end(*mf), srcReg) == 399 srcRegClass->allocation_order_end(*mf)) 400 continue; 401 } 402 403 if (dstRegIsPhysical) { 404 if (std::find(dstRegClass->allocation_order_begin(*mf), 405 dstRegClass->allocation_order_end(*mf), dstReg) == 406 dstRegClass->allocation_order_end(*mf)) 407 continue; 408 } 409 410 // If we've made it here we have a copy with compatible register classes. 411 // We can probably coalesce, but we need to consider overlap. 412 const LiveInterval *srcLI = &lis->getInterval(srcReg), 413 *dstLI = &lis->getInterval(dstReg); 414 415 if (srcLI->overlaps(*dstLI)) { 416 // Even in the case of an overlap we might still be able to coalesce, 417 // but we need to make sure that no definition of either range occurs 418 // while the other range is live. 419 420 // Otherwise start by assuming we're ok. 421 bool badDef = false; 422 423 // Test all defs of the source range. 424 for (VNIIterator 425 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 426 vniItr != vniEnd; ++vniItr) { 427 428 // If we find a def that kills the coalescing opportunity then 429 // record it and break from the loop. 430 if (dstLI->liveAt((*vniItr)->def)) { 431 badDef = true; 432 break; 433 } 434 } 435 436 // If we have a bad def give up, continue to the next instruction. 437 if (badDef) 438 continue; 439 440 // Otherwise test definitions of the destination range. 441 for (VNIIterator 442 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 443 vniItr != vniEnd; ++vniItr) { 444 445 // We want to make sure we skip the copy instruction itself. 446 if ((*vniItr)->copy == instr) 447 continue; 448 449 if (srcLI->liveAt((*vniItr)->def)) { 450 badDef = true; 451 break; 452 } 453 } 454 455 // As before a bad def we give up and continue to the next instr. 456 if (badDef) 457 continue; 458 } 459 460 // If we make it to here then either the ranges didn't overlap, or they 461 // did, but none of their definitions would prevent us from coalescing. 462 // We're good to go with the coalesce. 463 464 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0; 465 466 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 467 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 468 } 469 470 } 471 472 return coalescesFound; 473} 474 475void PBQPRegAlloc::findVRegIntervalsToAlloc() { 476 477 // Iterate over all live ranges. 478 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 479 itr != end; ++itr) { 480 481 // Ignore physical ones. 482 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 483 continue; 484 485 LiveInterval *li = itr->second; 486 487 // If this live interval is non-empty we will use pbqp to allocate it. 488 // Empty intervals we allocate in a simple post-processing stage in 489 // finalizeAlloc. 490 if (!li->empty()) { 491 vregIntervalsToAlloc.insert(li); 492 } 493 else { 494 emptyVRegIntervals.insert(li); 495 } 496 } 497} 498 499pbqp* PBQPRegAlloc::constructPBQPProblem() { 500 501 typedef std::vector<const LiveInterval*> LIVector; 502 typedef std::vector<unsigned> RegVector; 503 504 // This will store the physical intervals for easy reference. 505 LIVector physIntervals; 506 507 // Start by clearing the old node <-> live interval mappings & allowed sets 508 li2Node.clear(); 509 node2LI.clear(); 510 allowedSets.clear(); 511 512 // Populate physIntervals, update preg use: 513 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 514 itr != end; ++itr) { 515 516 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 517 physIntervals.push_back(itr->second); 518 mri->setPhysRegUsed(itr->second->reg); 519 } 520 } 521 522 // Iterate over vreg intervals, construct live interval <-> node number 523 // mappings. 524 for (LiveIntervalSet::const_iterator 525 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 526 itr != end; ++itr) { 527 const LiveInterval *li = *itr; 528 529 li2Node[li] = node2LI.size(); 530 node2LI.push_back(li); 531 } 532 533 // Get the set of potential coalesces. 534 CoalesceMap coalesces(findCoalesces()); 535 536 // Construct a PBQP solver for this problem 537 pbqp *solver = alloc_pbqp(vregIntervalsToAlloc.size()); 538 539 // Resize allowedSets container appropriately. 540 allowedSets.resize(vregIntervalsToAlloc.size()); 541 542 // Iterate over virtual register intervals to compute allowed sets... 543 for (unsigned node = 0; node < node2LI.size(); ++node) { 544 545 // Grab pointers to the interval and its register class. 546 const LiveInterval *li = node2LI[node]; 547 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 548 549 // Start by assuming all allocable registers in the class are allowed... 550 RegVector liAllowed(liRC->allocation_order_begin(*mf), 551 liRC->allocation_order_end(*mf)); 552 553 // Eliminate the physical registers which overlap with this range, along 554 // with all their aliases. 555 for (LIVector::iterator pItr = physIntervals.begin(), 556 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 557 558 if (!li->overlaps(**pItr)) 559 continue; 560 561 unsigned pReg = (*pItr)->reg; 562 563 // If we get here then the live intervals overlap, but we're still ok 564 // if they're coalescable. 565 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 566 continue; 567 568 // If we get here then we have a genuine exclusion. 569 570 // Remove the overlapping reg... 571 RegVector::iterator eraseItr = 572 std::find(liAllowed.begin(), liAllowed.end(), pReg); 573 574 if (eraseItr != liAllowed.end()) 575 liAllowed.erase(eraseItr); 576 577 const unsigned *aliasItr = tri->getAliasSet(pReg); 578 579 if (aliasItr != 0) { 580 // ...and its aliases. 581 for (; *aliasItr != 0; ++aliasItr) { 582 RegVector::iterator eraseItr = 583 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 584 585 if (eraseItr != liAllowed.end()) { 586 liAllowed.erase(eraseItr); 587 } 588 } 589 } 590 } 591 592 // Copy the allowed set into a member vector for use when constructing cost 593 // vectors & matrices, and mapping PBQP solutions back to assignments. 594 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 595 596 // Set the spill cost to the interval weight, or epsilon if the 597 // interval weight is zero 598 PBQPNum spillCost = (li->weight != 0.0) ? 599 li->weight : std::numeric_limits<PBQPNum>::min(); 600 601 // Build a cost vector for this interval. 602 add_pbqp_nodecosts(solver, node, 603 buildCostVector(li->reg, allowedSets[node], coalesces, 604 spillCost)); 605 606 } 607 608 609 // Now add the cost matrices... 610 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 611 const LiveInterval *li = node2LI[node1]; 612 613 // Test for live range overlaps and insert interference matrices. 614 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 615 const LiveInterval *li2 = node2LI[node2]; 616 617 CoalesceMap::const_iterator cmItr = 618 coalesces.find(RegPair(li->reg, li2->reg)); 619 620 PBQPMatrix *m = 0; 621 622 if (cmItr != coalesces.end()) { 623 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 624 cmItr->second); 625 } 626 else if (li->overlaps(*li2)) { 627 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 628 } 629 630 if (m != 0) { 631 add_pbqp_edgecosts(solver, node1, node2, m); 632 delete m; 633 } 634 } 635 } 636 637 // We're done, PBQP problem constructed - return it. 638 return solver; 639} 640 641void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight) { 642 int stackSlot = vrm->getStackSlot(spilled->reg); 643 644 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 645 return; 646 647 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot); 648 stackInterval.weight += weight; 649 650 VNInfo *vni; 651 if (stackInterval.getNumValNums() != 0) 652 vni = stackInterval.getValNumInfo(0); 653 else 654 vni = stackInterval.getNextValue(-0U, 0, lss->getVNInfoAllocator()); 655 656 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 657 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 658} 659 660bool PBQPRegAlloc::mapPBQPToRegAlloc(pbqp *problem) { 661 662 // Set to true if we have any spills 663 bool anotherRoundNeeded = false; 664 665 // Clear the existing allocation. 666 vrm->clearAllVirt(); 667 668 // Iterate over the nodes mapping the PBQP solution to a register assignment. 669 for (unsigned node = 0; node < node2LI.size(); ++node) { 670 unsigned virtReg = node2LI[node]->reg, 671 allocSelection = get_pbqp_solution(problem, node); 672 673 // If the PBQP solution is non-zero it's a physical register... 674 if (allocSelection != 0) { 675 // Get the physical reg, subtracting 1 to account for the spill option. 676 unsigned physReg = allowedSets[node][allocSelection - 1]; 677 678 DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n"; 679 680 assert(physReg != 0); 681 682 // Add to the virt reg map and update the used phys regs. 683 vrm->assignVirt2Phys(virtReg, physReg); 684 } 685 // ...Otherwise it's a spill. 686 else { 687 688 // Make sure we ignore this virtual reg on the next round 689 // of allocation 690 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 691 692 float ssWeight; 693 694 // Insert spill ranges for this live range 695 const LiveInterval *spillInterval = node2LI[node]; 696 double oldSpillWeight = spillInterval->weight; 697 SmallVector<LiveInterval*, 8> spillIs; 698 std::vector<LiveInterval*> newSpills = 699 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm, 700 ssWeight); 701 addStackInterval(spillInterval, ssWeight); 702 703 DOUT << "VREG " << virtReg << " -> SPILLED (Cost: " 704 << oldSpillWeight << ", New vregs: "; 705 706 // Copy any newly inserted live intervals into the list of regs to 707 // allocate. 708 for (std::vector<LiveInterval*>::const_iterator 709 itr = newSpills.begin(), end = newSpills.end(); 710 itr != end; ++itr) { 711 712 assert(!(*itr)->empty() && "Empty spill range."); 713 714 DOUT << (*itr)->reg << " "; 715 716 vregIntervalsToAlloc.insert(*itr); 717 } 718 719 DOUT << ")\n"; 720 721 // We need another round if spill intervals were added. 722 anotherRoundNeeded |= !newSpills.empty(); 723 } 724 } 725 726 return !anotherRoundNeeded; 727} 728 729void PBQPRegAlloc::finalizeAlloc() const { 730 typedef LiveIntervals::iterator LIIterator; 731 typedef LiveInterval::Ranges::const_iterator LRIterator; 732 733 // First allocate registers for the empty intervals. 734 for (LiveIntervalSet::const_iterator 735 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 736 itr != end; ++itr) { 737 LiveInterval *li = *itr; 738 739 unsigned physReg = li->preference; 740 741 if (physReg == 0) { 742 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 743 physReg = *liRC->allocation_order_begin(*mf); 744 } 745 746 vrm->assignVirt2Phys(li->reg, physReg); 747 } 748 749 // Finally iterate over the basic blocks to compute and set the live-in sets. 750 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 751 MachineBasicBlock *entryMBB = &*mf->begin(); 752 753 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 754 liItr != liEnd; ++liItr) { 755 756 const LiveInterval *li = liItr->second; 757 unsigned reg = 0; 758 759 // Get the physical register for this interval 760 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 761 reg = li->reg; 762 } 763 else if (vrm->isAssignedReg(li->reg)) { 764 reg = vrm->getPhys(li->reg); 765 } 766 else { 767 // Ranges which are assigned a stack slot only are ignored. 768 continue; 769 } 770 771 // Iterate over the ranges of the current interval... 772 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 773 lrItr != lrEnd; ++lrItr) { 774 775 // Find the set of basic blocks which this range is live into... 776 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 777 // And add the physreg for this interval to their live-in sets. 778 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 779 if (liveInMBBs[i] != entryMBB) { 780 if (!liveInMBBs[i]->isLiveIn(reg)) { 781 liveInMBBs[i]->addLiveIn(reg); 782 } 783 } 784 } 785 liveInMBBs.clear(); 786 } 787 } 788 } 789 790} 791 792bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 793 794 mf = &MF; 795 tm = &mf->getTarget(); 796 tri = tm->getRegisterInfo(); 797 tii = tm->getInstrInfo(); 798 mri = &mf->getRegInfo(); 799 800 lis = &getAnalysis<LiveIntervals>(); 801 lss = &getAnalysis<LiveStacks>(); 802 loopInfo = &getAnalysis<MachineLoopInfo>(); 803 804 std::auto_ptr<VirtRegMap> vrmAutoPtr(new VirtRegMap(*mf)); 805 vrm = vrmAutoPtr.get(); 806 807 DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"; 808 809 // Allocator main loop: 810 // 811 // * Map current regalloc problem to a PBQP problem 812 // * Solve the PBQP problem 813 // * Map the solution back to a register allocation 814 // * Spill if necessary 815 // 816 // This process is continued till no more spills are generated. 817 818 // Find the vreg intervals in need of allocation. 819 findVRegIntervalsToAlloc(); 820 821 // If there aren't any then we're done here. 822 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty()) 823 return true; 824 825 // If there are non-empty intervals allocate them using pbqp. 826 if (!vregIntervalsToAlloc.empty()) { 827 828 bool pbqpAllocComplete = false; 829 unsigned round = 0; 830 831 while (!pbqpAllocComplete) { 832 DOUT << " PBQP Regalloc round " << round << ":\n"; 833 834 pbqp *problem = constructPBQPProblem(); 835 836 solve_pbqp(problem); 837 838 pbqpAllocComplete = mapPBQPToRegAlloc(problem); 839 840 free_pbqp(problem); 841 842 ++round; 843 } 844 } 845 846 // Finalise allocation, allocate empty ranges. 847 finalizeAlloc(); 848 849 vregIntervalsToAlloc.clear(); 850 emptyVRegIntervals.clear(); 851 li2Node.clear(); 852 node2LI.clear(); 853 allowedSets.clear(); 854 855 DOUT << "Post alloc VirtRegMap:\n" << *vrm << "\n"; 856 857 // Run spiller 858 std::auto_ptr<Spiller> spiller(createSpiller()); 859 spiller->runOnMachineFunction(*mf, *vrm); 860 861 return true; 862} 863 864FunctionPass* llvm::createPBQPRegisterAllocator() { 865 return new PBQPRegAlloc(); 866} 867 868 869#undef DEBUG_TYPE 870