RegAllocPBQP.cpp revision 6699fb27091927528f9f6059c3034d566dbed623
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "PBQP/HeuristicSolver.h" 35#include "PBQP/SimpleGraph.h" 36#include "PBQP/Heuristics/Briggs.h" 37#include "VirtRegMap.h" 38#include "VirtRegRewriter.h" 39#include "llvm/CodeGen/LiveIntervalAnalysis.h" 40#include "llvm/CodeGen/LiveStackAnalysis.h" 41#include "llvm/CodeGen/MachineFunctionPass.h" 42#include "llvm/CodeGen/MachineLoopInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/RegAllocRegistry.h" 45#include "llvm/CodeGen/RegisterCoalescer.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/raw_ostream.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetMachine.h" 50#include <limits> 51#include <map> 52#include <memory> 53#include <set> 54#include <vector> 55 56using namespace llvm; 57 58static RegisterRegAlloc 59registerPBQPRepAlloc("pbqp", "PBQP register allocator.", 60 llvm::createPBQPRegisterAllocator); 61 62namespace { 63 64 /// 65 /// PBQP based allocators solve the register allocation problem by mapping 66 /// register allocation problems to Partitioned Boolean Quadratic 67 /// Programming problems. 68 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass { 69 public: 70 71 static char ID; 72 73 /// Construct a PBQP register allocator. 74 PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {} 75 76 /// Return the pass name. 77 virtual const char* getPassName() const throw() { 78 return "PBQP Register Allocator"; 79 } 80 81 /// PBQP analysis usage. 82 virtual void getAnalysisUsage(AnalysisUsage &au) const { 83 au.addRequired<LiveIntervals>(); 84 //au.addRequiredID(SplitCriticalEdgesID); 85 au.addRequired<LiveStacks>(); 86 au.addPreserved<LiveStacks>(); 87 au.addRequired<MachineLoopInfo>(); 88 au.addPreserved<MachineLoopInfo>(); 89 au.addRequired<VirtRegMap>(); 90 MachineFunctionPass::getAnalysisUsage(au); 91 } 92 93 /// Perform register allocation 94 virtual bool runOnMachineFunction(MachineFunction &MF); 95 96 private: 97 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 98 typedef std::vector<const LiveInterval*> Node2LIMap; 99 typedef std::vector<unsigned> AllowedSet; 100 typedef std::vector<AllowedSet> AllowedSetMap; 101 typedef std::set<unsigned> RegSet; 102 typedef std::pair<unsigned, unsigned> RegPair; 103 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap; 104 105 typedef std::set<LiveInterval*> LiveIntervalSet; 106 107 MachineFunction *mf; 108 const TargetMachine *tm; 109 const TargetRegisterInfo *tri; 110 const TargetInstrInfo *tii; 111 const MachineLoopInfo *loopInfo; 112 MachineRegisterInfo *mri; 113 114 LiveIntervals *lis; 115 LiveStacks *lss; 116 VirtRegMap *vrm; 117 118 LI2NodeMap li2Node; 119 Node2LIMap node2LI; 120 AllowedSetMap allowedSets; 121 LiveIntervalSet vregIntervalsToAlloc, 122 emptyVRegIntervals; 123 124 125 /// Builds a PBQP cost vector. 126 template <typename RegContainer> 127 PBQP::Vector buildCostVector(unsigned vReg, 128 const RegContainer &allowed, 129 const CoalesceMap &cealesces, 130 PBQP::PBQPNum spillCost) const; 131 132 /// \brief Builds a PBQP interference matrix. 133 /// 134 /// @return Either a pointer to a non-zero PBQP matrix representing the 135 /// allocation option costs, or a null pointer for a zero matrix. 136 /// 137 /// Expects allowed sets for two interfering LiveIntervals. These allowed 138 /// sets should contain only allocable registers from the LiveInterval's 139 /// register class, with any interfering pre-colored registers removed. 140 template <typename RegContainer> 141 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, 142 const RegContainer &allowed2) const; 143 144 /// 145 /// Expects allowed sets for two potentially coalescable LiveIntervals, 146 /// and an estimated benefit due to coalescing. The allowed sets should 147 /// contain only allocable registers from the LiveInterval's register 148 /// classes, with any interfering pre-colored registers removed. 149 template <typename RegContainer> 150 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, 151 const RegContainer &allowed2, 152 PBQP::PBQPNum cBenefit) const; 153 154 /// \brief Finds coalescing opportunities and returns them as a map. 155 /// 156 /// Any entries in the map are guaranteed coalescable, even if their 157 /// corresponding live intervals overlap. 158 CoalesceMap findCoalesces(); 159 160 /// \brief Finds the initial set of vreg intervals to allocate. 161 void findVRegIntervalsToAlloc(); 162 163 /// \brief Constructs a PBQP problem representation of the register 164 /// allocation problem for this function. 165 /// 166 /// @return a PBQP solver object for the register allocation problem. 167 PBQP::SimpleGraph constructPBQPProblem(); 168 169 /// \brief Adds a stack interval if the given live interval has been 170 /// spilled. Used to support stack slot coloring. 171 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); 172 173 /// \brief Given a solved PBQP problem maps this solution back to a register 174 /// assignment. 175 bool mapPBQPToRegAlloc(const PBQP::Solution &solution); 176 177 /// \brief Postprocessing before final spilling. Sets basic block "live in" 178 /// variables. 179 void finalizeAlloc() const; 180 181 }; 182 183 char PBQPRegAlloc::ID = 0; 184} 185 186 187template <typename RegContainer> 188PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg, 189 const RegContainer &allowed, 190 const CoalesceMap &coalesces, 191 PBQP::PBQPNum spillCost) const { 192 193 typedef typename RegContainer::const_iterator AllowedItr; 194 195 // Allocate vector. Additional element (0th) used for spill option 196 PBQP::Vector v(allowed.size() + 1, 0); 197 198 v[0] = spillCost; 199 200 // Iterate over the allowed registers inserting coalesce benefits if there 201 // are any. 202 unsigned ai = 0; 203 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 204 itr != end; ++itr, ++ai) { 205 206 unsigned pReg = *itr; 207 208 CoalesceMap::const_iterator cmItr = 209 coalesces.find(RegPair(vReg, pReg)); 210 211 // No coalesce - on to the next preg. 212 if (cmItr == coalesces.end()) 213 continue; 214 215 // We have a coalesce - insert the benefit. 216 v[ai + 1] = -cmItr->second; 217 } 218 219 return v; 220} 221 222template <typename RegContainer> 223PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix( 224 const RegContainer &allowed1, const RegContainer &allowed2) const { 225 226 typedef typename RegContainer::const_iterator RegContainerIterator; 227 228 // Construct a PBQP matrix representing the cost of allocation options. The 229 // rows and columns correspond to the allocation options for the two live 230 // intervals. Elements will be infinite where corresponding registers alias, 231 // since we cannot allocate aliasing registers to interfering live intervals. 232 // All other elements (non-aliasing combinations) will have zero cost. Note 233 // that the spill option (element 0,0) has zero cost, since we can allocate 234 // both intervals to memory safely (the cost for each individual allocation 235 // to memory is accounted for by the cost vectors for each live interval). 236 PBQP::Matrix *m = 237 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 238 239 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 240 // between interfering live ranges with non-overlapping register sets (e.g. 241 // non-overlapping reg classes, or disjoint sets of allowed regs within the 242 // same class). The term "overlapping" is used advisedly: sets which do not 243 // intersect, but contain registers which alias, will have non-zero matrices. 244 // We optimize zero matrices away to improve solver speed. 245 bool isZeroMatrix = true; 246 247 248 // Row index. Starts at 1, since the 0th row is for the spill option, which 249 // is always zero. 250 unsigned ri = 1; 251 252 // Iterate over allowed sets, insert infinities where required. 253 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 254 a1Itr != a1End; ++a1Itr) { 255 256 // Column index, starts at 1 as for row index. 257 unsigned ci = 1; 258 unsigned reg1 = *a1Itr; 259 260 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 261 a2Itr != a2End; ++a2Itr) { 262 263 unsigned reg2 = *a2Itr; 264 265 // If the row/column regs are identical or alias insert an infinity. 266 if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) { 267 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity(); 268 isZeroMatrix = false; 269 } 270 271 ++ci; 272 } 273 274 ++ri; 275 } 276 277 // If this turns out to be a zero matrix... 278 if (isZeroMatrix) { 279 // free it and return null. 280 delete m; 281 return 0; 282 } 283 284 // ...otherwise return the cost matrix. 285 return m; 286} 287 288template <typename RegContainer> 289PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix( 290 const RegContainer &allowed1, const RegContainer &allowed2, 291 PBQP::PBQPNum cBenefit) const { 292 293 typedef typename RegContainer::const_iterator RegContainerIterator; 294 295 // Construct a PBQP Matrix representing the benefits of coalescing. As with 296 // interference matrices the rows and columns represent allowed registers 297 // for the LiveIntervals which are (potentially) to be coalesced. The amount 298 // -cBenefit will be placed in any element representing the same register 299 // for both intervals. 300 PBQP::Matrix *m = 301 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 302 303 // Reset costs to zero. 304 m->reset(0); 305 306 // Assume the matrix is zero till proven otherwise. Zero matrices will be 307 // optimized away as in the interference case. 308 bool isZeroMatrix = true; 309 310 // Row index. Starts at 1, since the 0th row is for the spill option, which 311 // is always zero. 312 unsigned ri = 1; 313 314 // Iterate over the allowed sets, insert coalescing benefits where 315 // appropriate. 316 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 317 a1Itr != a1End; ++a1Itr) { 318 319 // Column index, starts at 1 as for row index. 320 unsigned ci = 1; 321 unsigned reg1 = *a1Itr; 322 323 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 324 a2Itr != a2End; ++a2Itr) { 325 326 // If the row and column represent the same register insert a beneficial 327 // cost to preference this allocation - it would allow us to eliminate a 328 // move instruction. 329 if (reg1 == *a2Itr) { 330 (*m)[ri][ci] = -cBenefit; 331 isZeroMatrix = false; 332 } 333 334 ++ci; 335 } 336 337 ++ri; 338 } 339 340 // If this turns out to be a zero matrix... 341 if (isZeroMatrix) { 342 // ...free it and return null. 343 delete m; 344 return 0; 345 } 346 347 return m; 348} 349 350PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 351 352 typedef MachineFunction::const_iterator MFIterator; 353 typedef MachineBasicBlock::const_iterator MBBIterator; 354 typedef LiveInterval::const_vni_iterator VNIIterator; 355 356 CoalesceMap coalescesFound; 357 358 // To find coalesces we need to iterate over the function looking for 359 // copy instructions. 360 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 361 bbItr != bbEnd; ++bbItr) { 362 363 const MachineBasicBlock *mbb = &*bbItr; 364 365 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 366 iItr != iEnd; ++iItr) { 367 368 const MachineInstr *instr = &*iItr; 369 unsigned srcReg, dstReg, srcSubReg, dstSubReg; 370 371 // If this isn't a copy then continue to the next instruction. 372 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) 373 continue; 374 375 // If the registers are already the same our job is nice and easy. 376 if (dstReg == srcReg) 377 continue; 378 379 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 380 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 381 382 // If both registers are physical then we can't coalesce. 383 if (srcRegIsPhysical && dstRegIsPhysical) 384 continue; 385 386 // If it's a copy that includes a virtual register but the source and 387 // destination classes differ then we can't coalesce, so continue with 388 // the next instruction. 389 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? 390 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg); 391 392 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? 393 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg); 394 395 if (srcRegClass != dstRegClass) 396 continue; 397 398 // We also need any physical regs to be allocable, coalescing with 399 // a non-allocable register is invalid. 400 if (srcRegIsPhysical) { 401 if (std::find(srcRegClass->allocation_order_begin(*mf), 402 srcRegClass->allocation_order_end(*mf), srcReg) == 403 srcRegClass->allocation_order_end(*mf)) 404 continue; 405 } 406 407 if (dstRegIsPhysical) { 408 if (std::find(dstRegClass->allocation_order_begin(*mf), 409 dstRegClass->allocation_order_end(*mf), dstReg) == 410 dstRegClass->allocation_order_end(*mf)) 411 continue; 412 } 413 414 // If we've made it here we have a copy with compatible register classes. 415 // We can probably coalesce, but we need to consider overlap. 416 const LiveInterval *srcLI = &lis->getInterval(srcReg), 417 *dstLI = &lis->getInterval(dstReg); 418 419 if (srcLI->overlaps(*dstLI)) { 420 // Even in the case of an overlap we might still be able to coalesce, 421 // but we need to make sure that no definition of either range occurs 422 // while the other range is live. 423 424 // Otherwise start by assuming we're ok. 425 bool badDef = false; 426 427 // Test all defs of the source range. 428 for (VNIIterator 429 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 430 vniItr != vniEnd; ++vniItr) { 431 432 // If we find a def that kills the coalescing opportunity then 433 // record it and break from the loop. 434 if (dstLI->liveAt((*vniItr)->def)) { 435 badDef = true; 436 break; 437 } 438 } 439 440 // If we have a bad def give up, continue to the next instruction. 441 if (badDef) 442 continue; 443 444 // Otherwise test definitions of the destination range. 445 for (VNIIterator 446 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 447 vniItr != vniEnd; ++vniItr) { 448 449 // We want to make sure we skip the copy instruction itself. 450 if ((*vniItr)->copy == instr) 451 continue; 452 453 if (srcLI->liveAt((*vniItr)->def)) { 454 badDef = true; 455 break; 456 } 457 } 458 459 // As before a bad def we give up and continue to the next instr. 460 if (badDef) 461 continue; 462 } 463 464 // If we make it to here then either the ranges didn't overlap, or they 465 // did, but none of their definitions would prevent us from coalescing. 466 // We're good to go with the coalesce. 467 468 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0; 469 470 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 471 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 472 } 473 474 } 475 476 return coalescesFound; 477} 478 479void PBQPRegAlloc::findVRegIntervalsToAlloc() { 480 481 // Iterate over all live ranges. 482 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 483 itr != end; ++itr) { 484 485 // Ignore physical ones. 486 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 487 continue; 488 489 LiveInterval *li = itr->second; 490 491 // If this live interval is non-empty we will use pbqp to allocate it. 492 // Empty intervals we allocate in a simple post-processing stage in 493 // finalizeAlloc. 494 if (!li->empty()) { 495 vregIntervalsToAlloc.insert(li); 496 } 497 else { 498 emptyVRegIntervals.insert(li); 499 } 500 } 501} 502 503PBQP::SimpleGraph PBQPRegAlloc::constructPBQPProblem() { 504 505 typedef std::vector<const LiveInterval*> LIVector; 506 typedef std::vector<unsigned> RegVector; 507 typedef std::vector<PBQP::SimpleGraph::NodeIterator> NodeVector; 508 509 // This will store the physical intervals for easy reference. 510 LIVector physIntervals; 511 512 // Start by clearing the old node <-> live interval mappings & allowed sets 513 li2Node.clear(); 514 node2LI.clear(); 515 allowedSets.clear(); 516 517 // Populate physIntervals, update preg use: 518 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 519 itr != end; ++itr) { 520 521 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 522 physIntervals.push_back(itr->second); 523 mri->setPhysRegUsed(itr->second->reg); 524 } 525 } 526 527 // Iterate over vreg intervals, construct live interval <-> node number 528 // mappings. 529 for (LiveIntervalSet::const_iterator 530 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 531 itr != end; ++itr) { 532 const LiveInterval *li = *itr; 533 534 li2Node[li] = node2LI.size(); 535 node2LI.push_back(li); 536 } 537 538 // Get the set of potential coalesces. 539 CoalesceMap coalesces;//(findCoalesces()); 540 541 // Construct a PBQP solver for this problem 542 PBQP::SimpleGraph problem; 543 NodeVector problemNodes(vregIntervalsToAlloc.size()); 544 545 // Resize allowedSets container appropriately. 546 allowedSets.resize(vregIntervalsToAlloc.size()); 547 548 // Iterate over virtual register intervals to compute allowed sets... 549 for (unsigned node = 0; node < node2LI.size(); ++node) { 550 551 // Grab pointers to the interval and its register class. 552 const LiveInterval *li = node2LI[node]; 553 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 554 555 // Start by assuming all allocable registers in the class are allowed... 556 RegVector liAllowed(liRC->allocation_order_begin(*mf), 557 liRC->allocation_order_end(*mf)); 558 559 // Eliminate the physical registers which overlap with this range, along 560 // with all their aliases. 561 for (LIVector::iterator pItr = physIntervals.begin(), 562 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 563 564 if (!li->overlaps(**pItr)) 565 continue; 566 567 unsigned pReg = (*pItr)->reg; 568 569 // If we get here then the live intervals overlap, but we're still ok 570 // if they're coalescable. 571 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 572 continue; 573 574 // If we get here then we have a genuine exclusion. 575 576 // Remove the overlapping reg... 577 RegVector::iterator eraseItr = 578 std::find(liAllowed.begin(), liAllowed.end(), pReg); 579 580 if (eraseItr != liAllowed.end()) 581 liAllowed.erase(eraseItr); 582 583 const unsigned *aliasItr = tri->getAliasSet(pReg); 584 585 if (aliasItr != 0) { 586 // ...and its aliases. 587 for (; *aliasItr != 0; ++aliasItr) { 588 RegVector::iterator eraseItr = 589 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 590 591 if (eraseItr != liAllowed.end()) { 592 liAllowed.erase(eraseItr); 593 } 594 } 595 } 596 } 597 598 // Copy the allowed set into a member vector for use when constructing cost 599 // vectors & matrices, and mapping PBQP solutions back to assignments. 600 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 601 602 // Set the spill cost to the interval weight, or epsilon if the 603 // interval weight is zero 604 PBQP::PBQPNum spillCost = (li->weight != 0.0) ? 605 li->weight : std::numeric_limits<PBQP::PBQPNum>::min(); 606 607 // Build a cost vector for this interval. 608 problemNodes[node] = 609 problem.addNode( 610 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost)); 611 612 } 613 614 615 // Now add the cost matrices... 616 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 617 const LiveInterval *li = node2LI[node1]; 618 619 // Test for live range overlaps and insert interference matrices. 620 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 621 const LiveInterval *li2 = node2LI[node2]; 622 623 CoalesceMap::const_iterator cmItr = 624 coalesces.find(RegPair(li->reg, li2->reg)); 625 626 PBQP::Matrix *m = 0; 627 628 if (cmItr != coalesces.end()) { 629 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 630 cmItr->second); 631 } 632 else if (li->overlaps(*li2)) { 633 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 634 } 635 636 if (m != 0) { 637 problem.addEdge(problemNodes[node1], 638 problemNodes[node2], 639 *m); 640 641 delete m; 642 } 643 } 644 } 645 646 problem.assignNodeIDs(); 647 648 assert(problem.getNumNodes() == allowedSets.size()); 649 for (unsigned i = 0; i < allowedSets.size(); ++i) { 650 assert(problem.getNodeItr(i) == problemNodes[i]); 651 } 652/* 653 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, " 654 << problem.getNumEdges() << " edges.\n"; 655 656 problem.printDot(std::cerr); 657*/ 658 // We're done, PBQP problem constructed - return it. 659 return problem; 660} 661 662void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, 663 MachineRegisterInfo* mri) { 664 int stackSlot = vrm->getStackSlot(spilled->reg); 665 666 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 667 return; 668 669 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); 670 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC); 671 672 VNInfo *vni; 673 if (stackInterval.getNumValNums() != 0) 674 vni = stackInterval.getValNumInfo(0); 675 else 676 vni = stackInterval.getNextValue(0, 0, false, lss->getVNInfoAllocator()); 677 678 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 679 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 680} 681 682bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { 683 684 static unsigned round = 0; 685 686 // Set to true if we have any spills 687 bool anotherRoundNeeded = false; 688 689 // Clear the existing allocation. 690 vrm->clearAllVirt(); 691 692 CoalesceMap coalesces;//(findCoalesces()); 693 694 for (unsigned i = 0; i < node2LI.size(); ++i) { 695 if (solution.getSelection(i) == 0) { 696 continue; 697 } 698 699 unsigned iSel = solution.getSelection(i); 700 unsigned iAlloc = allowedSets[i][iSel - 1]; 701 702 for (unsigned j = i + 1; j < node2LI.size(); ++j) { 703 704 if (solution.getSelection(j) == 0) { 705 continue; 706 } 707 708 unsigned jSel = solution.getSelection(j); 709 unsigned jAlloc = allowedSets[j][jSel - 1]; 710 711 if ((iAlloc != jAlloc) && !tri->areAliases(iAlloc, jAlloc)) { 712 continue; 713 } 714 715 if (node2LI[i]->overlaps(*node2LI[j])) { 716 if (coalesces.find(RegPair(node2LI[i]->reg, node2LI[j]->reg)) == coalesces.end()) { 717 DEBUG(errs() << "In round " << ++round << ":\n" 718 << "Bogusness in " << mf->getFunction()->getName() << "!\n" 719 << "Live interval " << i << " (reg" << node2LI[i]->reg << ") and\n" 720 << "Live interval " << j << " (reg" << node2LI[j]->reg << ")\n" 721 << " were allocated registers " << iAlloc << " (index " << iSel << ") and " 722 << jAlloc << "(index " << jSel 723 << ") respectively in a graph of " << solution.numNodes() << " nodes.\n" 724 << "li[i]->empty() = " << node2LI[i]->empty() << "\n" 725 << "li[j]->empty() = " << node2LI[j]->empty() << "\n" 726 << "li[i]->overlaps(li[j]) = " << node2LI[i]->overlaps(*node2LI[j]) << "\n" 727 << "coalesce = " << (coalesces.find(RegPair(node2LI[i]->reg, node2LI[j]->reg)) != coalesces.end()) << "\n"); 728 729 DEBUG(errs() << "solution.getCost() = " << solution.getCost() << "\n"); 730 exit(1); 731 } 732 } 733 } 734 } 735 736 737 // Iterate over the nodes mapping the PBQP solution to a register assignment. 738 for (unsigned node = 0; node < node2LI.size(); ++node) { 739 unsigned virtReg = node2LI[node]->reg, 740 allocSelection = solution.getSelection(node); 741 742 743 // If the PBQP solution is non-zero it's a physical register... 744 if (allocSelection != 0) { 745 // Get the physical reg, subtracting 1 to account for the spill option. 746 unsigned physReg = allowedSets[node][allocSelection - 1]; 747 748 DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n"; 749 750 assert(physReg != 0); 751 752 // Add to the virt reg map and update the used phys regs. 753 vrm->assignVirt2Phys(virtReg, physReg); 754 } 755 // ...Otherwise it's a spill. 756 else { 757 758 // Make sure we ignore this virtual reg on the next round 759 // of allocation 760 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 761 762 // Insert spill ranges for this live range 763 const LiveInterval *spillInterval = node2LI[node]; 764 double oldSpillWeight = spillInterval->weight; 765 SmallVector<LiveInterval*, 8> spillIs; 766 std::vector<LiveInterval*> newSpills = 767 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); 768 addStackInterval(spillInterval, mri); 769 770 DOUT << "VREG " << virtReg << " -> SPILLED (Cost: " 771 << oldSpillWeight << ", New vregs: "; 772 773 // Copy any newly inserted live intervals into the list of regs to 774 // allocate. 775 for (std::vector<LiveInterval*>::const_iterator 776 itr = newSpills.begin(), end = newSpills.end(); 777 itr != end; ++itr) { 778 779 assert(!(*itr)->empty() && "Empty spill range."); 780 781 DOUT << (*itr)->reg << " "; 782 783 vregIntervalsToAlloc.insert(*itr); 784 } 785 786 DOUT << ")\n"; 787 788 // We need another round if spill intervals were added. 789 anotherRoundNeeded |= !newSpills.empty(); 790 } 791 } 792 793 return !anotherRoundNeeded; 794} 795 796void PBQPRegAlloc::finalizeAlloc() const { 797 typedef LiveIntervals::iterator LIIterator; 798 typedef LiveInterval::Ranges::const_iterator LRIterator; 799 800 // First allocate registers for the empty intervals. 801 for (LiveIntervalSet::const_iterator 802 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 803 itr != end; ++itr) { 804 LiveInterval *li = *itr; 805 806 unsigned physReg = vrm->getRegAllocPref(li->reg); 807 808 if (physReg == 0) { 809 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 810 physReg = *liRC->allocation_order_begin(*mf); 811 } 812 813 vrm->assignVirt2Phys(li->reg, physReg); 814 } 815 816 // Finally iterate over the basic blocks to compute and set the live-in sets. 817 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 818 MachineBasicBlock *entryMBB = &*mf->begin(); 819 820 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 821 liItr != liEnd; ++liItr) { 822 823 const LiveInterval *li = liItr->second; 824 unsigned reg = 0; 825 826 // Get the physical register for this interval 827 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 828 reg = li->reg; 829 } 830 else if (vrm->isAssignedReg(li->reg)) { 831 reg = vrm->getPhys(li->reg); 832 } 833 else { 834 // Ranges which are assigned a stack slot only are ignored. 835 continue; 836 } 837 838 if (reg == 0) { 839 // Filter out zero regs - they're for intervals that were spilled. 840 continue; 841 } 842 843 // Iterate over the ranges of the current interval... 844 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 845 lrItr != lrEnd; ++lrItr) { 846 847 // Find the set of basic blocks which this range is live into... 848 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 849 // And add the physreg for this interval to their live-in sets. 850 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 851 if (liveInMBBs[i] != entryMBB) { 852 if (!liveInMBBs[i]->isLiveIn(reg)) { 853 liveInMBBs[i]->addLiveIn(reg); 854 } 855 } 856 } 857 liveInMBBs.clear(); 858 } 859 } 860 } 861 862} 863 864bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 865 866 mf = &MF; 867 tm = &mf->getTarget(); 868 tri = tm->getRegisterInfo(); 869 tii = tm->getInstrInfo(); 870 mri = &mf->getRegInfo(); 871 872 lis = &getAnalysis<LiveIntervals>(); 873 lss = &getAnalysis<LiveStacks>(); 874 loopInfo = &getAnalysis<MachineLoopInfo>(); 875 876 vrm = &getAnalysis<VirtRegMap>(); 877 878 DEBUG(errs() << "PBQP2 Register Allocating for " << mf->getFunction()->getName() << "\n"); 879 880 // Allocator main loop: 881 // 882 // * Map current regalloc problem to a PBQP problem 883 // * Solve the PBQP problem 884 // * Map the solution back to a register allocation 885 // * Spill if necessary 886 // 887 // This process is continued till no more spills are generated. 888 889 // Find the vreg intervals in need of allocation. 890 findVRegIntervalsToAlloc(); 891 892 // If there aren't any then we're done here. 893 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty()) 894 return true; 895 896 // If there are non-empty intervals allocate them using pbqp. 897 if (!vregIntervalsToAlloc.empty()) { 898 899 bool pbqpAllocComplete = false; 900 unsigned round = 0; 901 902 while (!pbqpAllocComplete) { 903 DEBUG(errs() << " PBQP Regalloc round " << round << ":\n"); 904 905 PBQP::SimpleGraph problem = constructPBQPProblem(); 906 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs> solver; 907 problem.assignNodeIDs(); 908 PBQP::Solution solution = solver.solve(problem); 909/* 910 std::cerr << "Solution:\n"; 911 for (unsigned i = 0; i < solution.numNodes(); ++i) { 912 std::cerr << " " << i << " -> " << solution.getSelection(i) << "\n"; 913 } 914*/ 915 pbqpAllocComplete = mapPBQPToRegAlloc(solution); 916 917 ++round; 918 } 919 } 920 921 // Finalise allocation, allocate empty ranges. 922 finalizeAlloc(); 923 924 vregIntervalsToAlloc.clear(); 925 emptyVRegIntervals.clear(); 926 li2Node.clear(); 927 node2LI.clear(); 928 allowedSets.clear(); 929 930 DEBUG(errs() << "Post alloc VirtRegMap:\n" << *vrm << "\n"); 931 932 // Run rewriter 933 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); 934 935 rewriter->runOnMachineFunction(*mf, *vrm, lis); 936 937 return true; 938} 939 940FunctionPass* llvm::createPBQPRegisterAllocator() { 941 return new PBQPRegAlloc(); 942} 943 944 945#undef DEBUG_TYPE 946