RegAllocPBQP.cpp revision 860d482b5940d0e7fff09f50f2df409de4b989ff
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "PBQP.h" 35#include "VirtRegMap.h" 36#include "Spiller.h" 37#include "llvm/CodeGen/LiveIntervalAnalysis.h" 38#include "llvm/CodeGen/LiveStackAnalysis.h" 39#include "llvm/CodeGen/MachineFunctionPass.h" 40#include "llvm/CodeGen/MachineLoopInfo.h" 41#include "llvm/CodeGen/MachineRegisterInfo.h" 42#include "llvm/CodeGen/RegAllocRegistry.h" 43#include "llvm/CodeGen/RegisterCoalescer.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Target/TargetInstrInfo.h" 46#include "llvm/Target/TargetMachine.h" 47#include <limits> 48#include <map> 49#include <memory> 50#include <set> 51#include <vector> 52 53using namespace llvm; 54 55static RegisterRegAlloc 56registerPBQPRepAlloc("pbqp", "PBQP register allocator", 57 createPBQPRegisterAllocator); 58 59namespace { 60 61 //! 62 //! PBQP based allocators solve the register allocation problem by mapping 63 //! register allocation problems to Partitioned Boolean Quadratic 64 //! Programming problems. 65 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass { 66 public: 67 68 static char ID; 69 70 //! Construct a PBQP register allocator. 71 PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {} 72 73 //! Return the pass name. 74 virtual const char* getPassName() const throw() { 75 return "PBQP Register Allocator"; 76 } 77 78 //! PBQP analysis usage. 79 virtual void getAnalysisUsage(AnalysisUsage &au) const { 80 au.addRequired<LiveIntervals>(); 81 au.addRequiredTransitive<RegisterCoalescer>(); 82 au.addRequired<LiveStacks>(); 83 au.addPreserved<LiveStacks>(); 84 au.addRequired<MachineLoopInfo>(); 85 au.addPreserved<MachineLoopInfo>(); 86 MachineFunctionPass::getAnalysisUsage(au); 87 } 88 89 //! Perform register allocation 90 virtual bool runOnMachineFunction(MachineFunction &MF); 91 92 private: 93 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 94 typedef std::vector<const LiveInterval*> Node2LIMap; 95 typedef std::vector<unsigned> AllowedSet; 96 typedef std::vector<AllowedSet> AllowedSetMap; 97 typedef std::set<unsigned> RegSet; 98 typedef std::pair<unsigned, unsigned> RegPair; 99 typedef std::map<RegPair, PBQPNum> CoalesceMap; 100 101 typedef std::set<LiveInterval*> LiveIntervalSet; 102 103 MachineFunction *mf; 104 const TargetMachine *tm; 105 const TargetRegisterInfo *tri; 106 const TargetInstrInfo *tii; 107 const MachineLoopInfo *loopInfo; 108 MachineRegisterInfo *mri; 109 110 LiveIntervals *lis; 111 LiveStacks *lss; 112 VirtRegMap *vrm; 113 114 LI2NodeMap li2Node; 115 Node2LIMap node2LI; 116 AllowedSetMap allowedSets; 117 LiveIntervalSet vregIntervalsToAlloc, 118 emptyVRegIntervals; 119 120 121 //! Builds a PBQP cost vector. 122 template <typename RegContainer> 123 PBQPVector* buildCostVector(unsigned vReg, 124 const RegContainer &allowed, 125 const CoalesceMap &cealesces, 126 PBQPNum spillCost) const; 127 128 //! \brief Builds a PBQP interference matrix. 129 //! 130 //! @return Either a pointer to a non-zero PBQP matrix representing the 131 //! allocation option costs, or a null pointer for a zero matrix. 132 //! 133 //! Expects allowed sets for two interfering LiveIntervals. These allowed 134 //! sets should contain only allocable registers from the LiveInterval's 135 //! register class, with any interfering pre-colored registers removed. 136 template <typename RegContainer> 137 PBQPMatrix* buildInterferenceMatrix(const RegContainer &allowed1, 138 const RegContainer &allowed2) const; 139 140 //! 141 //! Expects allowed sets for two potentially coalescable LiveIntervals, 142 //! and an estimated benefit due to coalescing. The allowed sets should 143 //! contain only allocable registers from the LiveInterval's register 144 //! classes, with any interfering pre-colored registers removed. 145 template <typename RegContainer> 146 PBQPMatrix* buildCoalescingMatrix(const RegContainer &allowed1, 147 const RegContainer &allowed2, 148 PBQPNum cBenefit) const; 149 150 //! \brief Finds coalescing opportunities and returns them as a map. 151 //! 152 //! Any entries in the map are guaranteed coalescable, even if their 153 //! corresponding live intervals overlap. 154 CoalesceMap findCoalesces(); 155 156 //! \brief Finds the initial set of vreg intervals to allocate. 157 void findVRegIntervalsToAlloc(); 158 159 //! \brief Constructs a PBQP problem representation of the register 160 //! allocation problem for this function. 161 //! 162 //! @return a PBQP solver object for the register allocation problem. 163 pbqp* constructPBQPProblem(); 164 165 //! \brief Adds a stack interval if the given live interval has been 166 //! spilled. Used to support stack slot coloring. 167 void addStackInterval(const LiveInterval *spilled, float &weight); 168 169 //! \brief Given a solved PBQP problem maps this solution back to a register 170 //! assignment. 171 bool mapPBQPToRegAlloc(pbqp *problem); 172 173 //! \brief Postprocessing before final spilling. Sets basic block "live in" 174 //! variables. 175 void finalizeAlloc() const; 176 177 }; 178 179 char PBQPRegAlloc::ID = 0; 180} 181 182 183template <typename RegContainer> 184PBQPVector* PBQPRegAlloc::buildCostVector(unsigned vReg, 185 const RegContainer &allowed, 186 const CoalesceMap &coalesces, 187 PBQPNum spillCost) const { 188 189 typedef typename RegContainer::const_iterator AllowedItr; 190 191 // Allocate vector. Additional element (0th) used for spill option 192 PBQPVector *v = new PBQPVector(allowed.size() + 1); 193 194 (*v)[0] = spillCost; 195 196 // Iterate over the allowed registers inserting coalesce benefits if there 197 // are any. 198 unsigned ai = 0; 199 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 200 itr != end; ++itr, ++ai) { 201 202 unsigned pReg = *itr; 203 204 CoalesceMap::const_iterator cmItr = 205 coalesces.find(RegPair(vReg, pReg)); 206 207 // No coalesce - on to the next preg. 208 if (cmItr == coalesces.end()) 209 continue; 210 211 // We have a coalesce - insert the benefit. 212 (*v)[ai + 1] = -cmItr->second; 213 } 214 215 return v; 216} 217 218template <typename RegContainer> 219PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix( 220 const RegContainer &allowed1, const RegContainer &allowed2) const { 221 222 typedef typename RegContainer::const_iterator RegContainerIterator; 223 224 // Construct a PBQP matrix representing the cost of allocation options. The 225 // rows and columns correspond to the allocation options for the two live 226 // intervals. Elements will be infinite where corresponding registers alias, 227 // since we cannot allocate aliasing registers to interfering live intervals. 228 // All other elements (non-aliasing combinations) will have zero cost. Note 229 // that the spill option (element 0,0) has zero cost, since we can allocate 230 // both intervals to memory safely (the cost for each individual allocation 231 // to memory is accounted for by the cost vectors for each live interval). 232 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1); 233 234 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 235 // between interfering live ranges with non-overlapping register sets (e.g. 236 // non-overlapping reg classes, or disjoint sets of allowed regs within the 237 // same class). The term "overlapping" is used advisedly: sets which do not 238 // intersect, but contain registers which alias, will have non-zero matrices. 239 // We optimize zero matrices away to improve solver speed. 240 bool isZeroMatrix = true; 241 242 243 // Row index. Starts at 1, since the 0th row is for the spill option, which 244 // is always zero. 245 unsigned ri = 1; 246 247 // Iterate over allowed sets, insert infinities where required. 248 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 249 a1Itr != a1End; ++a1Itr) { 250 251 // Column index, starts at 1 as for row index. 252 unsigned ci = 1; 253 unsigned reg1 = *a1Itr; 254 255 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 256 a2Itr != a2End; ++a2Itr) { 257 258 unsigned reg2 = *a2Itr; 259 260 // If the row/column regs are identical or alias insert an infinity. 261 if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) { 262 (*m)[ri][ci] = std::numeric_limits<PBQPNum>::infinity(); 263 isZeroMatrix = false; 264 } 265 266 ++ci; 267 } 268 269 ++ri; 270 } 271 272 // If this turns out to be a zero matrix... 273 if (isZeroMatrix) { 274 // free it and return null. 275 delete m; 276 return 0; 277 } 278 279 // ...otherwise return the cost matrix. 280 return m; 281} 282 283template <typename RegContainer> 284PBQPMatrix* PBQPRegAlloc::buildCoalescingMatrix( 285 const RegContainer &allowed1, const RegContainer &allowed2, 286 PBQPNum cBenefit) const { 287 288 typedef typename RegContainer::const_iterator RegContainerIterator; 289 290 // Construct a PBQP Matrix representing the benefits of coalescing. As with 291 // interference matrices the rows and columns represent allowed registers 292 // for the LiveIntervals which are (potentially) to be coalesced. The amount 293 // -cBenefit will be placed in any element representing the same register 294 // for both intervals. 295 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1); 296 297 // Reset costs to zero. 298 m->reset(0); 299 300 // Assume the matrix is zero till proven otherwise. Zero matrices will be 301 // optimized away as in the interference case. 302 bool isZeroMatrix = true; 303 304 // Row index. Starts at 1, since the 0th row is for the spill option, which 305 // is always zero. 306 unsigned ri = 1; 307 308 // Iterate over the allowed sets, insert coalescing benefits where 309 // appropriate. 310 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 311 a1Itr != a1End; ++a1Itr) { 312 313 // Column index, starts at 1 as for row index. 314 unsigned ci = 1; 315 unsigned reg1 = *a1Itr; 316 317 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 318 a2Itr != a2End; ++a2Itr) { 319 320 // If the row and column represent the same register insert a beneficial 321 // cost to preference this allocation - it would allow us to eliminate a 322 // move instruction. 323 if (reg1 == *a2Itr) { 324 (*m)[ri][ci] = -cBenefit; 325 isZeroMatrix = false; 326 } 327 328 ++ci; 329 } 330 331 ++ri; 332 } 333 334 // If this turns out to be a zero matrix... 335 if (isZeroMatrix) { 336 // ...free it and return null. 337 delete m; 338 return 0; 339 } 340 341 return m; 342} 343 344PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 345 346 typedef MachineFunction::const_iterator MFIterator; 347 typedef MachineBasicBlock::const_iterator MBBIterator; 348 typedef LiveInterval::const_vni_iterator VNIIterator; 349 350 CoalesceMap coalescesFound; 351 352 // To find coalesces we need to iterate over the function looking for 353 // copy instructions. 354 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 355 bbItr != bbEnd; ++bbItr) { 356 357 const MachineBasicBlock *mbb = &*bbItr; 358 359 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 360 iItr != iEnd; ++iItr) { 361 362 const MachineInstr *instr = &*iItr; 363 unsigned srcReg, dstReg, srcSubReg, dstSubReg; 364 365 // If this isn't a copy then continue to the next instruction. 366 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) 367 continue; 368 369 // If the registers are already the same our job is nice and easy. 370 if (dstReg == srcReg) 371 continue; 372 373 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 374 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 375 376 // If both registers are physical then we can't coalesce. 377 if (srcRegIsPhysical && dstRegIsPhysical) 378 continue; 379 380 // If it's a copy that includes a virtual register but the source and 381 // destination classes differ then we can't coalesce, so continue with 382 // the next instruction. 383 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? 384 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg); 385 386 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? 387 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg); 388 389 if (srcRegClass != dstRegClass) 390 continue; 391 392 // We also need any physical regs to be allocable, coalescing with 393 // a non-allocable register is invalid. 394 if (srcRegIsPhysical) { 395 if (std::find(srcRegClass->allocation_order_begin(*mf), 396 srcRegClass->allocation_order_end(*mf), srcReg) == 397 srcRegClass->allocation_order_end(*mf)) 398 continue; 399 } 400 401 if (dstRegIsPhysical) { 402 if (std::find(dstRegClass->allocation_order_begin(*mf), 403 dstRegClass->allocation_order_end(*mf), dstReg) == 404 dstRegClass->allocation_order_end(*mf)) 405 continue; 406 } 407 408 // If we've made it here we have a copy with compatible register classes. 409 // We can probably coalesce, but we need to consider overlap. 410 const LiveInterval *srcLI = &lis->getInterval(srcReg), 411 *dstLI = &lis->getInterval(dstReg); 412 413 if (srcLI->overlaps(*dstLI)) { 414 // Even in the case of an overlap we might still be able to coalesce, 415 // but we need to make sure that no definition of either range occurs 416 // while the other range is live. 417 418 // Otherwise start by assuming we're ok. 419 bool badDef = false; 420 421 // Test all defs of the source range. 422 for (VNIIterator 423 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 424 vniItr != vniEnd; ++vniItr) { 425 426 // If we find a def that kills the coalescing opportunity then 427 // record it and break from the loop. 428 if (dstLI->liveAt((*vniItr)->def)) { 429 badDef = true; 430 break; 431 } 432 } 433 434 // If we have a bad def give up, continue to the next instruction. 435 if (badDef) 436 continue; 437 438 // Otherwise test definitions of the destination range. 439 for (VNIIterator 440 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 441 vniItr != vniEnd; ++vniItr) { 442 443 // We want to make sure we skip the copy instruction itself. 444 if ((*vniItr)->copy == instr) 445 continue; 446 447 if (srcLI->liveAt((*vniItr)->def)) { 448 badDef = true; 449 break; 450 } 451 } 452 453 // As before a bad def we give up and continue to the next instr. 454 if (badDef) 455 continue; 456 } 457 458 // If we make it to here then either the ranges didn't overlap, or they 459 // did, but none of their definitions would prevent us from coalescing. 460 // We're good to go with the coalesce. 461 462 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0; 463 464 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 465 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 466 } 467 468 } 469 470 return coalescesFound; 471} 472 473void PBQPRegAlloc::findVRegIntervalsToAlloc() { 474 475 // Iterate over all live ranges. 476 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 477 itr != end; ++itr) { 478 479 // Ignore physical ones. 480 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 481 continue; 482 483 LiveInterval *li = itr->second; 484 485 // If this live interval is non-empty we will use pbqp to allocate it. 486 // Empty intervals we allocate in a simple post-processing stage in 487 // finalizeAlloc. 488 if (!li->empty()) { 489 vregIntervalsToAlloc.insert(li); 490 } 491 else { 492 emptyVRegIntervals.insert(li); 493 } 494 } 495} 496 497pbqp* PBQPRegAlloc::constructPBQPProblem() { 498 499 typedef std::vector<const LiveInterval*> LIVector; 500 typedef std::vector<unsigned> RegVector; 501 502 // This will store the physical intervals for easy reference. 503 LIVector physIntervals; 504 505 // Start by clearing the old node <-> live interval mappings & allowed sets 506 li2Node.clear(); 507 node2LI.clear(); 508 allowedSets.clear(); 509 510 // Populate physIntervals, update preg use: 511 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 512 itr != end; ++itr) { 513 514 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 515 physIntervals.push_back(itr->second); 516 mri->setPhysRegUsed(itr->second->reg); 517 } 518 } 519 520 // Iterate over vreg intervals, construct live interval <-> node number 521 // mappings. 522 for (LiveIntervalSet::const_iterator 523 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 524 itr != end; ++itr) { 525 const LiveInterval *li = *itr; 526 527 li2Node[li] = node2LI.size(); 528 node2LI.push_back(li); 529 } 530 531 // Get the set of potential coalesces. 532 CoalesceMap coalesces(findCoalesces()); 533 534 // Construct a PBQP solver for this problem 535 pbqp *solver = alloc_pbqp(vregIntervalsToAlloc.size()); 536 537 // Resize allowedSets container appropriately. 538 allowedSets.resize(vregIntervalsToAlloc.size()); 539 540 // Iterate over virtual register intervals to compute allowed sets... 541 for (unsigned node = 0; node < node2LI.size(); ++node) { 542 543 // Grab pointers to the interval and its register class. 544 const LiveInterval *li = node2LI[node]; 545 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 546 547 // Start by assuming all allocable registers in the class are allowed... 548 RegVector liAllowed(liRC->allocation_order_begin(*mf), 549 liRC->allocation_order_end(*mf)); 550 551 // Eliminate the physical registers which overlap with this range, along 552 // with all their aliases. 553 for (LIVector::iterator pItr = physIntervals.begin(), 554 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 555 556 if (!li->overlaps(**pItr)) 557 continue; 558 559 unsigned pReg = (*pItr)->reg; 560 561 // If we get here then the live intervals overlap, but we're still ok 562 // if they're coalescable. 563 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 564 continue; 565 566 // If we get here then we have a genuine exclusion. 567 568 // Remove the overlapping reg... 569 RegVector::iterator eraseItr = 570 std::find(liAllowed.begin(), liAllowed.end(), pReg); 571 572 if (eraseItr != liAllowed.end()) 573 liAllowed.erase(eraseItr); 574 575 const unsigned *aliasItr = tri->getAliasSet(pReg); 576 577 if (aliasItr != 0) { 578 // ...and its aliases. 579 for (; *aliasItr != 0; ++aliasItr) { 580 RegVector::iterator eraseItr = 581 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 582 583 if (eraseItr != liAllowed.end()) { 584 liAllowed.erase(eraseItr); 585 } 586 } 587 } 588 } 589 590 // Copy the allowed set into a member vector for use when constructing cost 591 // vectors & matrices, and mapping PBQP solutions back to assignments. 592 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 593 594 // Set the spill cost to the interval weight, or epsilon if the 595 // interval weight is zero 596 PBQPNum spillCost = (li->weight != 0.0) ? 597 li->weight : std::numeric_limits<PBQPNum>::min(); 598 599 // Build a cost vector for this interval. 600 add_pbqp_nodecosts(solver, node, 601 buildCostVector(li->reg, allowedSets[node], coalesces, 602 spillCost)); 603 604 } 605 606 607 // Now add the cost matrices... 608 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 609 const LiveInterval *li = node2LI[node1]; 610 611 // Test for live range overlaps and insert interference matrices. 612 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 613 const LiveInterval *li2 = node2LI[node2]; 614 615 CoalesceMap::const_iterator cmItr = 616 coalesces.find(RegPair(li->reg, li2->reg)); 617 618 PBQPMatrix *m = 0; 619 620 if (cmItr != coalesces.end()) { 621 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 622 cmItr->second); 623 } 624 else if (li->overlaps(*li2)) { 625 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 626 } 627 628 if (m != 0) { 629 add_pbqp_edgecosts(solver, node1, node2, m); 630 delete m; 631 } 632 } 633 } 634 635 // We're done, PBQP problem constructed - return it. 636 return solver; 637} 638 639void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight) { 640 int stackSlot = vrm->getStackSlot(spilled->reg); 641 642 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 643 return; 644 645 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot); 646 stackInterval.weight += weight; 647 648 VNInfo *vni; 649 if (stackInterval.getNumValNums() != 0) 650 vni = stackInterval.getValNumInfo(0); 651 else 652 vni = stackInterval.getNextValue(-0U, 0, lss->getVNInfoAllocator()); 653 654 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 655 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 656} 657 658bool PBQPRegAlloc::mapPBQPToRegAlloc(pbqp *problem) { 659 660 // Set to true if we have any spills 661 bool anotherRoundNeeded = false; 662 663 // Clear the existing allocation. 664 vrm->clearAllVirt(); 665 666 // Iterate over the nodes mapping the PBQP solution to a register assignment. 667 for (unsigned node = 0; node < node2LI.size(); ++node) { 668 unsigned virtReg = node2LI[node]->reg, 669 allocSelection = get_pbqp_solution(problem, node); 670 671 // If the PBQP solution is non-zero it's a physical register... 672 if (allocSelection != 0) { 673 // Get the physical reg, subtracting 1 to account for the spill option. 674 unsigned physReg = allowedSets[node][allocSelection - 1]; 675 676 DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n"; 677 678 assert(physReg != 0); 679 680 // Add to the virt reg map and update the used phys regs. 681 vrm->assignVirt2Phys(virtReg, physReg); 682 } 683 // ...Otherwise it's a spill. 684 else { 685 686 // Make sure we ignore this virtual reg on the next round 687 // of allocation 688 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 689 690 float ssWeight; 691 692 // Insert spill ranges for this live range 693 const LiveInterval *spillInterval = node2LI[node]; 694 double oldSpillWeight = spillInterval->weight; 695 SmallVector<LiveInterval*, 8> spillIs; 696 std::vector<LiveInterval*> newSpills = 697 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm, 698 ssWeight); 699 addStackInterval(spillInterval, ssWeight); 700 701 DOUT << "VREG " << virtReg << " -> SPILLED (Cost: " 702 << oldSpillWeight << ", New vregs: "; 703 704 // Copy any newly inserted live intervals into the list of regs to 705 // allocate. 706 for (std::vector<LiveInterval*>::const_iterator 707 itr = newSpills.begin(), end = newSpills.end(); 708 itr != end; ++itr) { 709 710 assert(!(*itr)->empty() && "Empty spill range."); 711 712 DOUT << (*itr)->reg << " "; 713 714 vregIntervalsToAlloc.insert(*itr); 715 } 716 717 DOUT << ")\n"; 718 719 // We need another round if spill intervals were added. 720 anotherRoundNeeded |= !newSpills.empty(); 721 } 722 } 723 724 return !anotherRoundNeeded; 725} 726 727void PBQPRegAlloc::finalizeAlloc() const { 728 typedef LiveIntervals::iterator LIIterator; 729 typedef LiveInterval::Ranges::const_iterator LRIterator; 730 731 // First allocate registers for the empty intervals. 732 for (LiveIntervalSet::const_iterator 733 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 734 itr != end; ++itr) { 735 LiveInterval *li = *itr; 736 737 unsigned physReg = li->preference; 738 739 if (physReg == 0) { 740 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 741 physReg = *liRC->allocation_order_begin(*mf); 742 } 743 744 vrm->assignVirt2Phys(li->reg, physReg); 745 } 746 747 // Finally iterate over the basic blocks to compute and set the live-in sets. 748 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 749 MachineBasicBlock *entryMBB = &*mf->begin(); 750 751 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 752 liItr != liEnd; ++liItr) { 753 754 const LiveInterval *li = liItr->second; 755 unsigned reg = 0; 756 757 // Get the physical register for this interval 758 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 759 reg = li->reg; 760 } 761 else if (vrm->isAssignedReg(li->reg)) { 762 reg = vrm->getPhys(li->reg); 763 } 764 else { 765 // Ranges which are assigned a stack slot only are ignored. 766 continue; 767 } 768 769 // Iterate over the ranges of the current interval... 770 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 771 lrItr != lrEnd; ++lrItr) { 772 773 // Find the set of basic blocks which this range is live into... 774 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 775 // And add the physreg for this interval to their live-in sets. 776 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 777 if (liveInMBBs[i] != entryMBB) { 778 if (!liveInMBBs[i]->isLiveIn(reg)) { 779 liveInMBBs[i]->addLiveIn(reg); 780 } 781 } 782 } 783 liveInMBBs.clear(); 784 } 785 } 786 } 787 788} 789 790bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 791 792 mf = &MF; 793 tm = &mf->getTarget(); 794 tri = tm->getRegisterInfo(); 795 tii = tm->getInstrInfo(); 796 mri = &mf->getRegInfo(); 797 798 lis = &getAnalysis<LiveIntervals>(); 799 lss = &getAnalysis<LiveStacks>(); 800 loopInfo = &getAnalysis<MachineLoopInfo>(); 801 802 std::auto_ptr<VirtRegMap> vrmAutoPtr(new VirtRegMap(*mf)); 803 vrm = vrmAutoPtr.get(); 804 805 DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"; 806 807 // Allocator main loop: 808 // 809 // * Map current regalloc problem to a PBQP problem 810 // * Solve the PBQP problem 811 // * Map the solution back to a register allocation 812 // * Spill if necessary 813 // 814 // This process is continued till no more spills are generated. 815 816 // Find the vreg intervals in need of allocation. 817 findVRegIntervalsToAlloc(); 818 819 // If there aren't any then we're done here. 820 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty()) 821 return true; 822 823 // If there are non-empty intervals allocate them using pbqp. 824 if (!vregIntervalsToAlloc.empty()) { 825 826 bool pbqpAllocComplete = false; 827 unsigned round = 0; 828 829 while (!pbqpAllocComplete) { 830 DOUT << " PBQP Regalloc round " << round << ":\n"; 831 832 pbqp *problem = constructPBQPProblem(); 833 834 solve_pbqp(problem); 835 836 pbqpAllocComplete = mapPBQPToRegAlloc(problem); 837 838 free_pbqp(problem); 839 840 ++round; 841 } 842 } 843 844 // Finalise allocation, allocate empty ranges. 845 finalizeAlloc(); 846 847 vregIntervalsToAlloc.clear(); 848 emptyVRegIntervals.clear(); 849 li2Node.clear(); 850 node2LI.clear(); 851 allowedSets.clear(); 852 853 DOUT << "Post alloc VirtRegMap:\n" << *vrm << "\n"; 854 855 // Run spiller 856 std::auto_ptr<Spiller> spiller(createSpiller()); 857 spiller->runOnMachineFunction(*mf, *vrm); 858 859 return true; 860} 861 862FunctionPass* llvm::createPBQPRegisterAllocator() { 863 return new PBQPRegAlloc(); 864} 865 866 867#undef DEBUG_TYPE 868