RegAllocPBQP.cpp revision 997816499cbf966a1b574b1d34c2c13de4b91b12
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "PBQP/HeuristicSolver.h" 35#include "PBQP/SimpleGraph.h" 36#include "PBQP/Heuristics/Briggs.h" 37#include "VirtRegMap.h" 38#include "VirtRegRewriter.h" 39#include "llvm/CodeGen/CalcSpillWeights.h" 40#include "llvm/CodeGen/LiveIntervalAnalysis.h" 41#include "llvm/CodeGen/LiveStackAnalysis.h" 42#include "llvm/CodeGen/MachineFunctionPass.h" 43#include "llvm/CodeGen/MachineLoopInfo.h" 44#include "llvm/CodeGen/MachineRegisterInfo.h" 45#include "llvm/CodeGen/RegAllocRegistry.h" 46#include "llvm/CodeGen/RegisterCoalescer.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetMachine.h" 51#include <limits> 52#include <map> 53#include <memory> 54#include <set> 55#include <vector> 56 57using namespace llvm; 58 59static RegisterRegAlloc 60registerPBQPRepAlloc("pbqp", "PBQP register allocator.", 61 llvm::createPBQPRegisterAllocator); 62 63static cl::opt<bool> 64pbqpCoalescing("pbqp-coalescing", 65 cl::desc("Attempt coalescing during PBQP register allocation."), 66 cl::init(false), cl::Hidden); 67 68namespace { 69 70 /// 71 /// PBQP based allocators solve the register allocation problem by mapping 72 /// register allocation problems to Partitioned Boolean Quadratic 73 /// Programming problems. 74 class PBQPRegAlloc : public MachineFunctionPass { 75 public: 76 77 static char ID; 78 79 /// Construct a PBQP register allocator. 80 PBQPRegAlloc() : MachineFunctionPass(&ID) {} 81 82 /// Return the pass name. 83 virtual const char* getPassName() const { 84 return "PBQP Register Allocator"; 85 } 86 87 /// PBQP analysis usage. 88 virtual void getAnalysisUsage(AnalysisUsage &au) const { 89 au.addRequired<SlotIndexes>(); 90 au.addPreserved<SlotIndexes>(); 91 au.addRequired<LiveIntervals>(); 92 //au.addRequiredID(SplitCriticalEdgesID); 93 au.addRequired<RegisterCoalescer>(); 94 au.addRequired<CalculateSpillWeights>(); 95 au.addRequired<LiveStacks>(); 96 au.addPreserved<LiveStacks>(); 97 au.addRequired<MachineLoopInfo>(); 98 au.addPreserved<MachineLoopInfo>(); 99 au.addRequired<VirtRegMap>(); 100 MachineFunctionPass::getAnalysisUsage(au); 101 } 102 103 /// Perform register allocation 104 virtual bool runOnMachineFunction(MachineFunction &MF); 105 106 private: 107 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 108 typedef std::vector<const LiveInterval*> Node2LIMap; 109 typedef std::vector<unsigned> AllowedSet; 110 typedef std::vector<AllowedSet> AllowedSetMap; 111 typedef std::set<unsigned> RegSet; 112 typedef std::pair<unsigned, unsigned> RegPair; 113 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap; 114 115 typedef std::set<LiveInterval*> LiveIntervalSet; 116 117 MachineFunction *mf; 118 const TargetMachine *tm; 119 const TargetRegisterInfo *tri; 120 const TargetInstrInfo *tii; 121 const MachineLoopInfo *loopInfo; 122 MachineRegisterInfo *mri; 123 124 LiveIntervals *lis; 125 LiveStacks *lss; 126 VirtRegMap *vrm; 127 128 LI2NodeMap li2Node; 129 Node2LIMap node2LI; 130 AllowedSetMap allowedSets; 131 LiveIntervalSet vregIntervalsToAlloc, 132 emptyVRegIntervals; 133 134 135 /// Builds a PBQP cost vector. 136 template <typename RegContainer> 137 PBQP::Vector buildCostVector(unsigned vReg, 138 const RegContainer &allowed, 139 const CoalesceMap &cealesces, 140 PBQP::PBQPNum spillCost) const; 141 142 /// \brief Builds a PBQP interference matrix. 143 /// 144 /// @return Either a pointer to a non-zero PBQP matrix representing the 145 /// allocation option costs, or a null pointer for a zero matrix. 146 /// 147 /// Expects allowed sets for two interfering LiveIntervals. These allowed 148 /// sets should contain only allocable registers from the LiveInterval's 149 /// register class, with any interfering pre-colored registers removed. 150 template <typename RegContainer> 151 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, 152 const RegContainer &allowed2) const; 153 154 /// 155 /// Expects allowed sets for two potentially coalescable LiveIntervals, 156 /// and an estimated benefit due to coalescing. The allowed sets should 157 /// contain only allocable registers from the LiveInterval's register 158 /// classes, with any interfering pre-colored registers removed. 159 template <typename RegContainer> 160 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, 161 const RegContainer &allowed2, 162 PBQP::PBQPNum cBenefit) const; 163 164 /// \brief Finds coalescing opportunities and returns them as a map. 165 /// 166 /// Any entries in the map are guaranteed coalescable, even if their 167 /// corresponding live intervals overlap. 168 CoalesceMap findCoalesces(); 169 170 /// \brief Finds the initial set of vreg intervals to allocate. 171 void findVRegIntervalsToAlloc(); 172 173 /// \brief Constructs a PBQP problem representation of the register 174 /// allocation problem for this function. 175 /// 176 /// @return a PBQP solver object for the register allocation problem. 177 PBQP::SimpleGraph constructPBQPProblem(); 178 179 /// \brief Adds a stack interval if the given live interval has been 180 /// spilled. Used to support stack slot coloring. 181 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); 182 183 /// \brief Given a solved PBQP problem maps this solution back to a register 184 /// assignment. 185 bool mapPBQPToRegAlloc(const PBQP::Solution &solution); 186 187 /// \brief Postprocessing before final spilling. Sets basic block "live in" 188 /// variables. 189 void finalizeAlloc() const; 190 191 }; 192 193 char PBQPRegAlloc::ID = 0; 194} 195 196 197template <typename RegContainer> 198PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg, 199 const RegContainer &allowed, 200 const CoalesceMap &coalesces, 201 PBQP::PBQPNum spillCost) const { 202 203 typedef typename RegContainer::const_iterator AllowedItr; 204 205 // Allocate vector. Additional element (0th) used for spill option 206 PBQP::Vector v(allowed.size() + 1, 0); 207 208 v[0] = spillCost; 209 210 // Iterate over the allowed registers inserting coalesce benefits if there 211 // are any. 212 unsigned ai = 0; 213 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 214 itr != end; ++itr, ++ai) { 215 216 unsigned pReg = *itr; 217 218 CoalesceMap::const_iterator cmItr = 219 coalesces.find(RegPair(vReg, pReg)); 220 221 // No coalesce - on to the next preg. 222 if (cmItr == coalesces.end()) 223 continue; 224 225 // We have a coalesce - insert the benefit. 226 v[ai + 1] = -cmItr->second; 227 } 228 229 return v; 230} 231 232template <typename RegContainer> 233PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix( 234 const RegContainer &allowed1, const RegContainer &allowed2) const { 235 236 typedef typename RegContainer::const_iterator RegContainerIterator; 237 238 // Construct a PBQP matrix representing the cost of allocation options. The 239 // rows and columns correspond to the allocation options for the two live 240 // intervals. Elements will be infinite where corresponding registers alias, 241 // since we cannot allocate aliasing registers to interfering live intervals. 242 // All other elements (non-aliasing combinations) will have zero cost. Note 243 // that the spill option (element 0,0) has zero cost, since we can allocate 244 // both intervals to memory safely (the cost for each individual allocation 245 // to memory is accounted for by the cost vectors for each live interval). 246 PBQP::Matrix *m = 247 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 248 249 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 250 // between interfering live ranges with non-overlapping register sets (e.g. 251 // non-overlapping reg classes, or disjoint sets of allowed regs within the 252 // same class). The term "overlapping" is used advisedly: sets which do not 253 // intersect, but contain registers which alias, will have non-zero matrices. 254 // We optimize zero matrices away to improve solver speed. 255 bool isZeroMatrix = true; 256 257 258 // Row index. Starts at 1, since the 0th row is for the spill option, which 259 // is always zero. 260 unsigned ri = 1; 261 262 // Iterate over allowed sets, insert infinities where required. 263 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 264 a1Itr != a1End; ++a1Itr) { 265 266 // Column index, starts at 1 as for row index. 267 unsigned ci = 1; 268 unsigned reg1 = *a1Itr; 269 270 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 271 a2Itr != a2End; ++a2Itr) { 272 273 unsigned reg2 = *a2Itr; 274 275 // If the row/column regs are identical or alias insert an infinity. 276 if (tri->regsOverlap(reg1, reg2)) { 277 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity(); 278 isZeroMatrix = false; 279 } 280 281 ++ci; 282 } 283 284 ++ri; 285 } 286 287 // If this turns out to be a zero matrix... 288 if (isZeroMatrix) { 289 // free it and return null. 290 delete m; 291 return 0; 292 } 293 294 // ...otherwise return the cost matrix. 295 return m; 296} 297 298template <typename RegContainer> 299PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix( 300 const RegContainer &allowed1, const RegContainer &allowed2, 301 PBQP::PBQPNum cBenefit) const { 302 303 typedef typename RegContainer::const_iterator RegContainerIterator; 304 305 // Construct a PBQP Matrix representing the benefits of coalescing. As with 306 // interference matrices the rows and columns represent allowed registers 307 // for the LiveIntervals which are (potentially) to be coalesced. The amount 308 // -cBenefit will be placed in any element representing the same register 309 // for both intervals. 310 PBQP::Matrix *m = 311 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 312 313 // Reset costs to zero. 314 m->reset(0); 315 316 // Assume the matrix is zero till proven otherwise. Zero matrices will be 317 // optimized away as in the interference case. 318 bool isZeroMatrix = true; 319 320 // Row index. Starts at 1, since the 0th row is for the spill option, which 321 // is always zero. 322 unsigned ri = 1; 323 324 // Iterate over the allowed sets, insert coalescing benefits where 325 // appropriate. 326 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 327 a1Itr != a1End; ++a1Itr) { 328 329 // Column index, starts at 1 as for row index. 330 unsigned ci = 1; 331 unsigned reg1 = *a1Itr; 332 333 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 334 a2Itr != a2End; ++a2Itr) { 335 336 // If the row and column represent the same register insert a beneficial 337 // cost to preference this allocation - it would allow us to eliminate a 338 // move instruction. 339 if (reg1 == *a2Itr) { 340 (*m)[ri][ci] = -cBenefit; 341 isZeroMatrix = false; 342 } 343 344 ++ci; 345 } 346 347 ++ri; 348 } 349 350 // If this turns out to be a zero matrix... 351 if (isZeroMatrix) { 352 // ...free it and return null. 353 delete m; 354 return 0; 355 } 356 357 return m; 358} 359 360PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 361 362 typedef MachineFunction::const_iterator MFIterator; 363 typedef MachineBasicBlock::const_iterator MBBIterator; 364 typedef LiveInterval::const_vni_iterator VNIIterator; 365 366 CoalesceMap coalescesFound; 367 368 // To find coalesces we need to iterate over the function looking for 369 // copy instructions. 370 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 371 bbItr != bbEnd; ++bbItr) { 372 373 const MachineBasicBlock *mbb = &*bbItr; 374 375 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 376 iItr != iEnd; ++iItr) { 377 378 const MachineInstr *instr = &*iItr; 379 unsigned srcReg, dstReg, srcSubReg, dstSubReg; 380 381 // If this isn't a copy then continue to the next instruction. 382 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) 383 continue; 384 385 // If the registers are already the same our job is nice and easy. 386 if (dstReg == srcReg) 387 continue; 388 389 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 390 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 391 392 // If both registers are physical then we can't coalesce. 393 if (srcRegIsPhysical && dstRegIsPhysical) 394 continue; 395 396 // If it's a copy that includes a virtual register but the source and 397 // destination classes differ then we can't coalesce, so continue with 398 // the next instruction. 399 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? 400 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg); 401 402 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? 403 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg); 404 405 if (srcRegClass != dstRegClass) 406 continue; 407 408 // We also need any physical regs to be allocable, coalescing with 409 // a non-allocable register is invalid. 410 if (srcRegIsPhysical) { 411 if (std::find(srcRegClass->allocation_order_begin(*mf), 412 srcRegClass->allocation_order_end(*mf), srcReg) == 413 srcRegClass->allocation_order_end(*mf)) 414 continue; 415 } 416 417 if (dstRegIsPhysical) { 418 if (std::find(dstRegClass->allocation_order_begin(*mf), 419 dstRegClass->allocation_order_end(*mf), dstReg) == 420 dstRegClass->allocation_order_end(*mf)) 421 continue; 422 } 423 424 // If we've made it here we have a copy with compatible register classes. 425 // We can probably coalesce, but we need to consider overlap. 426 const LiveInterval *srcLI = &lis->getInterval(srcReg), 427 *dstLI = &lis->getInterval(dstReg); 428 429 if (srcLI->overlaps(*dstLI)) { 430 // Even in the case of an overlap we might still be able to coalesce, 431 // but we need to make sure that no definition of either range occurs 432 // while the other range is live. 433 434 // Otherwise start by assuming we're ok. 435 bool badDef = false; 436 437 // Test all defs of the source range. 438 for (VNIIterator 439 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 440 vniItr != vniEnd; ++vniItr) { 441 442 // If we find a def that kills the coalescing opportunity then 443 // record it and break from the loop. 444 if (dstLI->liveAt((*vniItr)->def)) { 445 badDef = true; 446 break; 447 } 448 } 449 450 // If we have a bad def give up, continue to the next instruction. 451 if (badDef) 452 continue; 453 454 // Otherwise test definitions of the destination range. 455 for (VNIIterator 456 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 457 vniItr != vniEnd; ++vniItr) { 458 459 // We want to make sure we skip the copy instruction itself. 460 if ((*vniItr)->getCopy() == instr) 461 continue; 462 463 if (srcLI->liveAt((*vniItr)->def)) { 464 badDef = true; 465 break; 466 } 467 } 468 469 // As before a bad def we give up and continue to the next instr. 470 if (badDef) 471 continue; 472 } 473 474 // If we make it to here then either the ranges didn't overlap, or they 475 // did, but none of their definitions would prevent us from coalescing. 476 // We're good to go with the coalesce. 477 478 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0; 479 480 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 481 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 482 } 483 484 } 485 486 return coalescesFound; 487} 488 489void PBQPRegAlloc::findVRegIntervalsToAlloc() { 490 491 // Iterate over all live ranges. 492 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 493 itr != end; ++itr) { 494 495 // Ignore physical ones. 496 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 497 continue; 498 499 LiveInterval *li = itr->second; 500 501 // If this live interval is non-empty we will use pbqp to allocate it. 502 // Empty intervals we allocate in a simple post-processing stage in 503 // finalizeAlloc. 504 if (!li->empty()) { 505 vregIntervalsToAlloc.insert(li); 506 } 507 else { 508 emptyVRegIntervals.insert(li); 509 } 510 } 511} 512 513PBQP::SimpleGraph PBQPRegAlloc::constructPBQPProblem() { 514 515 typedef std::vector<const LiveInterval*> LIVector; 516 typedef std::vector<unsigned> RegVector; 517 typedef std::vector<PBQP::SimpleGraph::NodeIterator> NodeVector; 518 519 // This will store the physical intervals for easy reference. 520 LIVector physIntervals; 521 522 // Start by clearing the old node <-> live interval mappings & allowed sets 523 li2Node.clear(); 524 node2LI.clear(); 525 allowedSets.clear(); 526 527 // Populate physIntervals, update preg use: 528 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 529 itr != end; ++itr) { 530 531 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 532 physIntervals.push_back(itr->second); 533 mri->setPhysRegUsed(itr->second->reg); 534 } 535 } 536 537 // Iterate over vreg intervals, construct live interval <-> node number 538 // mappings. 539 for (LiveIntervalSet::const_iterator 540 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 541 itr != end; ++itr) { 542 const LiveInterval *li = *itr; 543 544 li2Node[li] = node2LI.size(); 545 node2LI.push_back(li); 546 } 547 548 // Get the set of potential coalesces. 549 CoalesceMap coalesces; 550 551 if (pbqpCoalescing) { 552 coalesces = findCoalesces(); 553 } 554 555 // Construct a PBQP solver for this problem 556 PBQP::SimpleGraph problem; 557 NodeVector problemNodes(vregIntervalsToAlloc.size()); 558 559 // Resize allowedSets container appropriately. 560 allowedSets.resize(vregIntervalsToAlloc.size()); 561 562 // Iterate over virtual register intervals to compute allowed sets... 563 for (unsigned node = 0; node < node2LI.size(); ++node) { 564 565 // Grab pointers to the interval and its register class. 566 const LiveInterval *li = node2LI[node]; 567 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 568 569 // Start by assuming all allocable registers in the class are allowed... 570 RegVector liAllowed(liRC->allocation_order_begin(*mf), 571 liRC->allocation_order_end(*mf)); 572 573 // Eliminate the physical registers which overlap with this range, along 574 // with all their aliases. 575 for (LIVector::iterator pItr = physIntervals.begin(), 576 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 577 578 if (!li->overlaps(**pItr)) 579 continue; 580 581 unsigned pReg = (*pItr)->reg; 582 583 // If we get here then the live intervals overlap, but we're still ok 584 // if they're coalescable. 585 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 586 continue; 587 588 // If we get here then we have a genuine exclusion. 589 590 // Remove the overlapping reg... 591 RegVector::iterator eraseItr = 592 std::find(liAllowed.begin(), liAllowed.end(), pReg); 593 594 if (eraseItr != liAllowed.end()) 595 liAllowed.erase(eraseItr); 596 597 const unsigned *aliasItr = tri->getAliasSet(pReg); 598 599 if (aliasItr != 0) { 600 // ...and its aliases. 601 for (; *aliasItr != 0; ++aliasItr) { 602 RegVector::iterator eraseItr = 603 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 604 605 if (eraseItr != liAllowed.end()) { 606 liAllowed.erase(eraseItr); 607 } 608 } 609 } 610 } 611 612 // Copy the allowed set into a member vector for use when constructing cost 613 // vectors & matrices, and mapping PBQP solutions back to assignments. 614 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 615 616 // Set the spill cost to the interval weight, or epsilon if the 617 // interval weight is zero 618 PBQP::PBQPNum spillCost = (li->weight != 0.0) ? 619 li->weight : std::numeric_limits<PBQP::PBQPNum>::min(); 620 621 // Build a cost vector for this interval. 622 problemNodes[node] = 623 problem.addNode( 624 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost)); 625 626 } 627 628 629 // Now add the cost matrices... 630 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 631 const LiveInterval *li = node2LI[node1]; 632 633 // Test for live range overlaps and insert interference matrices. 634 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 635 const LiveInterval *li2 = node2LI[node2]; 636 637 CoalesceMap::const_iterator cmItr = 638 coalesces.find(RegPair(li->reg, li2->reg)); 639 640 PBQP::Matrix *m = 0; 641 642 if (cmItr != coalesces.end()) { 643 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 644 cmItr->second); 645 } 646 else if (li->overlaps(*li2)) { 647 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 648 } 649 650 if (m != 0) { 651 problem.addEdge(problemNodes[node1], 652 problemNodes[node2], 653 *m); 654 655 delete m; 656 } 657 } 658 } 659 660 problem.assignNodeIDs(); 661 662 assert(problem.getNumNodes() == allowedSets.size()); 663 for (unsigned i = 0; i < allowedSets.size(); ++i) { 664 assert(problem.getNodeItr(i) == problemNodes[i]); 665 } 666/* 667 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, " 668 << problem.getNumEdges() << " edges.\n"; 669 670 problem.printDot(std::cerr); 671*/ 672 // We're done, PBQP problem constructed - return it. 673 return problem; 674} 675 676void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, 677 MachineRegisterInfo* mri) { 678 int stackSlot = vrm->getStackSlot(spilled->reg); 679 680 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 681 return; 682 683 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); 684 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC); 685 686 VNInfo *vni; 687 if (stackInterval.getNumValNums() != 0) 688 vni = stackInterval.getValNumInfo(0); 689 else 690 vni = stackInterval.getNextValue( 691 SlotIndex(), 0, false, lss->getVNInfoAllocator()); 692 693 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 694 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 695} 696 697bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { 698 699 // Assert that this is a valid solution to the regalloc problem. 700 assert(solution.getCost() != std::numeric_limits<PBQP::PBQPNum>::infinity() && 701 "Invalid (infinite cost) solution for PBQP problem."); 702 703 // Set to true if we have any spills 704 bool anotherRoundNeeded = false; 705 706 // Clear the existing allocation. 707 vrm->clearAllVirt(); 708 709 // Iterate over the nodes mapping the PBQP solution to a register assignment. 710 for (unsigned node = 0; node < node2LI.size(); ++node) { 711 unsigned virtReg = node2LI[node]->reg, 712 allocSelection = solution.getSelection(node); 713 714 715 // If the PBQP solution is non-zero it's a physical register... 716 if (allocSelection != 0) { 717 // Get the physical reg, subtracting 1 to account for the spill option. 718 unsigned physReg = allowedSets[node][allocSelection - 1]; 719 720 DEBUG(dbgs() << "VREG " << virtReg << " -> " 721 << tri->getName(physReg) << "\n"); 722 723 assert(physReg != 0); 724 725 // Add to the virt reg map and update the used phys regs. 726 vrm->assignVirt2Phys(virtReg, physReg); 727 } 728 // ...Otherwise it's a spill. 729 else { 730 731 // Make sure we ignore this virtual reg on the next round 732 // of allocation 733 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 734 735 // Insert spill ranges for this live range 736 const LiveInterval *spillInterval = node2LI[node]; 737 double oldSpillWeight = spillInterval->weight; 738 SmallVector<LiveInterval*, 8> spillIs; 739 std::vector<LiveInterval*> newSpills = 740 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); 741 addStackInterval(spillInterval, mri); 742 743 (void) oldSpillWeight; 744 DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: " 745 << oldSpillWeight << ", New vregs: "); 746 747 // Copy any newly inserted live intervals into the list of regs to 748 // allocate. 749 for (std::vector<LiveInterval*>::const_iterator 750 itr = newSpills.begin(), end = newSpills.end(); 751 itr != end; ++itr) { 752 753 assert(!(*itr)->empty() && "Empty spill range."); 754 755 DEBUG(dbgs() << (*itr)->reg << " "); 756 757 vregIntervalsToAlloc.insert(*itr); 758 } 759 760 DEBUG(dbgs() << ")\n"); 761 762 // We need another round if spill intervals were added. 763 anotherRoundNeeded |= !newSpills.empty(); 764 } 765 } 766 767 return !anotherRoundNeeded; 768} 769 770void PBQPRegAlloc::finalizeAlloc() const { 771 typedef LiveIntervals::iterator LIIterator; 772 typedef LiveInterval::Ranges::const_iterator LRIterator; 773 774 // First allocate registers for the empty intervals. 775 for (LiveIntervalSet::const_iterator 776 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 777 itr != end; ++itr) { 778 LiveInterval *li = *itr; 779 780 unsigned physReg = vrm->getRegAllocPref(li->reg); 781 782 if (physReg == 0) { 783 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 784 physReg = *liRC->allocation_order_begin(*mf); 785 } 786 787 vrm->assignVirt2Phys(li->reg, physReg); 788 } 789 790 // Finally iterate over the basic blocks to compute and set the live-in sets. 791 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 792 MachineBasicBlock *entryMBB = &*mf->begin(); 793 794 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 795 liItr != liEnd; ++liItr) { 796 797 const LiveInterval *li = liItr->second; 798 unsigned reg = 0; 799 800 // Get the physical register for this interval 801 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 802 reg = li->reg; 803 } 804 else if (vrm->isAssignedReg(li->reg)) { 805 reg = vrm->getPhys(li->reg); 806 } 807 else { 808 // Ranges which are assigned a stack slot only are ignored. 809 continue; 810 } 811 812 if (reg == 0) { 813 // Filter out zero regs - they're for intervals that were spilled. 814 continue; 815 } 816 817 // Iterate over the ranges of the current interval... 818 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 819 lrItr != lrEnd; ++lrItr) { 820 821 // Find the set of basic blocks which this range is live into... 822 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 823 // And add the physreg for this interval to their live-in sets. 824 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 825 if (liveInMBBs[i] != entryMBB) { 826 if (!liveInMBBs[i]->isLiveIn(reg)) { 827 liveInMBBs[i]->addLiveIn(reg); 828 } 829 } 830 } 831 liveInMBBs.clear(); 832 } 833 } 834 } 835 836} 837 838bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 839 840 mf = &MF; 841 tm = &mf->getTarget(); 842 tri = tm->getRegisterInfo(); 843 tii = tm->getInstrInfo(); 844 mri = &mf->getRegInfo(); 845 846 lis = &getAnalysis<LiveIntervals>(); 847 lss = &getAnalysis<LiveStacks>(); 848 loopInfo = &getAnalysis<MachineLoopInfo>(); 849 850 vrm = &getAnalysis<VirtRegMap>(); 851 852 DEBUG(dbgs() << "PBQP2 Register Allocating for " << mf->getFunction()->getName() << "\n"); 853 854 // Allocator main loop: 855 // 856 // * Map current regalloc problem to a PBQP problem 857 // * Solve the PBQP problem 858 // * Map the solution back to a register allocation 859 // * Spill if necessary 860 // 861 // This process is continued till no more spills are generated. 862 863 // Find the vreg intervals in need of allocation. 864 findVRegIntervalsToAlloc(); 865 866 // If there aren't any then we're done here. 867 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty()) 868 return true; 869 870 // If there are non-empty intervals allocate them using pbqp. 871 if (!vregIntervalsToAlloc.empty()) { 872 873 bool pbqpAllocComplete = false; 874 unsigned round = 0; 875 876 while (!pbqpAllocComplete) { 877 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); 878 879 PBQP::SimpleGraph problem = constructPBQPProblem(); 880 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs> solver; 881 problem.assignNodeIDs(); 882 PBQP::Solution solution = solver.solve(problem); 883 884 pbqpAllocComplete = mapPBQPToRegAlloc(solution); 885 886 ++round; 887 } 888 } 889 890 // Finalise allocation, allocate empty ranges. 891 finalizeAlloc(); 892 893 vregIntervalsToAlloc.clear(); 894 emptyVRegIntervals.clear(); 895 li2Node.clear(); 896 node2LI.clear(); 897 allowedSets.clear(); 898 899 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n"); 900 901 // Run rewriter 902 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); 903 904 rewriter->runOnMachineFunction(*mf, *vrm, lis); 905 906 return true; 907} 908 909FunctionPass* llvm::createPBQPRegisterAllocator() { 910 return new PBQPRegAlloc(); 911} 912 913 914#undef DEBUG_TYPE 915