RegAllocPBQP.cpp revision cbeb3db8fd502a21f07592f75712d59691ce471f
1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based 11// register allocator for LLVM. This allocator works by constructing a PBQP 12// problem representing the register allocation problem under consideration, 13// solving this using a PBQP solver, and mapping the solution back to a 14// register assignment. If any variables are selected for spilling then spill 15// code is inserted and the process repeated. 16// 17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned 18// for register allocation. For more information on PBQP for register 19// allocation, see the following papers: 20// 21// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with 22// PBQP. In Proceedings of the 7th Joint Modular Languages Conference 23// (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. 24// 25// (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular 26// architectures. In Proceedings of the Joint Conference on Languages, 27// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York, 28// NY, USA, 139-148. 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "regalloc" 33 34#include "PBQP/HeuristicSolver.h" 35#include "PBQP/Graph.h" 36#include "PBQP/Heuristics/Briggs.h" 37#include "VirtRegMap.h" 38#include "VirtRegRewriter.h" 39#include "llvm/CodeGen/CalcSpillWeights.h" 40#include "llvm/CodeGen/LiveIntervalAnalysis.h" 41#include "llvm/CodeGen/LiveStackAnalysis.h" 42#include "llvm/CodeGen/MachineFunctionPass.h" 43#include "llvm/CodeGen/MachineLoopInfo.h" 44#include "llvm/CodeGen/MachineRegisterInfo.h" 45#include "llvm/CodeGen/RegAllocRegistry.h" 46#include "llvm/CodeGen/RegisterCoalescer.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetMachine.h" 51#include <limits> 52#include <map> 53#include <memory> 54#include <set> 55#include <vector> 56 57using namespace llvm; 58 59static RegisterRegAlloc 60registerPBQPRepAlloc("pbqp", "PBQP register allocator", 61 llvm::createPBQPRegisterAllocator); 62 63static cl::opt<bool> 64pbqpCoalescing("pbqp-coalescing", 65 cl::desc("Attempt coalescing during PBQP register allocation."), 66 cl::init(false), cl::Hidden); 67 68namespace { 69 70 /// 71 /// PBQP based allocators solve the register allocation problem by mapping 72 /// register allocation problems to Partitioned Boolean Quadratic 73 /// Programming problems. 74 class PBQPRegAlloc : public MachineFunctionPass { 75 public: 76 77 static char ID; 78 79 /// Construct a PBQP register allocator. 80 PBQPRegAlloc() : MachineFunctionPass(&ID) {} 81 82 /// Return the pass name. 83 virtual const char* getPassName() const { 84 return "PBQP Register Allocator"; 85 } 86 87 /// PBQP analysis usage. 88 virtual void getAnalysisUsage(AnalysisUsage &au) const { 89 au.addRequired<SlotIndexes>(); 90 au.addPreserved<SlotIndexes>(); 91 au.addRequired<LiveIntervals>(); 92 //au.addRequiredID(SplitCriticalEdgesID); 93 au.addRequired<RegisterCoalescer>(); 94 au.addRequired<CalculateSpillWeights>(); 95 au.addRequired<LiveStacks>(); 96 au.addPreserved<LiveStacks>(); 97 au.addRequired<MachineLoopInfo>(); 98 au.addPreserved<MachineLoopInfo>(); 99 au.addRequired<VirtRegMap>(); 100 MachineFunctionPass::getAnalysisUsage(au); 101 } 102 103 /// Perform register allocation 104 virtual bool runOnMachineFunction(MachineFunction &MF); 105 106 private: 107 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap; 108 typedef std::vector<const LiveInterval*> Node2LIMap; 109 typedef std::vector<unsigned> AllowedSet; 110 typedef std::vector<AllowedSet> AllowedSetMap; 111 typedef std::set<unsigned> RegSet; 112 typedef std::pair<unsigned, unsigned> RegPair; 113 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap; 114 115 typedef std::set<LiveInterval*> LiveIntervalSet; 116 117 typedef std::vector<PBQP::Graph::NodeItr> NodeVector; 118 119 MachineFunction *mf; 120 const TargetMachine *tm; 121 const TargetRegisterInfo *tri; 122 const TargetInstrInfo *tii; 123 const MachineLoopInfo *loopInfo; 124 MachineRegisterInfo *mri; 125 126 LiveIntervals *lis; 127 LiveStacks *lss; 128 VirtRegMap *vrm; 129 130 LI2NodeMap li2Node; 131 Node2LIMap node2LI; 132 AllowedSetMap allowedSets; 133 LiveIntervalSet vregIntervalsToAlloc, 134 emptyVRegIntervals; 135 NodeVector problemNodes; 136 137 138 /// Builds a PBQP cost vector. 139 template <typename RegContainer> 140 PBQP::Vector buildCostVector(unsigned vReg, 141 const RegContainer &allowed, 142 const CoalesceMap &cealesces, 143 PBQP::PBQPNum spillCost) const; 144 145 /// \brief Builds a PBQP interference matrix. 146 /// 147 /// @return Either a pointer to a non-zero PBQP matrix representing the 148 /// allocation option costs, or a null pointer for a zero matrix. 149 /// 150 /// Expects allowed sets for two interfering LiveIntervals. These allowed 151 /// sets should contain only allocable registers from the LiveInterval's 152 /// register class, with any interfering pre-colored registers removed. 153 template <typename RegContainer> 154 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1, 155 const RegContainer &allowed2) const; 156 157 /// 158 /// Expects allowed sets for two potentially coalescable LiveIntervals, 159 /// and an estimated benefit due to coalescing. The allowed sets should 160 /// contain only allocable registers from the LiveInterval's register 161 /// classes, with any interfering pre-colored registers removed. 162 template <typename RegContainer> 163 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1, 164 const RegContainer &allowed2, 165 PBQP::PBQPNum cBenefit) const; 166 167 /// \brief Finds coalescing opportunities and returns them as a map. 168 /// 169 /// Any entries in the map are guaranteed coalescable, even if their 170 /// corresponding live intervals overlap. 171 CoalesceMap findCoalesces(); 172 173 /// \brief Finds the initial set of vreg intervals to allocate. 174 void findVRegIntervalsToAlloc(); 175 176 /// \brief Constructs a PBQP problem representation of the register 177 /// allocation problem for this function. 178 /// 179 /// @return a PBQP solver object for the register allocation problem. 180 PBQP::Graph constructPBQPProblem(); 181 182 /// \brief Adds a stack interval if the given live interval has been 183 /// spilled. Used to support stack slot coloring. 184 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri); 185 186 /// \brief Given a solved PBQP problem maps this solution back to a register 187 /// assignment. 188 bool mapPBQPToRegAlloc(const PBQP::Solution &solution); 189 190 /// \brief Postprocessing before final spilling. Sets basic block "live in" 191 /// variables. 192 void finalizeAlloc() const; 193 194 }; 195 196 char PBQPRegAlloc::ID = 0; 197} 198 199 200template <typename RegContainer> 201PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg, 202 const RegContainer &allowed, 203 const CoalesceMap &coalesces, 204 PBQP::PBQPNum spillCost) const { 205 206 typedef typename RegContainer::const_iterator AllowedItr; 207 208 // Allocate vector. Additional element (0th) used for spill option 209 PBQP::Vector v(allowed.size() + 1, 0); 210 211 v[0] = spillCost; 212 213 // Iterate over the allowed registers inserting coalesce benefits if there 214 // are any. 215 unsigned ai = 0; 216 for (AllowedItr itr = allowed.begin(), end = allowed.end(); 217 itr != end; ++itr, ++ai) { 218 219 unsigned pReg = *itr; 220 221 CoalesceMap::const_iterator cmItr = 222 coalesces.find(RegPair(vReg, pReg)); 223 224 // No coalesce - on to the next preg. 225 if (cmItr == coalesces.end()) 226 continue; 227 228 // We have a coalesce - insert the benefit. 229 v[ai + 1] = -cmItr->second; 230 } 231 232 return v; 233} 234 235template <typename RegContainer> 236PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix( 237 const RegContainer &allowed1, const RegContainer &allowed2) const { 238 239 typedef typename RegContainer::const_iterator RegContainerIterator; 240 241 // Construct a PBQP matrix representing the cost of allocation options. The 242 // rows and columns correspond to the allocation options for the two live 243 // intervals. Elements will be infinite where corresponding registers alias, 244 // since we cannot allocate aliasing registers to interfering live intervals. 245 // All other elements (non-aliasing combinations) will have zero cost. Note 246 // that the spill option (element 0,0) has zero cost, since we can allocate 247 // both intervals to memory safely (the cost for each individual allocation 248 // to memory is accounted for by the cost vectors for each live interval). 249 PBQP::Matrix *m = 250 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 251 252 // Assume this is a zero matrix until proven otherwise. Zero matrices occur 253 // between interfering live ranges with non-overlapping register sets (e.g. 254 // non-overlapping reg classes, or disjoint sets of allowed regs within the 255 // same class). The term "overlapping" is used advisedly: sets which do not 256 // intersect, but contain registers which alias, will have non-zero matrices. 257 // We optimize zero matrices away to improve solver speed. 258 bool isZeroMatrix = true; 259 260 261 // Row index. Starts at 1, since the 0th row is for the spill option, which 262 // is always zero. 263 unsigned ri = 1; 264 265 // Iterate over allowed sets, insert infinities where required. 266 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 267 a1Itr != a1End; ++a1Itr) { 268 269 // Column index, starts at 1 as for row index. 270 unsigned ci = 1; 271 unsigned reg1 = *a1Itr; 272 273 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 274 a2Itr != a2End; ++a2Itr) { 275 276 unsigned reg2 = *a2Itr; 277 278 // If the row/column regs are identical or alias insert an infinity. 279 if (tri->regsOverlap(reg1, reg2)) { 280 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity(); 281 isZeroMatrix = false; 282 } 283 284 ++ci; 285 } 286 287 ++ri; 288 } 289 290 // If this turns out to be a zero matrix... 291 if (isZeroMatrix) { 292 // free it and return null. 293 delete m; 294 return 0; 295 } 296 297 // ...otherwise return the cost matrix. 298 return m; 299} 300 301template <typename RegContainer> 302PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix( 303 const RegContainer &allowed1, const RegContainer &allowed2, 304 PBQP::PBQPNum cBenefit) const { 305 306 typedef typename RegContainer::const_iterator RegContainerIterator; 307 308 // Construct a PBQP Matrix representing the benefits of coalescing. As with 309 // interference matrices the rows and columns represent allowed registers 310 // for the LiveIntervals which are (potentially) to be coalesced. The amount 311 // -cBenefit will be placed in any element representing the same register 312 // for both intervals. 313 PBQP::Matrix *m = 314 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0); 315 316 // Reset costs to zero. 317 m->reset(0); 318 319 // Assume the matrix is zero till proven otherwise. Zero matrices will be 320 // optimized away as in the interference case. 321 bool isZeroMatrix = true; 322 323 // Row index. Starts at 1, since the 0th row is for the spill option, which 324 // is always zero. 325 unsigned ri = 1; 326 327 // Iterate over the allowed sets, insert coalescing benefits where 328 // appropriate. 329 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end(); 330 a1Itr != a1End; ++a1Itr) { 331 332 // Column index, starts at 1 as for row index. 333 unsigned ci = 1; 334 unsigned reg1 = *a1Itr; 335 336 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end(); 337 a2Itr != a2End; ++a2Itr) { 338 339 // If the row and column represent the same register insert a beneficial 340 // cost to preference this allocation - it would allow us to eliminate a 341 // move instruction. 342 if (reg1 == *a2Itr) { 343 (*m)[ri][ci] = -cBenefit; 344 isZeroMatrix = false; 345 } 346 347 ++ci; 348 } 349 350 ++ri; 351 } 352 353 // If this turns out to be a zero matrix... 354 if (isZeroMatrix) { 355 // ...free it and return null. 356 delete m; 357 return 0; 358 } 359 360 return m; 361} 362 363PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() { 364 365 typedef MachineFunction::const_iterator MFIterator; 366 typedef MachineBasicBlock::const_iterator MBBIterator; 367 typedef LiveInterval::const_vni_iterator VNIIterator; 368 369 CoalesceMap coalescesFound; 370 371 // To find coalesces we need to iterate over the function looking for 372 // copy instructions. 373 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end(); 374 bbItr != bbEnd; ++bbItr) { 375 376 const MachineBasicBlock *mbb = &*bbItr; 377 378 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end(); 379 iItr != iEnd; ++iItr) { 380 381 const MachineInstr *instr = &*iItr; 382 unsigned srcReg, dstReg, srcSubReg, dstSubReg; 383 384 // If this isn't a copy then continue to the next instruction. 385 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg)) 386 continue; 387 388 // If the registers are already the same our job is nice and easy. 389 if (dstReg == srcReg) 390 continue; 391 392 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg), 393 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg); 394 395 // If both registers are physical then we can't coalesce. 396 if (srcRegIsPhysical && dstRegIsPhysical) 397 continue; 398 399 // If it's a copy that includes two virtual register but the source and 400 // destination classes differ then we can't coalesce. 401 if (!srcRegIsPhysical && !dstRegIsPhysical && 402 mri->getRegClass(srcReg) != mri->getRegClass(dstReg)) 403 continue; 404 405 // If one is physical and one is virtual, check that the physical is 406 // allocatable in the class of the virtual. 407 if (srcRegIsPhysical && !dstRegIsPhysical) { 408 const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg); 409 if (std::find(dstRegClass->allocation_order_begin(*mf), 410 dstRegClass->allocation_order_end(*mf), srcReg) == 411 dstRegClass->allocation_order_end(*mf)) 412 continue; 413 } 414 if (!srcRegIsPhysical && dstRegIsPhysical) { 415 const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg); 416 if (std::find(srcRegClass->allocation_order_begin(*mf), 417 srcRegClass->allocation_order_end(*mf), dstReg) == 418 srcRegClass->allocation_order_end(*mf)) 419 continue; 420 } 421 422 // If we've made it here we have a copy with compatible register classes. 423 // We can probably coalesce, but we need to consider overlap. 424 const LiveInterval *srcLI = &lis->getInterval(srcReg), 425 *dstLI = &lis->getInterval(dstReg); 426 427 if (srcLI->overlaps(*dstLI)) { 428 // Even in the case of an overlap we might still be able to coalesce, 429 // but we need to make sure that no definition of either range occurs 430 // while the other range is live. 431 432 // Otherwise start by assuming we're ok. 433 bool badDef = false; 434 435 // Test all defs of the source range. 436 for (VNIIterator 437 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end(); 438 vniItr != vniEnd; ++vniItr) { 439 440 // If we find a poorly defined def we err on the side of caution. 441 if (!(*vniItr)->def.isValid()) { 442 badDef = true; 443 break; 444 } 445 446 // If we find a def that kills the coalescing opportunity then 447 // record it and break from the loop. 448 if (dstLI->liveAt((*vniItr)->def)) { 449 badDef = true; 450 break; 451 } 452 } 453 454 // If we have a bad def give up, continue to the next instruction. 455 if (badDef) 456 continue; 457 458 // Otherwise test definitions of the destination range. 459 for (VNIIterator 460 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end(); 461 vniItr != vniEnd; ++vniItr) { 462 463 // We want to make sure we skip the copy instruction itself. 464 if ((*vniItr)->getCopy() == instr) 465 continue; 466 467 if (!(*vniItr)->def.isValid()) { 468 badDef = true; 469 break; 470 } 471 472 if (srcLI->liveAt((*vniItr)->def)) { 473 badDef = true; 474 break; 475 } 476 } 477 478 // As before a bad def we give up and continue to the next instr. 479 if (badDef) 480 continue; 481 } 482 483 // If we make it to here then either the ranges didn't overlap, or they 484 // did, but none of their definitions would prevent us from coalescing. 485 // We're good to go with the coalesce. 486 487 float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0; 488 489 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit; 490 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit; 491 } 492 493 } 494 495 return coalescesFound; 496} 497 498void PBQPRegAlloc::findVRegIntervalsToAlloc() { 499 500 // Iterate over all live ranges. 501 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 502 itr != end; ++itr) { 503 504 // Ignore physical ones. 505 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) 506 continue; 507 508 LiveInterval *li = itr->second; 509 510 // If this live interval is non-empty we will use pbqp to allocate it. 511 // Empty intervals we allocate in a simple post-processing stage in 512 // finalizeAlloc. 513 if (!li->empty()) { 514 vregIntervalsToAlloc.insert(li); 515 } 516 else { 517 emptyVRegIntervals.insert(li); 518 } 519 } 520} 521 522PBQP::Graph PBQPRegAlloc::constructPBQPProblem() { 523 524 typedef std::vector<const LiveInterval*> LIVector; 525 typedef std::vector<unsigned> RegVector; 526 527 // This will store the physical intervals for easy reference. 528 LIVector physIntervals; 529 530 // Start by clearing the old node <-> live interval mappings & allowed sets 531 li2Node.clear(); 532 node2LI.clear(); 533 allowedSets.clear(); 534 535 // Populate physIntervals, update preg use: 536 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end(); 537 itr != end; ++itr) { 538 539 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) { 540 physIntervals.push_back(itr->second); 541 mri->setPhysRegUsed(itr->second->reg); 542 } 543 } 544 545 // Iterate over vreg intervals, construct live interval <-> node number 546 // mappings. 547 for (LiveIntervalSet::const_iterator 548 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end(); 549 itr != end; ++itr) { 550 const LiveInterval *li = *itr; 551 552 li2Node[li] = node2LI.size(); 553 node2LI.push_back(li); 554 } 555 556 // Get the set of potential coalesces. 557 CoalesceMap coalesces; 558 559 if (pbqpCoalescing) { 560 coalesces = findCoalesces(); 561 } 562 563 // Construct a PBQP solver for this problem 564 PBQP::Graph problem; 565 problemNodes.resize(vregIntervalsToAlloc.size()); 566 567 // Resize allowedSets container appropriately. 568 allowedSets.resize(vregIntervalsToAlloc.size()); 569 570 // Iterate over virtual register intervals to compute allowed sets... 571 for (unsigned node = 0; node < node2LI.size(); ++node) { 572 573 // Grab pointers to the interval and its register class. 574 const LiveInterval *li = node2LI[node]; 575 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 576 577 // Start by assuming all allocable registers in the class are allowed... 578 RegVector liAllowed(liRC->allocation_order_begin(*mf), 579 liRC->allocation_order_end(*mf)); 580 581 // Eliminate the physical registers which overlap with this range, along 582 // with all their aliases. 583 for (LIVector::iterator pItr = physIntervals.begin(), 584 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) { 585 586 if (!li->overlaps(**pItr)) 587 continue; 588 589 unsigned pReg = (*pItr)->reg; 590 591 // If we get here then the live intervals overlap, but we're still ok 592 // if they're coalescable. 593 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) 594 continue; 595 596 // If we get here then we have a genuine exclusion. 597 598 // Remove the overlapping reg... 599 RegVector::iterator eraseItr = 600 std::find(liAllowed.begin(), liAllowed.end(), pReg); 601 602 if (eraseItr != liAllowed.end()) 603 liAllowed.erase(eraseItr); 604 605 const unsigned *aliasItr = tri->getAliasSet(pReg); 606 607 if (aliasItr != 0) { 608 // ...and its aliases. 609 for (; *aliasItr != 0; ++aliasItr) { 610 RegVector::iterator eraseItr = 611 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr); 612 613 if (eraseItr != liAllowed.end()) { 614 liAllowed.erase(eraseItr); 615 } 616 } 617 } 618 } 619 620 // Copy the allowed set into a member vector for use when constructing cost 621 // vectors & matrices, and mapping PBQP solutions back to assignments. 622 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end()); 623 624 // Set the spill cost to the interval weight, or epsilon if the 625 // interval weight is zero 626 PBQP::PBQPNum spillCost = (li->weight != 0.0) ? 627 li->weight : std::numeric_limits<PBQP::PBQPNum>::min(); 628 629 // Build a cost vector for this interval. 630 problemNodes[node] = 631 problem.addNode( 632 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost)); 633 634 } 635 636 637 // Now add the cost matrices... 638 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) { 639 const LiveInterval *li = node2LI[node1]; 640 641 // Test for live range overlaps and insert interference matrices. 642 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) { 643 const LiveInterval *li2 = node2LI[node2]; 644 645 CoalesceMap::const_iterator cmItr = 646 coalesces.find(RegPair(li->reg, li2->reg)); 647 648 PBQP::Matrix *m = 0; 649 650 if (cmItr != coalesces.end()) { 651 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2], 652 cmItr->second); 653 } 654 else if (li->overlaps(*li2)) { 655 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]); 656 } 657 658 if (m != 0) { 659 problem.addEdge(problemNodes[node1], 660 problemNodes[node2], 661 *m); 662 663 delete m; 664 } 665 } 666 } 667 668 assert(problem.getNumNodes() == allowedSets.size()); 669/* 670 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, " 671 << problem.getNumEdges() << " edges.\n"; 672 673 problem.printDot(std::cerr); 674*/ 675 // We're done, PBQP problem constructed - return it. 676 return problem; 677} 678 679void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, 680 MachineRegisterInfo* mri) { 681 int stackSlot = vrm->getStackSlot(spilled->reg); 682 683 if (stackSlot == VirtRegMap::NO_STACK_SLOT) 684 return; 685 686 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg); 687 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC); 688 689 VNInfo *vni; 690 if (stackInterval.getNumValNums() != 0) 691 vni = stackInterval.getValNumInfo(0); 692 else 693 vni = stackInterval.getNextValue( 694 SlotIndex(), 0, false, lss->getVNInfoAllocator()); 695 696 LiveInterval &rhsInterval = lis->getInterval(spilled->reg); 697 stackInterval.MergeRangesInAsValue(rhsInterval, vni); 698} 699 700bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) { 701 702 // Set to true if we have any spills 703 bool anotherRoundNeeded = false; 704 705 // Clear the existing allocation. 706 vrm->clearAllVirt(); 707 708 // Iterate over the nodes mapping the PBQP solution to a register assignment. 709 for (unsigned node = 0; node < node2LI.size(); ++node) { 710 unsigned virtReg = node2LI[node]->reg, 711 allocSelection = solution.getSelection(problemNodes[node]); 712 713 714 // If the PBQP solution is non-zero it's a physical register... 715 if (allocSelection != 0) { 716 // Get the physical reg, subtracting 1 to account for the spill option. 717 unsigned physReg = allowedSets[node][allocSelection - 1]; 718 719 DEBUG(dbgs() << "VREG " << virtReg << " -> " 720 << tri->getName(physReg) << "\n"); 721 722 assert(physReg != 0); 723 724 // Add to the virt reg map and update the used phys regs. 725 vrm->assignVirt2Phys(virtReg, physReg); 726 } 727 // ...Otherwise it's a spill. 728 else { 729 730 // Make sure we ignore this virtual reg on the next round 731 // of allocation 732 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg)); 733 734 // Insert spill ranges for this live range 735 const LiveInterval *spillInterval = node2LI[node]; 736 double oldSpillWeight = spillInterval->weight; 737 SmallVector<LiveInterval*, 8> spillIs; 738 std::vector<LiveInterval*> newSpills = 739 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); 740 addStackInterval(spillInterval, mri); 741 742 (void) oldSpillWeight; 743 DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: " 744 << oldSpillWeight << ", New vregs: "); 745 746 // Copy any newly inserted live intervals into the list of regs to 747 // allocate. 748 for (std::vector<LiveInterval*>::const_iterator 749 itr = newSpills.begin(), end = newSpills.end(); 750 itr != end; ++itr) { 751 752 assert(!(*itr)->empty() && "Empty spill range."); 753 754 DEBUG(dbgs() << (*itr)->reg << " "); 755 756 vregIntervalsToAlloc.insert(*itr); 757 } 758 759 DEBUG(dbgs() << ")\n"); 760 761 // We need another round if spill intervals were added. 762 anotherRoundNeeded |= !newSpills.empty(); 763 } 764 } 765 766 return !anotherRoundNeeded; 767} 768 769void PBQPRegAlloc::finalizeAlloc() const { 770 typedef LiveIntervals::iterator LIIterator; 771 typedef LiveInterval::Ranges::const_iterator LRIterator; 772 773 // First allocate registers for the empty intervals. 774 for (LiveIntervalSet::const_iterator 775 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end(); 776 itr != end; ++itr) { 777 LiveInterval *li = *itr; 778 779 unsigned physReg = vrm->getRegAllocPref(li->reg); 780 781 if (physReg == 0) { 782 const TargetRegisterClass *liRC = mri->getRegClass(li->reg); 783 physReg = *liRC->allocation_order_begin(*mf); 784 } 785 786 vrm->assignVirt2Phys(li->reg, physReg); 787 } 788 789 // Finally iterate over the basic blocks to compute and set the live-in sets. 790 SmallVector<MachineBasicBlock*, 8> liveInMBBs; 791 MachineBasicBlock *entryMBB = &*mf->begin(); 792 793 for (LIIterator liItr = lis->begin(), liEnd = lis->end(); 794 liItr != liEnd; ++liItr) { 795 796 const LiveInterval *li = liItr->second; 797 unsigned reg = 0; 798 799 // Get the physical register for this interval 800 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) { 801 reg = li->reg; 802 } 803 else if (vrm->isAssignedReg(li->reg)) { 804 reg = vrm->getPhys(li->reg); 805 } 806 else { 807 // Ranges which are assigned a stack slot only are ignored. 808 continue; 809 } 810 811 if (reg == 0) { 812 // Filter out zero regs - they're for intervals that were spilled. 813 continue; 814 } 815 816 // Iterate over the ranges of the current interval... 817 for (LRIterator lrItr = li->begin(), lrEnd = li->end(); 818 lrItr != lrEnd; ++lrItr) { 819 820 // Find the set of basic blocks which this range is live into... 821 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) { 822 // And add the physreg for this interval to their live-in sets. 823 for (unsigned i = 0; i < liveInMBBs.size(); ++i) { 824 if (liveInMBBs[i] != entryMBB) { 825 if (!liveInMBBs[i]->isLiveIn(reg)) { 826 liveInMBBs[i]->addLiveIn(reg); 827 } 828 } 829 } 830 liveInMBBs.clear(); 831 } 832 } 833 } 834 835} 836 837bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { 838 839 mf = &MF; 840 tm = &mf->getTarget(); 841 tri = tm->getRegisterInfo(); 842 tii = tm->getInstrInfo(); 843 mri = &mf->getRegInfo(); 844 845 lis = &getAnalysis<LiveIntervals>(); 846 lss = &getAnalysis<LiveStacks>(); 847 loopInfo = &getAnalysis<MachineLoopInfo>(); 848 849 vrm = &getAnalysis<VirtRegMap>(); 850 851 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"); 852 853 // Allocator main loop: 854 // 855 // * Map current regalloc problem to a PBQP problem 856 // * Solve the PBQP problem 857 // * Map the solution back to a register allocation 858 // * Spill if necessary 859 // 860 // This process is continued till no more spills are generated. 861 862 // Find the vreg intervals in need of allocation. 863 findVRegIntervalsToAlloc(); 864 865 // If there are non-empty intervals allocate them using pbqp. 866 if (!vregIntervalsToAlloc.empty()) { 867 868 bool pbqpAllocComplete = false; 869 unsigned round = 0; 870 871 while (!pbqpAllocComplete) { 872 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n"); 873 874 PBQP::Graph problem = constructPBQPProblem(); 875 PBQP::Solution solution = 876 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem); 877 878 pbqpAllocComplete = mapPBQPToRegAlloc(solution); 879 880 ++round; 881 } 882 } 883 884 // Finalise allocation, allocate empty ranges. 885 finalizeAlloc(); 886 887 vregIntervalsToAlloc.clear(); 888 emptyVRegIntervals.clear(); 889 li2Node.clear(); 890 node2LI.clear(); 891 allowedSets.clear(); 892 problemNodes.clear(); 893 894 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n"); 895 896 // Run rewriter 897 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); 898 899 rewriter->runOnMachineFunction(*mf, *vrm, lis); 900 901 return true; 902} 903 904FunctionPass* llvm::createPBQPRegisterAllocator() { 905 return new PBQPRegAlloc(); 906} 907 908 909#undef DEBUG_TYPE 910