RegisterClassInfo.cpp revision b6632ba380cf624e60fe16b03d6e21b05dd07724 
1//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the RegisterClassInfo class which provides dynamic
11// information about target register classes. Callee saved and reserved
12// registers depends on calling conventions and other dynamic information, so
13// some things cannot be determined statically.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "regalloc"
18#include "RegisterClassInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/raw_ostream.h"
24
25using namespace llvm;
26
27static cl::opt<unsigned>
28StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
29         cl::desc("Limit all regclasses to N registers"));
30
31RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
32{}
33
34void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
35  bool Update = false;
36  MF = &mf;
37
38  // Allocate new array the first time we see a new target.
39  if (MF->getTarget().getRegisterInfo() != TRI) {
40    TRI = MF->getTarget().getRegisterInfo();
41    RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
42    Update = true;
43  }
44
45  // Does this MF have different CSRs?
46  const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
47  if (Update || CSR != CalleeSaved) {
48    // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
49    // overlapping CSR.
50    CSRNum.clear();
51    CSRNum.resize(TRI->getNumRegs(), 0);
52    for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
53      for (const unsigned *AS = TRI->getOverlaps(Reg);
54           unsigned Alias = *AS; ++AS)
55        CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
56    Update = true;
57  }
58  CalleeSaved = CSR;
59
60  // Different reserved registers?
61  BitVector RR = TRI->getReservedRegs(*MF);
62  if (RR != Reserved)
63    Update = true;
64  Reserved = RR;
65
66  // Invalidate cached information from previous function.
67  if (Update)
68    ++Tag;
69}
70
71/// compute - Compute the preferred allocation order for RC with reserved
72/// registers filtered out. Volatile registers come first followed by CSR
73/// aliases ordered according to the CSR order specified by the target.
74void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
75  RCInfo &RCI = RegClass[RC->getID()];
76
77  // Raw register count, including all reserved regs.
78  unsigned NumRegs = RC->getNumRegs();
79
80  if (!RCI.Order)
81    RCI.Order.reset(new unsigned[NumRegs]);
82
83  unsigned N = 0;
84  SmallVector<unsigned, 16> CSRAlias;
85
86  // FIXME: Once targets reserve registers instead of removing them from the
87  // allocation order, we can simply use begin/end here.
88  ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF);
89  for (unsigned i = 0; i != RawOrder.size(); ++i) {
90    unsigned PhysReg = RawOrder[i];
91    // Remove reserved registers from the allocation order.
92    if (Reserved.test(PhysReg))
93      continue;
94    if (CSRNum[PhysReg])
95      // PhysReg aliases a CSR, save it for later.
96      CSRAlias.push_back(PhysReg);
97    else
98      RCI.Order[N++] = PhysReg;
99  }
100  RCI.NumRegs = N + CSRAlias.size();
101  assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
102
103  // CSR aliases go after the volatile registers, preserve the target's order.
104  std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
105
106  // Register allocator stress test.  Clip register class to N registers.
107  if (StressRA && RCI.NumRegs > StressRA)
108    RCI.NumRegs = StressRA;
109
110  // Check if RC is a proper sub-class.
111  if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
112    if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
113      RCI.ProperSubClass = true;
114
115  DEBUG({
116    dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
117    for (unsigned I = 0; I != RCI.NumRegs; ++I)
118      dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
119    dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
120  });
121
122  // RCI is now up-to-date.
123  RCI.Tag = Tag;
124}
125
126