| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 1f8b48ab3262bd5623ecbda7b0c024884e8169d3 |
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21-Jun-2013 |
Andrew Trick <atrick@apple.com> |
MI-Sched: Adjust regpressure limits for reserved regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| c7a275245f501e2f68a55af05c75bc9b6b50ec84 |
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12-Jan-2013 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Precompute some information about register costs.
Remember the minimum cost of the registers in an allocation order and
the number of registers at the end of the allocation order that have the
same cost per use.
This information can be used to limit the search space for
RAGreedy::tryEvict() when looking for a cheaper register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172280 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
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03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 39b5c0c049a19c7a7feffc9506da07923cc136e4 |
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29-Nov-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use MCPhysReg for RegisterClassInfo allocation orders.
This saves a bit of memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| fb9ebbf236974beac31705eaeb9f50ab585af6ab |
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15-Oct-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 1525260b3e50cc578939ef41b60609689eecfdd2 |
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06-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 396618b43a85e12d290a90b181c6af5d7c0c5f11 |
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02-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch all register list clients to the new MC*Iterator interface.
No functional change intended.
Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.
This makes it possible to do so without changing all clients (again).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| e4fd907e72a599eddfa7a81eac4366b5b82523e3 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| b6632ba380cf624e60fe16b03d6e21b05dd07724 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 015f228861ef9b337366f92f637d4e8d624bb006 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store registers in callee saved register tables to reduce size of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| f79b489571610cc5a97c050415b982e94a9989fd |
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24-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 27bc818eaf73efe169f95c4dd8f564fd051dd824 |
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24-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a -stress-regalloc=<N> option.
This will limit all register classes to N registers in order to stress
test register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| f39031b360f135ece3bdc86151804dd1f3f51733 |
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05-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Detect proper register sub-classes.
Some instructions require restricted register classes, but most of the
time that doesn't affect register allocation. For example, some
instructions don't work with the stack pointer, but that is a reserved
register anyway.
Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For
such a proper sub-class, the register allocator should try to enable
register class inflation since that makes more registers available for
allocation.
Make sure only legal super-classes are considered. For example, tGPR is
not a proper sub-class in Thumb mode, but in ARM mode it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 79c890f64f3b67f9b11341aa452c4302b75184aa |
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16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetRegisterInfo::getRawAllocationOrder().
This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.
Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 687397c01387534e98d2e8332d4b91536290d778 |
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13-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Include callee-saved registers in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 7c48913af62ced0da03ba58755cf5f53ad587ba8 |
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06-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't try to be clever, just preserve the target's allocation order.
The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.
When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.
We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| d365fa9415ce31b5f0a6019b33c6f099a82f4e34 |
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03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL)
Print out the computed allocation orders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 6edf90b8a7168e53409d161fb8b285094c4c9182 |
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03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Just use a SmallVector.
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.
This should fix the test failures on darwin 9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 19e1f633af989f52f066553cbe85dded14686ac3 |
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02-Jun-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Start with a zeroed CSRNum map.
Found by valgrind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132457 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| ab5ceacbc11b68f1a4993aa38bad11bcfea42a4c |
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02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Initialize members to fix problem found by valgrind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
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| 491a13691d3b30b8288dfc6e01ad6a58f69a4ce6 |
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02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterClassInfo class that lazily caches information about
register classes.
It provides information for each register class that cannot be
determined statically, like:
- The number of allocatable registers in a class after filtering out the
reserved and invalid registers.
- The preferred allocation order with registers that overlap callee-saved
registers last.
- The last callee-saved register that overlaps a given physical register.
This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible. The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.
Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.cpp
|