RegisterScavenging.cpp revision a0e180ac4672e4a304f93a2d0207428c83de155e 
1//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the machine register scavenger. It can provide
11// information, such as unused registers, at any point in a machine basic block.
12// It also provides a mechanism to make registers available by evicting them to
13// spill slots.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "reg-scavenging"
18#include "llvm/CodeGen/RegisterScavenging.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Target/TargetRegisterInfo.h"
26#include "llvm/Target/TargetInstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/SmallPtrSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/STLExtras.h"
32using namespace llvm;
33
34/// setUsed - Set the register and its sub-registers as being used.
35void RegScavenger::setUsed(unsigned Reg) {
36  RegsAvailable.reset(Reg);
37
38  for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
39       unsigned SubReg = *SubRegs; ++SubRegs)
40    RegsAvailable.reset(SubReg);
41}
42
43bool RegScavenger::isAliasUsed(unsigned Reg) const {
44  if (isUsed(Reg))
45    return true;
46  for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
47    if (isUsed(*R))
48      return true;
49  return false;
50}
51
52void RegScavenger::initRegState() {
53  ScavengedReg = 0;
54  ScavengedRC = NULL;
55  ScavengeRestore = NULL;
56
57  // All registers started out unused.
58  RegsAvailable.set();
59
60  // Reserved registers are always used.
61  RegsAvailable ^= ReservedRegs;
62
63  if (!MBB)
64    return;
65
66  // Live-in registers are in use.
67  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
68         E = MBB->livein_end(); I != E; ++I)
69    setUsed(*I);
70
71  // Pristine CSRs are also unavailable.
72  BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
73  for (int I = PR.find_first(); I>0; I = PR.find_next(I))
74    setUsed(I);
75}
76
77void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
78  MachineFunction &MF = *mbb->getParent();
79  const TargetMachine &TM = MF.getTarget();
80  TII = TM.getInstrInfo();
81  TRI = TM.getRegisterInfo();
82  MRI = &MF.getRegInfo();
83
84  assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
85         "Target changed?");
86
87  // Self-initialize.
88  if (!MBB) {
89    NumPhysRegs = TRI->getNumRegs();
90    RegsAvailable.resize(NumPhysRegs);
91
92    // Create reserved registers bitvector.
93    ReservedRegs = TRI->getReservedRegs(MF);
94
95    // Create callee-saved registers bitvector.
96    CalleeSavedRegs.resize(NumPhysRegs);
97    const unsigned *CSRegs = TRI->getCalleeSavedRegs();
98    if (CSRegs != NULL)
99      for (unsigned i = 0; CSRegs[i]; ++i)
100        CalleeSavedRegs.set(CSRegs[i]);
101  }
102
103  // RS used within emit{Pro,Epi}logue()
104  if (mbb != MBB) {
105    MBB = mbb;
106    initRegState();
107  }
108
109  Tracking = false;
110}
111
112void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
113  BV.set(Reg);
114  for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
115    BV.set(*R);
116}
117
118void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
119  BV.set(Reg);
120  for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
121    BV.set(*R);
122}
123
124void RegScavenger::forward() {
125  // Move ptr forward.
126  if (!Tracking) {
127    MBBI = MBB->begin();
128    Tracking = true;
129  } else {
130    assert(MBBI != MBB->end() && "Already at the end of the basic block!");
131    MBBI = next(MBBI);
132  }
133
134  MachineInstr *MI = MBBI;
135
136  if (MI == ScavengeRestore) {
137    ScavengedReg = 0;
138    ScavengedRC = NULL;
139    ScavengeRestore = NULL;
140  }
141
142  // Find out which registers are early clobbered, killed, defined, and marked
143  // def-dead in this instruction.
144  BitVector EarlyClobberRegs(NumPhysRegs);
145  BitVector KillRegs(NumPhysRegs);
146  BitVector DefRegs(NumPhysRegs);
147  BitVector DeadRegs(NumPhysRegs);
148  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
149    const MachineOperand &MO = MI->getOperand(i);
150    if (!MO.isReg() || MO.isUndef())
151      continue;
152    unsigned Reg = MO.getReg();
153    if (!Reg || isReserved(Reg))
154      continue;
155
156    if (MO.isUse()) {
157      // Two-address operands implicitly kill.
158      if (MO.isKill() || MI->isRegTiedToDefOperand(i))
159        addRegWithSubRegs(KillRegs, Reg);
160    } else {
161      assert(MO.isDef());
162      if (MO.isDead())
163        addRegWithSubRegs(DeadRegs, Reg);
164      else
165        addRegWithSubRegs(DefRegs, Reg);
166      if (MO.isEarlyClobber())
167        addRegWithAliases(EarlyClobberRegs, Reg);
168    }
169  }
170
171  // Verify uses and defs.
172  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
173    const MachineOperand &MO = MI->getOperand(i);
174    if (!MO.isReg() || MO.isUndef())
175      continue;
176    unsigned Reg = MO.getReg();
177    if (!Reg || isReserved(Reg))
178      continue;
179    if (MO.isUse()) {
180      assert(isUsed(Reg) && "Using an undefined register!");
181      assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
182             "Using an early clobbered register!");
183    } else {
184      assert(MO.isDef());
185#if 0
186      // FIXME: Enable this once we've figured out how to correctly transfer
187      // implicit kills during codegen passes like the coalescer.
188      assert((KillRegs.test(Reg) || isUnused(Reg) ||
189              isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
190             "Re-defining a live register!");
191#endif
192    }
193  }
194
195  // Commit the changes.
196  setUnused(KillRegs);
197  setUnused(DeadRegs);
198  setUsed(DefRegs);
199}
200
201void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
202  if (includeReserved)
203    used = ~RegsAvailable;
204  else
205    used = ~RegsAvailable & ~ReservedRegs;
206}
207
208/// CreateRegClassMask - Set the bits that represent the registers in the
209/// TargetRegisterClass.
210static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
211  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
212       ++I)
213    Mask.set(*I);
214}
215
216unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
217  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
218       I != E; ++I)
219    if (!isAliasUsed(*I))
220      return *I;
221  return 0;
222}
223
224/// findSurvivorReg - Return the candidate register that is unused for the
225/// longest after MBBI. UseMI is set to the instruction where the search
226/// stopped.
227///
228/// No more than InstrLimit instructions are inspected.
229///
230unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator MI,
231                                       BitVector &Candidates,
232                                       unsigned InstrLimit,
233                                       MachineBasicBlock::iterator &UseMI) {
234  int Survivor = Candidates.find_first();
235  assert(Survivor > 0 && "No candidates for scavenging");
236
237  MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
238  assert(MI != ME && "MI already at terminator");
239
240  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
241    // Remove any candidates touched by instruction.
242    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243      const MachineOperand &MO = MI->getOperand(i);
244      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
245          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
246        continue;
247      Candidates.reset(MO.getReg());
248      for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
249        Candidates.reset(*R);
250    }
251
252    // Was our survivor untouched by this instruction?
253    if (Candidates.test(Survivor))
254      continue;
255
256    // All candidates gone?
257    if (Candidates.none())
258      break;
259
260    Survivor = Candidates.find_first();
261  }
262
263  // We ran out of candidates, so stop the search.
264  UseMI = MI;
265  return Survivor;
266}
267
268unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
269                                        MachineBasicBlock::iterator I,
270                                        int SPAdj) {
271  assert(ScavengingFrameIndex >= 0 &&
272         "Cannot scavenge a register without an emergency spill slot!");
273
274  // Mask off the registers which are not in the TargetRegisterClass.
275  BitVector Candidates(NumPhysRegs, false);
276  CreateRegClassMask(RC, Candidates);
277  // Do not include reserved registers.
278  Candidates ^= ReservedRegs & Candidates;
279
280  // Exclude all the registers being used by the instruction.
281  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
282    MachineOperand &MO = I->getOperand(i);
283    if (MO.isReg() && MO.getReg() != 0 &&
284        !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
285      Candidates.reset(MO.getReg());
286  }
287
288  // Find the register whose use is furthest away.
289  MachineBasicBlock::iterator UseMI;
290  unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
291
292  // If we found an unused register there is no reason to spill it. We have
293  // probably found a callee-saved register that has been saved in the
294  // prologue, but happens to be unused at this point.
295  if (!isAliasUsed(SReg))
296    return SReg;
297
298  assert(ScavengedReg == 0 &&
299         "Scavenger slot is live, unable to scavenge another register!");
300
301  // Avoid infinite regress
302  ScavengedReg = SReg;
303
304  // Spill the scavenged register before I.
305  TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
306  MachineBasicBlock::iterator II = prior(I);
307  TRI->eliminateFrameIndex(II, SPAdj, this);
308
309  // Restore the scavenged register before its use (or first terminator).
310  TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
311  ScavengeRestore = prior(UseMI);
312  // Doing this here leads to infinite regress.
313  // ScavengedReg = SReg;
314  ScavengedRC = RC;
315
316  return SReg;
317}
318