RegisterScavenging.cpp revision d61c40360c3acc847263c5e5184b715c17528b09 
1//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the machine register scavenger. It can provide
11// information, such as unused registers, at any point in a machine basic block.
12// It also provides a mechanism to make registers available by evicting them to
13// spill slots.
14//
15//===----------------------------------------------------------------------===//
16
17#define DEBUG_TYPE "reg-scavenging"
18#include "llvm/CodeGen/RegisterScavenging.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/Target/TargetRegisterInfo.h"
28#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/STLExtras.h"
34using namespace llvm;
35
36/// setUsed - Set the register and its sub-registers as being used.
37void RegScavenger::setUsed(unsigned Reg) {
38  RegsAvailable.reset(Reg);
39
40  for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
41       unsigned SubReg = *SubRegs; ++SubRegs)
42    RegsAvailable.reset(SubReg);
43}
44
45bool RegScavenger::isAliasUsed(unsigned Reg) const {
46  if (isUsed(Reg))
47    return true;
48  for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
49    if (isUsed(*R))
50      return true;
51  return false;
52}
53
54void RegScavenger::initRegState() {
55  ScavengedReg = 0;
56  ScavengedRC = NULL;
57  ScavengeRestore = NULL;
58
59  // All registers started out unused.
60  RegsAvailable.set();
61
62  // Reserved registers are always used.
63  RegsAvailable ^= ReservedRegs;
64
65  if (!MBB)
66    return;
67
68  // Live-in registers are in use.
69  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
70         E = MBB->livein_end(); I != E; ++I)
71    setUsed(*I);
72
73  // Pristine CSRs are also unavailable.
74  BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
75  for (int I = PR.find_first(); I>0; I = PR.find_next(I))
76    setUsed(I);
77}
78
79void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
80  MachineFunction &MF = *mbb->getParent();
81  const TargetMachine &TM = MF.getTarget();
82  TII = TM.getInstrInfo();
83  TRI = TM.getRegisterInfo();
84  MRI = &MF.getRegInfo();
85
86  assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
87         "Target changed?");
88
89  // Self-initialize.
90  if (!MBB) {
91    NumPhysRegs = TRI->getNumRegs();
92    RegsAvailable.resize(NumPhysRegs);
93
94    // Create reserved registers bitvector.
95    ReservedRegs = TRI->getReservedRegs(MF);
96
97    // Create callee-saved registers bitvector.
98    CalleeSavedRegs.resize(NumPhysRegs);
99    const unsigned *CSRegs = TRI->getCalleeSavedRegs();
100    if (CSRegs != NULL)
101      for (unsigned i = 0; CSRegs[i]; ++i)
102        CalleeSavedRegs.set(CSRegs[i]);
103  }
104
105  MBB = mbb;
106  initRegState();
107
108  Tracking = false;
109}
110
111void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
112  BV.set(Reg);
113  for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
114    BV.set(*R);
115}
116
117void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
118  BV.set(Reg);
119  for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
120    BV.set(*R);
121}
122
123void RegScavenger::forward() {
124  // Move ptr forward.
125  if (!Tracking) {
126    MBBI = MBB->begin();
127    Tracking = true;
128  } else {
129    assert(MBBI != MBB->end() && "Already past the end of the basic block!");
130    MBBI = llvm::next(MBBI);
131  }
132  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
133
134  MachineInstr *MI = MBBI;
135
136  if (MI == ScavengeRestore) {
137    ScavengedReg = 0;
138    ScavengedRC = NULL;
139    ScavengeRestore = NULL;
140  }
141
142  if (MI->isDebugValue())
143    return;
144
145  // Find out which registers are early clobbered, killed, defined, and marked
146  // def-dead in this instruction.
147  // FIXME: The scavenger is not predication aware. If the instruction is
148  // predicated, conservatively assume "kill" markers do not actually kill the
149  // register. Similarly ignores "dead" markers.
150  bool isPred = TII->isPredicated(MI);
151  BitVector EarlyClobberRegs(NumPhysRegs);
152  BitVector KillRegs(NumPhysRegs);
153  BitVector DefRegs(NumPhysRegs);
154  BitVector DeadRegs(NumPhysRegs);
155  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
156    const MachineOperand &MO = MI->getOperand(i);
157    if (!MO.isReg())
158      continue;
159    unsigned Reg = MO.getReg();
160    if (!Reg || isReserved(Reg))
161      continue;
162
163    if (MO.isUse()) {
164      // Ignore undef uses.
165      if (MO.isUndef())
166        continue;
167      // Two-address operands implicitly kill.
168      if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
169        addRegWithSubRegs(KillRegs, Reg);
170    } else {
171      assert(MO.isDef());
172      if (!isPred && MO.isDead())
173        addRegWithSubRegs(DeadRegs, Reg);
174      else
175        addRegWithSubRegs(DefRegs, Reg);
176      if (MO.isEarlyClobber())
177        addRegWithAliases(EarlyClobberRegs, Reg);
178    }
179  }
180
181  // Verify uses and defs.
182  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183    const MachineOperand &MO = MI->getOperand(i);
184    if (!MO.isReg())
185      continue;
186    unsigned Reg = MO.getReg();
187    if (!Reg || isReserved(Reg))
188      continue;
189    if (MO.isUse()) {
190      if (MO.isUndef())
191        continue;
192      if (!isUsed(Reg)) {
193        // Check if it's partial live: e.g.
194        // D0 = insert_subreg D0<undef>, S0
195        // ... D0
196        // The problem is the insert_subreg could be eliminated. The use of
197        // D0 is using a partially undef value. This is not *incorrect* since
198        // S1 is can be freely clobbered.
199        // Ideally we would like a way to model this, but leaving the
200        // insert_subreg around causes both correctness and performance issues.
201        bool SubUsed = false;
202        for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
203             unsigned SubReg = *SubRegs; ++SubRegs)
204          if (isUsed(SubReg)) {
205            SubUsed = true;
206            break;
207          }
208        assert(SubUsed && "Using an undefined register!");
209      }
210      assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
211             "Using an early clobbered register!");
212    } else {
213      assert(MO.isDef());
214#if 0
215      // FIXME: Enable this once we've figured out how to correctly transfer
216      // implicit kills during codegen passes like the coalescer.
217      assert((KillRegs.test(Reg) || isUnused(Reg) ||
218              isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
219             "Re-defining a live register!");
220#endif
221    }
222  }
223
224  // Commit the changes.
225  setUnused(KillRegs);
226  setUnused(DeadRegs);
227  setUsed(DefRegs);
228}
229
230void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
231  if (includeReserved)
232    used = ~RegsAvailable;
233  else
234    used = ~RegsAvailable & ~ReservedRegs;
235}
236
237unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
238  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
239       I != E; ++I)
240    if (!isAliasUsed(*I)) {
241      DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
242            "\n");
243      return *I;
244    }
245  return 0;
246}
247
248/// getRegsAvailable - Return all available registers in the register class
249/// in Mask.
250BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
251  BitVector Mask(TRI->getNumRegs());
252  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
253       I != E; ++I)
254    if (!isAliasUsed(*I))
255      Mask.set(*I);
256  return Mask;
257}
258
259/// findSurvivorReg - Return the candidate register that is unused for the
260/// longest after StargMII. UseMI is set to the instruction where the search
261/// stopped.
262///
263/// No more than InstrLimit instructions are inspected.
264///
265unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
266                                       BitVector &Candidates,
267                                       unsigned InstrLimit,
268                                       MachineBasicBlock::iterator &UseMI) {
269  int Survivor = Candidates.find_first();
270  assert(Survivor > 0 && "No candidates for scavenging");
271
272  MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
273  assert(StartMI != ME && "MI already at terminator");
274  MachineBasicBlock::iterator RestorePointMI = StartMI;
275  MachineBasicBlock::iterator MI = StartMI;
276
277  bool inVirtLiveRange = false;
278  for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
279    if (MI->isDebugValue()) {
280      ++InstrLimit; // Don't count debug instructions
281      continue;
282    }
283    bool isVirtKillInsn = false;
284    bool isVirtDefInsn = false;
285    // Remove any candidates touched by instruction.
286    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
287      const MachineOperand &MO = MI->getOperand(i);
288      if (!MO.isReg() || MO.isUndef() || !MO.getReg())
289        continue;
290      if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
291        if (MO.isDef())
292          isVirtDefInsn = true;
293        else if (MO.isKill())
294          isVirtKillInsn = true;
295        continue;
296      }
297      Candidates.reset(MO.getReg());
298      for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
299        Candidates.reset(*R);
300    }
301    // If we're not in a virtual reg's live range, this is a valid
302    // restore point.
303    if (!inVirtLiveRange) RestorePointMI = MI;
304
305    // Update whether we're in the live range of a virtual register
306    if (isVirtKillInsn) inVirtLiveRange = false;
307    if (isVirtDefInsn) inVirtLiveRange = true;
308
309    // Was our survivor untouched by this instruction?
310    if (Candidates.test(Survivor))
311      continue;
312
313    // All candidates gone?
314    if (Candidates.none())
315      break;
316
317    Survivor = Candidates.find_first();
318  }
319  // If we ran off the end, that's where we want to restore.
320  if (MI == ME) RestorePointMI = ME;
321  assert (RestorePointMI != StartMI &&
322          "No available scavenger restore location!");
323
324  // We ran out of candidates, so stop the search.
325  UseMI = RestorePointMI;
326  return Survivor;
327}
328
329unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
330                                        MachineBasicBlock::iterator I,
331                                        int SPAdj) {
332  // Consider all allocatable registers in the register class initially
333  BitVector Candidates =
334    TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
335
336  // Exclude all the registers being used by the instruction.
337  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
338    MachineOperand &MO = I->getOperand(i);
339    if (MO.isReg() && MO.getReg() != 0 &&
340        !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
341      Candidates.reset(MO.getReg());
342  }
343
344  // Try to find a register that's unused if there is one, as then we won't
345  // have to spill. Search explicitly rather than masking out based on
346  // RegsAvailable, as RegsAvailable does not take aliases into account.
347  // That's what getRegsAvailable() is for.
348  BitVector Available = getRegsAvailable(RC);
349
350  if ((Candidates & Available).any())
351     Candidates &= Available;
352
353  // Find the register whose use is furthest away.
354  MachineBasicBlock::iterator UseMI;
355  unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
356
357  // If we found an unused register there is no reason to spill it.
358  if (!isAliasUsed(SReg)) {
359    DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
360    return SReg;
361  }
362
363  assert(ScavengedReg == 0 &&
364         "Scavenger slot is live, unable to scavenge another register!");
365
366  // Avoid infinite regress
367  ScavengedReg = SReg;
368
369  // If the target knows how to save/restore the register, let it do so;
370  // otherwise, use the emergency stack spill slot.
371  if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
372    // Spill the scavenged register before I.
373    assert(ScavengingFrameIndex >= 0 &&
374           "Cannot scavenge register without an emergency spill slot!");
375    TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
376    MachineBasicBlock::iterator II = prior(I);
377    TRI->eliminateFrameIndex(II, SPAdj, this);
378
379    // Restore the scavenged register before its use (or first terminator).
380    TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
381    II = prior(UseMI);
382    TRI->eliminateFrameIndex(II, SPAdj, this);
383  }
384
385  ScavengeRestore = prior(UseMI);
386
387  // Doing this here leads to infinite regress.
388  // ScavengedReg = SReg;
389  ScavengedRC = RC;
390
391  DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
392        "\n");
393
394  return SReg;
395}
396