ScheduleDAGRRList.cpp revision 48fb0205803f2fadef072d33720c11536490d213
1//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements bottom-up and top-down register pressure reduction list 11// schedulers, using standard algorithms. The basic approach uses a priority 12// queue of available nodes to schedule. One at a time, nodes are taken from 13// the priority queue (thus in priority order), checked for legality to 14// schedule, and emitted if legal. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "pre-RA-sched" 19#include "llvm/CodeGen/ScheduleDAG.h" 20#include "llvm/CodeGen/SchedulerRegistry.h" 21#include "llvm/CodeGen/SSARegMap.h" 22#include "llvm/Target/MRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Support/Debug.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/ADT/SmallPtrSet.h" 29#include "llvm/ADT/SmallSet.h" 30#include "llvm/ADT/Statistic.h" 31#include <climits> 32#include <queue> 33#include "llvm/Support/CommandLine.h" 34using namespace llvm; 35 36STATISTIC(NumBacktracks, "Number of times scheduler backtraced"); 37STATISTIC(NumUnfolds, "Number of nodes unfolded"); 38STATISTIC(NumDups, "Number of duplicated nodes"); 39STATISTIC(NumCCCopies, "Number of cross class copies"); 40 41static RegisterScheduler 42 burrListDAGScheduler("list-burr", 43 " Bottom-up register reduction list scheduling", 44 createBURRListDAGScheduler); 45static RegisterScheduler 46 tdrListrDAGScheduler("list-tdrr", 47 " Top-down register reduction list scheduling", 48 createTDRRListDAGScheduler); 49 50namespace { 51//===----------------------------------------------------------------------===// 52/// ScheduleDAGRRList - The actual register reduction list scheduler 53/// implementation. This supports both top-down and bottom-up scheduling. 54/// 55class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG { 56private: 57 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if 58 /// it is top-down. 59 bool isBottomUp; 60 61 /// AvailableQueue - The priority queue to use for the available SUnits. 62 ///a 63 SchedulingPriorityQueue *AvailableQueue; 64 65 /// LiveRegs / LiveRegDefs - A set of physical registers and their definition 66 /// that are "live". These nodes must be scheduled before any other nodes that 67 /// modifies the registers can be scheduled. 68 SmallSet<unsigned, 4> LiveRegs; 69 std::vector<SUnit*> LiveRegDefs; 70 std::vector<unsigned> LiveRegCycles; 71 72public: 73 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb, 74 const TargetMachine &tm, bool isbottomup, 75 SchedulingPriorityQueue *availqueue) 76 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), 77 AvailableQueue(availqueue) { 78 } 79 80 ~ScheduleDAGRRList() { 81 delete AvailableQueue; 82 } 83 84 void Schedule(); 85 86private: 87 void ReleasePred(SUnit*, bool, unsigned); 88 void ReleaseSucc(SUnit*, bool isChain, unsigned); 89 void CapturePred(SUnit*, SUnit*, bool); 90 void ScheduleNodeBottomUp(SUnit*, unsigned); 91 void ScheduleNodeTopDown(SUnit*, unsigned); 92 void UnscheduleNodeBottomUp(SUnit*); 93 void BacktrackBottomUp(SUnit*, unsigned, unsigned&); 94 SUnit *CopyAndMoveSuccessors(SUnit*); 95 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned, 96 const TargetRegisterClass*, 97 const TargetRegisterClass*, 98 SmallVector<SUnit*, 2>&); 99 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&); 100 void ListScheduleTopDown(); 101 void ListScheduleBottomUp(); 102 void CommuteNodesToReducePressure(); 103}; 104} // end anonymous namespace 105 106 107/// Schedule - Schedule the DAG using list scheduling. 108void ScheduleDAGRRList::Schedule() { 109 DOUT << "********** List Scheduling **********\n"; 110 111 LiveRegDefs.resize(MRI->getNumRegs(), NULL); 112 LiveRegCycles.resize(MRI->getNumRegs(), 0); 113 114 // Build scheduling units. 115 BuildSchedUnits(); 116 117 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) 118 SUnits[su].dumpAll(&DAG)); 119 CalculateDepths(); 120 CalculateHeights(); 121 122 AvailableQueue->initNodes(SUnitMap, SUnits); 123 124 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate. 125 if (isBottomUp) 126 ListScheduleBottomUp(); 127 else 128 ListScheduleTopDown(); 129 130 AvailableQueue->releaseState(); 131 132 CommuteNodesToReducePressure(); 133 134 DOUT << "*** Final schedule ***\n"; 135 DEBUG(dumpSchedule()); 136 DOUT << "\n"; 137 138 // Emit in scheduled order 139 EmitSchedule(); 140} 141 142/// CommuteNodesToReducePressure - If a node is two-address and commutable, and 143/// it is not the last use of its first operand, add it to the CommuteSet if 144/// possible. It will be commuted when it is translated to a MI. 145void ScheduleDAGRRList::CommuteNodesToReducePressure() { 146 SmallPtrSet<SUnit*, 4> OperandSeen; 147 for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node. 148 SUnit *SU = Sequence[i]; 149 if (!SU || !SU->Node) continue; 150 if (SU->isCommutable) { 151 unsigned Opc = SU->Node->getTargetOpcode(); 152 unsigned NumRes = TII->getNumDefs(Opc); 153 unsigned NumOps = CountOperands(SU->Node); 154 for (unsigned j = 0; j != NumOps; ++j) { 155 if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1) 156 continue; 157 158 SDNode *OpN = SU->Node->getOperand(j).Val; 159 SUnit *OpSU = SUnitMap[OpN][SU->InstanceNo]; 160 if (OpSU && OperandSeen.count(OpSU) == 1) { 161 // Ok, so SU is not the last use of OpSU, but SU is two-address so 162 // it will clobber OpSU. Try to commute SU if no other source operands 163 // are live below. 164 bool DoCommute = true; 165 for (unsigned k = 0; k < NumOps; ++k) { 166 if (k != j) { 167 OpN = SU->Node->getOperand(k).Val; 168 OpSU = SUnitMap[OpN][SU->InstanceNo]; 169 if (OpSU && OperandSeen.count(OpSU) == 1) { 170 DoCommute = false; 171 break; 172 } 173 } 174 } 175 if (DoCommute) 176 CommuteSet.insert(SU->Node); 177 } 178 179 // Only look at the first use&def node for now. 180 break; 181 } 182 } 183 184 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 185 I != E; ++I) { 186 if (!I->isCtrl) 187 OperandSeen.insert(I->Dep); 188 } 189 } 190} 191 192//===----------------------------------------------------------------------===// 193// Bottom-Up Scheduling 194//===----------------------------------------------------------------------===// 195 196/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to 197/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 198void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, 199 unsigned CurCycle) { 200 // FIXME: the distance between two nodes is not always == the predecessor's 201 // latency. For example, the reader can very well read the register written 202 // by the predecessor later than the issue cycle. It also depends on the 203 // interrupt model (drain vs. freeze). 204 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency); 205 206 --PredSU->NumSuccsLeft; 207 208#ifndef NDEBUG 209 if (PredSU->NumSuccsLeft < 0) { 210 cerr << "*** List scheduling failed! ***\n"; 211 PredSU->dump(&DAG); 212 cerr << " has been released too many times!\n"; 213 assert(0); 214 } 215#endif 216 217 if (PredSU->NumSuccsLeft == 0) { 218 // EntryToken has to go last! Special case it here. 219 if (!PredSU->Node || PredSU->Node->getOpcode() != ISD::EntryToken) { 220 PredSU->isAvailable = true; 221 AvailableQueue->push(PredSU); 222 } 223 } 224} 225 226/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending 227/// count of its predecessors. If a predecessor pending count is zero, add it to 228/// the Available queue. 229void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { 230 DOUT << "*** Scheduling [" << CurCycle << "]: "; 231 DEBUG(SU->dump(&DAG)); 232 SU->Cycle = CurCycle; 233 234 AvailableQueue->ScheduledNode(SU); 235 236 // Bottom up: release predecessors 237 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 238 I != E; ++I) { 239 ReleasePred(I->Dep, I->isCtrl, CurCycle); 240 if (I->Cost < 0) { 241 // This is a physical register dependency and it's impossible or 242 // expensive to copy the register. Make sure nothing that can 243 // clobber the register is scheduled between the predecessor and 244 // this node. 245 if (LiveRegs.insert(I->Reg)) { 246 LiveRegDefs[I->Reg] = I->Dep; 247 LiveRegCycles[I->Reg] = CurCycle; 248 } 249 } 250 } 251 252 // Release all the implicit physical register defs that are live. 253 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 254 I != E; ++I) { 255 if (I->Cost < 0) { 256 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) { 257 LiveRegs.erase(I->Reg); 258 assert(LiveRegDefs[I->Reg] == SU && 259 "Physical register dependency violated?"); 260 LiveRegDefs[I->Reg] = NULL; 261 LiveRegCycles[I->Reg] = 0; 262 } 263 } 264 } 265 266 SU->isScheduled = true; 267} 268 269/// CapturePred - This does the opposite of ReleasePred. Since SU is being 270/// unscheduled, incrcease the succ left count of its predecessors. Remove 271/// them from AvailableQueue if necessary. 272void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { 273 PredSU->CycleBound = 0; 274 for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end(); 275 I != E; ++I) { 276 if (I->Dep == SU) 277 continue; 278 PredSU->CycleBound = std::max(PredSU->CycleBound, 279 I->Dep->Cycle + PredSU->Latency); 280 } 281 282 if (PredSU->isAvailable) { 283 PredSU->isAvailable = false; 284 if (!PredSU->isPending) 285 AvailableQueue->remove(PredSU); 286 } 287 288 ++PredSU->NumSuccsLeft; 289} 290 291/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and 292/// its predecessor states to reflect the change. 293void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { 294 DOUT << "*** Unscheduling [" << SU->Cycle << "]: "; 295 DEBUG(SU->dump(&DAG)); 296 297 AvailableQueue->UnscheduledNode(SU); 298 299 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 300 I != E; ++I) { 301 CapturePred(I->Dep, SU, I->isCtrl); 302 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) { 303 LiveRegs.erase(I->Reg); 304 assert(LiveRegDefs[I->Reg] == I->Dep && 305 "Physical register dependency violated?"); 306 LiveRegDefs[I->Reg] = NULL; 307 LiveRegCycles[I->Reg] = 0; 308 } 309 } 310 311 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 312 I != E; ++I) { 313 if (I->Cost < 0) { 314 if (LiveRegs.insert(I->Reg)) { 315 assert(!LiveRegDefs[I->Reg] && 316 "Physical register dependency violated?"); 317 LiveRegDefs[I->Reg] = SU; 318 } 319 if (I->Dep->Cycle < LiveRegCycles[I->Reg]) 320 LiveRegCycles[I->Reg] = I->Dep->Cycle; 321 } 322 } 323 324 SU->Cycle = 0; 325 SU->isScheduled = false; 326 SU->isAvailable = true; 327 AvailableQueue->push(SU); 328} 329 330// FIXME: This is probably too slow! 331static void isReachable(SUnit *SU, SUnit *TargetSU, 332 SmallPtrSet<SUnit*, 32> &Visited, bool &Reached) { 333 if (Reached) return; 334 if (SU == TargetSU) { 335 Reached = true; 336 return; 337 } 338 if (!Visited.insert(SU)) return; 339 340 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; 341 ++I) 342 isReachable(I->Dep, TargetSU, Visited, Reached); 343} 344 345static bool isReachable(SUnit *SU, SUnit *TargetSU) { 346 SmallPtrSet<SUnit*, 32> Visited; 347 bool Reached = false; 348 isReachable(SU, TargetSU, Visited, Reached); 349 return Reached; 350} 351 352/// willCreateCycle - Returns true if adding an edge from SU to TargetSU will 353/// create a cycle. 354static bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { 355 if (isReachable(TargetSU, SU)) 356 return true; 357 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 358 I != E; ++I) 359 if (I->Cost < 0 && isReachable(TargetSU, I->Dep)) 360 return true; 361 return false; 362} 363 364/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in 365/// BTCycle in order to schedule a specific node. Returns the last unscheduled 366/// SUnit. Also returns if a successor is unscheduled in the process. 367void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle, 368 unsigned &CurCycle) { 369 SUnit *OldSU = NULL; 370 while (CurCycle > BtCycle) { 371 OldSU = Sequence.back(); 372 Sequence.pop_back(); 373 if (SU->isSucc(OldSU)) 374 // Don't try to remove SU from AvailableQueue. 375 SU->isAvailable = false; 376 UnscheduleNodeBottomUp(OldSU); 377 --CurCycle; 378 } 379 380 381 if (SU->isSucc(OldSU)) { 382 assert(false && "Something is wrong!"); 383 abort(); 384 } 385 386 ++NumBacktracks; 387} 388 389/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled 390/// successors to the newly created node. 391SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { 392 if (SU->FlaggedNodes.size()) 393 return NULL; 394 395 SDNode *N = SU->Node; 396 if (!N) 397 return NULL; 398 399 SUnit *NewSU; 400 bool TryUnfold = false; 401 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 402 MVT::ValueType VT = N->getValueType(i); 403 if (VT == MVT::Flag) 404 return NULL; 405 else if (VT == MVT::Other) 406 TryUnfold = true; 407 } 408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 409 const SDOperand &Op = N->getOperand(i); 410 MVT::ValueType VT = Op.Val->getValueType(Op.ResNo); 411 if (VT == MVT::Flag) 412 return NULL; 413 } 414 415 if (TryUnfold) { 416 SmallVector<SDNode*, 4> NewNodes; 417 if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes)) 418 return NULL; 419 420 DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; 421 assert(NewNodes.size() == 2 && "Expected a load folding node!"); 422 423 N = NewNodes[1]; 424 SDNode *LoadNode = NewNodes[0]; 425 unsigned NumVals = N->getNumValues(); 426 unsigned OldNumVals = SU->Node->getNumValues(); 427 for (unsigned i = 0; i != NumVals; ++i) 428 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i)); 429 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1), 430 SDOperand(LoadNode, 1)); 431 432 SUnit *LoadSU = NewSUnit(LoadNode); 433 SUnit *NewSU = NewSUnit(N); 434 SUnitMap[LoadNode].push_back(LoadSU); 435 SUnitMap[N].push_back(NewSU); 436 const TargetInstrDescriptor *TID = &TII->get(LoadNode->getTargetOpcode()); 437 for (unsigned i = 0; i != TID->numOperands; ++i) { 438 if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) { 439 LoadSU->isTwoAddress = true; 440 break; 441 } 442 } 443 if (TID->Flags & M_COMMUTABLE) 444 LoadSU->isCommutable = true; 445 446 TID = &TII->get(N->getTargetOpcode()); 447 for (unsigned i = 0; i != TID->numOperands; ++i) { 448 if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) { 449 NewSU->isTwoAddress = true; 450 break; 451 } 452 } 453 if (TID->Flags & M_COMMUTABLE) 454 NewSU->isCommutable = true; 455 456 // FIXME: Calculate height / depth and propagate the changes? 457 LoadSU->Depth = NewSU->Depth = SU->Depth; 458 LoadSU->Height = NewSU->Height = SU->Height; 459 ComputeLatency(LoadSU); 460 ComputeLatency(NewSU); 461 462 SUnit *ChainPred = NULL; 463 SmallVector<SDep, 4> ChainSuccs; 464 SmallVector<SDep, 4> LoadPreds; 465 SmallVector<SDep, 4> NodePreds; 466 SmallVector<SDep, 4> NodeSuccs; 467 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 468 I != E; ++I) { 469 if (I->isCtrl) 470 ChainPred = I->Dep; 471 else if (I->Dep->Node && I->Dep->Node->isOperand(LoadNode)) 472 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); 473 else 474 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); 475 } 476 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 477 I != E; ++I) { 478 if (I->isCtrl) 479 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, 480 I->isCtrl, I->isSpecial)); 481 else 482 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, 483 I->isCtrl, I->isSpecial)); 484 } 485 486 SU->removePred(ChainPred, true, false); 487 LoadSU->addPred(ChainPred, true, false); 488 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { 489 SDep *Pred = &LoadPreds[i]; 490 SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial); 491 LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial, 492 Pred->Reg, Pred->Cost); 493 } 494 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { 495 SDep *Pred = &NodePreds[i]; 496 SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial); 497 NewSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial, 498 Pred->Reg, Pred->Cost); 499 } 500 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { 501 SDep *Succ = &NodeSuccs[i]; 502 Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial); 503 Succ->Dep->addPred(NewSU, Succ->isCtrl, Succ->isSpecial, 504 Succ->Reg, Succ->Cost); 505 } 506 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { 507 SDep *Succ = &ChainSuccs[i]; 508 Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial); 509 Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial, 510 Succ->Reg, Succ->Cost); 511 } 512 NewSU->addPred(LoadSU, false, false); 513 514 AvailableQueue->addNode(LoadSU); 515 AvailableQueue->addNode(NewSU); 516 517 ++NumUnfolds; 518 519 if (NewSU->NumSuccsLeft == 0) { 520 NewSU->isAvailable = true; 521 return NewSU; 522 } else 523 SU = NewSU; 524 } 525 526 DOUT << "Duplicating SU # " << SU->NodeNum << "\n"; 527 NewSU = Clone(SU); 528 529 // New SUnit has the exact same predecessors. 530 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 531 I != E; ++I) 532 if (!I->isSpecial) { 533 NewSU->addPred(I->Dep, I->isCtrl, false, I->Reg, I->Cost); 534 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1); 535 } 536 537 // Only copy scheduled successors. Cut them from old node's successor 538 // list and move them over. 539 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps; 540 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 541 I != E; ++I) { 542 if (I->isSpecial) 543 continue; 544 if (I->Dep->isScheduled) { 545 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1); 546 I->Dep->addPred(NewSU, I->isCtrl, false, I->Reg, I->Cost); 547 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); 548 } 549 } 550 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { 551 SUnit *Succ = DelDeps[i].first; 552 bool isCtrl = DelDeps[i].second; 553 Succ->removePred(SU, isCtrl, false); 554 } 555 556 AvailableQueue->updateNode(SU); 557 AvailableQueue->addNode(NewSU); 558 559 ++NumDups; 560 return NewSU; 561} 562 563/// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies 564/// and move all scheduled successors of the given SUnit to the last copy. 565void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, 566 const TargetRegisterClass *DestRC, 567 const TargetRegisterClass *SrcRC, 568 SmallVector<SUnit*, 2> &Copies) { 569 SUnit *CopyFromSU = NewSUnit(NULL); 570 CopyFromSU->CopySrcRC = SrcRC; 571 CopyFromSU->CopyDstRC = DestRC; 572 CopyFromSU->Depth = SU->Depth; 573 CopyFromSU->Height = SU->Height; 574 575 SUnit *CopyToSU = NewSUnit(NULL); 576 CopyToSU->CopySrcRC = DestRC; 577 CopyToSU->CopyDstRC = SrcRC; 578 579 // Only copy scheduled successors. Cut them from old node's successor 580 // list and move them over. 581 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps; 582 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 583 I != E; ++I) { 584 if (I->isSpecial) 585 continue; 586 if (I->Dep->isScheduled) { 587 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1); 588 I->Dep->addPred(CopyToSU, I->isCtrl, false, I->Reg, I->Cost); 589 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); 590 } 591 } 592 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { 593 SUnit *Succ = DelDeps[i].first; 594 bool isCtrl = DelDeps[i].second; 595 Succ->removePred(SU, isCtrl, false); 596 } 597 598 CopyFromSU->addPred(SU, false, false, Reg, -1); 599 CopyToSU->addPred(CopyFromSU, false, false, Reg, 1); 600 601 AvailableQueue->updateNode(SU); 602 AvailableQueue->addNode(CopyFromSU); 603 AvailableQueue->addNode(CopyToSU); 604 Copies.push_back(CopyFromSU); 605 Copies.push_back(CopyToSU); 606 607 ++NumCCCopies; 608} 609 610/// getPhysicalRegisterVT - Returns the ValueType of the physical register 611/// definition of the specified node. 612/// FIXME: Move to SelectionDAG? 613static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, 614 const TargetInstrInfo *TII) { 615 const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode()); 616 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 617 unsigned NumRes = TID.numDefs; 618 for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) { 619 if (Reg == *ImpDef) 620 break; 621 ++NumRes; 622 } 623 return N->getValueType(NumRes); 624} 625 626/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay 627/// scheduling of the given node to satisfy live physical register dependencies. 628/// If the specific node is the last one that's available to schedule, do 629/// whatever is necessary (i.e. backtracking or cloning) to make it possible. 630bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, 631 SmallVector<unsigned, 4> &LRegs){ 632 if (LiveRegs.empty()) 633 return false; 634 635 SmallSet<unsigned, 4> RegAdded; 636 // If this node would clobber any "live" register, then it's not ready. 637 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 638 I != E; ++I) { 639 if (I->Cost < 0) { 640 unsigned Reg = I->Reg; 641 if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) { 642 if (RegAdded.insert(Reg)) 643 LRegs.push_back(Reg); 644 } 645 for (const unsigned *Alias = MRI->getAliasSet(Reg); 646 *Alias; ++Alias) 647 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { 648 if (RegAdded.insert(*Alias)) 649 LRegs.push_back(*Alias); 650 } 651 } 652 } 653 654 for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) { 655 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1]; 656 if (!Node || !Node->isTargetOpcode()) 657 continue; 658 const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode()); 659 if (!TID.ImplicitDefs) 660 continue; 661 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { 662 if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) { 663 if (RegAdded.insert(*Reg)) 664 LRegs.push_back(*Reg); 665 } 666 for (const unsigned *Alias = MRI->getAliasSet(*Reg); 667 *Alias; ++Alias) 668 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { 669 if (RegAdded.insert(*Alias)) 670 LRegs.push_back(*Alias); 671 } 672 } 673 } 674 return !LRegs.empty(); 675} 676 677 678/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up 679/// schedulers. 680void ScheduleDAGRRList::ListScheduleBottomUp() { 681 unsigned CurCycle = 0; 682 // Add root to Available queue. 683 SUnit *RootSU = SUnitMap[DAG.getRoot().Val].front(); 684 RootSU->isAvailable = true; 685 AvailableQueue->push(RootSU); 686 687 // While Available queue is not empty, grab the node with the highest 688 // priority. If it is not ready put it back. Schedule the node. 689 SmallVector<SUnit*, 4> NotReady; 690 while (!AvailableQueue->empty()) { 691 bool Delayed = false; 692 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap; 693 SUnit *CurSU = AvailableQueue->pop(); 694 while (CurSU) { 695 if (CurSU->CycleBound <= CurCycle) { 696 SmallVector<unsigned, 4> LRegs; 697 if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) 698 break; 699 Delayed = true; 700 LRegsMap.insert(std::make_pair(CurSU, LRegs)); 701 } 702 703 CurSU->isPending = true; // This SU is not in AvailableQueue right now. 704 NotReady.push_back(CurSU); 705 CurSU = AvailableQueue->pop(); 706 } 707 708 // All candidates are delayed due to live physical reg dependencies. 709 // Try backtracking, code duplication, or inserting cross class copies 710 // to resolve it. 711 if (Delayed && !CurSU) { 712 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 713 SUnit *TrySU = NotReady[i]; 714 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 715 716 // Try unscheduling up to the point where it's safe to schedule 717 // this node. 718 unsigned LiveCycle = CurCycle; 719 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) { 720 unsigned Reg = LRegs[j]; 721 unsigned LCycle = LiveRegCycles[Reg]; 722 LiveCycle = std::min(LiveCycle, LCycle); 723 } 724 SUnit *OldSU = Sequence[LiveCycle]; 725 if (!WillCreateCycle(TrySU, OldSU)) { 726 BacktrackBottomUp(TrySU, LiveCycle, CurCycle); 727 // Force the current node to be scheduled before the node that 728 // requires the physical reg dep. 729 if (OldSU->isAvailable) { 730 OldSU->isAvailable = false; 731 AvailableQueue->remove(OldSU); 732 } 733 TrySU->addPred(OldSU, true, true); 734 // If one or more successors has been unscheduled, then the current 735 // node is no longer avaialable. Schedule a successor that's now 736 // available instead. 737 if (!TrySU->isAvailable) 738 CurSU = AvailableQueue->pop(); 739 else { 740 CurSU = TrySU; 741 TrySU->isPending = false; 742 NotReady.erase(NotReady.begin()+i); 743 } 744 break; 745 } 746 } 747 748 if (!CurSU) { 749 // Can't backtrace. Try duplicating the nodes that produces these 750 // "expensive to copy" values to break the dependency. In case even 751 // that doesn't work, insert cross class copies. 752 SUnit *TrySU = NotReady[0]; 753 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 754 assert(LRegs.size() == 1 && "Can't handle this yet!"); 755 unsigned Reg = LRegs[0]; 756 SUnit *LRDef = LiveRegDefs[Reg]; 757 SUnit *NewDef = CopyAndMoveSuccessors(LRDef); 758 if (!NewDef) { 759 // Issue expensive cross register class copies. 760 MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); 761 const TargetRegisterClass *RC = 762 MRI->getPhysicalRegisterRegClass(VT, Reg); 763 const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC); 764 if (!DestRC) { 765 assert(false && "Don't know how to copy this physical register!"); 766 abort(); 767 } 768 SmallVector<SUnit*, 2> Copies; 769 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); 770 DOUT << "Adding an edge from SU # " << TrySU->NodeNum 771 << " to SU #" << Copies.front()->NodeNum << "\n"; 772 TrySU->addPred(Copies.front(), true, true); 773 NewDef = Copies.back(); 774 } 775 776 DOUT << "Adding an edge from SU # " << NewDef->NodeNum 777 << " to SU #" << TrySU->NodeNum << "\n"; 778 LiveRegDefs[Reg] = NewDef; 779 NewDef->addPred(TrySU, true, true); 780 TrySU->isAvailable = false; 781 CurSU = NewDef; 782 } 783 784 if (!CurSU) { 785 assert(false && "Unable to resolve live physical register dependencies!"); 786 abort(); 787 } 788 } 789 790 // Add the nodes that aren't ready back onto the available list. 791 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 792 NotReady[i]->isPending = false; 793 // May no longer be available due to backtracking. 794 if (NotReady[i]->isAvailable) 795 AvailableQueue->push(NotReady[i]); 796 } 797 NotReady.clear(); 798 799 if (!CurSU) 800 Sequence.push_back(0); 801 else { 802 ScheduleNodeBottomUp(CurSU, CurCycle); 803 Sequence.push_back(CurSU); 804 } 805 ++CurCycle; 806 } 807 808 // Add entry node last 809 if (DAG.getEntryNode().Val != DAG.getRoot().Val) { 810 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); 811 Sequence.push_back(Entry); 812 } 813 814 // Reverse the order if it is bottom up. 815 std::reverse(Sequence.begin(), Sequence.end()); 816 817 818#ifndef NDEBUG 819 // Verify that all SUnits were scheduled. 820 bool AnyNotSched = false; 821 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 822 if (SUnits[i].NumSuccsLeft != 0) { 823 if (!AnyNotSched) 824 cerr << "*** List scheduling failed! ***\n"; 825 SUnits[i].dump(&DAG); 826 cerr << "has not been scheduled!\n"; 827 AnyNotSched = true; 828 } 829 } 830 assert(!AnyNotSched); 831#endif 832} 833 834//===----------------------------------------------------------------------===// 835// Top-Down Scheduling 836//===----------------------------------------------------------------------===// 837 838/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to 839/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 840void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain, 841 unsigned CurCycle) { 842 // FIXME: the distance between two nodes is not always == the predecessor's 843 // latency. For example, the reader can very well read the register written 844 // by the predecessor later than the issue cycle. It also depends on the 845 // interrupt model (drain vs. freeze). 846 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency); 847 848 --SuccSU->NumPredsLeft; 849 850#ifndef NDEBUG 851 if (SuccSU->NumPredsLeft < 0) { 852 cerr << "*** List scheduling failed! ***\n"; 853 SuccSU->dump(&DAG); 854 cerr << " has been released too many times!\n"; 855 assert(0); 856 } 857#endif 858 859 if (SuccSU->NumPredsLeft == 0) { 860 SuccSU->isAvailable = true; 861 AvailableQueue->push(SuccSU); 862 } 863} 864 865 866/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending 867/// count of its successors. If a successor pending count is zero, add it to 868/// the Available queue. 869void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { 870 DOUT << "*** Scheduling [" << CurCycle << "]: "; 871 DEBUG(SU->dump(&DAG)); 872 SU->Cycle = CurCycle; 873 874 AvailableQueue->ScheduledNode(SU); 875 876 // Top down: release successors 877 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 878 I != E; ++I) 879 ReleaseSucc(I->Dep, I->isCtrl, CurCycle); 880 SU->isScheduled = true; 881} 882 883/// ListScheduleTopDown - The main loop of list scheduling for top-down 884/// schedulers. 885void ScheduleDAGRRList::ListScheduleTopDown() { 886 unsigned CurCycle = 0; 887 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); 888 889 // All leaves to Available queue. 890 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 891 // It is available if it has no predecessors. 892 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) { 893 AvailableQueue->push(&SUnits[i]); 894 SUnits[i].isAvailable = true; 895 } 896 } 897 898 // Emit the entry node first. 899 ScheduleNodeTopDown(Entry, CurCycle); 900 Sequence.push_back(Entry); 901 ++CurCycle; 902 903 // While Available queue is not empty, grab the node with the highest 904 // priority. If it is not ready put it back. Schedule the node. 905 std::vector<SUnit*> NotReady; 906 while (!AvailableQueue->empty()) { 907 SUnit *CurSU = AvailableQueue->pop(); 908 while (CurSU && CurSU->CycleBound > CurCycle) { 909 NotReady.push_back(CurSU); 910 CurSU = AvailableQueue->pop(); 911 } 912 913 // Add the nodes that aren't ready back onto the available list. 914 AvailableQueue->push_all(NotReady); 915 NotReady.clear(); 916 917 if (!CurSU) 918 Sequence.push_back(0); 919 else { 920 ScheduleNodeTopDown(CurSU, CurCycle); 921 Sequence.push_back(CurSU); 922 } 923 CurCycle++; 924 } 925 926 927#ifndef NDEBUG 928 // Verify that all SUnits were scheduled. 929 bool AnyNotSched = false; 930 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 931 if (!SUnits[i].isScheduled) { 932 if (!AnyNotSched) 933 cerr << "*** List scheduling failed! ***\n"; 934 SUnits[i].dump(&DAG); 935 cerr << "has not been scheduled!\n"; 936 AnyNotSched = true; 937 } 938 } 939 assert(!AnyNotSched); 940#endif 941} 942 943 944 945//===----------------------------------------------------------------------===// 946// RegReductionPriorityQueue Implementation 947//===----------------------------------------------------------------------===// 948// 949// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers 950// to reduce register pressure. 951// 952namespace { 953 template<class SF> 954 class RegReductionPriorityQueue; 955 956 /// Sorting functions for the Available queue. 957 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 958 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ; 959 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {} 960 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 961 962 bool operator()(const SUnit* left, const SUnit* right) const; 963 }; 964 965 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 966 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ; 967 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {} 968 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 969 970 bool operator()(const SUnit* left, const SUnit* right) const; 971 }; 972} // end anonymous namespace 973 974static inline bool isCopyFromLiveIn(const SUnit *SU) { 975 SDNode *N = SU->Node; 976 return N && N->getOpcode() == ISD::CopyFromReg && 977 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; 978} 979 980namespace { 981 template<class SF> 982 class VISIBILITY_HIDDEN RegReductionPriorityQueue 983 : public SchedulingPriorityQueue { 984 std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue; 985 986 public: 987 RegReductionPriorityQueue() : 988 Queue(SF(this)) {} 989 990 virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap, 991 std::vector<SUnit> &sunits) {} 992 993 virtual void addNode(const SUnit *SU) {} 994 995 virtual void updateNode(const SUnit *SU) {} 996 997 virtual void releaseState() {} 998 999 virtual unsigned getNodePriority(const SUnit *SU) const { 1000 return 0; 1001 } 1002 1003 unsigned size() const { return Queue.size(); } 1004 1005 bool empty() const { return Queue.empty(); } 1006 1007 void push(SUnit *U) { 1008 Queue.push(U); 1009 } 1010 void push_all(const std::vector<SUnit *> &Nodes) { 1011 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) 1012 Queue.push(Nodes[i]); 1013 } 1014 1015 SUnit *pop() { 1016 if (empty()) return NULL; 1017 SUnit *V = Queue.top(); 1018 Queue.pop(); 1019 return V; 1020 } 1021 1022 /// remove - This is a really inefficient way to remove a node from a 1023 /// priority queue. We should roll our own heap to make this better or 1024 /// something. 1025 void remove(SUnit *SU) { 1026 std::vector<SUnit*> Temp; 1027 1028 assert(!Queue.empty() && "Not in queue!"); 1029 while (Queue.top() != SU) { 1030 Temp.push_back(Queue.top()); 1031 Queue.pop(); 1032 assert(!Queue.empty() && "Not in queue!"); 1033 } 1034 1035 // Remove the node from the PQ. 1036 Queue.pop(); 1037 1038 // Add all the other nodes back. 1039 for (unsigned i = 0, e = Temp.size(); i != e; ++i) 1040 Queue.push(Temp[i]); 1041 } 1042 }; 1043 1044 template<class SF> 1045 class VISIBILITY_HIDDEN BURegReductionPriorityQueue 1046 : public RegReductionPriorityQueue<SF> { 1047 // SUnitMap SDNode to SUnit mapping (n -> n). 1048 DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap; 1049 1050 // SUnits - The SUnits for the current graph. 1051 const std::vector<SUnit> *SUnits; 1052 1053 // SethiUllmanNumbers - The SethiUllman number for each node. 1054 std::vector<unsigned> SethiUllmanNumbers; 1055 1056 const TargetInstrInfo *TII; 1057 public: 1058 explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii) 1059 : TII(tii) {} 1060 1061 void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap, 1062 std::vector<SUnit> &sunits) { 1063 SUnitMap = &sumap; 1064 SUnits = &sunits; 1065 // Add pseudo dependency edges for two-address nodes. 1066 AddPseudoTwoAddrDeps(); 1067 // Calculate node priorities. 1068 CalculateSethiUllmanNumbers(); 1069 } 1070 1071 void addNode(const SUnit *SU) { 1072 SethiUllmanNumbers.resize(SUnits->size(), 0); 1073 CalcNodeSethiUllmanNumber(SU); 1074 } 1075 1076 void updateNode(const SUnit *SU) { 1077 SethiUllmanNumbers[SU->NodeNum] = 0; 1078 CalcNodeSethiUllmanNumber(SU); 1079 } 1080 1081 void releaseState() { 1082 SUnits = 0; 1083 SethiUllmanNumbers.clear(); 1084 } 1085 1086 unsigned getNodePriority(const SUnit *SU) const { 1087 assert(SU->NodeNum < SethiUllmanNumbers.size()); 1088 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; 1089 if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU)) 1090 // CopyFromReg should be close to its def because it restricts 1091 // allocation choices. But if it is a livein then perhaps we want it 1092 // closer to its uses so it can be coalesced. 1093 return 0xffff; 1094 else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) 1095 // CopyToReg should be close to its uses to facilitate coalescing and 1096 // avoid spilling. 1097 return 0; 1098 else if (Opc == TargetInstrInfo::EXTRACT_SUBREG || 1099 Opc == TargetInstrInfo::INSERT_SUBREG) 1100 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to 1101 // facilitate coalescing. 1102 return 0; 1103 else if (SU->NumSuccs == 0) 1104 // If SU does not have a use, i.e. it doesn't produce a value that would 1105 // be consumed (e.g. store), then it terminates a chain of computation. 1106 // Give it a large SethiUllman number so it will be scheduled right 1107 // before its predecessors that it doesn't lengthen their live ranges. 1108 return 0xffff; 1109 else if (SU->NumPreds == 0) 1110 // If SU does not have a def, schedule it close to its uses because it 1111 // does not lengthen any live ranges. 1112 return 0; 1113 else 1114 return SethiUllmanNumbers[SU->NodeNum]; 1115 } 1116 1117 private: 1118 bool canClobber(SUnit *SU, SUnit *Op); 1119 void AddPseudoTwoAddrDeps(); 1120 void CalculateSethiUllmanNumbers(); 1121 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU); 1122 }; 1123 1124 1125 template<class SF> 1126 class VISIBILITY_HIDDEN TDRegReductionPriorityQueue 1127 : public RegReductionPriorityQueue<SF> { 1128 // SUnitMap SDNode to SUnit mapping (n -> n). 1129 DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap; 1130 1131 // SUnits - The SUnits for the current graph. 1132 const std::vector<SUnit> *SUnits; 1133 1134 // SethiUllmanNumbers - The SethiUllman number for each node. 1135 std::vector<unsigned> SethiUllmanNumbers; 1136 1137 public: 1138 TDRegReductionPriorityQueue() {} 1139 1140 void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap, 1141 std::vector<SUnit> &sunits) { 1142 SUnitMap = &sumap; 1143 SUnits = &sunits; 1144 // Calculate node priorities. 1145 CalculateSethiUllmanNumbers(); 1146 } 1147 1148 void addNode(const SUnit *SU) { 1149 SethiUllmanNumbers.resize(SUnits->size(), 0); 1150 CalcNodeSethiUllmanNumber(SU); 1151 } 1152 1153 void updateNode(const SUnit *SU) { 1154 SethiUllmanNumbers[SU->NodeNum] = 0; 1155 CalcNodeSethiUllmanNumber(SU); 1156 } 1157 1158 void releaseState() { 1159 SUnits = 0; 1160 SethiUllmanNumbers.clear(); 1161 } 1162 1163 unsigned getNodePriority(const SUnit *SU) const { 1164 assert(SU->NodeNum < SethiUllmanNumbers.size()); 1165 return SethiUllmanNumbers[SU->NodeNum]; 1166 } 1167 1168 private: 1169 void CalculateSethiUllmanNumbers(); 1170 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU); 1171 }; 1172} 1173 1174/// closestSucc - Returns the scheduled cycle of the successor which is 1175/// closet to the current cycle. 1176static unsigned closestSucc(const SUnit *SU) { 1177 unsigned MaxCycle = 0; 1178 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1179 I != E; ++I) { 1180 unsigned Cycle = I->Dep->Cycle; 1181 // If there are bunch of CopyToRegs stacked up, they should be considered 1182 // to be at the same position. 1183 if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg) 1184 Cycle = closestSucc(I->Dep)+1; 1185 if (Cycle > MaxCycle) 1186 MaxCycle = Cycle; 1187 } 1188 return MaxCycle; 1189} 1190 1191// Bottom up 1192bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1193 // There used to be a special tie breaker here that looked for 1194 // two-address instructions and preferred the instruction with a 1195 // def&use operand. The special case triggered diagnostics when 1196 // _GLIBCXX_DEBUG was enabled because it broke the strict weak 1197 // ordering that priority_queue requires. It didn't help much anyway 1198 // because AddPseudoTwoAddrDeps already covers many of the cases 1199 // where it would have applied. In addition, it's counter-intuitive 1200 // that a tie breaker would be the first thing attempted. There's a 1201 // "real" tie breaker below that is the operation of last resort. 1202 // The fact that the "special tie breaker" would trigger when there 1203 // wasn't otherwise a tie is what broke the strict weak ordering 1204 // constraint. 1205 1206 unsigned LPriority = SPQ->getNodePriority(left); 1207 unsigned RPriority = SPQ->getNodePriority(right); 1208 if (LPriority > RPriority) 1209 return true; 1210 else if (LPriority == RPriority) { 1211 // Try schedule def + use closer when Sethi-Ullman numbers are the same. 1212 // e.g. 1213 // t1 = op t2, c1 1214 // t3 = op t4, c2 1215 // 1216 // and the following instructions are both ready. 1217 // t2 = op c3 1218 // t4 = op c4 1219 // 1220 // Then schedule t2 = op first. 1221 // i.e. 1222 // t4 = op c4 1223 // t2 = op c3 1224 // t1 = op t2, c1 1225 // t3 = op t4, c2 1226 // 1227 // This creates more short live intervals. 1228 unsigned LDist = closestSucc(left); 1229 unsigned RDist = closestSucc(right); 1230 if (LDist < RDist) 1231 return true; 1232 else if (LDist == RDist) { 1233 if (left->Height > right->Height) 1234 return true; 1235 else if (left->Height == right->Height) 1236 if (left->Depth < right->Depth) 1237 return true; 1238 else if (left->Depth == right->Depth) 1239 if (left->CycleBound > right->CycleBound) 1240 return true; 1241 } 1242 } 1243 return false; 1244} 1245 1246template<class SF> 1247bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) { 1248 if (SU->isTwoAddress) { 1249 unsigned Opc = SU->Node->getTargetOpcode(); 1250 unsigned NumRes = TII->getNumDefs(Opc); 1251 unsigned NumOps = ScheduleDAG::CountOperands(SU->Node); 1252 for (unsigned i = 0; i != NumOps; ++i) { 1253 if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) { 1254 SDNode *DU = SU->Node->getOperand(i).Val; 1255 if (Op == (*SUnitMap)[DU][SU->InstanceNo]) 1256 return true; 1257 } 1258 } 1259 } 1260 return false; 1261} 1262 1263 1264/// hasCopyToRegUse - Return true if SU has a value successor that is a 1265/// CopyToReg node. 1266static bool hasCopyToRegUse(SUnit *SU) { 1267 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1268 I != E; ++I) { 1269 if (I->isCtrl) continue; 1270 SUnit *SuccSU = I->Dep; 1271 if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg) 1272 return true; 1273 } 1274 return false; 1275} 1276 1277/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses 1278/// it as a def&use operand. Add a pseudo control edge from it to the other 1279/// node (if it won't create a cycle) so the two-address one will be scheduled 1280/// first (lower in the schedule). If both nodes are two-address, favor the 1281/// one that has a CopyToReg use (more likely to be a loop induction update). 1282/// If both are two-address, but one is commutable while the other is not 1283/// commutable, favor the one that's not commutable. 1284template<class SF> 1285void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() { 1286 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { 1287 SUnit *SU = (SUnit *)&((*SUnits)[i]); 1288 if (!SU->isTwoAddress) 1289 continue; 1290 1291 SDNode *Node = SU->Node; 1292 if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0) 1293 continue; 1294 1295 unsigned Opc = Node->getTargetOpcode(); 1296 unsigned NumRes = TII->getNumDefs(Opc); 1297 unsigned NumOps = ScheduleDAG::CountOperands(Node); 1298 for (unsigned j = 0; j != NumOps; ++j) { 1299 if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) { 1300 SDNode *DU = SU->Node->getOperand(j).Val; 1301 SUnit *DUSU = (*SUnitMap)[DU][SU->InstanceNo]; 1302 if (!DUSU) continue; 1303 for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end(); 1304 I != E; ++I) { 1305 if (I->isCtrl) continue; 1306 SUnit *SuccSU = I->Dep; 1307 // Don't constrain nodes with implicit defs. It can create cycles 1308 // plus it may increase register pressures. 1309 if (SuccSU == SU || SuccSU->hasPhysRegDefs) 1310 continue; 1311 // Be conservative. Ignore if nodes aren't at roughly the same 1312 // depth and height. 1313 if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1) 1314 continue; 1315 if (SuccSU->Depth > SU->Depth && (SuccSU->Depth - SU->Depth) > 1) 1316 continue; 1317 if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode()) 1318 continue; 1319 // Don't constraint extract_subreg / insert_subreg these may be 1320 // coalesced away. We don't them close to their uses. 1321 unsigned SuccOpc = SuccSU->Node->getTargetOpcode(); 1322 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || 1323 SuccOpc == TargetInstrInfo::INSERT_SUBREG) 1324 continue; 1325 if ((!canClobber(SuccSU, DUSU) || 1326 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) || 1327 (!SU->isCommutable && SuccSU->isCommutable)) && 1328 !isReachable(SuccSU, SU)) { 1329 DOUT << "Adding an edge from SU # " << SU->NodeNum 1330 << " to SU #" << SuccSU->NodeNum << "\n"; 1331 SU->addPred(SuccSU, true, true); 1332 } 1333 } 1334 } 1335 } 1336 } 1337} 1338 1339/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. 1340/// Smaller number is the higher priority. 1341template<class SF> 1342unsigned BURegReductionPriorityQueue<SF>:: 1343CalcNodeSethiUllmanNumber(const SUnit *SU) { 1344 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; 1345 if (SethiUllmanNumber != 0) 1346 return SethiUllmanNumber; 1347 1348 unsigned Extra = 0; 1349 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1350 I != E; ++I) { 1351 if (I->isCtrl) continue; // ignore chain preds 1352 SUnit *PredSU = I->Dep; 1353 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU); 1354 if (PredSethiUllman > SethiUllmanNumber) { 1355 SethiUllmanNumber = PredSethiUllman; 1356 Extra = 0; 1357 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) 1358 ++Extra; 1359 } 1360 1361 SethiUllmanNumber += Extra; 1362 1363 if (SethiUllmanNumber == 0) 1364 SethiUllmanNumber = 1; 1365 1366 return SethiUllmanNumber; 1367} 1368 1369/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1370/// scheduling units. 1371template<class SF> 1372void BURegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() { 1373 SethiUllmanNumbers.assign(SUnits->size(), 0); 1374 1375 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1376 CalcNodeSethiUllmanNumber(&(*SUnits)[i]); 1377} 1378 1379static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) { 1380 unsigned Sum = 0; 1381 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1382 I != E; ++I) { 1383 SUnit *SuccSU = I->Dep; 1384 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(), 1385 EE = SuccSU->Preds.end(); II != EE; ++II) { 1386 SUnit *PredSU = II->Dep; 1387 if (!PredSU->isScheduled) 1388 ++Sum; 1389 } 1390 } 1391 1392 return Sum; 1393} 1394 1395 1396// Top down 1397bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1398 unsigned LPriority = SPQ->getNodePriority(left); 1399 unsigned RPriority = SPQ->getNodePriority(right); 1400 bool LIsTarget = left->Node && left->Node->isTargetOpcode(); 1401 bool RIsTarget = right->Node && right->Node->isTargetOpcode(); 1402 bool LIsFloater = LIsTarget && left->NumPreds == 0; 1403 bool RIsFloater = RIsTarget && right->NumPreds == 0; 1404 unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0; 1405 unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0; 1406 1407 if (left->NumSuccs == 0 && right->NumSuccs != 0) 1408 return false; 1409 else if (left->NumSuccs != 0 && right->NumSuccs == 0) 1410 return true; 1411 1412 // Special tie breaker: if two nodes share a operand, the one that use it 1413 // as a def&use operand is preferred. 1414 if (LIsTarget && RIsTarget) { 1415 if (left->isTwoAddress && !right->isTwoAddress) { 1416 SDNode *DUNode = left->Node->getOperand(0).Val; 1417 if (DUNode->isOperand(right->Node)) 1418 RBonus += 2; 1419 } 1420 if (!left->isTwoAddress && right->isTwoAddress) { 1421 SDNode *DUNode = right->Node->getOperand(0).Val; 1422 if (DUNode->isOperand(left->Node)) 1423 LBonus += 2; 1424 } 1425 } 1426 if (LIsFloater) 1427 LBonus -= 2; 1428 if (RIsFloater) 1429 RBonus -= 2; 1430 if (left->NumSuccs == 1) 1431 LBonus += 2; 1432 if (right->NumSuccs == 1) 1433 RBonus += 2; 1434 1435 if (LPriority+LBonus < RPriority+RBonus) 1436 return true; 1437 else if (LPriority == RPriority) 1438 if (left->Depth < right->Depth) 1439 return true; 1440 else if (left->Depth == right->Depth) 1441 if (left->NumSuccsLeft > right->NumSuccsLeft) 1442 return true; 1443 else if (left->NumSuccsLeft == right->NumSuccsLeft) 1444 if (left->CycleBound > right->CycleBound) 1445 return true; 1446 return false; 1447} 1448 1449/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. 1450/// Smaller number is the higher priority. 1451template<class SF> 1452unsigned TDRegReductionPriorityQueue<SF>:: 1453CalcNodeSethiUllmanNumber(const SUnit *SU) { 1454 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; 1455 if (SethiUllmanNumber != 0) 1456 return SethiUllmanNumber; 1457 1458 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; 1459 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) 1460 SethiUllmanNumber = 0xffff; 1461 else if (SU->NumSuccsLeft == 0) 1462 // If SU does not have a use, i.e. it doesn't produce a value that would 1463 // be consumed (e.g. store), then it terminates a chain of computation. 1464 // Give it a small SethiUllman number so it will be scheduled right before 1465 // its predecessors that it doesn't lengthen their live ranges. 1466 SethiUllmanNumber = 0; 1467 else if (SU->NumPredsLeft == 0 && 1468 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU))) 1469 SethiUllmanNumber = 0xffff; 1470 else { 1471 int Extra = 0; 1472 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1473 I != E; ++I) { 1474 if (I->isCtrl) continue; // ignore chain preds 1475 SUnit *PredSU = I->Dep; 1476 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU); 1477 if (PredSethiUllman > SethiUllmanNumber) { 1478 SethiUllmanNumber = PredSethiUllman; 1479 Extra = 0; 1480 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) 1481 ++Extra; 1482 } 1483 1484 SethiUllmanNumber += Extra; 1485 } 1486 1487 return SethiUllmanNumber; 1488} 1489 1490/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1491/// scheduling units. 1492template<class SF> 1493void TDRegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() { 1494 SethiUllmanNumbers.assign(SUnits->size(), 0); 1495 1496 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1497 CalcNodeSethiUllmanNumber(&(*SUnits)[i]); 1498} 1499 1500//===----------------------------------------------------------------------===// 1501// Public Constructor Functions 1502//===----------------------------------------------------------------------===// 1503 1504llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, 1505 SelectionDAG *DAG, 1506 MachineBasicBlock *BB) { 1507 const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); 1508 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, 1509 new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII)); 1510} 1511 1512llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, 1513 SelectionDAG *DAG, 1514 MachineBasicBlock *BB) { 1515 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, 1516 new TDRegReductionPriorityQueue<td_ls_rr_sort>()); 1517} 1518 1519