ScheduleDAGRRList.cpp revision 8181bd1f95ae9994edb390dd9acd0b7b12375219
1//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements bottom-up and top-down register pressure reduction list 11// schedulers, using standard algorithms. The basic approach uses a priority 12// queue of available nodes to schedule. One at a time, nodes are taken from 13// the priority queue (thus in priority order), checked for legality to 14// schedule, and emitted if legal. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "pre-RA-sched" 19#include "llvm/CodeGen/ScheduleDAG.h" 20#include "llvm/CodeGen/SchedulerRegistry.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/Compiler.h" 27#include "llvm/ADT/BitVector.h" 28#include "llvm/ADT/PriorityQueue.h" 29#include "llvm/ADT/SmallPtrSet.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/ADT/STLExtras.h" 33#include <climits> 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37STATISTIC(NumBacktracks, "Number of times scheduler backtracked"); 38STATISTIC(NumUnfolds, "Number of nodes unfolded"); 39STATISTIC(NumDups, "Number of duplicated nodes"); 40STATISTIC(NumCCCopies, "Number of cross class copies"); 41 42static RegisterScheduler 43 burrListDAGScheduler("list-burr", 44 " Bottom-up register reduction list scheduling", 45 createBURRListDAGScheduler); 46static RegisterScheduler 47 tdrListrDAGScheduler("list-tdrr", 48 " Top-down register reduction list scheduling", 49 createTDRRListDAGScheduler); 50 51namespace { 52//===----------------------------------------------------------------------===// 53/// ScheduleDAGRRList - The actual register reduction list scheduler 54/// implementation. This supports both top-down and bottom-up scheduling. 55/// 56class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG { 57private: 58 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if 59 /// it is top-down. 60 bool isBottomUp; 61 62 /// Fast - True if we are performing fast scheduling. 63 /// 64 bool Fast; 65 66 /// AvailableQueue - The priority queue to use for the available SUnits. 67 SchedulingPriorityQueue *AvailableQueue; 68 69 /// LiveRegs / LiveRegDefs - A set of physical registers and their definition 70 /// that are "live". These nodes must be scheduled before any other nodes that 71 /// modifies the registers can be scheduled. 72 SmallSet<unsigned, 4> LiveRegs; 73 std::vector<SUnit*> LiveRegDefs; 74 std::vector<unsigned> LiveRegCycles; 75 76public: 77 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb, 78 const TargetMachine &tm, bool isbottomup, bool f, 79 SchedulingPriorityQueue *availqueue) 80 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), Fast(f), 81 AvailableQueue(availqueue) { 82 } 83 84 ~ScheduleDAGRRList() { 85 delete AvailableQueue; 86 } 87 88 void Schedule(); 89 90 /// IsReachable - Checks if SU is reachable from TargetSU. 91 bool IsReachable(SUnit *SU, SUnit *TargetSU); 92 93 /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will 94 /// create a cycle. 95 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 96 97 /// AddPred - This adds the specified node X as a predecessor of 98 /// the current node Y if not already. 99 /// This returns true if this is a new predecessor. 100 /// Updates the topological ordering if required. 101 bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, 102 unsigned PhyReg = 0, int Cost = 1); 103 104 /// RemovePred - This removes the specified node N from the predecessors of 105 /// the current node M. Updates the topological ordering if required. 106 bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial); 107 108private: 109 void ReleasePred(SUnit*, bool, unsigned); 110 void ReleaseSucc(SUnit*, bool isChain, unsigned); 111 void CapturePred(SUnit*, SUnit*, bool); 112 void ScheduleNodeBottomUp(SUnit*, unsigned); 113 void ScheduleNodeTopDown(SUnit*, unsigned); 114 void UnscheduleNodeBottomUp(SUnit*); 115 void BacktrackBottomUp(SUnit*, unsigned, unsigned&); 116 SUnit *CopyAndMoveSuccessors(SUnit*); 117 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned, 118 const TargetRegisterClass*, 119 const TargetRegisterClass*, 120 SmallVector<SUnit*, 2>&); 121 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&); 122 void ListScheduleTopDown(); 123 void ListScheduleBottomUp(); 124 void CommuteNodesToReducePressure(); 125 126 127 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it. 128 /// Updates the topological ordering if required. 129 SUnit *CreateNewSUnit(SDNode *N) { 130 SUnit *NewNode = NewSUnit(N); 131 // Update the topological ordering. 132 if (NewNode->NodeNum >= Node2Index.size()) 133 InitDAGTopologicalSorting(); 134 return NewNode; 135 } 136 137 /// CreateClone - Creates a new SUnit from an existing one. 138 /// Updates the topological ordering if required. 139 SUnit *CreateClone(SUnit *N) { 140 SUnit *NewNode = Clone(N); 141 // Update the topological ordering. 142 if (NewNode->NodeNum >= Node2Index.size()) 143 InitDAGTopologicalSorting(); 144 return NewNode; 145 } 146 147 /// Functions for preserving the topological ordering 148 /// even after dynamic insertions of new edges. 149 /// This allows a very fast implementation of IsReachable. 150 151 /// InitDAGTopologicalSorting - create the initial topological 152 /// ordering from the DAG to be scheduled. 153 void InitDAGTopologicalSorting(); 154 155 /// DFS - make a DFS traversal and mark all nodes affected by the 156 /// edge insertion. These nodes will later get new topological indexes 157 /// by means of the Shift method. 158 void DFS(SUnit *SU, int UpperBound, bool& HasLoop); 159 160 /// Shift - reassign topological indexes for the nodes in the DAG 161 /// to preserve the topological ordering. 162 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 163 164 /// Allocate - assign the topological index to the node n. 165 void Allocate(int n, int index); 166 167 /// Index2Node - Maps topological index to the node number. 168 std::vector<int> Index2Node; 169 /// Node2Index - Maps the node number to its topological index. 170 std::vector<int> Node2Index; 171 /// Visited - a set of nodes visited during a DFS traversal. 172 BitVector Visited; 173}; 174} // end anonymous namespace 175 176 177/// Schedule - Schedule the DAG using list scheduling. 178void ScheduleDAGRRList::Schedule() { 179 DOUT << "********** List Scheduling **********\n"; 180 181 LiveRegDefs.resize(TRI->getNumRegs(), NULL); 182 LiveRegCycles.resize(TRI->getNumRegs(), 0); 183 184 // Build scheduling units. 185 BuildSchedUnits(); 186 187 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) 188 SUnits[su].dumpAll(&DAG)); 189 if (!Fast) { 190 CalculateDepths(); 191 CalculateHeights(); 192 } 193 InitDAGTopologicalSorting(); 194 195 AvailableQueue->initNodes(SUnits); 196 197 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate. 198 if (isBottomUp) 199 ListScheduleBottomUp(); 200 else 201 ListScheduleTopDown(); 202 203 AvailableQueue->releaseState(); 204 205 if (!Fast) 206 CommuteNodesToReducePressure(); 207} 208 209/// CommuteNodesToReducePressure - If a node is two-address and commutable, and 210/// it is not the last use of its first operand, add it to the CommuteSet if 211/// possible. It will be commuted when it is translated to a MI. 212void ScheduleDAGRRList::CommuteNodesToReducePressure() { 213 SmallPtrSet<SUnit*, 4> OperandSeen; 214 for (unsigned i = Sequence.size(); i != 0; ) { 215 --i; 216 SUnit *SU = Sequence[i]; 217 if (!SU || !SU->Node) continue; 218 if (SU->isCommutable) { 219 unsigned Opc = SU->Node->getMachineOpcode(); 220 const TargetInstrDesc &TID = TII->get(Opc); 221 unsigned NumRes = TID.getNumDefs(); 222 unsigned NumOps = TID.getNumOperands() - NumRes; 223 for (unsigned j = 0; j != NumOps; ++j) { 224 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) 225 continue; 226 227 SDNode *OpN = SU->Node->getOperand(j).Val; 228 SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; 229 if (OpSU && OperandSeen.count(OpSU) == 1) { 230 // Ok, so SU is not the last use of OpSU, but SU is two-address so 231 // it will clobber OpSU. Try to commute SU if no other source operands 232 // are live below. 233 bool DoCommute = true; 234 for (unsigned k = 0; k < NumOps; ++k) { 235 if (k != j) { 236 OpN = SU->Node->getOperand(k).Val; 237 OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; 238 if (OpSU && OperandSeen.count(OpSU) == 1) { 239 DoCommute = false; 240 break; 241 } 242 } 243 } 244 if (DoCommute) 245 CommuteSet.insert(SU->Node); 246 } 247 248 // Only look at the first use&def node for now. 249 break; 250 } 251 } 252 253 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 254 I != E; ++I) { 255 if (!I->isCtrl) 256 OperandSeen.insert(I->Dep->OrigNode); 257 } 258 } 259} 260 261//===----------------------------------------------------------------------===// 262// Bottom-Up Scheduling 263//===----------------------------------------------------------------------===// 264 265/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to 266/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 267void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, 268 unsigned CurCycle) { 269 // FIXME: the distance between two nodes is not always == the predecessor's 270 // latency. For example, the reader can very well read the register written 271 // by the predecessor later than the issue cycle. It also depends on the 272 // interrupt model (drain vs. freeze). 273 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency); 274 275 --PredSU->NumSuccsLeft; 276 277#ifndef NDEBUG 278 if (PredSU->NumSuccsLeft < 0) { 279 cerr << "*** List scheduling failed! ***\n"; 280 PredSU->dump(&DAG); 281 cerr << " has been released too many times!\n"; 282 assert(0); 283 } 284#endif 285 286 if (PredSU->NumSuccsLeft == 0) { 287 PredSU->isAvailable = true; 288 AvailableQueue->push(PredSU); 289 } 290} 291 292/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending 293/// count of its predecessors. If a predecessor pending count is zero, add it to 294/// the Available queue. 295void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { 296 DOUT << "*** Scheduling [" << CurCycle << "]: "; 297 DEBUG(SU->dump(&DAG)); 298 SU->Cycle = CurCycle; 299 300 AvailableQueue->ScheduledNode(SU); 301 302 // Bottom up: release predecessors 303 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 304 I != E; ++I) { 305 ReleasePred(I->Dep, I->isCtrl, CurCycle); 306 if (I->Cost < 0) { 307 // This is a physical register dependency and it's impossible or 308 // expensive to copy the register. Make sure nothing that can 309 // clobber the register is scheduled between the predecessor and 310 // this node. 311 if (LiveRegs.insert(I->Reg)) { 312 LiveRegDefs[I->Reg] = I->Dep; 313 LiveRegCycles[I->Reg] = CurCycle; 314 } 315 } 316 } 317 318 // Release all the implicit physical register defs that are live. 319 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 320 I != E; ++I) { 321 if (I->Cost < 0) { 322 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) { 323 LiveRegs.erase(I->Reg); 324 assert(LiveRegDefs[I->Reg] == SU && 325 "Physical register dependency violated?"); 326 LiveRegDefs[I->Reg] = NULL; 327 LiveRegCycles[I->Reg] = 0; 328 } 329 } 330 } 331 332 SU->isScheduled = true; 333} 334 335/// CapturePred - This does the opposite of ReleasePred. Since SU is being 336/// unscheduled, incrcease the succ left count of its predecessors. Remove 337/// them from AvailableQueue if necessary. 338void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { 339 unsigned CycleBound = 0; 340 for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end(); 341 I != E; ++I) { 342 if (I->Dep == SU) 343 continue; 344 CycleBound = std::max(CycleBound, 345 I->Dep->Cycle + PredSU->Latency); 346 } 347 348 if (PredSU->isAvailable) { 349 PredSU->isAvailable = false; 350 if (!PredSU->isPending) 351 AvailableQueue->remove(PredSU); 352 } 353 354 PredSU->CycleBound = CycleBound; 355 ++PredSU->NumSuccsLeft; 356} 357 358/// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and 359/// its predecessor states to reflect the change. 360void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { 361 DOUT << "*** Unscheduling [" << SU->Cycle << "]: "; 362 DEBUG(SU->dump(&DAG)); 363 364 AvailableQueue->UnscheduledNode(SU); 365 366 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 367 I != E; ++I) { 368 CapturePred(I->Dep, SU, I->isCtrl); 369 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) { 370 LiveRegs.erase(I->Reg); 371 assert(LiveRegDefs[I->Reg] == I->Dep && 372 "Physical register dependency violated?"); 373 LiveRegDefs[I->Reg] = NULL; 374 LiveRegCycles[I->Reg] = 0; 375 } 376 } 377 378 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 379 I != E; ++I) { 380 if (I->Cost < 0) { 381 if (LiveRegs.insert(I->Reg)) { 382 assert(!LiveRegDefs[I->Reg] && 383 "Physical register dependency violated?"); 384 LiveRegDefs[I->Reg] = SU; 385 } 386 if (I->Dep->Cycle < LiveRegCycles[I->Reg]) 387 LiveRegCycles[I->Reg] = I->Dep->Cycle; 388 } 389 } 390 391 SU->Cycle = 0; 392 SU->isScheduled = false; 393 SU->isAvailable = true; 394 AvailableQueue->push(SU); 395} 396 397/// IsReachable - Checks if SU is reachable from TargetSU. 398bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) { 399 // If insertion of the edge SU->TargetSU would create a cycle 400 // then there is a path from TargetSU to SU. 401 int UpperBound, LowerBound; 402 LowerBound = Node2Index[TargetSU->NodeNum]; 403 UpperBound = Node2Index[SU->NodeNum]; 404 bool HasLoop = false; 405 // Is Ord(TargetSU) < Ord(SU) ? 406 if (LowerBound < UpperBound) { 407 Visited.reset(); 408 // There may be a path from TargetSU to SU. Check for it. 409 DFS(TargetSU, UpperBound, HasLoop); 410 } 411 return HasLoop; 412} 413 414/// Allocate - assign the topological index to the node n. 415inline void ScheduleDAGRRList::Allocate(int n, int index) { 416 Node2Index[n] = index; 417 Index2Node[index] = n; 418} 419 420/// InitDAGTopologicalSorting - create the initial topological 421/// ordering from the DAG to be scheduled. 422 423/// The idea of the algorithm is taken from 424/// "Online algorithms for managing the topological order of 425/// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly 426/// This is the MNR algorithm, which was first introduced by 427/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in 428/// "Maintaining a topological order under edge insertions". 429/// 430/// Short description of the algorithm: 431/// 432/// Topological ordering, ord, of a DAG maps each node to a topological 433/// index so that for all edges X->Y it is the case that ord(X) < ord(Y). 434/// 435/// This means that if there is a path from the node X to the node Z, 436/// then ord(X) < ord(Z). 437/// 438/// This property can be used to check for reachability of nodes: 439/// if Z is reachable from X, then an insertion of the edge Z->X would 440/// create a cycle. 441/// 442/// The algorithm first computes a topological ordering for the DAG by 443/// initializing the Index2Node and Node2Index arrays and then tries to keep 444/// the ordering up-to-date after edge insertions by reordering the DAG. 445/// 446/// On insertion of the edge X->Y, the algorithm first marks by calling DFS 447/// the nodes reachable from Y, and then shifts them using Shift to lie 448/// immediately after X in Index2Node. 449void ScheduleDAGRRList::InitDAGTopologicalSorting() { 450 unsigned DAGSize = SUnits.size(); 451 std::vector<unsigned> InDegree(DAGSize); 452 std::vector<SUnit*> WorkList; 453 WorkList.reserve(DAGSize); 454 std::vector<SUnit*> TopOrder; 455 TopOrder.reserve(DAGSize); 456 457 // Initialize the data structures. 458 for (unsigned i = 0, e = DAGSize; i != e; ++i) { 459 SUnit *SU = &SUnits[i]; 460 int NodeNum = SU->NodeNum; 461 unsigned Degree = SU->Succs.size(); 462 InDegree[NodeNum] = Degree; 463 464 // Is it a node without dependencies? 465 if (Degree == 0) { 466 assert(SU->Succs.empty() && "SUnit should have no successors"); 467 // Collect leaf nodes. 468 WorkList.push_back(SU); 469 } 470 } 471 472 while (!WorkList.empty()) { 473 SUnit *SU = WorkList.back(); 474 WorkList.pop_back(); 475 TopOrder.push_back(SU); 476 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 477 I != E; ++I) { 478 SUnit *SU = I->Dep; 479 if (!--InDegree[SU->NodeNum]) 480 // If all dependencies of the node are processed already, 481 // then the node can be computed now. 482 WorkList.push_back(SU); 483 } 484 } 485 486 // Second pass, assign the actual topological order as node ids. 487 int Id = 0; 488 489 Index2Node.clear(); 490 Node2Index.clear(); 491 Index2Node.resize(DAGSize); 492 Node2Index.resize(DAGSize); 493 Visited.resize(DAGSize); 494 495 for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(), 496 TE = TopOrder.rend();TI != TE; ++TI) { 497 Allocate((*TI)->NodeNum, Id); 498 Id++; 499 } 500 501#ifndef NDEBUG 502 // Check correctness of the ordering 503 for (unsigned i = 0, e = DAGSize; i != e; ++i) { 504 SUnit *SU = &SUnits[i]; 505 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 506 I != E; ++I) { 507 assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && 508 "Wrong topological sorting"); 509 } 510 } 511#endif 512} 513 514/// AddPred - adds an edge from SUnit X to SUnit Y. 515/// Updates the topological ordering if required. 516bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, 517 unsigned PhyReg, int Cost) { 518 int UpperBound, LowerBound; 519 LowerBound = Node2Index[Y->NodeNum]; 520 UpperBound = Node2Index[X->NodeNum]; 521 bool HasLoop = false; 522 // Is Ord(X) < Ord(Y) ? 523 if (LowerBound < UpperBound) { 524 // Update the topological order. 525 Visited.reset(); 526 DFS(Y, UpperBound, HasLoop); 527 assert(!HasLoop && "Inserted edge creates a loop!"); 528 // Recompute topological indexes. 529 Shift(Visited, LowerBound, UpperBound); 530 } 531 // Now really insert the edge. 532 return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost); 533} 534 535/// RemovePred - This removes the specified node N from the predecessors of 536/// the current node M. Updates the topological ordering if required. 537bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N, 538 bool isCtrl, bool isSpecial) { 539 // InitDAGTopologicalSorting(); 540 return M->removePred(N, isCtrl, isSpecial); 541} 542 543/// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark 544/// all nodes affected by the edge insertion. These nodes will later get new 545/// topological indexes by means of the Shift method. 546void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { 547 std::vector<SUnit*> WorkList; 548 WorkList.reserve(SUnits.size()); 549 550 WorkList.push_back(SU); 551 while (!WorkList.empty()) { 552 SU = WorkList.back(); 553 WorkList.pop_back(); 554 Visited.set(SU->NodeNum); 555 for (int I = SU->Succs.size()-1; I >= 0; --I) { 556 int s = SU->Succs[I].Dep->NodeNum; 557 if (Node2Index[s] == UpperBound) { 558 HasLoop = true; 559 return; 560 } 561 // Visit successors if not already and in affected region. 562 if (!Visited.test(s) && Node2Index[s] < UpperBound) { 563 WorkList.push_back(SU->Succs[I].Dep); 564 } 565 } 566 } 567} 568 569/// Shift - Renumber the nodes so that the topological ordering is 570/// preserved. 571void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound, 572 int UpperBound) { 573 std::vector<int> L; 574 int shift = 0; 575 int i; 576 577 for (i = LowerBound; i <= UpperBound; ++i) { 578 // w is node at topological index i. 579 int w = Index2Node[i]; 580 if (Visited.test(w)) { 581 // Unmark. 582 Visited.reset(w); 583 L.push_back(w); 584 shift = shift + 1; 585 } else { 586 Allocate(w, i - shift); 587 } 588 } 589 590 for (unsigned j = 0; j < L.size(); ++j) { 591 Allocate(L[j], i - shift); 592 i = i + 1; 593 } 594} 595 596 597/// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 598/// create a cycle. 599bool ScheduleDAGRRList::WillCreateCycle(SUnit *SU, SUnit *TargetSU) { 600 if (IsReachable(TargetSU, SU)) 601 return true; 602 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 603 I != E; ++I) 604 if (I->Cost < 0 && IsReachable(TargetSU, I->Dep)) 605 return true; 606 return false; 607} 608 609/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in 610/// BTCycle in order to schedule a specific node. Returns the last unscheduled 611/// SUnit. Also returns if a successor is unscheduled in the process. 612void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle, 613 unsigned &CurCycle) { 614 SUnit *OldSU = NULL; 615 while (CurCycle > BtCycle) { 616 OldSU = Sequence.back(); 617 Sequence.pop_back(); 618 if (SU->isSucc(OldSU)) 619 // Don't try to remove SU from AvailableQueue. 620 SU->isAvailable = false; 621 UnscheduleNodeBottomUp(OldSU); 622 --CurCycle; 623 } 624 625 626 if (SU->isSucc(OldSU)) { 627 assert(false && "Something is wrong!"); 628 abort(); 629 } 630 631 ++NumBacktracks; 632} 633 634/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled 635/// successors to the newly created node. 636SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { 637 if (SU->FlaggedNodes.size()) 638 return NULL; 639 640 SDNode *N = SU->Node; 641 if (!N) 642 return NULL; 643 644 SUnit *NewSU; 645 bool TryUnfold = false; 646 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 647 MVT VT = N->getValueType(i); 648 if (VT == MVT::Flag) 649 return NULL; 650 else if (VT == MVT::Other) 651 TryUnfold = true; 652 } 653 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 654 const SDValue &Op = N->getOperand(i); 655 MVT VT = Op.Val->getValueType(Op.ResNo); 656 if (VT == MVT::Flag) 657 return NULL; 658 } 659 660 if (TryUnfold) { 661 SmallVector<SDNode*, 2> NewNodes; 662 if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) 663 return NULL; 664 665 DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; 666 assert(NewNodes.size() == 2 && "Expected a load folding node!"); 667 668 N = NewNodes[1]; 669 SDNode *LoadNode = NewNodes[0]; 670 unsigned NumVals = N->getNumValues(); 671 unsigned OldNumVals = SU->Node->getNumValues(); 672 for (unsigned i = 0; i != NumVals; ++i) 673 DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); 674 DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), 675 SDValue(LoadNode, 1)); 676 677 SUnit *NewSU = CreateNewSUnit(N); 678 assert(N->getNodeId() == -1 && "Node already inserted!"); 679 N->setNodeId(NewSU->NodeNum); 680 681 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 682 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 683 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 684 NewSU->isTwoAddress = true; 685 break; 686 } 687 } 688 if (TID.isCommutable()) 689 NewSU->isCommutable = true; 690 // FIXME: Calculate height / depth and propagate the changes? 691 NewSU->Depth = SU->Depth; 692 NewSU->Height = SU->Height; 693 ComputeLatency(NewSU); 694 695 // LoadNode may already exist. This can happen when there is another 696 // load from the same location and producing the same type of value 697 // but it has different alignment or volatileness. 698 bool isNewLoad = true; 699 SUnit *LoadSU; 700 if (LoadNode->getNodeId() != -1) { 701 LoadSU = &SUnits[LoadNode->getNodeId()]; 702 isNewLoad = false; 703 } else { 704 LoadSU = CreateNewSUnit(LoadNode); 705 LoadNode->setNodeId(LoadSU->NodeNum); 706 707 LoadSU->Depth = SU->Depth; 708 LoadSU->Height = SU->Height; 709 ComputeLatency(LoadSU); 710 } 711 712 SUnit *ChainPred = NULL; 713 SmallVector<SDep, 4> ChainSuccs; 714 SmallVector<SDep, 4> LoadPreds; 715 SmallVector<SDep, 4> NodePreds; 716 SmallVector<SDep, 4> NodeSuccs; 717 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 718 I != E; ++I) { 719 if (I->isCtrl) 720 ChainPred = I->Dep; 721 else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode)) 722 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); 723 else 724 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); 725 } 726 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 727 I != E; ++I) { 728 if (I->isCtrl) 729 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, 730 I->isCtrl, I->isSpecial)); 731 else 732 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, 733 I->isCtrl, I->isSpecial)); 734 } 735 736 if (ChainPred) { 737 RemovePred(SU, ChainPred, true, false); 738 if (isNewLoad) 739 AddPred(LoadSU, ChainPred, true, false); 740 } 741 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { 742 SDep *Pred = &LoadPreds[i]; 743 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); 744 if (isNewLoad) { 745 AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, 746 Pred->Reg, Pred->Cost); 747 } 748 } 749 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { 750 SDep *Pred = &NodePreds[i]; 751 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); 752 AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, 753 Pred->Reg, Pred->Cost); 754 } 755 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { 756 SDep *Succ = &NodeSuccs[i]; 757 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); 758 AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial, 759 Succ->Reg, Succ->Cost); 760 } 761 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { 762 SDep *Succ = &ChainSuccs[i]; 763 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); 764 if (isNewLoad) { 765 AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial, 766 Succ->Reg, Succ->Cost); 767 } 768 } 769 if (isNewLoad) { 770 AddPred(NewSU, LoadSU, false, false); 771 } 772 773 if (isNewLoad) 774 AvailableQueue->addNode(LoadSU); 775 AvailableQueue->addNode(NewSU); 776 777 ++NumUnfolds; 778 779 if (NewSU->NumSuccsLeft == 0) { 780 NewSU->isAvailable = true; 781 return NewSU; 782 } 783 SU = NewSU; 784 } 785 786 DOUT << "Duplicating SU # " << SU->NodeNum << "\n"; 787 NewSU = CreateClone(SU); 788 789 // New SUnit has the exact same predecessors. 790 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 791 I != E; ++I) 792 if (!I->isSpecial) { 793 AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost); 794 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1); 795 } 796 797 // Only copy scheduled successors. Cut them from old node's successor 798 // list and move them over. 799 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps; 800 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 801 I != E; ++I) { 802 if (I->isSpecial) 803 continue; 804 if (I->Dep->isScheduled) { 805 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1); 806 AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost); 807 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); 808 } 809 } 810 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { 811 SUnit *Succ = DelDeps[i].first; 812 bool isCtrl = DelDeps[i].second; 813 RemovePred(Succ, SU, isCtrl, false); 814 } 815 816 AvailableQueue->updateNode(SU); 817 AvailableQueue->addNode(NewSU); 818 819 ++NumDups; 820 return NewSU; 821} 822 823/// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies 824/// and move all scheduled successors of the given SUnit to the last copy. 825void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, 826 const TargetRegisterClass *DestRC, 827 const TargetRegisterClass *SrcRC, 828 SmallVector<SUnit*, 2> &Copies) { 829 SUnit *CopyFromSU = CreateNewSUnit(NULL); 830 CopyFromSU->CopySrcRC = SrcRC; 831 CopyFromSU->CopyDstRC = DestRC; 832 CopyFromSU->Depth = SU->Depth; 833 CopyFromSU->Height = SU->Height; 834 835 SUnit *CopyToSU = CreateNewSUnit(NULL); 836 CopyToSU->CopySrcRC = DestRC; 837 CopyToSU->CopyDstRC = SrcRC; 838 839 // Only copy scheduled successors. Cut them from old node's successor 840 // list and move them over. 841 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps; 842 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 843 I != E; ++I) { 844 if (I->isSpecial) 845 continue; 846 if (I->Dep->isScheduled) { 847 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1); 848 AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost); 849 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); 850 } 851 } 852 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { 853 SUnit *Succ = DelDeps[i].first; 854 bool isCtrl = DelDeps[i].second; 855 RemovePred(Succ, SU, isCtrl, false); 856 } 857 858 AddPred(CopyFromSU, SU, false, false, Reg, -1); 859 AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1); 860 861 AvailableQueue->updateNode(SU); 862 AvailableQueue->addNode(CopyFromSU); 863 AvailableQueue->addNode(CopyToSU); 864 Copies.push_back(CopyFromSU); 865 Copies.push_back(CopyToSU); 866 867 ++NumCCCopies; 868} 869 870/// getPhysicalRegisterVT - Returns the ValueType of the physical register 871/// definition of the specified node. 872/// FIXME: Move to SelectionDAG? 873static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, 874 const TargetInstrInfo *TII) { 875 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); 876 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 877 unsigned NumRes = TID.getNumDefs(); 878 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { 879 if (Reg == *ImpDef) 880 break; 881 ++NumRes; 882 } 883 return N->getValueType(NumRes); 884} 885 886/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay 887/// scheduling of the given node to satisfy live physical register dependencies. 888/// If the specific node is the last one that's available to schedule, do 889/// whatever is necessary (i.e. backtracking or cloning) to make it possible. 890bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, 891 SmallVector<unsigned, 4> &LRegs){ 892 if (LiveRegs.empty()) 893 return false; 894 895 SmallSet<unsigned, 4> RegAdded; 896 // If this node would clobber any "live" register, then it's not ready. 897 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 898 I != E; ++I) { 899 if (I->Cost < 0) { 900 unsigned Reg = I->Reg; 901 if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) { 902 if (RegAdded.insert(Reg)) 903 LRegs.push_back(Reg); 904 } 905 for (const unsigned *Alias = TRI->getAliasSet(Reg); 906 *Alias; ++Alias) 907 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { 908 if (RegAdded.insert(*Alias)) 909 LRegs.push_back(*Alias); 910 } 911 } 912 } 913 914 for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) { 915 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1]; 916 if (!Node || !Node->isMachineOpcode()) 917 continue; 918 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); 919 if (!TID.ImplicitDefs) 920 continue; 921 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { 922 if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) { 923 if (RegAdded.insert(*Reg)) 924 LRegs.push_back(*Reg); 925 } 926 for (const unsigned *Alias = TRI->getAliasSet(*Reg); 927 *Alias; ++Alias) 928 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { 929 if (RegAdded.insert(*Alias)) 930 LRegs.push_back(*Alias); 931 } 932 } 933 } 934 return !LRegs.empty(); 935} 936 937 938/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up 939/// schedulers. 940void ScheduleDAGRRList::ListScheduleBottomUp() { 941 unsigned CurCycle = 0; 942 // Add root to Available queue. 943 if (!SUnits.empty()) { 944 SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()]; 945 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); 946 RootSU->isAvailable = true; 947 AvailableQueue->push(RootSU); 948 } 949 950 // While Available queue is not empty, grab the node with the highest 951 // priority. If it is not ready put it back. Schedule the node. 952 SmallVector<SUnit*, 4> NotReady; 953 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap; 954 Sequence.reserve(SUnits.size()); 955 while (!AvailableQueue->empty()) { 956 bool Delayed = false; 957 LRegsMap.clear(); 958 SUnit *CurSU = AvailableQueue->pop(); 959 while (CurSU) { 960 if (CurSU->CycleBound <= CurCycle) { 961 SmallVector<unsigned, 4> LRegs; 962 if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) 963 break; 964 Delayed = true; 965 LRegsMap.insert(std::make_pair(CurSU, LRegs)); 966 } 967 968 CurSU->isPending = true; // This SU is not in AvailableQueue right now. 969 NotReady.push_back(CurSU); 970 CurSU = AvailableQueue->pop(); 971 } 972 973 // All candidates are delayed due to live physical reg dependencies. 974 // Try backtracking, code duplication, or inserting cross class copies 975 // to resolve it. 976 if (Delayed && !CurSU) { 977 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 978 SUnit *TrySU = NotReady[i]; 979 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 980 981 // Try unscheduling up to the point where it's safe to schedule 982 // this node. 983 unsigned LiveCycle = CurCycle; 984 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) { 985 unsigned Reg = LRegs[j]; 986 unsigned LCycle = LiveRegCycles[Reg]; 987 LiveCycle = std::min(LiveCycle, LCycle); 988 } 989 SUnit *OldSU = Sequence[LiveCycle]; 990 if (!WillCreateCycle(TrySU, OldSU)) { 991 BacktrackBottomUp(TrySU, LiveCycle, CurCycle); 992 // Force the current node to be scheduled before the node that 993 // requires the physical reg dep. 994 if (OldSU->isAvailable) { 995 OldSU->isAvailable = false; 996 AvailableQueue->remove(OldSU); 997 } 998 AddPred(TrySU, OldSU, true, true); 999 // If one or more successors has been unscheduled, then the current 1000 // node is no longer avaialable. Schedule a successor that's now 1001 // available instead. 1002 if (!TrySU->isAvailable) 1003 CurSU = AvailableQueue->pop(); 1004 else { 1005 CurSU = TrySU; 1006 TrySU->isPending = false; 1007 NotReady.erase(NotReady.begin()+i); 1008 } 1009 break; 1010 } 1011 } 1012 1013 if (!CurSU) { 1014 // Can't backtrack. Try duplicating the nodes that produces these 1015 // "expensive to copy" values to break the dependency. In case even 1016 // that doesn't work, insert cross class copies. 1017 SUnit *TrySU = NotReady[0]; 1018 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU]; 1019 assert(LRegs.size() == 1 && "Can't handle this yet!"); 1020 unsigned Reg = LRegs[0]; 1021 SUnit *LRDef = LiveRegDefs[Reg]; 1022 SUnit *NewDef = CopyAndMoveSuccessors(LRDef); 1023 if (!NewDef) { 1024 // Issue expensive cross register class copies. 1025 MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); 1026 const TargetRegisterClass *RC = 1027 TRI->getPhysicalRegisterRegClass(Reg, VT); 1028 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 1029 if (!DestRC) { 1030 assert(false && "Don't know how to copy this physical register!"); 1031 abort(); 1032 } 1033 SmallVector<SUnit*, 2> Copies; 1034 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); 1035 DOUT << "Adding an edge from SU # " << TrySU->NodeNum 1036 << " to SU #" << Copies.front()->NodeNum << "\n"; 1037 AddPred(TrySU, Copies.front(), true, true); 1038 NewDef = Copies.back(); 1039 } 1040 1041 DOUT << "Adding an edge from SU # " << NewDef->NodeNum 1042 << " to SU #" << TrySU->NodeNum << "\n"; 1043 LiveRegDefs[Reg] = NewDef; 1044 AddPred(NewDef, TrySU, true, true); 1045 TrySU->isAvailable = false; 1046 CurSU = NewDef; 1047 } 1048 1049 if (!CurSU) { 1050 assert(false && "Unable to resolve live physical register dependencies!"); 1051 abort(); 1052 } 1053 } 1054 1055 // Add the nodes that aren't ready back onto the available list. 1056 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) { 1057 NotReady[i]->isPending = false; 1058 // May no longer be available due to backtracking. 1059 if (NotReady[i]->isAvailable) 1060 AvailableQueue->push(NotReady[i]); 1061 } 1062 NotReady.clear(); 1063 1064 if (!CurSU) 1065 Sequence.push_back(0); 1066 else { 1067 ScheduleNodeBottomUp(CurSU, CurCycle); 1068 Sequence.push_back(CurSU); 1069 } 1070 ++CurCycle; 1071 } 1072 1073 // Reverse the order if it is bottom up. 1074 std::reverse(Sequence.begin(), Sequence.end()); 1075 1076 1077#ifndef NDEBUG 1078 // Verify that all SUnits were scheduled. 1079 bool AnyNotSched = false; 1080 unsigned DeadNodes = 0; 1081 unsigned Noops = 0; 1082 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 1083 if (!SUnits[i].isScheduled) { 1084 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { 1085 ++DeadNodes; 1086 continue; 1087 } 1088 if (!AnyNotSched) 1089 cerr << "*** List scheduling failed! ***\n"; 1090 SUnits[i].dump(&DAG); 1091 cerr << "has not been scheduled!\n"; 1092 AnyNotSched = true; 1093 } 1094 if (SUnits[i].NumSuccsLeft != 0) { 1095 if (!AnyNotSched) 1096 cerr << "*** List scheduling failed! ***\n"; 1097 SUnits[i].dump(&DAG); 1098 cerr << "has successors left!\n"; 1099 AnyNotSched = true; 1100 } 1101 } 1102 for (unsigned i = 0, e = Sequence.size(); i != e; ++i) 1103 if (!Sequence[i]) 1104 ++Noops; 1105 assert(!AnyNotSched); 1106 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && 1107 "The number of nodes scheduled doesn't match the expected number!"); 1108#endif 1109} 1110 1111//===----------------------------------------------------------------------===// 1112// Top-Down Scheduling 1113//===----------------------------------------------------------------------===// 1114 1115/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to 1116/// the AvailableQueue if the count reaches zero. Also update its cycle bound. 1117void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain, 1118 unsigned CurCycle) { 1119 // FIXME: the distance between two nodes is not always == the predecessor's 1120 // latency. For example, the reader can very well read the register written 1121 // by the predecessor later than the issue cycle. It also depends on the 1122 // interrupt model (drain vs. freeze). 1123 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency); 1124 1125 --SuccSU->NumPredsLeft; 1126 1127#ifndef NDEBUG 1128 if (SuccSU->NumPredsLeft < 0) { 1129 cerr << "*** List scheduling failed! ***\n"; 1130 SuccSU->dump(&DAG); 1131 cerr << " has been released too many times!\n"; 1132 assert(0); 1133 } 1134#endif 1135 1136 if (SuccSU->NumPredsLeft == 0) { 1137 SuccSU->isAvailable = true; 1138 AvailableQueue->push(SuccSU); 1139 } 1140} 1141 1142 1143/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending 1144/// count of its successors. If a successor pending count is zero, add it to 1145/// the Available queue. 1146void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { 1147 DOUT << "*** Scheduling [" << CurCycle << "]: "; 1148 DEBUG(SU->dump(&DAG)); 1149 SU->Cycle = CurCycle; 1150 1151 AvailableQueue->ScheduledNode(SU); 1152 1153 // Top down: release successors 1154 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1155 I != E; ++I) 1156 ReleaseSucc(I->Dep, I->isCtrl, CurCycle); 1157 SU->isScheduled = true; 1158} 1159 1160/// ListScheduleTopDown - The main loop of list scheduling for top-down 1161/// schedulers. 1162void ScheduleDAGRRList::ListScheduleTopDown() { 1163 unsigned CurCycle = 0; 1164 1165 // All leaves to Available queue. 1166 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 1167 // It is available if it has no predecessors. 1168 if (SUnits[i].Preds.empty()) { 1169 AvailableQueue->push(&SUnits[i]); 1170 SUnits[i].isAvailable = true; 1171 } 1172 } 1173 1174 // While Available queue is not empty, grab the node with the highest 1175 // priority. If it is not ready put it back. Schedule the node. 1176 std::vector<SUnit*> NotReady; 1177 Sequence.reserve(SUnits.size()); 1178 while (!AvailableQueue->empty()) { 1179 SUnit *CurSU = AvailableQueue->pop(); 1180 while (CurSU && CurSU->CycleBound > CurCycle) { 1181 NotReady.push_back(CurSU); 1182 CurSU = AvailableQueue->pop(); 1183 } 1184 1185 // Add the nodes that aren't ready back onto the available list. 1186 AvailableQueue->push_all(NotReady); 1187 NotReady.clear(); 1188 1189 if (!CurSU) 1190 Sequence.push_back(0); 1191 else { 1192 ScheduleNodeTopDown(CurSU, CurCycle); 1193 Sequence.push_back(CurSU); 1194 } 1195 ++CurCycle; 1196 } 1197 1198 1199#ifndef NDEBUG 1200 // Verify that all SUnits were scheduled. 1201 bool AnyNotSched = false; 1202 unsigned DeadNodes = 0; 1203 unsigned Noops = 0; 1204 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 1205 if (!SUnits[i].isScheduled) { 1206 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { 1207 ++DeadNodes; 1208 continue; 1209 } 1210 if (!AnyNotSched) 1211 cerr << "*** List scheduling failed! ***\n"; 1212 SUnits[i].dump(&DAG); 1213 cerr << "has not been scheduled!\n"; 1214 AnyNotSched = true; 1215 } 1216 if (SUnits[i].NumPredsLeft != 0) { 1217 if (!AnyNotSched) 1218 cerr << "*** List scheduling failed! ***\n"; 1219 SUnits[i].dump(&DAG); 1220 cerr << "has predecessors left!\n"; 1221 AnyNotSched = true; 1222 } 1223 } 1224 for (unsigned i = 0, e = Sequence.size(); i != e; ++i) 1225 if (!Sequence[i]) 1226 ++Noops; 1227 assert(!AnyNotSched); 1228 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && 1229 "The number of nodes scheduled doesn't match the expected number!"); 1230#endif 1231} 1232 1233 1234 1235//===----------------------------------------------------------------------===// 1236// RegReductionPriorityQueue Implementation 1237//===----------------------------------------------------------------------===// 1238// 1239// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers 1240// to reduce register pressure. 1241// 1242namespace { 1243 template<class SF> 1244 class RegReductionPriorityQueue; 1245 1246 /// Sorting functions for the Available queue. 1247 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 1248 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ; 1249 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {} 1250 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 1251 1252 bool operator()(const SUnit* left, const SUnit* right) const; 1253 }; 1254 1255 struct bu_ls_rr_fast_sort : public std::binary_function<SUnit*, SUnit*, bool>{ 1256 RegReductionPriorityQueue<bu_ls_rr_fast_sort> *SPQ; 1257 bu_ls_rr_fast_sort(RegReductionPriorityQueue<bu_ls_rr_fast_sort> *spq) 1258 : SPQ(spq) {} 1259 bu_ls_rr_fast_sort(const bu_ls_rr_fast_sort &RHS) : SPQ(RHS.SPQ) {} 1260 1261 bool operator()(const SUnit* left, const SUnit* right) const; 1262 }; 1263 1264 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> { 1265 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ; 1266 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {} 1267 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {} 1268 1269 bool operator()(const SUnit* left, const SUnit* right) const; 1270 }; 1271} // end anonymous namespace 1272 1273static inline bool isCopyFromLiveIn(const SUnit *SU) { 1274 SDNode *N = SU->Node; 1275 return N && N->getOpcode() == ISD::CopyFromReg && 1276 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; 1277} 1278 1279/// CalcNodeBUSethiUllmanNumber - Compute Sethi Ullman number for bottom up 1280/// scheduling. Smaller number is the higher priority. 1281static unsigned 1282CalcNodeBUSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { 1283 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; 1284 if (SethiUllmanNumber != 0) 1285 return SethiUllmanNumber; 1286 1287 unsigned Extra = 0; 1288 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1289 I != E; ++I) { 1290 if (I->isCtrl) continue; // ignore chain preds 1291 SUnit *PredSU = I->Dep; 1292 unsigned PredSethiUllman = CalcNodeBUSethiUllmanNumber(PredSU, SUNumbers); 1293 if (PredSethiUllman > SethiUllmanNumber) { 1294 SethiUllmanNumber = PredSethiUllman; 1295 Extra = 0; 1296 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) 1297 ++Extra; 1298 } 1299 1300 SethiUllmanNumber += Extra; 1301 1302 if (SethiUllmanNumber == 0) 1303 SethiUllmanNumber = 1; 1304 1305 return SethiUllmanNumber; 1306} 1307 1308/// CalcNodeTDSethiUllmanNumber - Compute Sethi Ullman number for top down 1309/// scheduling. Smaller number is the higher priority. 1310static unsigned 1311CalcNodeTDSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { 1312 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; 1313 if (SethiUllmanNumber != 0) 1314 return SethiUllmanNumber; 1315 1316 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; 1317 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) 1318 SethiUllmanNumber = 0xffff; 1319 else if (SU->NumSuccsLeft == 0) 1320 // If SU does not have a use, i.e. it doesn't produce a value that would 1321 // be consumed (e.g. store), then it terminates a chain of computation. 1322 // Give it a small SethiUllman number so it will be scheduled right before 1323 // its predecessors that it doesn't lengthen their live ranges. 1324 SethiUllmanNumber = 0; 1325 else if (SU->NumPredsLeft == 0 && 1326 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU))) 1327 SethiUllmanNumber = 0xffff; 1328 else { 1329 int Extra = 0; 1330 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1331 I != E; ++I) { 1332 if (I->isCtrl) continue; // ignore chain preds 1333 SUnit *PredSU = I->Dep; 1334 unsigned PredSethiUllman = CalcNodeTDSethiUllmanNumber(PredSU, SUNumbers); 1335 if (PredSethiUllman > SethiUllmanNumber) { 1336 SethiUllmanNumber = PredSethiUllman; 1337 Extra = 0; 1338 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) 1339 ++Extra; 1340 } 1341 1342 SethiUllmanNumber += Extra; 1343 } 1344 1345 return SethiUllmanNumber; 1346} 1347 1348 1349namespace { 1350 template<class SF> 1351 class VISIBILITY_HIDDEN RegReductionPriorityQueue 1352 : public SchedulingPriorityQueue { 1353 PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue; 1354 unsigned currentQueueId; 1355 1356 public: 1357 RegReductionPriorityQueue() : 1358 Queue(SF(this)), currentQueueId(0) {} 1359 1360 virtual void initNodes(std::vector<SUnit> &sunits) {} 1361 1362 virtual void addNode(const SUnit *SU) {} 1363 1364 virtual void updateNode(const SUnit *SU) {} 1365 1366 virtual void releaseState() {} 1367 1368 virtual unsigned getNodePriority(const SUnit *SU) const { 1369 return 0; 1370 } 1371 1372 unsigned size() const { return Queue.size(); } 1373 1374 bool empty() const { return Queue.empty(); } 1375 1376 void push(SUnit *U) { 1377 assert(!U->NodeQueueId && "Node in the queue already"); 1378 U->NodeQueueId = ++currentQueueId; 1379 Queue.push(U); 1380 } 1381 1382 void push_all(const std::vector<SUnit *> &Nodes) { 1383 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) 1384 push(Nodes[i]); 1385 } 1386 1387 SUnit *pop() { 1388 if (empty()) return NULL; 1389 SUnit *V = Queue.top(); 1390 Queue.pop(); 1391 V->NodeQueueId = 0; 1392 return V; 1393 } 1394 1395 void remove(SUnit *SU) { 1396 assert(!Queue.empty() && "Queue is empty!"); 1397 assert(SU->NodeQueueId != 0 && "Not in queue!"); 1398 Queue.erase_one(SU); 1399 SU->NodeQueueId = 0; 1400 } 1401 }; 1402 1403 class VISIBILITY_HIDDEN BURegReductionPriorityQueue 1404 : public RegReductionPriorityQueue<bu_ls_rr_sort> { 1405 // SUnits - The SUnits for the current graph. 1406 const std::vector<SUnit> *SUnits; 1407 1408 // SethiUllmanNumbers - The SethiUllman number for each node. 1409 std::vector<unsigned> SethiUllmanNumbers; 1410 1411 const TargetInstrInfo *TII; 1412 const TargetRegisterInfo *TRI; 1413 ScheduleDAGRRList *scheduleDAG; 1414 1415 public: 1416 explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, 1417 const TargetRegisterInfo *tri) 1418 : TII(tii), TRI(tri), scheduleDAG(NULL) {} 1419 1420 void initNodes(std::vector<SUnit> &sunits) { 1421 SUnits = &sunits; 1422 // Add pseudo dependency edges for two-address nodes. 1423 AddPseudoTwoAddrDeps(); 1424 // Calculate node priorities. 1425 CalculateSethiUllmanNumbers(); 1426 } 1427 1428 void addNode(const SUnit *SU) { 1429 unsigned SUSize = SethiUllmanNumbers.size(); 1430 if (SUnits->size() > SUSize) 1431 SethiUllmanNumbers.resize(SUSize*2, 0); 1432 CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); 1433 } 1434 1435 void updateNode(const SUnit *SU) { 1436 SethiUllmanNumbers[SU->NodeNum] = 0; 1437 CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); 1438 } 1439 1440 void releaseState() { 1441 SUnits = 0; 1442 SethiUllmanNumbers.clear(); 1443 } 1444 1445 unsigned getNodePriority(const SUnit *SU) const { 1446 assert(SU->NodeNum < SethiUllmanNumbers.size()); 1447 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; 1448 if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU)) 1449 // CopyFromReg should be close to its def because it restricts 1450 // allocation choices. But if it is a livein then perhaps we want it 1451 // closer to its uses so it can be coalesced. 1452 return 0xffff; 1453 else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) 1454 // CopyToReg should be close to its uses to facilitate coalescing and 1455 // avoid spilling. 1456 return 0; 1457 else if (Opc == TargetInstrInfo::EXTRACT_SUBREG || 1458 Opc == TargetInstrInfo::INSERT_SUBREG) 1459 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to 1460 // facilitate coalescing. 1461 return 0; 1462 else if (SU->NumSuccs == 0) 1463 // If SU does not have a use, i.e. it doesn't produce a value that would 1464 // be consumed (e.g. store), then it terminates a chain of computation. 1465 // Give it a large SethiUllman number so it will be scheduled right 1466 // before its predecessors that it doesn't lengthen their live ranges. 1467 return 0xffff; 1468 else if (SU->NumPreds == 0) 1469 // If SU does not have a def, schedule it close to its uses because it 1470 // does not lengthen any live ranges. 1471 return 0; 1472 else 1473 return SethiUllmanNumbers[SU->NodeNum]; 1474 } 1475 1476 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) { 1477 scheduleDAG = scheduleDag; 1478 } 1479 1480 private: 1481 bool canClobber(const SUnit *SU, const SUnit *Op); 1482 void AddPseudoTwoAddrDeps(); 1483 void CalculateSethiUllmanNumbers(); 1484 }; 1485 1486 1487 class VISIBILITY_HIDDEN BURegReductionFastPriorityQueue 1488 : public RegReductionPriorityQueue<bu_ls_rr_fast_sort> { 1489 // SUnits - The SUnits for the current graph. 1490 const std::vector<SUnit> *SUnits; 1491 1492 // SethiUllmanNumbers - The SethiUllman number for each node. 1493 std::vector<unsigned> SethiUllmanNumbers; 1494 public: 1495 explicit BURegReductionFastPriorityQueue() {} 1496 1497 void initNodes(std::vector<SUnit> &sunits) { 1498 SUnits = &sunits; 1499 // Calculate node priorities. 1500 CalculateSethiUllmanNumbers(); 1501 } 1502 1503 void addNode(const SUnit *SU) { 1504 unsigned SUSize = SethiUllmanNumbers.size(); 1505 if (SUnits->size() > SUSize) 1506 SethiUllmanNumbers.resize(SUSize*2, 0); 1507 CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); 1508 } 1509 1510 void updateNode(const SUnit *SU) { 1511 SethiUllmanNumbers[SU->NodeNum] = 0; 1512 CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); 1513 } 1514 1515 void releaseState() { 1516 SUnits = 0; 1517 SethiUllmanNumbers.clear(); 1518 } 1519 1520 unsigned getNodePriority(const SUnit *SU) const { 1521 return SethiUllmanNumbers[SU->NodeNum]; 1522 } 1523 1524 private: 1525 void CalculateSethiUllmanNumbers(); 1526 }; 1527 1528 1529 class VISIBILITY_HIDDEN TDRegReductionPriorityQueue 1530 : public RegReductionPriorityQueue<td_ls_rr_sort> { 1531 // SUnits - The SUnits for the current graph. 1532 const std::vector<SUnit> *SUnits; 1533 1534 // SethiUllmanNumbers - The SethiUllman number for each node. 1535 std::vector<unsigned> SethiUllmanNumbers; 1536 1537 public: 1538 TDRegReductionPriorityQueue() {} 1539 1540 void initNodes(std::vector<SUnit> &sunits) { 1541 SUnits = &sunits; 1542 // Calculate node priorities. 1543 CalculateSethiUllmanNumbers(); 1544 } 1545 1546 void addNode(const SUnit *SU) { 1547 unsigned SUSize = SethiUllmanNumbers.size(); 1548 if (SUnits->size() > SUSize) 1549 SethiUllmanNumbers.resize(SUSize*2, 0); 1550 CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers); 1551 } 1552 1553 void updateNode(const SUnit *SU) { 1554 SethiUllmanNumbers[SU->NodeNum] = 0; 1555 CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers); 1556 } 1557 1558 void releaseState() { 1559 SUnits = 0; 1560 SethiUllmanNumbers.clear(); 1561 } 1562 1563 unsigned getNodePriority(const SUnit *SU) const { 1564 assert(SU->NodeNum < SethiUllmanNumbers.size()); 1565 return SethiUllmanNumbers[SU->NodeNum]; 1566 } 1567 1568 private: 1569 void CalculateSethiUllmanNumbers(); 1570 }; 1571} 1572 1573/// closestSucc - Returns the scheduled cycle of the successor which is 1574/// closet to the current cycle. 1575static unsigned closestSucc(const SUnit *SU) { 1576 unsigned MaxCycle = 0; 1577 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1578 I != E; ++I) { 1579 unsigned Cycle = I->Dep->Cycle; 1580 // If there are bunch of CopyToRegs stacked up, they should be considered 1581 // to be at the same position. 1582 if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg) 1583 Cycle = closestSucc(I->Dep)+1; 1584 if (Cycle > MaxCycle) 1585 MaxCycle = Cycle; 1586 } 1587 return MaxCycle; 1588} 1589 1590/// calcMaxScratches - Returns an cost estimate of the worse case requirement 1591/// for scratch registers. Live-in operands and live-out results don't count 1592/// since they are "fixed". 1593static unsigned calcMaxScratches(const SUnit *SU) { 1594 unsigned Scratches = 0; 1595 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1596 I != E; ++I) { 1597 if (I->isCtrl) continue; // ignore chain preds 1598 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg) 1599 Scratches++; 1600 } 1601 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1602 I != E; ++I) { 1603 if (I->isCtrl) continue; // ignore chain succs 1604 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg) 1605 Scratches += 10; 1606 } 1607 return Scratches; 1608} 1609 1610// Bottom up 1611bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1612 unsigned LPriority = SPQ->getNodePriority(left); 1613 unsigned RPriority = SPQ->getNodePriority(right); 1614 if (LPriority != RPriority) 1615 return LPriority > RPriority; 1616 1617 // Try schedule def + use closer when Sethi-Ullman numbers are the same. 1618 // e.g. 1619 // t1 = op t2, c1 1620 // t3 = op t4, c2 1621 // 1622 // and the following instructions are both ready. 1623 // t2 = op c3 1624 // t4 = op c4 1625 // 1626 // Then schedule t2 = op first. 1627 // i.e. 1628 // t4 = op c4 1629 // t2 = op c3 1630 // t1 = op t2, c1 1631 // t3 = op t4, c2 1632 // 1633 // This creates more short live intervals. 1634 unsigned LDist = closestSucc(left); 1635 unsigned RDist = closestSucc(right); 1636 if (LDist != RDist) 1637 return LDist < RDist; 1638 1639 // Intuitively, it's good to push down instructions whose results are 1640 // liveout so their long live ranges won't conflict with other values 1641 // which are needed inside the BB. Further prioritize liveout instructions 1642 // by the number of operands which are calculated within the BB. 1643 unsigned LScratch = calcMaxScratches(left); 1644 unsigned RScratch = calcMaxScratches(right); 1645 if (LScratch != RScratch) 1646 return LScratch > RScratch; 1647 1648 if (left->Height != right->Height) 1649 return left->Height > right->Height; 1650 1651 if (left->Depth != right->Depth) 1652 return left->Depth < right->Depth; 1653 1654 if (left->CycleBound != right->CycleBound) 1655 return left->CycleBound > right->CycleBound; 1656 1657 assert(left->NodeQueueId && right->NodeQueueId && 1658 "NodeQueueId cannot be zero"); 1659 return (left->NodeQueueId > right->NodeQueueId); 1660} 1661 1662bool 1663bu_ls_rr_fast_sort::operator()(const SUnit *left, const SUnit *right) const { 1664 unsigned LPriority = SPQ->getNodePriority(left); 1665 unsigned RPriority = SPQ->getNodePriority(right); 1666 if (LPriority != RPriority) 1667 return LPriority > RPriority; 1668 assert(left->NodeQueueId && right->NodeQueueId && 1669 "NodeQueueId cannot be zero"); 1670 return (left->NodeQueueId > right->NodeQueueId); 1671} 1672 1673bool 1674BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { 1675 if (SU->isTwoAddress) { 1676 unsigned Opc = SU->Node->getMachineOpcode(); 1677 const TargetInstrDesc &TID = TII->get(Opc); 1678 unsigned NumRes = TID.getNumDefs(); 1679 unsigned NumOps = TID.getNumOperands() - NumRes; 1680 for (unsigned i = 0; i != NumOps; ++i) { 1681 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { 1682 SDNode *DU = SU->Node->getOperand(i).Val; 1683 if (DU->getNodeId() != -1 && 1684 Op->OrigNode == &(*SUnits)[DU->getNodeId()]) 1685 return true; 1686 } 1687 } 1688 } 1689 return false; 1690} 1691 1692 1693/// hasCopyToRegUse - Return true if SU has a value successor that is a 1694/// CopyToReg node. 1695static bool hasCopyToRegUse(SUnit *SU) { 1696 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1697 I != E; ++I) { 1698 if (I->isCtrl) continue; 1699 SUnit *SuccSU = I->Dep; 1700 if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg) 1701 return true; 1702 } 1703 return false; 1704} 1705 1706/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's 1707/// physical register defs. 1708static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, 1709 const TargetInstrInfo *TII, 1710 const TargetRegisterInfo *TRI) { 1711 SDNode *N = SuccSU->Node; 1712 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); 1713 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); 1714 assert(ImpDefs && "Caller should check hasPhysRegDefs"); 1715 const unsigned *SUImpDefs = 1716 TII->get(SU->Node->getMachineOpcode()).getImplicitDefs(); 1717 if (!SUImpDefs) 1718 return false; 1719 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { 1720 MVT VT = N->getValueType(i); 1721 if (VT == MVT::Flag || VT == MVT::Other) 1722 continue; 1723 unsigned Reg = ImpDefs[i - NumDefs]; 1724 for (;*SUImpDefs; ++SUImpDefs) { 1725 unsigned SUReg = *SUImpDefs; 1726 if (TRI->regsOverlap(Reg, SUReg)) 1727 return true; 1728 } 1729 } 1730 return false; 1731} 1732 1733/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses 1734/// it as a def&use operand. Add a pseudo control edge from it to the other 1735/// node (if it won't create a cycle) so the two-address one will be scheduled 1736/// first (lower in the schedule). If both nodes are two-address, favor the 1737/// one that has a CopyToReg use (more likely to be a loop induction update). 1738/// If both are two-address, but one is commutable while the other is not 1739/// commutable, favor the one that's not commutable. 1740void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { 1741 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { 1742 SUnit *SU = (SUnit *)&((*SUnits)[i]); 1743 if (!SU->isTwoAddress) 1744 continue; 1745 1746 SDNode *Node = SU->Node; 1747 if (!Node || !Node->isMachineOpcode() || SU->FlaggedNodes.size() > 0) 1748 continue; 1749 1750 unsigned Opc = Node->getMachineOpcode(); 1751 const TargetInstrDesc &TID = TII->get(Opc); 1752 unsigned NumRes = TID.getNumDefs(); 1753 unsigned NumOps = TID.getNumOperands() - NumRes; 1754 for (unsigned j = 0; j != NumOps; ++j) { 1755 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) { 1756 SDNode *DU = SU->Node->getOperand(j).Val; 1757 if (DU->getNodeId() == -1) 1758 continue; 1759 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; 1760 if (!DUSU) continue; 1761 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), 1762 E = DUSU->Succs.end(); I != E; ++I) { 1763 if (I->isCtrl) continue; 1764 SUnit *SuccSU = I->Dep; 1765 if (SuccSU == SU) 1766 continue; 1767 // Be conservative. Ignore if nodes aren't at roughly the same 1768 // depth and height. 1769 if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1) 1770 continue; 1771 if (!SuccSU->Node || !SuccSU->Node->isMachineOpcode()) 1772 continue; 1773 // Don't constrain nodes with physical register defs if the 1774 // predecessor can clobber them. 1775 if (SuccSU->hasPhysRegDefs) { 1776 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) 1777 continue; 1778 } 1779 // Don't constraint extract_subreg / insert_subreg these may be 1780 // coalesced away. We don't them close to their uses. 1781 unsigned SuccOpc = SuccSU->Node->getMachineOpcode(); 1782 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || 1783 SuccOpc == TargetInstrInfo::INSERT_SUBREG) 1784 continue; 1785 if ((!canClobber(SuccSU, DUSU) || 1786 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) || 1787 (!SU->isCommutable && SuccSU->isCommutable)) && 1788 !scheduleDAG->IsReachable(SuccSU, SU)) { 1789 DOUT << "Adding an edge from SU # " << SU->NodeNum 1790 << " to SU #" << SuccSU->NodeNum << "\n"; 1791 scheduleDAG->AddPred(SU, SuccSU, true, true); 1792 } 1793 } 1794 } 1795 } 1796 } 1797} 1798 1799/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1800/// scheduling units. 1801void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { 1802 SethiUllmanNumbers.assign(SUnits->size(), 0); 1803 1804 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1805 CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); 1806} 1807void BURegReductionFastPriorityQueue::CalculateSethiUllmanNumbers() { 1808 SethiUllmanNumbers.assign(SUnits->size(), 0); 1809 1810 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1811 CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); 1812} 1813 1814/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled 1815/// predecessors of the successors of the SUnit SU. Stop when the provided 1816/// limit is exceeded. 1817static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, 1818 unsigned Limit) { 1819 unsigned Sum = 0; 1820 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1821 I != E; ++I) { 1822 SUnit *SuccSU = I->Dep; 1823 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(), 1824 EE = SuccSU->Preds.end(); II != EE; ++II) { 1825 SUnit *PredSU = II->Dep; 1826 if (!PredSU->isScheduled) 1827 if (++Sum > Limit) 1828 return Sum; 1829 } 1830 } 1831 return Sum; 1832} 1833 1834 1835// Top down 1836bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { 1837 unsigned LPriority = SPQ->getNodePriority(left); 1838 unsigned RPriority = SPQ->getNodePriority(right); 1839 bool LIsTarget = left->Node && left->Node->isMachineOpcode(); 1840 bool RIsTarget = right->Node && right->Node->isMachineOpcode(); 1841 bool LIsFloater = LIsTarget && left->NumPreds == 0; 1842 bool RIsFloater = RIsTarget && right->NumPreds == 0; 1843 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0; 1844 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0; 1845 1846 if (left->NumSuccs == 0 && right->NumSuccs != 0) 1847 return false; 1848 else if (left->NumSuccs != 0 && right->NumSuccs == 0) 1849 return true; 1850 1851 if (LIsFloater) 1852 LBonus -= 2; 1853 if (RIsFloater) 1854 RBonus -= 2; 1855 if (left->NumSuccs == 1) 1856 LBonus += 2; 1857 if (right->NumSuccs == 1) 1858 RBonus += 2; 1859 1860 if (LPriority+LBonus != RPriority+RBonus) 1861 return LPriority+LBonus < RPriority+RBonus; 1862 1863 if (left->Depth != right->Depth) 1864 return left->Depth < right->Depth; 1865 1866 if (left->NumSuccsLeft != right->NumSuccsLeft) 1867 return left->NumSuccsLeft > right->NumSuccsLeft; 1868 1869 if (left->CycleBound != right->CycleBound) 1870 return left->CycleBound > right->CycleBound; 1871 1872 assert(left->NodeQueueId && right->NodeQueueId && 1873 "NodeQueueId cannot be zero"); 1874 return (left->NodeQueueId > right->NodeQueueId); 1875} 1876 1877/// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all 1878/// scheduling units. 1879void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { 1880 SethiUllmanNumbers.assign(SUnits->size(), 0); 1881 1882 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) 1883 CalcNodeTDSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); 1884} 1885 1886//===----------------------------------------------------------------------===// 1887// Public Constructor Functions 1888//===----------------------------------------------------------------------===// 1889 1890llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, 1891 SelectionDAG *DAG, 1892 MachineBasicBlock *BB, 1893 bool Fast) { 1894 if (Fast) 1895 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true, 1896 new BURegReductionFastPriorityQueue()); 1897 1898 const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); 1899 const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); 1900 1901 BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); 1902 1903 ScheduleDAGRRList *SD = 1904 new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ); 1905 PQ->setScheduleDAG(SD); 1906 return SD; 1907} 1908 1909llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, 1910 SelectionDAG *DAG, 1911 MachineBasicBlock *BB, 1912 bool Fast) { 1913 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast, 1914 new TDRegReductionPriorityQueue()); 1915} 1916