SelectionDAGBuilder.cpp revision 0a29cb045444c13160e90fe7942a9d7c720185ed
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/BranchProbabilityInfo.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Analysis/ValueTracking.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/CallingConv.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/DataLayout.h" 39#include "llvm/IR/DerivedTypes.h" 40#include "llvm/IR/Function.h" 41#include "llvm/IR/GlobalVariable.h" 42#include "llvm/IR/InlineAsm.h" 43#include "llvm/IR/Instructions.h" 44#include "llvm/IR/IntrinsicInst.h" 45#include "llvm/IR/Intrinsics.h" 46#include "llvm/IR/LLVMContext.h" 47#include "llvm/IR/Module.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/IntegersSubsetMapping.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetFrameLowering.h" 55#include "llvm/Target/TargetInstrInfo.h" 56#include "llvm/Target/TargetIntrinsicInfo.h" 57#include "llvm/Target/TargetLibraryInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetOptions.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74// Limit the width of DAG chains. This is important in general to prevent 75// prevent DAG-based analysis from blowing up. For example, alias analysis and 76// load clustering may not complete in reasonable time. It is difficult to 77// recognize and avoid this situation within each individual analysis, and 78// future analyses are likely to have the same behavior. Limiting DAG width is 79// the safe approach, and will be especially important with global DAGs. 80// 81// MaxParallelChains default is arbitrarily high to avoid affecting 82// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 83// sequence over this should have been converted to llvm.memcpy by the 84// frontend. It easy to induce this behavior with .ll code such as: 85// %buffer = alloca [4096 x i8] 86// %data = load [4096 x i8]* %argPtr 87// store [4096 x i8] %data, [4096 x i8]* %buffer 88static const unsigned MaxParallelChains = 64; 89 90static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 91 const SDValue *Parts, unsigned NumParts, 92 MVT PartVT, EVT ValueVT, const Value *V); 93 94/// getCopyFromParts - Create a value that contains the specified legal parts 95/// combined into the value they represent. If the parts combine to a type 96/// larger then ValueVT then AssertOp can be used to specify whether the extra 97/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 98/// (ISD::AssertSext). 99static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 100 const SDValue *Parts, 101 unsigned NumParts, MVT PartVT, EVT ValueVT, 102 const Value *V, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 106 PartVT, ValueVT, V); 107 108 assert(NumParts > 0 && "No parts to assemble!"); 109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 110 SDValue Val = Parts[0]; 111 112 if (NumParts > 1) { 113 // Assemble the value from multiple parts. 114 if (ValueVT.isInteger()) { 115 unsigned PartBits = PartVT.getSizeInBits(); 116 unsigned ValueBits = ValueVT.getSizeInBits(); 117 118 // Assemble the power of 2 part. 119 unsigned RoundParts = NumParts & (NumParts - 1) ? 120 1 << Log2_32(NumParts) : NumParts; 121 unsigned RoundBits = PartBits * RoundParts; 122 EVT RoundVT = RoundBits == ValueBits ? 123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 124 SDValue Lo, Hi; 125 126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 127 128 if (RoundParts > 2) { 129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 130 PartVT, HalfVT, V); 131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 132 RoundParts / 2, PartVT, HalfVT, V); 133 } else { 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 136 } 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 142 143 if (RoundParts < NumParts) { 144 // Assemble the trailing non-power-of-2 part. 145 unsigned OddParts = NumParts - RoundParts; 146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 147 Hi = getCopyFromParts(DAG, DL, 148 Parts + RoundParts, OddParts, PartVT, OddVT, V); 149 150 // Combine the round and odd parts. 151 Lo = Val; 152 if (TLI.isBigEndian()) 153 std::swap(Lo, Hi); 154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 157 DAG.getConstant(Lo.getValueType().getSizeInBits(), 158 TLI.getPointerTy())); 159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 161 } 162 } else if (PartVT.isFloatingPoint()) { 163 // FP split into multiple FP parts (for ppcf128) 164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && 165 "Unexpected split"); 166 SDValue Lo, Hi; 167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 169 if (TLI.isBigEndian()) 170 std::swap(Lo, Hi); 171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 172 } else { 173 // FP split into integer parts (soft fp) 174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 175 !PartVT.isVector() && "Unexpected split"); 176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 178 } 179 } 180 181 // There is now one part, held in Val. Correct it to match ValueVT. 182 EVT PartEVT = Val.getValueType(); 183 184 if (PartEVT == ValueVT) 185 return Val; 186 187 if (PartEVT.isInteger() && ValueVT.isInteger()) { 188 if (ValueVT.bitsLT(PartEVT)) { 189 // For a truncate, see if we have any information to 190 // indicate whether the truncated bits will always be 191 // zero or sign-extension. 192 if (AssertOp != ISD::DELETED_NODE) 193 Val = DAG.getNode(AssertOp, DL, PartEVT, Val, 194 DAG.getValueType(ValueVT)); 195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 196 } 197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 198 } 199 200 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 201 // FP_ROUND's are always exact here. 202 if (ValueVT.bitsLT(Val.getValueType())) 203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 204 DAG.getTargetConstant(1, TLI.getPointerTy())); 205 206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 207 } 208 209 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) 210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 211 212 llvm_unreachable("Unknown mismatch!"); 213} 214 215/// getCopyFromPartsVector - Create a value that contains the specified legal 216/// parts combined into the value they represent. If the parts combine to a 217/// type larger then ValueVT then AssertOp can be used to specify whether the 218/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 219/// ValueVT (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 MVT PartVT, EVT ValueVT, const Value *V) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT; 231 MVT RegisterVT; 232 unsigned NumIntermediates; 233 unsigned NumRegs = 234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 235 NumIntermediates, RegisterVT); 236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 237 NumParts = NumRegs; // Silence a compiler warning. 238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 239 assert(RegisterVT == Parts[0].getSimpleValueType() && 240 "Part type doesn't match part!"); 241 242 // Assemble the parts into intermediate operands. 243 SmallVector<SDValue, 8> Ops(NumIntermediates); 244 if (NumIntermediates == NumParts) { 245 // If the register was not expanded, truncate or copy the value, 246 // as appropriate. 247 for (unsigned i = 0; i != NumParts; ++i) 248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 249 PartVT, IntermediateVT, V); 250 } else if (NumParts > 0) { 251 // If the intermediate type was expanded, build the intermediate 252 // operands from the parts. 253 assert(NumParts % NumIntermediates == 0 && 254 "Must expand into a divisible number of parts!"); 255 unsigned Factor = NumParts / NumIntermediates; 256 for (unsigned i = 0; i != NumIntermediates; ++i) 257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 258 PartVT, IntermediateVT, V); 259 } 260 261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 262 // intermediate operands. 263 Val = DAG.getNode(IntermediateVT.isVector() ? 264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 265 ValueVT, &Ops[0], NumIntermediates); 266 } 267 268 // There is now one part, held in Val. Correct it to match ValueVT. 269 EVT PartEVT = Val.getValueType(); 270 271 if (PartEVT == ValueVT) 272 return Val; 273 274 if (PartEVT.isVector()) { 275 // If the element type of the source/dest vectors are the same, but the 276 // parts vector has more elements than the value vector, then we have a 277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 278 // elements we want. 279 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) { 280 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 281 "Cannot narrow, it would be a lossy transformation"); 282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 283 DAG.getIntPtrConstant(0)); 284 } 285 286 // Vector/Vector bitcast. 287 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) 288 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 289 290 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 291 "Cannot handle this kind of promotion"); 292 // Promoted vector extract 293 bool Smaller = ValueVT.bitsLE(PartEVT); 294 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 295 DL, ValueVT, Val); 296 297 } 298 299 // Trivial bitcast if the types are the same size and the destination 300 // vector type is legal. 301 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && 302 TLI.isTypeLegal(ValueVT)) 303 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 304 305 // Handle cases such as i8 -> <1 x i1> 306 if (ValueVT.getVectorNumElements() != 1) { 307 LLVMContext &Ctx = *DAG.getContext(); 308 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 309 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 310 if (const CallInst *CI = dyn_cast<CallInst>(I)) 311 if (isa<InlineAsm>(CI->getCalledValue())) 312 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 313 Ctx.emitError(I, ErrMsg); 314 } else { 315 Ctx.emitError(ErrMsg); 316 } 317 report_fatal_error("Cannot handle scalar-to-vector conversion!"); 318 } 319 320 if (ValueVT.getVectorNumElements() == 1 && 321 ValueVT.getVectorElementType() != PartEVT) { 322 bool Smaller = ValueVT.bitsLE(PartEVT); 323 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 324 DL, ValueVT.getScalarType(), Val); 325 } 326 327 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 328} 329 330static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 331 SDValue Val, SDValue *Parts, unsigned NumParts, 332 MVT PartVT, const Value *V); 333 334/// getCopyToParts - Create a series of nodes that contain the specified value 335/// split into legal parts. If the parts contain more bits than Val, then, for 336/// integers, ExtendKind can be used to specify how to generate the extra bits. 337static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 338 SDValue Val, SDValue *Parts, unsigned NumParts, 339 MVT PartVT, const Value *V, 340 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 341 EVT ValueVT = Val.getValueType(); 342 343 // Handle the vector case separately. 344 if (ValueVT.isVector()) 345 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 346 347 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 348 unsigned PartBits = PartVT.getSizeInBits(); 349 unsigned OrigNumParts = NumParts; 350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 351 352 if (NumParts == 0) 353 return; 354 355 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 356 EVT PartEVT = PartVT; 357 if (PartEVT == ValueVT) { 358 assert(NumParts == 1 && "No-op copy with multiple parts!"); 359 Parts[0] = Val; 360 return; 361 } 362 363 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 364 // If the parts cover more bits than the value has, promote the value. 365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 366 assert(NumParts == 1 && "Do not know what to promote to!"); 367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 368 } else { 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 } else if (PartBits == ValueVT.getSizeInBits()) { 378 // Different types of the same size. 379 assert(NumParts == 1 && PartEVT != ValueVT); 380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 382 // If the parts cover less bits than value has, truncate the value. 383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 384 ValueVT.isInteger() && 385 "Unknown mismatch!"); 386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 388 if (PartVT == MVT::x86mmx) 389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 390 } 391 392 // The value may have changed - recompute ValueVT. 393 ValueVT = Val.getValueType(); 394 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 395 "Failed to tile the value with PartVT!"); 396 397 if (NumParts == 1) { 398 if (PartEVT != ValueVT) { 399 LLVMContext &Ctx = *DAG.getContext(); 400 Twine ErrMsg("scalar-to-vector conversion failed"); 401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 402 if (const CallInst *CI = dyn_cast<CallInst>(I)) 403 if (isa<InlineAsm>(CI->getCalledValue())) 404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 405 Ctx.emitError(I, ErrMsg); 406 } else { 407 Ctx.emitError(ErrMsg); 408 } 409 } 410 411 Parts[0] = Val; 412 return; 413 } 414 415 // Expand the value into multiple parts. 416 if (NumParts & (NumParts - 1)) { 417 // The number of parts is not a power of 2. Split off and copy the tail. 418 assert(PartVT.isInteger() && ValueVT.isInteger() && 419 "Do not know what to expand to!"); 420 unsigned RoundParts = 1 << Log2_32(NumParts); 421 unsigned RoundBits = RoundParts * PartBits; 422 unsigned OddParts = NumParts - RoundParts; 423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 424 DAG.getIntPtrConstant(RoundBits)); 425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 426 427 if (TLI.isBigEndian()) 428 // The odd parts were reversed by getCopyToParts - unreverse them. 429 std::reverse(Parts + RoundParts, Parts + NumParts); 430 431 NumParts = RoundParts; 432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 434 } 435 436 // The number of parts is a power of 2. Repeatedly bisect the value using 437 // EXTRACT_ELEMENT. 438 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 439 EVT::getIntegerVT(*DAG.getContext(), 440 ValueVT.getSizeInBits()), 441 Val); 442 443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 444 for (unsigned i = 0; i < NumParts; i += StepSize) { 445 unsigned ThisBits = StepSize * PartBits / 2; 446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 447 SDValue &Part0 = Parts[i]; 448 SDValue &Part1 = Parts[i+StepSize/2]; 449 450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 451 ThisVT, Part0, DAG.getIntPtrConstant(1)); 452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 453 ThisVT, Part0, DAG.getIntPtrConstant(0)); 454 455 if (ThisBits == PartBits && ThisVT != PartVT) { 456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 458 } 459 } 460 } 461 462 if (TLI.isBigEndian()) 463 std::reverse(Parts, Parts + OrigNumParts); 464} 465 466 467/// getCopyToPartsVector - Create a series of nodes that contain the specified 468/// value split into legal parts. 469static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 470 SDValue Val, SDValue *Parts, unsigned NumParts, 471 MVT PartVT, const Value *V) { 472 EVT ValueVT = Val.getValueType(); 473 assert(ValueVT.isVector() && "Not a vector"); 474 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 475 476 if (NumParts == 1) { 477 EVT PartEVT = PartVT; 478 if (PartEVT == ValueVT) { 479 // Nothing to do. 480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 481 // Bitconvert vector->vector case. 482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 483 } else if (PartVT.isVector() && 484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() && 485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 486 EVT ElementVT = PartVT.getVectorElementType(); 487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 488 // undef elements. 489 SmallVector<SDValue, 16> Ops; 490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 ElementVT, Val, DAG.getIntPtrConstant(i))); 493 494 for (unsigned i = ValueVT.getVectorNumElements(), 495 e = PartVT.getVectorNumElements(); i != e; ++i) 496 Ops.push_back(DAG.getUNDEF(ElementVT)); 497 498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 499 500 // FIXME: Use CONCAT for 2x -> 4x. 501 502 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 504 } else if (PartVT.isVector() && 505 PartEVT.getVectorElementType().bitsGE( 506 ValueVT.getVectorElementType()) && 507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 508 509 // Promoted vector extract 510 bool Smaller = PartEVT.bitsLE(ValueVT); 511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 512 DL, PartVT, Val); 513 } else{ 514 // Vector -> scalar conversion. 515 assert(ValueVT.getVectorNumElements() == 1 && 516 "Only trivial vector-to-scalar conversions should get here!"); 517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 PartVT, Val, DAG.getIntPtrConstant(0)); 519 520 bool Smaller = ValueVT.bitsLE(PartVT); 521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 522 DL, PartVT, Val); 523 } 524 525 Parts[0] = Val; 526 return; 527 } 528 529 // Handle a multi-element vector. 530 EVT IntermediateVT; 531 MVT RegisterVT; 532 unsigned NumIntermediates; 533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 534 IntermediateVT, 535 NumIntermediates, RegisterVT); 536 unsigned NumElements = ValueVT.getVectorNumElements(); 537 538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 539 NumParts = NumRegs; // Silence a compiler warning. 540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 541 542 // Split the vector into intermediate operands. 543 SmallVector<SDValue, 8> Ops(NumIntermediates); 544 for (unsigned i = 0; i != NumIntermediates; ++i) { 545 if (IntermediateVT.isVector()) 546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 547 IntermediateVT, Val, 548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 549 else 550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 551 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 552 } 553 554 // Split the intermediate operands into legal parts. 555 if (NumParts == NumIntermediates) { 556 // If the register was not expanded, promote or copy the value, 557 // as appropriate. 558 for (unsigned i = 0; i != NumParts; ++i) 559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 560 } else if (NumParts > 0) { 561 // If the intermediate type was expanded, split each the value into 562 // legal parts. 563 assert(NumParts % NumIntermediates == 0 && 564 "Must expand into a divisible number of parts!"); 565 unsigned Factor = NumParts / NumIntermediates; 566 for (unsigned i = 0; i != NumIntermediates; ++i) 567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 568 } 569} 570 571namespace { 572 /// RegsForValue - This struct represents the registers (physical or virtual) 573 /// that a particular set of values is assigned, and the type information 574 /// about the value. The most common situation is to represent one value at a 575 /// time, but struct or array values are handled element-wise as multiple 576 /// values. The splitting of aggregates is performed recursively, so that we 577 /// never have aggregate-typed registers. The values at this point do not 578 /// necessarily have legal types, so each value may require one or more 579 /// registers of some legal type. 580 /// 581 struct RegsForValue { 582 /// ValueVTs - The value types of the values, which may not be legal, and 583 /// may need be promoted or synthesized from one or more registers. 584 /// 585 SmallVector<EVT, 4> ValueVTs; 586 587 /// RegVTs - The value types of the registers. This is the same size as 588 /// ValueVTs and it records, for each value, what the type of the assigned 589 /// register or registers are. (Individual values are never synthesized 590 /// from more than one type of register.) 591 /// 592 /// With virtual registers, the contents of RegVTs is redundant with TLI's 593 /// getRegisterType member function, however when with physical registers 594 /// it is necessary to have a separate record of the types. 595 /// 596 SmallVector<MVT, 4> RegVTs; 597 598 /// Regs - This list holds the registers assigned to the values. 599 /// Each legal or promoted value requires one register, and each 600 /// expanded value requires multiple registers. 601 /// 602 SmallVector<unsigned, 4> Regs; 603 604 RegsForValue() {} 605 606 RegsForValue(const SmallVector<unsigned, 4> ®s, 607 MVT regvt, EVT valuevt) 608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 609 610 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 611 unsigned Reg, Type *Ty) { 612 ComputeValueVTs(tli, Ty, ValueVTs); 613 614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 615 EVT ValueVT = ValueVTs[Value]; 616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 618 for (unsigned i = 0; i != NumRegs; ++i) 619 Regs.push_back(Reg + i); 620 RegVTs.push_back(RegisterVT); 621 Reg += NumRegs; 622 } 623 } 624 625 /// areValueTypesLegal - Return true if types of all the values are legal. 626 bool areValueTypesLegal(const TargetLowering &TLI) { 627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 628 MVT RegisterVT = RegVTs[Value]; 629 if (!TLI.isTypeLegal(RegisterVT)) 630 return false; 631 } 632 return true; 633 } 634 635 /// append - Add the specified values to this one. 636 void append(const RegsForValue &RHS) { 637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 639 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 640 } 641 642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643 /// this value and returns the result as a ValueVTs value. This uses 644 /// Chain/Flag as the input and updates them for the output Chain/Flag. 645 /// If the Flag pointer is NULL, no flag is used. 646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 647 DebugLoc dl, 648 SDValue &Chain, SDValue *Flag, 649 const Value *V = 0) const; 650 651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 652 /// specified value into the registers specified by this object. This uses 653 /// Chain/Flag as the input and updates them for the output Chain/Flag. 654 /// If the Flag pointer is NULL, no flag is used. 655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 656 SDValue &Chain, SDValue *Flag, const Value *V) const; 657 658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 659 /// operand list. This adds the code marker, matching input operand index 660 /// (if applicable), and includes the number of values added into it. 661 void AddInlineAsmOperands(unsigned Kind, 662 bool HasMatching, unsigned MatchingIdx, 663 SelectionDAG &DAG, 664 std::vector<SDValue> &Ops) const; 665 }; 666} 667 668/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 669/// this value and returns the result as a ValueVT value. This uses 670/// Chain/Flag as the input and updates them for the output Chain/Flag. 671/// If the Flag pointer is NULL, no flag is used. 672SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 673 FunctionLoweringInfo &FuncInfo, 674 DebugLoc dl, 675 SDValue &Chain, SDValue *Flag, 676 const Value *V) const { 677 // A Value with type {} or [0 x %t] needs no registers. 678 if (ValueVTs.empty()) 679 return SDValue(); 680 681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 682 683 // Assemble the legal parts into the final values. 684 SmallVector<SDValue, 4> Values(ValueVTs.size()); 685 SmallVector<SDValue, 8> Parts; 686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 687 // Copy the legal parts from the registers. 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 MVT RegisterVT = RegVTs[Value]; 691 692 Parts.resize(NumRegs); 693 for (unsigned i = 0; i != NumRegs; ++i) { 694 SDValue P; 695 if (Flag == 0) { 696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 697 } else { 698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 699 *Flag = P.getValue(2); 700 } 701 702 Chain = P.getValue(1); 703 Parts[i] = P; 704 705 // If the source register was virtual and if we know something about it, 706 // add an assert node. 707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 708 !RegisterVT.isInteger() || RegisterVT.isVector()) 709 continue; 710 711 const FunctionLoweringInfo::LiveOutInfo *LOI = 712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 713 if (!LOI) 714 continue; 715 716 unsigned RegSize = RegisterVT.getSizeInBits(); 717 unsigned NumSignBits = LOI->NumSignBits; 718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 719 720 // FIXME: We capture more information than the dag can represent. For 721 // now, just use the tightest assertzext/assertsext possible. 722 bool isSExt = true; 723 EVT FromVT(MVT::Other); 724 if (NumSignBits == RegSize) 725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 726 else if (NumZeroBits >= RegSize-1) 727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 728 else if (NumSignBits > RegSize-8) 729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 730 else if (NumZeroBits >= RegSize-8) 731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 732 else if (NumSignBits > RegSize-16) 733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 734 else if (NumZeroBits >= RegSize-16) 735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 736 else if (NumSignBits > RegSize-32) 737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 738 else if (NumZeroBits >= RegSize-32) 739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 740 else 741 continue; 742 743 // Add an assertion node. 744 assert(FromVT != MVT::Other); 745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 746 RegisterVT, P, DAG.getValueType(FromVT)); 747 } 748 749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 750 NumRegs, RegisterVT, ValueVT, V); 751 Part += NumRegs; 752 Parts.clear(); 753 } 754 755 return DAG.getNode(ISD::MERGE_VALUES, dl, 756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 757 &Values[0], ValueVTs.size()); 758} 759 760/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 761/// specified value into the registers specified by this object. This uses 762/// Chain/Flag as the input and updates them for the output Chain/Flag. 763/// If the Flag pointer is NULL, no flag is used. 764void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 765 SDValue &Chain, SDValue *Flag, 766 const Value *V) const { 767 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 768 769 // Get the list of the values's legal parts. 770 unsigned NumRegs = Regs.size(); 771 SmallVector<SDValue, 8> Parts(NumRegs); 772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 773 EVT ValueVT = ValueVTs[Value]; 774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 775 MVT RegisterVT = RegVTs[Value]; 776 ISD::NodeType ExtendKind = 777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 778 779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 781 Part += NumParts; 782 } 783 784 // Copy the parts into the registers. 785 SmallVector<SDValue, 8> Chains(NumRegs); 786 for (unsigned i = 0; i != NumRegs; ++i) { 787 SDValue Part; 788 if (Flag == 0) { 789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 790 } else { 791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 792 *Flag = Part.getValue(1); 793 } 794 795 Chains[i] = Part.getValue(0); 796 } 797 798 if (NumRegs == 1 || Flag) 799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 800 // flagged to it. That is the CopyToReg nodes and the user are considered 801 // a single scheduling unit. If we create a TokenFactor and return it as 802 // chain, then the TokenFactor is both a predecessor (operand) of the 803 // user as well as a successor (the TF operands are flagged to the user). 804 // c1, f1 = CopyToReg 805 // c2, f2 = CopyToReg 806 // c3 = TokenFactor c1, c2 807 // ... 808 // = op c3, ..., f2 809 Chain = Chains[NumRegs-1]; 810 else 811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 812} 813 814/// AddInlineAsmOperands - Add this value to the specified inlineasm node 815/// operand list. This adds the code marker and includes the number of 816/// values added into it. 817void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 818 unsigned MatchingIdx, 819 SelectionDAG &DAG, 820 std::vector<SDValue> &Ops) const { 821 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 822 823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 824 if (HasMatching) 825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 826 else if (!Regs.empty() && 827 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 828 // Put the register class of the virtual registers in the flag word. That 829 // way, later passes can recompute register class constraints for inline 830 // assembly as well as normal instructions. 831 // Don't do this for tied operands that can use the regclass information 832 // from the def. 833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 836 } 837 838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 839 Ops.push_back(Res); 840 841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 843 MVT RegisterVT = RegVTs[Value]; 844 for (unsigned i = 0; i != NumRegs; ++i) { 845 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 847 } 848 } 849} 850 851void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 852 const TargetLibraryInfo *li) { 853 AA = &aa; 854 GFI = gfi; 855 LibInfo = li; 856 TD = DAG.getTarget().getDataLayout(); 857 Context = DAG.getContext(); 858 LPadToCallSiteMap.clear(); 859} 860 861/// clear - Clear out the current SelectionDAG and the associated 862/// state and prepare this SelectionDAGBuilder object to be used 863/// for a new block. This doesn't clear out information about 864/// additional blocks that are needed to complete switch lowering 865/// or PHI node updating; that information is cleared out as it is 866/// consumed. 867void SelectionDAGBuilder::clear() { 868 NodeMap.clear(); 869 UnusedArgNodeMap.clear(); 870 PendingLoads.clear(); 871 PendingExports.clear(); 872 CurDebugLoc = DebugLoc(); 873 HasTailCall = false; 874} 875 876/// clearDanglingDebugInfo - Clear the dangling debug information 877/// map. This function is separated from the clear so that debug 878/// information that is dangling in a basic block can be properly 879/// resolved in a different basic block. This allows the 880/// SelectionDAG to resolve dangling debug information attached 881/// to PHI nodes. 882void SelectionDAGBuilder::clearDanglingDebugInfo() { 883 DanglingDebugInfoMap.clear(); 884} 885 886/// getRoot - Return the current virtual root of the Selection DAG, 887/// flushing any PendingLoad items. This must be done before emitting 888/// a store or any other node that may need to be ordered after any 889/// prior load instructions. 890/// 891SDValue SelectionDAGBuilder::getRoot() { 892 if (PendingLoads.empty()) 893 return DAG.getRoot(); 894 895 if (PendingLoads.size() == 1) { 896 SDValue Root = PendingLoads[0]; 897 DAG.setRoot(Root); 898 PendingLoads.clear(); 899 return Root; 900 } 901 902 // Otherwise, we have to make a token factor node. 903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingLoads[0], PendingLoads.size()); 905 PendingLoads.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910/// getControlRoot - Similar to getRoot, but instead of flushing all the 911/// PendingLoad items, flush all the PendingExports items. It is necessary 912/// to do this before emitting a terminator instruction. 913/// 914SDValue SelectionDAGBuilder::getControlRoot() { 915 SDValue Root = DAG.getRoot(); 916 917 if (PendingExports.empty()) 918 return Root; 919 920 // Turn all of the CopyToReg chains into one factored node. 921 if (Root.getOpcode() != ISD::EntryToken) { 922 unsigned i = 0, e = PendingExports.size(); 923 for (; i != e; ++i) { 924 assert(PendingExports[i].getNode()->getNumOperands() > 1); 925 if (PendingExports[i].getNode()->getOperand(0) == Root) 926 break; // Don't add the root if we already indirectly depend on it. 927 } 928 929 if (i == e) 930 PendingExports.push_back(Root); 931 } 932 933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 934 &PendingExports[0], 935 PendingExports.size()); 936 PendingExports.clear(); 937 DAG.setRoot(Root); 938 return Root; 939} 940 941void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 943 DAG.AssignOrdering(Node, SDNodeOrder); 944 945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 946 AssignOrderingToNode(Node->getOperand(I).getNode()); 947} 948 949void SelectionDAGBuilder::visit(const Instruction &I) { 950 // Set up outgoing PHI node register values before emitting the terminator. 951 if (isa<TerminatorInst>(&I)) 952 HandlePHINodesInSuccessorBlocks(I.getParent()); 953 954 CurDebugLoc = I.getDebugLoc(); 955 956 visit(I.getOpcode(), I); 957 958 if (!isa<TerminatorInst>(&I) && !HasTailCall) 959 CopyToExportRegsIfNeeded(&I); 960 961 CurDebugLoc = DebugLoc(); 962} 963 964void SelectionDAGBuilder::visitPHI(const PHINode &) { 965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 966} 967 968void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 969 // Note: this doesn't use InstVisitor, because it has to work with 970 // ConstantExpr's in addition to instructions. 971 switch (Opcode) { 972 default: llvm_unreachable("Unknown instruction type encountered!"); 973 // Build the switch statement using the Instruction.def file. 974#define HANDLE_INST(NUM, OPCODE, CLASS) \ 975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 976#include "llvm/IR/Instruction.def" 977 } 978 979 // Assign the ordering to the freshly created DAG nodes. 980 if (NodeMap.count(&I)) { 981 ++SDNodeOrder; 982 AssignOrderingToNode(getValue(&I).getNode()); 983 } 984} 985 986// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 987// generate the debug data structures now that we've seen its definition. 988void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 989 SDValue Val) { 990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 991 if (DDI.getDI()) { 992 const DbgValueInst *DI = DDI.getDI(); 993 DebugLoc dl = DDI.getdl(); 994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 995 MDNode *Variable = DI->getVariable(); 996 uint64_t Offset = DI->getOffset(); 997 SDDbgValue *SDV; 998 if (Val.getNode()) { 999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 1000 SDV = DAG.getDbgValue(Variable, Val.getNode(), 1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 1002 DAG.AddDbgValue(SDV, Val.getNode(), false); 1003 } 1004 } else 1005 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 1006 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1007 } 1008} 1009 1010/// getValue - Return an SDValue for the given Value. 1011SDValue SelectionDAGBuilder::getValue(const Value *V) { 1012 // If we already have an SDValue for this value, use it. It's important 1013 // to do this first, so that we don't create a CopyFromReg if we already 1014 // have a regular SDValue. 1015 SDValue &N = NodeMap[V]; 1016 if (N.getNode()) return N; 1017 1018 // If there's a virtual register allocated and initialized for this 1019 // value, use it. 1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1021 if (It != FuncInfo.ValueMap.end()) { 1022 unsigned InReg = It->second; 1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 1024 SDValue Chain = DAG.getEntryNode(); 1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1026 resolveDanglingDebugInfo(V, N); 1027 return N; 1028 } 1029 1030 // Otherwise create a new SDValue and remember it. 1031 SDValue Val = getValueImpl(V); 1032 NodeMap[V] = Val; 1033 resolveDanglingDebugInfo(V, Val); 1034 return Val; 1035} 1036 1037/// getNonRegisterValue - Return an SDValue for the given Value, but 1038/// don't look in FuncInfo.ValueMap for a virtual register. 1039SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1040 // If we already have an SDValue for this value, use it. 1041 SDValue &N = NodeMap[V]; 1042 if (N.getNode()) return N; 1043 1044 // Otherwise create a new SDValue and remember it. 1045 SDValue Val = getValueImpl(V); 1046 NodeMap[V] = Val; 1047 resolveDanglingDebugInfo(V, Val); 1048 return Val; 1049} 1050 1051/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1052/// Create an SDValue for the given value. 1053SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1054 if (const Constant *C = dyn_cast<Constant>(V)) { 1055 EVT VT = TLI.getValueType(V->getType(), true); 1056 1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1058 return DAG.getConstant(*CI, VT); 1059 1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1062 1063 if (isa<ConstantPointerNull>(C)) 1064 return DAG.getConstant(0, TLI.getPointerTy()); 1065 1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1067 return DAG.getConstantFP(*CFP, VT); 1068 1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1070 return DAG.getUNDEF(VT); 1071 1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1073 visit(CE->getOpcode(), *CE); 1074 SDValue N1 = NodeMap[V]; 1075 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1076 return N1; 1077 } 1078 1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1080 SmallVector<SDValue, 4> Constants; 1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1082 OI != OE; ++OI) { 1083 SDNode *Val = getValue(*OI).getNode(); 1084 // If the operand is an empty aggregate, there are no values. 1085 if (!Val) continue; 1086 // Add each leaf value from the operand to the Constants list 1087 // to form a flattened list of all the values. 1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1089 Constants.push_back(SDValue(Val, i)); 1090 } 1091 1092 return DAG.getMergeValues(&Constants[0], Constants.size(), 1093 getCurDebugLoc()); 1094 } 1095 1096 if (const ConstantDataSequential *CDS = 1097 dyn_cast<ConstantDataSequential>(C)) { 1098 SmallVector<SDValue, 4> Ops; 1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1101 // Add each leaf value from the operand to the Constants list 1102 // to form a flattened list of all the values. 1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1104 Ops.push_back(SDValue(Val, i)); 1105 } 1106 1107 if (isa<ArrayType>(CDS->getType())) 1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1115 "Unknown struct or array constant!"); 1116 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1119 unsigned NumElts = ValueVTs.size(); 1120 if (NumElts == 0) 1121 return SDValue(); // empty struct 1122 SmallVector<SDValue, 4> Constants(NumElts); 1123 for (unsigned i = 0; i != NumElts; ++i) { 1124 EVT EltVT = ValueVTs[i]; 1125 if (isa<UndefValue>(C)) 1126 Constants[i] = DAG.getUNDEF(EltVT); 1127 else if (EltVT.isFloatingPoint()) 1128 Constants[i] = DAG.getConstantFP(0, EltVT); 1129 else 1130 Constants[i] = DAG.getConstant(0, EltVT); 1131 } 1132 1133 return DAG.getMergeValues(&Constants[0], NumElts, 1134 getCurDebugLoc()); 1135 } 1136 1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1138 return DAG.getBlockAddress(BA, VT); 1139 1140 VectorType *VecTy = cast<VectorType>(V->getType()); 1141 unsigned NumElements = VecTy->getNumElements(); 1142 1143 // Now that we know the number and type of the elements, get that number of 1144 // elements into the Ops array based on what kind of constant it is. 1145 SmallVector<SDValue, 16> Ops; 1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1147 for (unsigned i = 0; i != NumElements; ++i) 1148 Ops.push_back(getValue(CV->getOperand(i))); 1149 } else { 1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1151 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1152 1153 SDValue Op; 1154 if (EltVT.isFloatingPoint()) 1155 Op = DAG.getConstantFP(0, EltVT); 1156 else 1157 Op = DAG.getConstant(0, EltVT); 1158 Ops.assign(NumElements, Op); 1159 } 1160 1161 // Create a BUILD_VECTOR node. 1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1163 VT, &Ops[0], Ops.size()); 1164 } 1165 1166 // If this is a static alloca, generate it as the frameindex instead of 1167 // computation. 1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1169 DenseMap<const AllocaInst*, int>::iterator SI = 1170 FuncInfo.StaticAllocaMap.find(AI); 1171 if (SI != FuncInfo.StaticAllocaMap.end()) 1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1173 } 1174 1175 // If this is an instruction which fast-isel has deferred, select it now. 1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1179 SDValue Chain = DAG.getEntryNode(); 1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1181 } 1182 1183 llvm_unreachable("Can't get register for value!"); 1184} 1185 1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1187 SDValue Chain = getControlRoot(); 1188 SmallVector<ISD::OutputArg, 8> Outs; 1189 SmallVector<SDValue, 8> OutVals; 1190 1191 if (!FuncInfo.CanLowerReturn) { 1192 unsigned DemoteReg = FuncInfo.DemoteRegister; 1193 const Function *F = I.getParent()->getParent(); 1194 1195 // Emit a store of the return value through the virtual register. 1196 // Leave Outs empty so that LowerReturn won't try to load return 1197 // registers the usual way. 1198 SmallVector<EVT, 1> PtrValueVTs; 1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1200 PtrValueVTs); 1201 1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1203 SDValue RetOp = getValue(I.getOperand(0)); 1204 1205 SmallVector<EVT, 4> ValueVTs; 1206 SmallVector<uint64_t, 4> Offsets; 1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1208 unsigned NumValues = ValueVTs.size(); 1209 1210 SmallVector<SDValue, 4> Chains(NumValues); 1211 for (unsigned i = 0; i != NumValues; ++i) { 1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1213 RetPtr.getValueType(), RetPtr, 1214 DAG.getIntPtrConstant(Offsets[i])); 1215 Chains[i] = 1216 DAG.getStore(Chain, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1218 // FIXME: better loc info would be nice. 1219 Add, MachinePointerInfo(), false, false, 0); 1220 } 1221 1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1223 MVT::Other, &Chains[0], NumValues); 1224 } else if (I.getNumOperands() != 0) { 1225 SmallVector<EVT, 4> ValueVTs; 1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1227 unsigned NumValues = ValueVTs.size(); 1228 if (NumValues) { 1229 SDValue RetOp = getValue(I.getOperand(0)); 1230 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1231 EVT VT = ValueVTs[j]; 1232 1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1234 1235 const Function *F = I.getParent()->getParent(); 1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1237 Attribute::SExt)) 1238 ExtendKind = ISD::SIGN_EXTEND; 1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1240 Attribute::ZExt)) 1241 ExtendKind = ISD::ZERO_EXTEND; 1242 1243 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1244 VT = TLI.getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind); 1245 1246 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1247 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1248 SmallVector<SDValue, 4> Parts(NumParts); 1249 getCopyToParts(DAG, getCurDebugLoc(), 1250 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1251 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1252 1253 // 'inreg' on function refers to return value 1254 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1255 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1256 Attribute::InReg)) 1257 Flags.setInReg(); 1258 1259 // Propagate extension type if any 1260 if (ExtendKind == ISD::SIGN_EXTEND) 1261 Flags.setSExt(); 1262 else if (ExtendKind == ISD::ZERO_EXTEND) 1263 Flags.setZExt(); 1264 1265 for (unsigned i = 0; i < NumParts; ++i) { 1266 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1267 /*isfixed=*/true, 0, 0)); 1268 OutVals.push_back(Parts[i]); 1269 } 1270 } 1271 } 1272 } 1273 1274 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1275 CallingConv::ID CallConv = 1276 DAG.getMachineFunction().getFunction()->getCallingConv(); 1277 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1278 Outs, OutVals, getCurDebugLoc(), DAG); 1279 1280 // Verify that the target's LowerReturn behaved as expected. 1281 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1282 "LowerReturn didn't return a valid chain!"); 1283 1284 // Update the DAG with the new chain value resulting from return lowering. 1285 DAG.setRoot(Chain); 1286} 1287 1288/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1289/// created for it, emit nodes to copy the value into the virtual 1290/// registers. 1291void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1292 // Skip empty types 1293 if (V->getType()->isEmptyTy()) 1294 return; 1295 1296 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1297 if (VMI != FuncInfo.ValueMap.end()) { 1298 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1299 CopyValueToVirtualRegister(V, VMI->second); 1300 } 1301} 1302 1303/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1304/// the current basic block, add it to ValueMap now so that we'll get a 1305/// CopyTo/FromReg. 1306void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1307 // No need to export constants. 1308 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1309 1310 // Already exported? 1311 if (FuncInfo.isExportedInst(V)) return; 1312 1313 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1314 CopyValueToVirtualRegister(V, Reg); 1315} 1316 1317bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1318 const BasicBlock *FromBB) { 1319 // The operands of the setcc have to be in this block. We don't know 1320 // how to export them from some other block. 1321 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1322 // Can export from current BB. 1323 if (VI->getParent() == FromBB) 1324 return true; 1325 1326 // Is already exported, noop. 1327 return FuncInfo.isExportedInst(V); 1328 } 1329 1330 // If this is an argument, we can export it if the BB is the entry block or 1331 // if it is already exported. 1332 if (isa<Argument>(V)) { 1333 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1334 return true; 1335 1336 // Otherwise, can only export this if it is already exported. 1337 return FuncInfo.isExportedInst(V); 1338 } 1339 1340 // Otherwise, constants can always be exported. 1341 return true; 1342} 1343 1344/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1345uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1346 const MachineBasicBlock *Dst) const { 1347 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1348 if (!BPI) 1349 return 0; 1350 const BasicBlock *SrcBB = Src->getBasicBlock(); 1351 const BasicBlock *DstBB = Dst->getBasicBlock(); 1352 return BPI->getEdgeWeight(SrcBB, DstBB); 1353} 1354 1355void SelectionDAGBuilder:: 1356addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1357 uint32_t Weight /* = 0 */) { 1358 if (!Weight) 1359 Weight = getEdgeWeight(Src, Dst); 1360 Src->addSuccessor(Dst, Weight); 1361} 1362 1363 1364static bool InBlock(const Value *V, const BasicBlock *BB) { 1365 if (const Instruction *I = dyn_cast<Instruction>(V)) 1366 return I->getParent() == BB; 1367 return true; 1368} 1369 1370/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1371/// This function emits a branch and is used at the leaves of an OR or an 1372/// AND operator tree. 1373/// 1374void 1375SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1376 MachineBasicBlock *TBB, 1377 MachineBasicBlock *FBB, 1378 MachineBasicBlock *CurBB, 1379 MachineBasicBlock *SwitchBB) { 1380 const BasicBlock *BB = CurBB->getBasicBlock(); 1381 1382 // If the leaf of the tree is a comparison, merge the condition into 1383 // the caseblock. 1384 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1385 // The operands of the cmp have to be in this block. We don't know 1386 // how to export them from some other block. If this is the first block 1387 // of the sequence, no exporting is needed. 1388 if (CurBB == SwitchBB || 1389 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1390 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1391 ISD::CondCode Condition; 1392 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1393 Condition = getICmpCondCode(IC->getPredicate()); 1394 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1395 Condition = getFCmpCondCode(FC->getPredicate()); 1396 if (TM.Options.NoNaNsFPMath) 1397 Condition = getFCmpCodeWithoutNaN(Condition); 1398 } else { 1399 Condition = ISD::SETEQ; // silence warning. 1400 llvm_unreachable("Unknown compare instruction"); 1401 } 1402 1403 CaseBlock CB(Condition, BOp->getOperand(0), 1404 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1405 SwitchCases.push_back(CB); 1406 return; 1407 } 1408 } 1409 1410 // Create a CaseBlock record representing this branch. 1411 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1412 NULL, TBB, FBB, CurBB); 1413 SwitchCases.push_back(CB); 1414} 1415 1416/// FindMergedConditions - If Cond is an expression like 1417void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1418 MachineBasicBlock *TBB, 1419 MachineBasicBlock *FBB, 1420 MachineBasicBlock *CurBB, 1421 MachineBasicBlock *SwitchBB, 1422 unsigned Opc) { 1423 // If this node is not part of the or/and tree, emit it as a branch. 1424 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1425 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1426 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1427 BOp->getParent() != CurBB->getBasicBlock() || 1428 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1429 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1430 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1431 return; 1432 } 1433 1434 // Create TmpBB after CurBB. 1435 MachineFunction::iterator BBI = CurBB; 1436 MachineFunction &MF = DAG.getMachineFunction(); 1437 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1438 CurBB->getParent()->insert(++BBI, TmpBB); 1439 1440 if (Opc == Instruction::Or) { 1441 // Codegen X | Y as: 1442 // jmp_if_X TBB 1443 // jmp TmpBB 1444 // TmpBB: 1445 // jmp_if_Y TBB 1446 // jmp FBB 1447 // 1448 1449 // Emit the LHS condition. 1450 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1451 1452 // Emit the RHS condition into TmpBB. 1453 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1454 } else { 1455 assert(Opc == Instruction::And && "Unknown merge op!"); 1456 // Codegen X & Y as: 1457 // jmp_if_X TmpBB 1458 // jmp FBB 1459 // TmpBB: 1460 // jmp_if_Y TBB 1461 // jmp FBB 1462 // 1463 // This requires creation of TmpBB after CurBB. 1464 1465 // Emit the LHS condition. 1466 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1467 1468 // Emit the RHS condition into TmpBB. 1469 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1470 } 1471} 1472 1473/// If the set of cases should be emitted as a series of branches, return true. 1474/// If we should emit this as a bunch of and/or'd together conditions, return 1475/// false. 1476bool 1477SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1478 if (Cases.size() != 2) return true; 1479 1480 // If this is two comparisons of the same values or'd or and'd together, they 1481 // will get folded into a single comparison, so don't emit two blocks. 1482 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1483 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1484 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1485 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1486 return false; 1487 } 1488 1489 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1490 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1491 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1492 Cases[0].CC == Cases[1].CC && 1493 isa<Constant>(Cases[0].CmpRHS) && 1494 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1495 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1496 return false; 1497 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1498 return false; 1499 } 1500 1501 return true; 1502} 1503 1504void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1505 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1506 1507 // Update machine-CFG edges. 1508 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1509 1510 // Figure out which block is immediately after the current one. 1511 MachineBasicBlock *NextBlock = 0; 1512 MachineFunction::iterator BBI = BrMBB; 1513 if (++BBI != FuncInfo.MF->end()) 1514 NextBlock = BBI; 1515 1516 if (I.isUnconditional()) { 1517 // Update machine-CFG edges. 1518 BrMBB->addSuccessor(Succ0MBB); 1519 1520 // If this is not a fall-through branch, emit the branch. 1521 if (Succ0MBB != NextBlock) 1522 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1523 MVT::Other, getControlRoot(), 1524 DAG.getBasicBlock(Succ0MBB))); 1525 1526 return; 1527 } 1528 1529 // If this condition is one of the special cases we handle, do special stuff 1530 // now. 1531 const Value *CondVal = I.getCondition(); 1532 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1533 1534 // If this is a series of conditions that are or'd or and'd together, emit 1535 // this as a sequence of branches instead of setcc's with and/or operations. 1536 // As long as jumps are not expensive, this should improve performance. 1537 // For example, instead of something like: 1538 // cmp A, B 1539 // C = seteq 1540 // cmp D, E 1541 // F = setle 1542 // or C, F 1543 // jnz foo 1544 // Emit: 1545 // cmp A, B 1546 // je foo 1547 // cmp D, E 1548 // jle foo 1549 // 1550 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1551 if (!TLI.isJumpExpensive() && 1552 BOp->hasOneUse() && 1553 (BOp->getOpcode() == Instruction::And || 1554 BOp->getOpcode() == Instruction::Or)) { 1555 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1556 BOp->getOpcode()); 1557 // If the compares in later blocks need to use values not currently 1558 // exported from this block, export them now. This block should always 1559 // be the first entry. 1560 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1561 1562 // Allow some cases to be rejected. 1563 if (ShouldEmitAsBranches(SwitchCases)) { 1564 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1565 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1566 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1567 } 1568 1569 // Emit the branch for this block. 1570 visitSwitchCase(SwitchCases[0], BrMBB); 1571 SwitchCases.erase(SwitchCases.begin()); 1572 return; 1573 } 1574 1575 // Okay, we decided not to do this, remove any inserted MBB's and clear 1576 // SwitchCases. 1577 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1578 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1579 1580 SwitchCases.clear(); 1581 } 1582 } 1583 1584 // Create a CaseBlock record representing this branch. 1585 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1586 NULL, Succ0MBB, Succ1MBB, BrMBB); 1587 1588 // Use visitSwitchCase to actually insert the fast branch sequence for this 1589 // cond branch. 1590 visitSwitchCase(CB, BrMBB); 1591} 1592 1593/// visitSwitchCase - Emits the necessary code to represent a single node in 1594/// the binary search tree resulting from lowering a switch instruction. 1595void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1596 MachineBasicBlock *SwitchBB) { 1597 SDValue Cond; 1598 SDValue CondLHS = getValue(CB.CmpLHS); 1599 DebugLoc dl = getCurDebugLoc(); 1600 1601 // Build the setcc now. 1602 if (CB.CmpMHS == NULL) { 1603 // Fold "(X == true)" to X and "(X == false)" to !X to 1604 // handle common cases produced by branch lowering. 1605 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1606 CB.CC == ISD::SETEQ) 1607 Cond = CondLHS; 1608 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1609 CB.CC == ISD::SETEQ) { 1610 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1611 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1612 } else 1613 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1614 } else { 1615 assert(CB.CC == ISD::SETCC_INVALID && 1616 "Condition is undefined for to-the-range belonging check."); 1617 1618 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1619 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1620 1621 SDValue CmpOp = getValue(CB.CmpMHS); 1622 EVT VT = CmpOp.getValueType(); 1623 1624 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1625 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1626 ISD::SETULE); 1627 } else { 1628 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1629 VT, CmpOp, DAG.getConstant(Low, VT)); 1630 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1631 DAG.getConstant(High-Low, VT), ISD::SETULE); 1632 } 1633 } 1634 1635 // Update successor info 1636 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1637 // TrueBB and FalseBB are always different unless the incoming IR is 1638 // degenerate. This only happens when running llc on weird IR. 1639 if (CB.TrueBB != CB.FalseBB) 1640 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1641 1642 // Set NextBlock to be the MBB immediately after the current one, if any. 1643 // This is used to avoid emitting unnecessary branches to the next block. 1644 MachineBasicBlock *NextBlock = 0; 1645 MachineFunction::iterator BBI = SwitchBB; 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 // If the lhs block is the next block, invert the condition so that we can 1650 // fall through to the lhs instead of the rhs block. 1651 if (CB.TrueBB == NextBlock) { 1652 std::swap(CB.TrueBB, CB.FalseBB); 1653 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1654 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1655 } 1656 1657 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1658 MVT::Other, getControlRoot(), Cond, 1659 DAG.getBasicBlock(CB.TrueBB)); 1660 1661 // Insert the false branch. Do this even if it's a fall through branch, 1662 // this makes it easier to do DAG optimizations which require inverting 1663 // the branch condition. 1664 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1665 DAG.getBasicBlock(CB.FalseBB)); 1666 1667 DAG.setRoot(BrCond); 1668} 1669 1670/// visitJumpTable - Emit JumpTable node in the current MBB 1671void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1672 // Emit the code for the jump table 1673 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1674 EVT PTy = TLI.getPointerTy(); 1675 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1676 JT.Reg, PTy); 1677 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1678 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1679 MVT::Other, Index.getValue(1), 1680 Table, Index); 1681 DAG.setRoot(BrJumpTable); 1682} 1683 1684/// visitJumpTableHeader - This function emits necessary code to produce index 1685/// in the JumpTable from switch case. 1686void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1687 JumpTableHeader &JTH, 1688 MachineBasicBlock *SwitchBB) { 1689 // Subtract the lowest switch case value from the value being switched on and 1690 // conditional branch to default mbb if the result is greater than the 1691 // difference between smallest and largest cases. 1692 SDValue SwitchOp = getValue(JTH.SValue); 1693 EVT VT = SwitchOp.getValueType(); 1694 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1695 DAG.getConstant(JTH.First, VT)); 1696 1697 // The SDNode we just created, which holds the value being switched on minus 1698 // the smallest case value, needs to be copied to a virtual register so it 1699 // can be used as an index into the jump table in a subsequent basic block. 1700 // This value may be smaller or larger than the target's pointer type, and 1701 // therefore require extension or truncating. 1702 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1703 1704 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1705 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1706 JumpTableReg, SwitchOp); 1707 JT.Reg = JumpTableReg; 1708 1709 // Emit the range check for the jump table, and branch to the default block 1710 // for the switch statement if the value being switched on exceeds the largest 1711 // case in the switch. 1712 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1713 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1714 DAG.getConstant(JTH.Last-JTH.First,VT), 1715 ISD::SETUGT); 1716 1717 // Set NextBlock to be the MBB immediately after the current one, if any. 1718 // This is used to avoid emitting unnecessary branches to the next block. 1719 MachineBasicBlock *NextBlock = 0; 1720 MachineFunction::iterator BBI = SwitchBB; 1721 1722 if (++BBI != FuncInfo.MF->end()) 1723 NextBlock = BBI; 1724 1725 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1726 MVT::Other, CopyTo, CMP, 1727 DAG.getBasicBlock(JT.Default)); 1728 1729 if (JT.MBB != NextBlock) 1730 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1731 DAG.getBasicBlock(JT.MBB)); 1732 1733 DAG.setRoot(BrCond); 1734} 1735 1736/// visitBitTestHeader - This function emits necessary code to produce value 1737/// suitable for "bit tests" 1738void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1739 MachineBasicBlock *SwitchBB) { 1740 // Subtract the minimum value 1741 SDValue SwitchOp = getValue(B.SValue); 1742 EVT VT = SwitchOp.getValueType(); 1743 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1744 DAG.getConstant(B.First, VT)); 1745 1746 // Check range 1747 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1748 TLI.getSetCCResultType(Sub.getValueType()), 1749 Sub, DAG.getConstant(B.Range, VT), 1750 ISD::SETUGT); 1751 1752 // Determine the type of the test operands. 1753 bool UsePtrType = false; 1754 if (!TLI.isTypeLegal(VT)) 1755 UsePtrType = true; 1756 else { 1757 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1758 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1759 // Switch table case range are encoded into series of masks. 1760 // Just use pointer type, it's guaranteed to fit. 1761 UsePtrType = true; 1762 break; 1763 } 1764 } 1765 if (UsePtrType) { 1766 VT = TLI.getPointerTy(); 1767 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1768 } 1769 1770 B.RegVT = VT.getSimpleVT(); 1771 B.Reg = FuncInfo.CreateReg(B.RegVT); 1772 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1773 B.Reg, Sub); 1774 1775 // Set NextBlock to be the MBB immediately after the current one, if any. 1776 // This is used to avoid emitting unnecessary branches to the next block. 1777 MachineBasicBlock *NextBlock = 0; 1778 MachineFunction::iterator BBI = SwitchBB; 1779 if (++BBI != FuncInfo.MF->end()) 1780 NextBlock = BBI; 1781 1782 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1783 1784 addSuccessorWithWeight(SwitchBB, B.Default); 1785 addSuccessorWithWeight(SwitchBB, MBB); 1786 1787 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1788 MVT::Other, CopyTo, RangeCmp, 1789 DAG.getBasicBlock(B.Default)); 1790 1791 if (MBB != NextBlock) 1792 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1793 DAG.getBasicBlock(MBB)); 1794 1795 DAG.setRoot(BrRange); 1796} 1797 1798/// visitBitTestCase - this function produces one "bit test" 1799void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1800 MachineBasicBlock* NextMBB, 1801 uint32_t BranchWeightToNext, 1802 unsigned Reg, 1803 BitTestCase &B, 1804 MachineBasicBlock *SwitchBB) { 1805 MVT VT = BB.RegVT; 1806 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1807 Reg, VT); 1808 SDValue Cmp; 1809 unsigned PopCount = CountPopulation_64(B.Mask); 1810 if (PopCount == 1) { 1811 // Testing for a single bit; just compare the shift count with what it 1812 // would need to be to shift a 1 bit in that position. 1813 Cmp = DAG.getSetCC(getCurDebugLoc(), 1814 TLI.getSetCCResultType(VT), 1815 ShiftOp, 1816 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1817 ISD::SETEQ); 1818 } else if (PopCount == BB.Range) { 1819 // There is only one zero bit in the range, test for it directly. 1820 Cmp = DAG.getSetCC(getCurDebugLoc(), 1821 TLI.getSetCCResultType(VT), 1822 ShiftOp, 1823 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1824 ISD::SETNE); 1825 } else { 1826 // Make desired shift 1827 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1828 DAG.getConstant(1, VT), ShiftOp); 1829 1830 // Emit bit tests and jumps 1831 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1832 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1833 Cmp = DAG.getSetCC(getCurDebugLoc(), 1834 TLI.getSetCCResultType(VT), 1835 AndOp, DAG.getConstant(0, VT), 1836 ISD::SETNE); 1837 } 1838 1839 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1840 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1841 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1842 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1843 1844 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1845 MVT::Other, getControlRoot(), 1846 Cmp, DAG.getBasicBlock(B.TargetBB)); 1847 1848 // Set NextBlock to be the MBB immediately after the current one, if any. 1849 // This is used to avoid emitting unnecessary branches to the next block. 1850 MachineBasicBlock *NextBlock = 0; 1851 MachineFunction::iterator BBI = SwitchBB; 1852 if (++BBI != FuncInfo.MF->end()) 1853 NextBlock = BBI; 1854 1855 if (NextMBB != NextBlock) 1856 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1857 DAG.getBasicBlock(NextMBB)); 1858 1859 DAG.setRoot(BrAnd); 1860} 1861 1862void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1863 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1864 1865 // Retrieve successors. 1866 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1867 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1868 1869 const Value *Callee(I.getCalledValue()); 1870 const Function *Fn = dyn_cast<Function>(Callee); 1871 if (isa<InlineAsm>(Callee)) 1872 visitInlineAsm(&I); 1873 else if (Fn && Fn->isIntrinsic()) { 1874 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1875 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1876 } else 1877 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1878 1879 // If the value of the invoke is used outside of its defining block, make it 1880 // available as a virtual register. 1881 CopyToExportRegsIfNeeded(&I); 1882 1883 // Update successor info 1884 addSuccessorWithWeight(InvokeMBB, Return); 1885 addSuccessorWithWeight(InvokeMBB, LandingPad); 1886 1887 // Drop into normal successor. 1888 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1889 MVT::Other, getControlRoot(), 1890 DAG.getBasicBlock(Return))); 1891} 1892 1893void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1894 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1895} 1896 1897void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1898 assert(FuncInfo.MBB->isLandingPad() && 1899 "Call to landingpad not in landing pad!"); 1900 1901 MachineBasicBlock *MBB = FuncInfo.MBB; 1902 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1903 AddLandingPadInfo(LP, MMI, MBB); 1904 1905 // If there aren't registers to copy the values into (e.g., during SjLj 1906 // exceptions), then don't bother to create these DAG nodes. 1907 if (TLI.getExceptionPointerRegister() == 0 && 1908 TLI.getExceptionSelectorRegister() == 0) 1909 return; 1910 1911 SmallVector<EVT, 2> ValueVTs; 1912 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1913 1914 // Insert the EXCEPTIONADDR instruction. 1915 assert(FuncInfo.MBB->isLandingPad() && 1916 "Call to eh.exception not in landing pad!"); 1917 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1918 SDValue Ops[2]; 1919 Ops[0] = DAG.getRoot(); 1920 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1921 SDValue Chain = Op1.getValue(1); 1922 1923 // Insert the EHSELECTION instruction. 1924 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1925 Ops[0] = Op1; 1926 Ops[1] = Chain; 1927 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1928 Chain = Op2.getValue(1); 1929 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1930 1931 Ops[0] = Op1; 1932 Ops[1] = Op2; 1933 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1934 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1935 &Ops[0], 2); 1936 1937 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1938 setValue(&LP, RetPair.first); 1939 DAG.setRoot(RetPair.second); 1940} 1941 1942/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1943/// small case ranges). 1944bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1945 CaseRecVector& WorkList, 1946 const Value* SV, 1947 MachineBasicBlock *Default, 1948 MachineBasicBlock *SwitchBB) { 1949 // Size is the number of Cases represented by this range. 1950 size_t Size = CR.Range.second - CR.Range.first; 1951 if (Size > 3) 1952 return false; 1953 1954 // Get the MachineFunction which holds the current MBB. This is used when 1955 // inserting any additional MBBs necessary to represent the switch. 1956 MachineFunction *CurMF = FuncInfo.MF; 1957 1958 // Figure out which block is immediately after the current one. 1959 MachineBasicBlock *NextBlock = 0; 1960 MachineFunction::iterator BBI = CR.CaseBB; 1961 1962 if (++BBI != FuncInfo.MF->end()) 1963 NextBlock = BBI; 1964 1965 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1966 // If any two of the cases has the same destination, and if one value 1967 // is the same as the other, but has one bit unset that the other has set, 1968 // use bit manipulation to do two compares at once. For example: 1969 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1970 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1971 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1972 if (Size == 2 && CR.CaseBB == SwitchBB) { 1973 Case &Small = *CR.Range.first; 1974 Case &Big = *(CR.Range.second-1); 1975 1976 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1977 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1978 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1979 1980 // Check that there is only one bit different. 1981 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1982 (SmallValue | BigValue) == BigValue) { 1983 // Isolate the common bit. 1984 APInt CommonBit = BigValue & ~SmallValue; 1985 assert((SmallValue | CommonBit) == BigValue && 1986 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1987 1988 SDValue CondLHS = getValue(SV); 1989 EVT VT = CondLHS.getValueType(); 1990 DebugLoc DL = getCurDebugLoc(); 1991 1992 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1993 DAG.getConstant(CommonBit, VT)); 1994 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1995 Or, DAG.getConstant(BigValue, VT), 1996 ISD::SETEQ); 1997 1998 // Update successor info. 1999 // Both Small and Big will jump to Small.BB, so we sum up the weights. 2000 addSuccessorWithWeight(SwitchBB, Small.BB, 2001 Small.ExtraWeight + Big.ExtraWeight); 2002 addSuccessorWithWeight(SwitchBB, Default, 2003 // The default destination is the first successor in IR. 2004 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2005 2006 // Insert the true branch. 2007 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2008 getControlRoot(), Cond, 2009 DAG.getBasicBlock(Small.BB)); 2010 2011 // Insert the false branch. 2012 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2013 DAG.getBasicBlock(Default)); 2014 2015 DAG.setRoot(BrCond); 2016 return true; 2017 } 2018 } 2019 } 2020 2021 // Order cases by weight so the most likely case will be checked first. 2022 uint32_t UnhandledWeights = 0; 2023 if (BPI) { 2024 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2025 uint32_t IWeight = I->ExtraWeight; 2026 UnhandledWeights += IWeight; 2027 for (CaseItr J = CR.Range.first; J < I; ++J) { 2028 uint32_t JWeight = J->ExtraWeight; 2029 if (IWeight > JWeight) 2030 std::swap(*I, *J); 2031 } 2032 } 2033 } 2034 // Rearrange the case blocks so that the last one falls through if possible. 2035 Case &BackCase = *(CR.Range.second-1); 2036 if (Size > 1 && 2037 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2038 // The last case block won't fall through into 'NextBlock' if we emit the 2039 // branches in this order. See if rearranging a case value would help. 2040 // We start at the bottom as it's the case with the least weight. 2041 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 2042 if (I->BB == NextBlock) { 2043 std::swap(*I, BackCase); 2044 break; 2045 } 2046 } 2047 } 2048 2049 // Create a CaseBlock record representing a conditional branch to 2050 // the Case's target mbb if the value being switched on SV is equal 2051 // to C. 2052 MachineBasicBlock *CurBlock = CR.CaseBB; 2053 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2054 MachineBasicBlock *FallThrough; 2055 if (I != E-1) { 2056 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2057 CurMF->insert(BBI, FallThrough); 2058 2059 // Put SV in a virtual register to make it available from the new blocks. 2060 ExportFromCurrentBlock(SV); 2061 } else { 2062 // If the last case doesn't match, go to the default block. 2063 FallThrough = Default; 2064 } 2065 2066 const Value *RHS, *LHS, *MHS; 2067 ISD::CondCode CC; 2068 if (I->High == I->Low) { 2069 // This is just small small case range :) containing exactly 1 case 2070 CC = ISD::SETEQ; 2071 LHS = SV; RHS = I->High; MHS = NULL; 2072 } else { 2073 CC = ISD::SETCC_INVALID; 2074 LHS = I->Low; MHS = SV; RHS = I->High; 2075 } 2076 2077 // The false weight should be sum of all un-handled cases. 2078 UnhandledWeights -= I->ExtraWeight; 2079 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2080 /* me */ CurBlock, 2081 /* trueweight */ I->ExtraWeight, 2082 /* falseweight */ UnhandledWeights); 2083 2084 // If emitting the first comparison, just call visitSwitchCase to emit the 2085 // code into the current block. Otherwise, push the CaseBlock onto the 2086 // vector to be later processed by SDISel, and insert the node's MBB 2087 // before the next MBB. 2088 if (CurBlock == SwitchBB) 2089 visitSwitchCase(CB, SwitchBB); 2090 else 2091 SwitchCases.push_back(CB); 2092 2093 CurBlock = FallThrough; 2094 } 2095 2096 return true; 2097} 2098 2099static inline bool areJTsAllowed(const TargetLowering &TLI) { 2100 return TLI.supportJumpTables() && 2101 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2102 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2103} 2104 2105static APInt ComputeRange(const APInt &First, const APInt &Last) { 2106 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2107 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2108 return (LastExt - FirstExt + 1ULL); 2109} 2110 2111/// handleJTSwitchCase - Emit jumptable for current switch case range 2112bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2113 CaseRecVector &WorkList, 2114 const Value *SV, 2115 MachineBasicBlock *Default, 2116 MachineBasicBlock *SwitchBB) { 2117 Case& FrontCase = *CR.Range.first; 2118 Case& BackCase = *(CR.Range.second-1); 2119 2120 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2121 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2122 2123 APInt TSize(First.getBitWidth(), 0); 2124 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2125 TSize += I->size(); 2126 2127 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries())) 2128 return false; 2129 2130 APInt Range = ComputeRange(First, Last); 2131 // The density is TSize / Range. Require at least 40%. 2132 // It should not be possible for IntTSize to saturate for sane code, but make 2133 // sure we handle Range saturation correctly. 2134 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2135 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2136 if (IntTSize * 10 < IntRange * 4) 2137 return false; 2138 2139 DEBUG(dbgs() << "Lowering jump table\n" 2140 << "First entry: " << First << ". Last entry: " << Last << '\n' 2141 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2142 2143 // Get the MachineFunction which holds the current MBB. This is used when 2144 // inserting any additional MBBs necessary to represent the switch. 2145 MachineFunction *CurMF = FuncInfo.MF; 2146 2147 // Figure out which block is immediately after the current one. 2148 MachineFunction::iterator BBI = CR.CaseBB; 2149 ++BBI; 2150 2151 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2152 2153 // Create a new basic block to hold the code for loading the address 2154 // of the jump table, and jumping to it. Update successor information; 2155 // we will either branch to the default case for the switch, or the jump 2156 // table. 2157 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2158 CurMF->insert(BBI, JumpTableBB); 2159 2160 addSuccessorWithWeight(CR.CaseBB, Default); 2161 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2162 2163 // Build a vector of destination BBs, corresponding to each target 2164 // of the jump table. If the value of the jump table slot corresponds to 2165 // a case statement, push the case's BB onto the vector, otherwise, push 2166 // the default BB. 2167 std::vector<MachineBasicBlock*> DestBBs; 2168 APInt TEI = First; 2169 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2170 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2171 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2172 2173 if (Low.ule(TEI) && TEI.ule(High)) { 2174 DestBBs.push_back(I->BB); 2175 if (TEI==High) 2176 ++I; 2177 } else { 2178 DestBBs.push_back(Default); 2179 } 2180 } 2181 2182 // Calculate weight for each unique destination in CR. 2183 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2184 if (FuncInfo.BPI) 2185 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2186 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2187 DestWeights.find(I->BB); 2188 if (Itr != DestWeights.end()) 2189 Itr->second += I->ExtraWeight; 2190 else 2191 DestWeights[I->BB] = I->ExtraWeight; 2192 } 2193 2194 // Update successor info. Add one edge to each unique successor. 2195 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2196 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2197 E = DestBBs.end(); I != E; ++I) { 2198 if (!SuccsHandled[(*I)->getNumber()]) { 2199 SuccsHandled[(*I)->getNumber()] = true; 2200 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2201 DestWeights.find(*I); 2202 addSuccessorWithWeight(JumpTableBB, *I, 2203 Itr != DestWeights.end() ? Itr->second : 0); 2204 } 2205 } 2206 2207 // Create a jump table index for this jump table. 2208 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2209 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2210 ->createJumpTableIndex(DestBBs); 2211 2212 // Set the jump table information so that we can codegen it as a second 2213 // MachineBasicBlock 2214 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2215 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2216 if (CR.CaseBB == SwitchBB) 2217 visitJumpTableHeader(JT, JTH, SwitchBB); 2218 2219 JTCases.push_back(JumpTableBlock(JTH, JT)); 2220 return true; 2221} 2222 2223/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2224/// 2 subtrees. 2225bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2226 CaseRecVector& WorkList, 2227 const Value* SV, 2228 MachineBasicBlock *Default, 2229 MachineBasicBlock *SwitchBB) { 2230 // Get the MachineFunction which holds the current MBB. This is used when 2231 // inserting any additional MBBs necessary to represent the switch. 2232 MachineFunction *CurMF = FuncInfo.MF; 2233 2234 // Figure out which block is immediately after the current one. 2235 MachineFunction::iterator BBI = CR.CaseBB; 2236 ++BBI; 2237 2238 Case& FrontCase = *CR.Range.first; 2239 Case& BackCase = *(CR.Range.second-1); 2240 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2241 2242 // Size is the number of Cases represented by this range. 2243 unsigned Size = CR.Range.second - CR.Range.first; 2244 2245 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2246 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2247 double FMetric = 0; 2248 CaseItr Pivot = CR.Range.first + Size/2; 2249 2250 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2251 // (heuristically) allow us to emit JumpTable's later. 2252 APInt TSize(First.getBitWidth(), 0); 2253 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2254 I!=E; ++I) 2255 TSize += I->size(); 2256 2257 APInt LSize = FrontCase.size(); 2258 APInt RSize = TSize-LSize; 2259 DEBUG(dbgs() << "Selecting best pivot: \n" 2260 << "First: " << First << ", Last: " << Last <<'\n' 2261 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2262 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2263 J!=E; ++I, ++J) { 2264 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2265 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2266 APInt Range = ComputeRange(LEnd, RBegin); 2267 assert((Range - 2ULL).isNonNegative() && 2268 "Invalid case distance"); 2269 // Use volatile double here to avoid excess precision issues on some hosts, 2270 // e.g. that use 80-bit X87 registers. 2271 volatile double LDensity = 2272 (double)LSize.roundToDouble() / 2273 (LEnd - First + 1ULL).roundToDouble(); 2274 volatile double RDensity = 2275 (double)RSize.roundToDouble() / 2276 (Last - RBegin + 1ULL).roundToDouble(); 2277 double Metric = Range.logBase2()*(LDensity+RDensity); 2278 // Should always split in some non-trivial place 2279 DEBUG(dbgs() <<"=>Step\n" 2280 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2281 << "LDensity: " << LDensity 2282 << ", RDensity: " << RDensity << '\n' 2283 << "Metric: " << Metric << '\n'); 2284 if (FMetric < Metric) { 2285 Pivot = J; 2286 FMetric = Metric; 2287 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2288 } 2289 2290 LSize += J->size(); 2291 RSize -= J->size(); 2292 } 2293 if (areJTsAllowed(TLI)) { 2294 // If our case is dense we *really* should handle it earlier! 2295 assert((FMetric > 0) && "Should handle dense range earlier!"); 2296 } else { 2297 Pivot = CR.Range.first + Size/2; 2298 } 2299 2300 CaseRange LHSR(CR.Range.first, Pivot); 2301 CaseRange RHSR(Pivot, CR.Range.second); 2302 const Constant *C = Pivot->Low; 2303 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2304 2305 // We know that we branch to the LHS if the Value being switched on is 2306 // less than the Pivot value, C. We use this to optimize our binary 2307 // tree a bit, by recognizing that if SV is greater than or equal to the 2308 // LHS's Case Value, and that Case Value is exactly one less than the 2309 // Pivot's Value, then we can branch directly to the LHS's Target, 2310 // rather than creating a leaf node for it. 2311 if ((LHSR.second - LHSR.first) == 1 && 2312 LHSR.first->High == CR.GE && 2313 cast<ConstantInt>(C)->getValue() == 2314 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2315 TrueBB = LHSR.first->BB; 2316 } else { 2317 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2318 CurMF->insert(BBI, TrueBB); 2319 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2320 2321 // Put SV in a virtual register to make it available from the new blocks. 2322 ExportFromCurrentBlock(SV); 2323 } 2324 2325 // Similar to the optimization above, if the Value being switched on is 2326 // known to be less than the Constant CR.LT, and the current Case Value 2327 // is CR.LT - 1, then we can branch directly to the target block for 2328 // the current Case Value, rather than emitting a RHS leaf node for it. 2329 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2330 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2331 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2332 FalseBB = RHSR.first->BB; 2333 } else { 2334 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2335 CurMF->insert(BBI, FalseBB); 2336 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2337 2338 // Put SV in a virtual register to make it available from the new blocks. 2339 ExportFromCurrentBlock(SV); 2340 } 2341 2342 // Create a CaseBlock record representing a conditional branch to 2343 // the LHS node if the value being switched on SV is less than C. 2344 // Otherwise, branch to LHS. 2345 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2346 2347 if (CR.CaseBB == SwitchBB) 2348 visitSwitchCase(CB, SwitchBB); 2349 else 2350 SwitchCases.push_back(CB); 2351 2352 return true; 2353} 2354 2355/// handleBitTestsSwitchCase - if current case range has few destination and 2356/// range span less, than machine word bitwidth, encode case range into series 2357/// of masks and emit bit tests with these masks. 2358bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2359 CaseRecVector& WorkList, 2360 const Value* SV, 2361 MachineBasicBlock* Default, 2362 MachineBasicBlock *SwitchBB){ 2363 EVT PTy = TLI.getPointerTy(); 2364 unsigned IntPtrBits = PTy.getSizeInBits(); 2365 2366 Case& FrontCase = *CR.Range.first; 2367 Case& BackCase = *(CR.Range.second-1); 2368 2369 // Get the MachineFunction which holds the current MBB. This is used when 2370 // inserting any additional MBBs necessary to represent the switch. 2371 MachineFunction *CurMF = FuncInfo.MF; 2372 2373 // If target does not have legal shift left, do not emit bit tests at all. 2374 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2375 return false; 2376 2377 size_t numCmps = 0; 2378 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2379 I!=E; ++I) { 2380 // Single case counts one, case range - two. 2381 numCmps += (I->Low == I->High ? 1 : 2); 2382 } 2383 2384 // Count unique destinations 2385 SmallSet<MachineBasicBlock*, 4> Dests; 2386 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2387 Dests.insert(I->BB); 2388 if (Dests.size() > 3) 2389 // Don't bother the code below, if there are too much unique destinations 2390 return false; 2391 } 2392 DEBUG(dbgs() << "Total number of unique destinations: " 2393 << Dests.size() << '\n' 2394 << "Total number of comparisons: " << numCmps << '\n'); 2395 2396 // Compute span of values. 2397 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2398 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2399 APInt cmpRange = maxValue - minValue; 2400 2401 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2402 << "Low bound: " << minValue << '\n' 2403 << "High bound: " << maxValue << '\n'); 2404 2405 if (cmpRange.uge(IntPtrBits) || 2406 (!(Dests.size() == 1 && numCmps >= 3) && 2407 !(Dests.size() == 2 && numCmps >= 5) && 2408 !(Dests.size() >= 3 && numCmps >= 6))) 2409 return false; 2410 2411 DEBUG(dbgs() << "Emitting bit tests\n"); 2412 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2413 2414 // Optimize the case where all the case values fit in a 2415 // word without having to subtract minValue. In this case, 2416 // we can optimize away the subtraction. 2417 if (maxValue.ult(IntPtrBits)) { 2418 cmpRange = maxValue; 2419 } else { 2420 lowBound = minValue; 2421 } 2422 2423 CaseBitsVector CasesBits; 2424 unsigned i, count = 0; 2425 2426 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2427 MachineBasicBlock* Dest = I->BB; 2428 for (i = 0; i < count; ++i) 2429 if (Dest == CasesBits[i].BB) 2430 break; 2431 2432 if (i == count) { 2433 assert((count < 3) && "Too much destinations to test!"); 2434 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2435 count++; 2436 } 2437 2438 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2439 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2440 2441 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2442 uint64_t hi = (highValue - lowBound).getZExtValue(); 2443 CasesBits[i].ExtraWeight += I->ExtraWeight; 2444 2445 for (uint64_t j = lo; j <= hi; j++) { 2446 CasesBits[i].Mask |= 1ULL << j; 2447 CasesBits[i].Bits++; 2448 } 2449 2450 } 2451 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2452 2453 BitTestInfo BTC; 2454 2455 // Figure out which block is immediately after the current one. 2456 MachineFunction::iterator BBI = CR.CaseBB; 2457 ++BBI; 2458 2459 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2460 2461 DEBUG(dbgs() << "Cases:\n"); 2462 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2463 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2464 << ", Bits: " << CasesBits[i].Bits 2465 << ", BB: " << CasesBits[i].BB << '\n'); 2466 2467 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2468 CurMF->insert(BBI, CaseBB); 2469 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2470 CaseBB, 2471 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2472 2473 // Put SV in a virtual register to make it available from the new blocks. 2474 ExportFromCurrentBlock(SV); 2475 } 2476 2477 BitTestBlock BTB(lowBound, cmpRange, SV, 2478 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2479 CR.CaseBB, Default, BTC); 2480 2481 if (CR.CaseBB == SwitchBB) 2482 visitBitTestHeader(BTB, SwitchBB); 2483 2484 BitTestCases.push_back(BTB); 2485 2486 return true; 2487} 2488 2489/// Clusterify - Transform simple list of Cases into list of CaseRange's 2490size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2491 const SwitchInst& SI) { 2492 2493 /// Use a shorter form of declaration, and also 2494 /// show the we want to use CRSBuilder as Clusterifier. 2495 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2496 2497 Clusterifier TheClusterifier; 2498 2499 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2500 // Start with "simple" cases 2501 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2502 i != e; ++i) { 2503 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2504 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2505 2506 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2507 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2508 } 2509 2510 TheClusterifier.optimize(); 2511 2512 size_t numCmps = 0; 2513 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2514 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2515 Clusterifier::Cluster &C = *i; 2516 // Update edge weight for the cluster. 2517 unsigned W = C.first.Weight; 2518 2519 // FIXME: Currently work with ConstantInt based numbers. 2520 // Changing it to APInt based is a pretty heavy for this commit. 2521 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2522 C.first.getHigh().toConstantInt(), C.second, W)); 2523 2524 if (C.first.getLow() != C.first.getHigh()) 2525 // A range counts double, since it requires two compares. 2526 ++numCmps; 2527 } 2528 2529 return numCmps; 2530} 2531 2532void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2533 MachineBasicBlock *Last) { 2534 // Update JTCases. 2535 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2536 if (JTCases[i].first.HeaderBB == First) 2537 JTCases[i].first.HeaderBB = Last; 2538 2539 // Update BitTestCases. 2540 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2541 if (BitTestCases[i].Parent == First) 2542 BitTestCases[i].Parent = Last; 2543} 2544 2545void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2546 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2547 2548 // Figure out which block is immediately after the current one. 2549 MachineBasicBlock *NextBlock = 0; 2550 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2551 2552 // If there is only the default destination, branch to it if it is not the 2553 // next basic block. Otherwise, just fall through. 2554 if (!SI.getNumCases()) { 2555 // Update machine-CFG edges. 2556 2557 // If this is not a fall-through branch, emit the branch. 2558 SwitchMBB->addSuccessor(Default); 2559 if (Default != NextBlock) 2560 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2561 MVT::Other, getControlRoot(), 2562 DAG.getBasicBlock(Default))); 2563 2564 return; 2565 } 2566 2567 // If there are any non-default case statements, create a vector of Cases 2568 // representing each one, and sort the vector so that we can efficiently 2569 // create a binary search tree from them. 2570 CaseVector Cases; 2571 size_t numCmps = Clusterify(Cases, SI); 2572 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2573 << ". Total compares: " << numCmps << '\n'); 2574 (void)numCmps; 2575 2576 // Get the Value to be switched on and default basic blocks, which will be 2577 // inserted into CaseBlock records, representing basic blocks in the binary 2578 // search tree. 2579 const Value *SV = SI.getCondition(); 2580 2581 // Push the initial CaseRec onto the worklist 2582 CaseRecVector WorkList; 2583 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2584 CaseRange(Cases.begin(),Cases.end()))); 2585 2586 while (!WorkList.empty()) { 2587 // Grab a record representing a case range to process off the worklist 2588 CaseRec CR = WorkList.back(); 2589 WorkList.pop_back(); 2590 2591 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2592 continue; 2593 2594 // If the range has few cases (two or less) emit a series of specific 2595 // tests. 2596 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2597 continue; 2598 2599 // If the switch has more than N blocks, and is at least 40% dense, and the 2600 // target supports indirect branches, then emit a jump table rather than 2601 // lowering the switch to a binary tree of conditional branches. 2602 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2603 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2604 continue; 2605 2606 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2607 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2608 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2609 } 2610} 2611 2612void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2613 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2614 2615 // Update machine-CFG edges with unique successors. 2616 SmallSet<BasicBlock*, 32> Done; 2617 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2618 BasicBlock *BB = I.getSuccessor(i); 2619 bool Inserted = Done.insert(BB); 2620 if (!Inserted) 2621 continue; 2622 2623 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2624 addSuccessorWithWeight(IndirectBrMBB, Succ); 2625 } 2626 2627 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2628 MVT::Other, getControlRoot(), 2629 getValue(I.getAddress()))); 2630} 2631 2632void SelectionDAGBuilder::visitFSub(const User &I) { 2633 // -0.0 - X --> fneg 2634 Type *Ty = I.getType(); 2635 if (isa<Constant>(I.getOperand(0)) && 2636 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2637 SDValue Op2 = getValue(I.getOperand(1)); 2638 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2639 Op2.getValueType(), Op2)); 2640 return; 2641 } 2642 2643 visitBinary(I, ISD::FSUB); 2644} 2645 2646void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2647 SDValue Op1 = getValue(I.getOperand(0)); 2648 SDValue Op2 = getValue(I.getOperand(1)); 2649 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2650 Op1.getValueType(), Op1, Op2)); 2651} 2652 2653void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2654 SDValue Op1 = getValue(I.getOperand(0)); 2655 SDValue Op2 = getValue(I.getOperand(1)); 2656 2657 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2658 2659 // Coerce the shift amount to the right type if we can. 2660 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2661 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2662 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2663 DebugLoc DL = getCurDebugLoc(); 2664 2665 // If the operand is smaller than the shift count type, promote it. 2666 if (ShiftSize > Op2Size) 2667 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2668 2669 // If the operand is larger than the shift count type but the shift 2670 // count type has enough bits to represent any shift value, truncate 2671 // it now. This is a common case and it exposes the truncate to 2672 // optimization early. 2673 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2674 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2675 // Otherwise we'll need to temporarily settle for some other convenient 2676 // type. Type legalization will make adjustments once the shiftee is split. 2677 else 2678 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2679 } 2680 2681 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2682 Op1.getValueType(), Op1, Op2)); 2683} 2684 2685void SelectionDAGBuilder::visitSDiv(const User &I) { 2686 SDValue Op1 = getValue(I.getOperand(0)); 2687 SDValue Op2 = getValue(I.getOperand(1)); 2688 2689 // Turn exact SDivs into multiplications. 2690 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2691 // exact bit. 2692 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2693 !isa<ConstantSDNode>(Op1) && 2694 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2695 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2696 else 2697 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2698 Op1, Op2)); 2699} 2700 2701void SelectionDAGBuilder::visitICmp(const User &I) { 2702 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2703 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2704 predicate = IC->getPredicate(); 2705 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2706 predicate = ICmpInst::Predicate(IC->getPredicate()); 2707 SDValue Op1 = getValue(I.getOperand(0)); 2708 SDValue Op2 = getValue(I.getOperand(1)); 2709 ISD::CondCode Opcode = getICmpCondCode(predicate); 2710 2711 EVT DestVT = TLI.getValueType(I.getType()); 2712 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2713} 2714 2715void SelectionDAGBuilder::visitFCmp(const User &I) { 2716 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2717 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2718 predicate = FC->getPredicate(); 2719 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2720 predicate = FCmpInst::Predicate(FC->getPredicate()); 2721 SDValue Op1 = getValue(I.getOperand(0)); 2722 SDValue Op2 = getValue(I.getOperand(1)); 2723 ISD::CondCode Condition = getFCmpCondCode(predicate); 2724 if (TM.Options.NoNaNsFPMath) 2725 Condition = getFCmpCodeWithoutNaN(Condition); 2726 EVT DestVT = TLI.getValueType(I.getType()); 2727 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2728} 2729 2730void SelectionDAGBuilder::visitSelect(const User &I) { 2731 SmallVector<EVT, 4> ValueVTs; 2732 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2733 unsigned NumValues = ValueVTs.size(); 2734 if (NumValues == 0) return; 2735 2736 SmallVector<SDValue, 4> Values(NumValues); 2737 SDValue Cond = getValue(I.getOperand(0)); 2738 SDValue TrueVal = getValue(I.getOperand(1)); 2739 SDValue FalseVal = getValue(I.getOperand(2)); 2740 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2741 ISD::VSELECT : ISD::SELECT; 2742 2743 for (unsigned i = 0; i != NumValues; ++i) 2744 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2745 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2746 Cond, 2747 SDValue(TrueVal.getNode(), 2748 TrueVal.getResNo() + i), 2749 SDValue(FalseVal.getNode(), 2750 FalseVal.getResNo() + i)); 2751 2752 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2753 DAG.getVTList(&ValueVTs[0], NumValues), 2754 &Values[0], NumValues)); 2755} 2756 2757void SelectionDAGBuilder::visitTrunc(const User &I) { 2758 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2759 SDValue N = getValue(I.getOperand(0)); 2760 EVT DestVT = TLI.getValueType(I.getType()); 2761 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2762} 2763 2764void SelectionDAGBuilder::visitZExt(const User &I) { 2765 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2766 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2767 SDValue N = getValue(I.getOperand(0)); 2768 EVT DestVT = TLI.getValueType(I.getType()); 2769 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2770} 2771 2772void SelectionDAGBuilder::visitSExt(const User &I) { 2773 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2774 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2775 SDValue N = getValue(I.getOperand(0)); 2776 EVT DestVT = TLI.getValueType(I.getType()); 2777 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2778} 2779 2780void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2781 // FPTrunc is never a no-op cast, no need to check 2782 SDValue N = getValue(I.getOperand(0)); 2783 EVT DestVT = TLI.getValueType(I.getType()); 2784 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2785 DestVT, N, 2786 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2787} 2788 2789void SelectionDAGBuilder::visitFPExt(const User &I){ 2790 // FPExt is never a no-op cast, no need to check 2791 SDValue N = getValue(I.getOperand(0)); 2792 EVT DestVT = TLI.getValueType(I.getType()); 2793 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2794} 2795 2796void SelectionDAGBuilder::visitFPToUI(const User &I) { 2797 // FPToUI is never a no-op cast, no need to check 2798 SDValue N = getValue(I.getOperand(0)); 2799 EVT DestVT = TLI.getValueType(I.getType()); 2800 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2801} 2802 2803void SelectionDAGBuilder::visitFPToSI(const User &I) { 2804 // FPToSI is never a no-op cast, no need to check 2805 SDValue N = getValue(I.getOperand(0)); 2806 EVT DestVT = TLI.getValueType(I.getType()); 2807 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2808} 2809 2810void SelectionDAGBuilder::visitUIToFP(const User &I) { 2811 // UIToFP is never a no-op cast, no need to check 2812 SDValue N = getValue(I.getOperand(0)); 2813 EVT DestVT = TLI.getValueType(I.getType()); 2814 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2815} 2816 2817void SelectionDAGBuilder::visitSIToFP(const User &I){ 2818 // SIToFP is never a no-op cast, no need to check 2819 SDValue N = getValue(I.getOperand(0)); 2820 EVT DestVT = TLI.getValueType(I.getType()); 2821 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2822} 2823 2824void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2825 // What to do depends on the size of the integer and the size of the pointer. 2826 // We can either truncate, zero extend, or no-op, accordingly. 2827 SDValue N = getValue(I.getOperand(0)); 2828 EVT DestVT = TLI.getValueType(I.getType()); 2829 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2830} 2831 2832void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2833 // What to do depends on the size of the integer and the size of the pointer. 2834 // We can either truncate, zero extend, or no-op, accordingly. 2835 SDValue N = getValue(I.getOperand(0)); 2836 EVT DestVT = TLI.getValueType(I.getType()); 2837 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2838} 2839 2840void SelectionDAGBuilder::visitBitCast(const User &I) { 2841 SDValue N = getValue(I.getOperand(0)); 2842 EVT DestVT = TLI.getValueType(I.getType()); 2843 2844 // BitCast assures us that source and destination are the same size so this is 2845 // either a BITCAST or a no-op. 2846 if (DestVT != N.getValueType()) 2847 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2848 DestVT, N)); // convert types. 2849 else 2850 setValue(&I, N); // noop cast. 2851} 2852 2853void SelectionDAGBuilder::visitInsertElement(const User &I) { 2854 SDValue InVec = getValue(I.getOperand(0)); 2855 SDValue InVal = getValue(I.getOperand(1)); 2856 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2857 TLI.getPointerTy(), 2858 getValue(I.getOperand(2))); 2859 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2860 TLI.getValueType(I.getType()), 2861 InVec, InVal, InIdx)); 2862} 2863 2864void SelectionDAGBuilder::visitExtractElement(const User &I) { 2865 SDValue InVec = getValue(I.getOperand(0)); 2866 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2867 TLI.getPointerTy(), 2868 getValue(I.getOperand(1))); 2869 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2870 TLI.getValueType(I.getType()), InVec, InIdx)); 2871} 2872 2873// Utility for visitShuffleVector - Return true if every element in Mask, 2874// beginning from position Pos and ending in Pos+Size, falls within the 2875// specified sequential range [L, L+Pos). or is undef. 2876static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2877 unsigned Pos, unsigned Size, int Low) { 2878 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2879 if (Mask[i] >= 0 && Mask[i] != Low) 2880 return false; 2881 return true; 2882} 2883 2884void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2885 SDValue Src1 = getValue(I.getOperand(0)); 2886 SDValue Src2 = getValue(I.getOperand(1)); 2887 2888 SmallVector<int, 8> Mask; 2889 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2890 unsigned MaskNumElts = Mask.size(); 2891 2892 EVT VT = TLI.getValueType(I.getType()); 2893 EVT SrcVT = Src1.getValueType(); 2894 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2895 2896 if (SrcNumElts == MaskNumElts) { 2897 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2898 &Mask[0])); 2899 return; 2900 } 2901 2902 // Normalize the shuffle vector since mask and vector length don't match. 2903 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2904 // Mask is longer than the source vectors and is a multiple of the source 2905 // vectors. We can use concatenate vector to make the mask and vectors 2906 // lengths match. 2907 if (SrcNumElts*2 == MaskNumElts) { 2908 // First check for Src1 in low and Src2 in high 2909 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2910 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2911 // The shuffle is concatenating two vectors together. 2912 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2913 VT, Src1, Src2)); 2914 return; 2915 } 2916 // Then check for Src2 in low and Src1 in high 2917 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2918 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2919 // The shuffle is concatenating two vectors together. 2920 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2921 VT, Src2, Src1)); 2922 return; 2923 } 2924 } 2925 2926 // Pad both vectors with undefs to make them the same length as the mask. 2927 unsigned NumConcat = MaskNumElts / SrcNumElts; 2928 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2929 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2930 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2931 2932 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2933 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2934 MOps1[0] = Src1; 2935 MOps2[0] = Src2; 2936 2937 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2938 getCurDebugLoc(), VT, 2939 &MOps1[0], NumConcat); 2940 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2941 getCurDebugLoc(), VT, 2942 &MOps2[0], NumConcat); 2943 2944 // Readjust mask for new input vector length. 2945 SmallVector<int, 8> MappedOps; 2946 for (unsigned i = 0; i != MaskNumElts; ++i) { 2947 int Idx = Mask[i]; 2948 if (Idx >= (int)SrcNumElts) 2949 Idx -= SrcNumElts - MaskNumElts; 2950 MappedOps.push_back(Idx); 2951 } 2952 2953 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2954 &MappedOps[0])); 2955 return; 2956 } 2957 2958 if (SrcNumElts > MaskNumElts) { 2959 // Analyze the access pattern of the vector to see if we can extract 2960 // two subvectors and do the shuffle. The analysis is done by calculating 2961 // the range of elements the mask access on both vectors. 2962 int MinRange[2] = { static_cast<int>(SrcNumElts), 2963 static_cast<int>(SrcNumElts)}; 2964 int MaxRange[2] = {-1, -1}; 2965 2966 for (unsigned i = 0; i != MaskNumElts; ++i) { 2967 int Idx = Mask[i]; 2968 unsigned Input = 0; 2969 if (Idx < 0) 2970 continue; 2971 2972 if (Idx >= (int)SrcNumElts) { 2973 Input = 1; 2974 Idx -= SrcNumElts; 2975 } 2976 if (Idx > MaxRange[Input]) 2977 MaxRange[Input] = Idx; 2978 if (Idx < MinRange[Input]) 2979 MinRange[Input] = Idx; 2980 } 2981 2982 // Check if the access is smaller than the vector size and can we find 2983 // a reasonable extract index. 2984 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2985 // Extract. 2986 int StartIdx[2]; // StartIdx to extract from 2987 for (unsigned Input = 0; Input < 2; ++Input) { 2988 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2989 RangeUse[Input] = 0; // Unused 2990 StartIdx[Input] = 0; 2991 continue; 2992 } 2993 2994 // Find a good start index that is a multiple of the mask length. Then 2995 // see if the rest of the elements are in range. 2996 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2997 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2998 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2999 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 3000 } 3001 3002 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3003 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3004 return; 3005 } 3006 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3007 // Extract appropriate subvector and generate a vector shuffle 3008 for (unsigned Input = 0; Input < 2; ++Input) { 3009 SDValue &Src = Input == 0 ? Src1 : Src2; 3010 if (RangeUse[Input] == 0) 3011 Src = DAG.getUNDEF(VT); 3012 else 3013 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 3014 Src, DAG.getIntPtrConstant(StartIdx[Input])); 3015 } 3016 3017 // Calculate new mask. 3018 SmallVector<int, 8> MappedOps; 3019 for (unsigned i = 0; i != MaskNumElts; ++i) { 3020 int Idx = Mask[i]; 3021 if (Idx >= 0) { 3022 if (Idx < (int)SrcNumElts) 3023 Idx -= StartIdx[0]; 3024 else 3025 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3026 } 3027 MappedOps.push_back(Idx); 3028 } 3029 3030 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 3031 &MappedOps[0])); 3032 return; 3033 } 3034 } 3035 3036 // We can't use either concat vectors or extract subvectors so fall back to 3037 // replacing the shuffle with extract and build vector. 3038 // to insert and build vector. 3039 EVT EltVT = VT.getVectorElementType(); 3040 EVT PtrVT = TLI.getPointerTy(); 3041 SmallVector<SDValue,8> Ops; 3042 for (unsigned i = 0; i != MaskNumElts; ++i) { 3043 int Idx = Mask[i]; 3044 SDValue Res; 3045 3046 if (Idx < 0) { 3047 Res = DAG.getUNDEF(EltVT); 3048 } else { 3049 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3050 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3051 3052 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 3053 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3054 } 3055 3056 Ops.push_back(Res); 3057 } 3058 3059 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 3060 VT, &Ops[0], Ops.size())); 3061} 3062 3063void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3064 const Value *Op0 = I.getOperand(0); 3065 const Value *Op1 = I.getOperand(1); 3066 Type *AggTy = I.getType(); 3067 Type *ValTy = Op1->getType(); 3068 bool IntoUndef = isa<UndefValue>(Op0); 3069 bool FromUndef = isa<UndefValue>(Op1); 3070 3071 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3072 3073 SmallVector<EVT, 4> AggValueVTs; 3074 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3075 SmallVector<EVT, 4> ValValueVTs; 3076 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3077 3078 unsigned NumAggValues = AggValueVTs.size(); 3079 unsigned NumValValues = ValValueVTs.size(); 3080 SmallVector<SDValue, 4> Values(NumAggValues); 3081 3082 SDValue Agg = getValue(Op0); 3083 unsigned i = 0; 3084 // Copy the beginning value(s) from the original aggregate. 3085 for (; i != LinearIndex; ++i) 3086 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3087 SDValue(Agg.getNode(), Agg.getResNo() + i); 3088 // Copy values from the inserted value(s). 3089 if (NumValValues) { 3090 SDValue Val = getValue(Op1); 3091 for (; i != LinearIndex + NumValValues; ++i) 3092 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3093 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3094 } 3095 // Copy remaining value(s) from the original aggregate. 3096 for (; i != NumAggValues; ++i) 3097 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3098 SDValue(Agg.getNode(), Agg.getResNo() + i); 3099 3100 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3101 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3102 &Values[0], NumAggValues)); 3103} 3104 3105void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3106 const Value *Op0 = I.getOperand(0); 3107 Type *AggTy = Op0->getType(); 3108 Type *ValTy = I.getType(); 3109 bool OutOfUndef = isa<UndefValue>(Op0); 3110 3111 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3112 3113 SmallVector<EVT, 4> ValValueVTs; 3114 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3115 3116 unsigned NumValValues = ValValueVTs.size(); 3117 3118 // Ignore a extractvalue that produces an empty object 3119 if (!NumValValues) { 3120 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3121 return; 3122 } 3123 3124 SmallVector<SDValue, 4> Values(NumValValues); 3125 3126 SDValue Agg = getValue(Op0); 3127 // Copy out the selected value(s). 3128 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3129 Values[i - LinearIndex] = 3130 OutOfUndef ? 3131 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3132 SDValue(Agg.getNode(), Agg.getResNo() + i); 3133 3134 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3135 DAG.getVTList(&ValValueVTs[0], NumValValues), 3136 &Values[0], NumValValues)); 3137} 3138 3139void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3140 SDValue N = getValue(I.getOperand(0)); 3141 // Note that the pointer operand may be a vector of pointers. Take the scalar 3142 // element which holds a pointer. 3143 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3144 3145 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3146 OI != E; ++OI) { 3147 const Value *Idx = *OI; 3148 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3149 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3150 if (Field) { 3151 // N = N + Offset 3152 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3153 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3154 DAG.getConstant(Offset, N.getValueType())); 3155 } 3156 3157 Ty = StTy->getElementType(Field); 3158 } else { 3159 Ty = cast<SequentialType>(Ty)->getElementType(); 3160 3161 // If this is a constant subscript, handle it quickly. 3162 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3163 if (CI->isZero()) continue; 3164 uint64_t Offs = 3165 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3166 SDValue OffsVal; 3167 EVT PTy = TLI.getPointerTy(); 3168 unsigned PtrBits = PTy.getSizeInBits(); 3169 if (PtrBits < 64) 3170 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3171 TLI.getPointerTy(), 3172 DAG.getConstant(Offs, MVT::i64)); 3173 else 3174 OffsVal = DAG.getIntPtrConstant(Offs); 3175 3176 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3177 OffsVal); 3178 continue; 3179 } 3180 3181 // N = N + Idx * ElementSize; 3182 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3183 TD->getTypeAllocSize(Ty)); 3184 SDValue IdxN = getValue(Idx); 3185 3186 // If the index is smaller or larger than intptr_t, truncate or extend 3187 // it. 3188 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3189 3190 // If this is a multiply by a power of two, turn it into a shl 3191 // immediately. This is a very common case. 3192 if (ElementSize != 1) { 3193 if (ElementSize.isPowerOf2()) { 3194 unsigned Amt = ElementSize.logBase2(); 3195 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3196 N.getValueType(), IdxN, 3197 DAG.getConstant(Amt, IdxN.getValueType())); 3198 } else { 3199 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3200 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3201 N.getValueType(), IdxN, Scale); 3202 } 3203 } 3204 3205 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3206 N.getValueType(), N, IdxN); 3207 } 3208 } 3209 3210 setValue(&I, N); 3211} 3212 3213void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3214 // If this is a fixed sized alloca in the entry block of the function, 3215 // allocate it statically on the stack. 3216 if (FuncInfo.StaticAllocaMap.count(&I)) 3217 return; // getValue will auto-populate this. 3218 3219 Type *Ty = I.getAllocatedType(); 3220 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 3221 unsigned Align = 3222 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty), 3223 I.getAlignment()); 3224 3225 SDValue AllocSize = getValue(I.getArraySize()); 3226 3227 EVT IntPtr = TLI.getPointerTy(); 3228 if (AllocSize.getValueType() != IntPtr) 3229 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3230 3231 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3232 AllocSize, 3233 DAG.getConstant(TySize, IntPtr)); 3234 3235 // Handle alignment. If the requested alignment is less than or equal to 3236 // the stack alignment, ignore it. If the size is greater than or equal to 3237 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3238 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3239 if (Align <= StackAlign) 3240 Align = 0; 3241 3242 // Round the size of the allocation up to the stack alignment size 3243 // by add SA-1 to the size. 3244 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3245 AllocSize.getValueType(), AllocSize, 3246 DAG.getIntPtrConstant(StackAlign-1)); 3247 3248 // Mask out the low bits for alignment purposes. 3249 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3250 AllocSize.getValueType(), AllocSize, 3251 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3252 3253 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3254 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3255 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3256 VTs, Ops, 3); 3257 setValue(&I, DSA); 3258 DAG.setRoot(DSA.getValue(1)); 3259 3260 // Inform the Frame Information that we have just allocated a variable-sized 3261 // object. 3262 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, 3263 I.getAlignment(), &I); 3264} 3265 3266void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3267 if (I.isAtomic()) 3268 return visitAtomicLoad(I); 3269 3270 const Value *SV = I.getOperand(0); 3271 SDValue Ptr = getValue(SV); 3272 3273 Type *Ty = I.getType(); 3274 3275 bool isVolatile = I.isVolatile(); 3276 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3277 bool isInvariant = I.getMetadata("invariant.load") != 0; 3278 unsigned Alignment = I.getAlignment(); 3279 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3280 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3281 3282 SmallVector<EVT, 4> ValueVTs; 3283 SmallVector<uint64_t, 4> Offsets; 3284 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3285 unsigned NumValues = ValueVTs.size(); 3286 if (NumValues == 0) 3287 return; 3288 3289 SDValue Root; 3290 bool ConstantMemory = false; 3291 if (I.isVolatile() || NumValues > MaxParallelChains) 3292 // Serialize volatile loads with other side effects. 3293 Root = getRoot(); 3294 else if (AA->pointsToConstantMemory( 3295 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3296 // Do not serialize (non-volatile) loads of constant memory with anything. 3297 Root = DAG.getEntryNode(); 3298 ConstantMemory = true; 3299 } else { 3300 // Do not serialize non-volatile loads against each other. 3301 Root = DAG.getRoot(); 3302 } 3303 3304 SmallVector<SDValue, 4> Values(NumValues); 3305 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3306 NumValues)); 3307 EVT PtrVT = Ptr.getValueType(); 3308 unsigned ChainI = 0; 3309 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3310 // Serializing loads here may result in excessive register pressure, and 3311 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3312 // could recover a bit by hoisting nodes upward in the chain by recognizing 3313 // they are side-effect free or do not alias. The optimizer should really 3314 // avoid this case by converting large object/array copies to llvm.memcpy 3315 // (MaxParallelChains should always remain as failsafe). 3316 if (ChainI == MaxParallelChains) { 3317 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3318 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3319 MVT::Other, &Chains[0], ChainI); 3320 Root = Chain; 3321 ChainI = 0; 3322 } 3323 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3324 PtrVT, Ptr, 3325 DAG.getConstant(Offsets[i], PtrVT)); 3326 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3327 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3328 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3329 Ranges); 3330 3331 Values[i] = L; 3332 Chains[ChainI] = L.getValue(1); 3333 } 3334 3335 if (!ConstantMemory) { 3336 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3337 MVT::Other, &Chains[0], ChainI); 3338 if (isVolatile) 3339 DAG.setRoot(Chain); 3340 else 3341 PendingLoads.push_back(Chain); 3342 } 3343 3344 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3345 DAG.getVTList(&ValueVTs[0], NumValues), 3346 &Values[0], NumValues)); 3347} 3348 3349void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3350 if (I.isAtomic()) 3351 return visitAtomicStore(I); 3352 3353 const Value *SrcV = I.getOperand(0); 3354 const Value *PtrV = I.getOperand(1); 3355 3356 SmallVector<EVT, 4> ValueVTs; 3357 SmallVector<uint64_t, 4> Offsets; 3358 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3359 unsigned NumValues = ValueVTs.size(); 3360 if (NumValues == 0) 3361 return; 3362 3363 // Get the lowered operands. Note that we do this after 3364 // checking if NumResults is zero, because with zero results 3365 // the operands won't have values in the map. 3366 SDValue Src = getValue(SrcV); 3367 SDValue Ptr = getValue(PtrV); 3368 3369 SDValue Root = getRoot(); 3370 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3371 NumValues)); 3372 EVT PtrVT = Ptr.getValueType(); 3373 bool isVolatile = I.isVolatile(); 3374 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3375 unsigned Alignment = I.getAlignment(); 3376 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3377 3378 unsigned ChainI = 0; 3379 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3380 // See visitLoad comments. 3381 if (ChainI == MaxParallelChains) { 3382 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3383 MVT::Other, &Chains[0], ChainI); 3384 Root = Chain; 3385 ChainI = 0; 3386 } 3387 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3388 DAG.getConstant(Offsets[i], PtrVT)); 3389 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3390 SDValue(Src.getNode(), Src.getResNo() + i), 3391 Add, MachinePointerInfo(PtrV, Offsets[i]), 3392 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3393 Chains[ChainI] = St; 3394 } 3395 3396 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3397 MVT::Other, &Chains[0], ChainI); 3398 ++SDNodeOrder; 3399 AssignOrderingToNode(StoreNode.getNode()); 3400 DAG.setRoot(StoreNode); 3401} 3402 3403static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3404 SynchronizationScope Scope, 3405 bool Before, DebugLoc dl, 3406 SelectionDAG &DAG, 3407 const TargetLowering &TLI) { 3408 // Fence, if necessary 3409 if (Before) { 3410 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3411 Order = Release; 3412 else if (Order == Acquire || Order == Monotonic) 3413 return Chain; 3414 } else { 3415 if (Order == AcquireRelease) 3416 Order = Acquire; 3417 else if (Order == Release || Order == Monotonic) 3418 return Chain; 3419 } 3420 SDValue Ops[3]; 3421 Ops[0] = Chain; 3422 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3423 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3424 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3425} 3426 3427void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3428 DebugLoc dl = getCurDebugLoc(); 3429 AtomicOrdering Order = I.getOrdering(); 3430 SynchronizationScope Scope = I.getSynchScope(); 3431 3432 SDValue InChain = getRoot(); 3433 3434 if (TLI.getInsertFencesForAtomic()) 3435 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3436 DAG, TLI); 3437 3438 SDValue L = 3439 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3440 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3441 InChain, 3442 getValue(I.getPointerOperand()), 3443 getValue(I.getCompareOperand()), 3444 getValue(I.getNewValOperand()), 3445 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3446 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3447 Scope); 3448 3449 SDValue OutChain = L.getValue(1); 3450 3451 if (TLI.getInsertFencesForAtomic()) 3452 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3453 DAG, TLI); 3454 3455 setValue(&I, L); 3456 DAG.setRoot(OutChain); 3457} 3458 3459void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3460 DebugLoc dl = getCurDebugLoc(); 3461 ISD::NodeType NT; 3462 switch (I.getOperation()) { 3463 default: llvm_unreachable("Unknown atomicrmw operation"); 3464 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3465 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3466 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3467 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3468 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3469 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3470 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3471 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3472 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3473 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3474 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3475 } 3476 AtomicOrdering Order = I.getOrdering(); 3477 SynchronizationScope Scope = I.getSynchScope(); 3478 3479 SDValue InChain = getRoot(); 3480 3481 if (TLI.getInsertFencesForAtomic()) 3482 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3483 DAG, TLI); 3484 3485 SDValue L = 3486 DAG.getAtomic(NT, dl, 3487 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3488 InChain, 3489 getValue(I.getPointerOperand()), 3490 getValue(I.getValOperand()), 3491 I.getPointerOperand(), 0 /* Alignment */, 3492 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3493 Scope); 3494 3495 SDValue OutChain = L.getValue(1); 3496 3497 if (TLI.getInsertFencesForAtomic()) 3498 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3499 DAG, TLI); 3500 3501 setValue(&I, L); 3502 DAG.setRoot(OutChain); 3503} 3504 3505void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3506 DebugLoc dl = getCurDebugLoc(); 3507 SDValue Ops[3]; 3508 Ops[0] = getRoot(); 3509 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3510 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3511 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3512} 3513 3514void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3515 DebugLoc dl = getCurDebugLoc(); 3516 AtomicOrdering Order = I.getOrdering(); 3517 SynchronizationScope Scope = I.getSynchScope(); 3518 3519 SDValue InChain = getRoot(); 3520 3521 EVT VT = TLI.getValueType(I.getType()); 3522 3523 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3524 report_fatal_error("Cannot generate unaligned atomic load"); 3525 3526 SDValue L = 3527 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3528 getValue(I.getPointerOperand()), 3529 I.getPointerOperand(), I.getAlignment(), 3530 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3531 Scope); 3532 3533 SDValue OutChain = L.getValue(1); 3534 3535 if (TLI.getInsertFencesForAtomic()) 3536 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3537 DAG, TLI); 3538 3539 setValue(&I, L); 3540 DAG.setRoot(OutChain); 3541} 3542 3543void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3544 DebugLoc dl = getCurDebugLoc(); 3545 3546 AtomicOrdering Order = I.getOrdering(); 3547 SynchronizationScope Scope = I.getSynchScope(); 3548 3549 SDValue InChain = getRoot(); 3550 3551 EVT VT = TLI.getValueType(I.getValueOperand()->getType()); 3552 3553 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3554 report_fatal_error("Cannot generate unaligned atomic store"); 3555 3556 if (TLI.getInsertFencesForAtomic()) 3557 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3558 DAG, TLI); 3559 3560 SDValue OutChain = 3561 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3562 InChain, 3563 getValue(I.getPointerOperand()), 3564 getValue(I.getValueOperand()), 3565 I.getPointerOperand(), I.getAlignment(), 3566 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3567 Scope); 3568 3569 if (TLI.getInsertFencesForAtomic()) 3570 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3571 DAG, TLI); 3572 3573 DAG.setRoot(OutChain); 3574} 3575 3576/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3577/// node. 3578void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3579 unsigned Intrinsic) { 3580 bool HasChain = !I.doesNotAccessMemory(); 3581 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3582 3583 // Build the operand list. 3584 SmallVector<SDValue, 8> Ops; 3585 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3586 if (OnlyLoad) { 3587 // We don't need to serialize loads against other loads. 3588 Ops.push_back(DAG.getRoot()); 3589 } else { 3590 Ops.push_back(getRoot()); 3591 } 3592 } 3593 3594 // Info is set by getTgtMemInstrinsic 3595 TargetLowering::IntrinsicInfo Info; 3596 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3597 3598 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3599 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3600 Info.opc == ISD::INTRINSIC_W_CHAIN) 3601 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3602 3603 // Add all operands of the call to the operand list. 3604 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3605 SDValue Op = getValue(I.getArgOperand(i)); 3606 Ops.push_back(Op); 3607 } 3608 3609 SmallVector<EVT, 4> ValueVTs; 3610 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3611 3612 if (HasChain) 3613 ValueVTs.push_back(MVT::Other); 3614 3615 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3616 3617 // Create the node. 3618 SDValue Result; 3619 if (IsTgtIntrinsic) { 3620 // This is target intrinsic that touches memory 3621 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3622 VTs, &Ops[0], Ops.size(), 3623 Info.memVT, 3624 MachinePointerInfo(Info.ptrVal, Info.offset), 3625 Info.align, Info.vol, 3626 Info.readMem, Info.writeMem); 3627 } else if (!HasChain) { 3628 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3629 VTs, &Ops[0], Ops.size()); 3630 } else if (!I.getType()->isVoidTy()) { 3631 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3632 VTs, &Ops[0], Ops.size()); 3633 } else { 3634 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3635 VTs, &Ops[0], Ops.size()); 3636 } 3637 3638 if (HasChain) { 3639 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3640 if (OnlyLoad) 3641 PendingLoads.push_back(Chain); 3642 else 3643 DAG.setRoot(Chain); 3644 } 3645 3646 if (!I.getType()->isVoidTy()) { 3647 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3648 EVT VT = TLI.getValueType(PTy); 3649 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3650 } 3651 3652 setValue(&I, Result); 3653 } else { 3654 // Assign order to result here. If the intrinsic does not produce a result, 3655 // it won't be mapped to a SDNode and visit() will not assign it an order 3656 // number. 3657 ++SDNodeOrder; 3658 AssignOrderingToNode(Result.getNode()); 3659 } 3660} 3661 3662/// GetSignificand - Get the significand and build it into a floating-point 3663/// number with exponent of 1: 3664/// 3665/// Op = (Op & 0x007fffff) | 0x3f800000; 3666/// 3667/// where Op is the hexidecimal representation of floating point value. 3668static SDValue 3669GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3670 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3671 DAG.getConstant(0x007fffff, MVT::i32)); 3672 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3673 DAG.getConstant(0x3f800000, MVT::i32)); 3674 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3675} 3676 3677/// GetExponent - Get the exponent: 3678/// 3679/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3680/// 3681/// where Op is the hexidecimal representation of floating point value. 3682static SDValue 3683GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3684 DebugLoc dl) { 3685 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3686 DAG.getConstant(0x7f800000, MVT::i32)); 3687 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3688 DAG.getConstant(23, TLI.getPointerTy())); 3689 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3690 DAG.getConstant(127, MVT::i32)); 3691 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3692} 3693 3694/// getF32Constant - Get 32-bit floating point constant. 3695static SDValue 3696getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3697 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), 3698 MVT::f32); 3699} 3700 3701/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3702/// limited-precision mode. 3703static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3704 const TargetLowering &TLI) { 3705 if (Op.getValueType() == MVT::f32 && 3706 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3707 3708 // Put the exponent in the right bit position for later addition to the 3709 // final result: 3710 // 3711 // #define LOG2OFe 1.4426950f 3712 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3713 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3714 getF32Constant(DAG, 0x3fb8aa3b)); 3715 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3716 3717 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3718 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3719 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3720 3721 // IntegerPartOfX <<= 23; 3722 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3723 DAG.getConstant(23, TLI.getPointerTy())); 3724 3725 SDValue TwoToFracPartOfX; 3726 if (LimitFloatPrecision <= 6) { 3727 // For floating-point precision of 6: 3728 // 3729 // TwoToFractionalPartOfX = 3730 // 0.997535578f + 3731 // (0.735607626f + 0.252464424f * x) * x; 3732 // 3733 // error 0.0144103317, which is 6 bits 3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3735 getF32Constant(DAG, 0x3e814304)); 3736 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3737 getF32Constant(DAG, 0x3f3c50c8)); 3738 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3739 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3740 getF32Constant(DAG, 0x3f7f5e7e)); 3741 } else if (LimitFloatPrecision <= 12) { 3742 // For floating-point precision of 12: 3743 // 3744 // TwoToFractionalPartOfX = 3745 // 0.999892986f + 3746 // (0.696457318f + 3747 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3748 // 3749 // 0.000107046256 error, which is 13 to 14 bits 3750 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3751 getF32Constant(DAG, 0x3da235e3)); 3752 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3753 getF32Constant(DAG, 0x3e65b8f3)); 3754 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3755 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3756 getF32Constant(DAG, 0x3f324b07)); 3757 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3758 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3759 getF32Constant(DAG, 0x3f7ff8fd)); 3760 } else { // LimitFloatPrecision <= 18 3761 // For floating-point precision of 18: 3762 // 3763 // TwoToFractionalPartOfX = 3764 // 0.999999982f + 3765 // (0.693148872f + 3766 // (0.240227044f + 3767 // (0.554906021e-1f + 3768 // (0.961591928e-2f + 3769 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3770 // 3771 // error 2.47208000*10^(-7), which is better than 18 bits 3772 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3773 getF32Constant(DAG, 0x3924b03e)); 3774 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3775 getF32Constant(DAG, 0x3ab24b87)); 3776 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3777 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3778 getF32Constant(DAG, 0x3c1d8c17)); 3779 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3780 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3781 getF32Constant(DAG, 0x3d634a1d)); 3782 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3783 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3784 getF32Constant(DAG, 0x3e75fe14)); 3785 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3786 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3787 getF32Constant(DAG, 0x3f317234)); 3788 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3789 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3790 getF32Constant(DAG, 0x3f800000)); 3791 } 3792 3793 // Add the exponent into the result in integer domain. 3794 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3795 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3796 DAG.getNode(ISD::ADD, dl, MVT::i32, 3797 t13, IntegerPartOfX)); 3798 } 3799 3800 // No special expansion. 3801 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3802} 3803 3804/// expandLog - Lower a log intrinsic. Handles the special sequences for 3805/// limited-precision mode. 3806static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3807 const TargetLowering &TLI) { 3808 if (Op.getValueType() == MVT::f32 && 3809 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3810 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3811 3812 // Scale the exponent by log(2) [0.69314718f]. 3813 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3814 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3815 getF32Constant(DAG, 0x3f317218)); 3816 3817 // Get the significand and build it into a floating-point number with 3818 // exponent of 1. 3819 SDValue X = GetSignificand(DAG, Op1, dl); 3820 3821 SDValue LogOfMantissa; 3822 if (LimitFloatPrecision <= 6) { 3823 // For floating-point precision of 6: 3824 // 3825 // LogofMantissa = 3826 // -1.1609546f + 3827 // (1.4034025f - 0.23903021f * x) * x; 3828 // 3829 // error 0.0034276066, which is better than 8 bits 3830 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3831 getF32Constant(DAG, 0xbe74c456)); 3832 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3833 getF32Constant(DAG, 0x3fb3a2b1)); 3834 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3835 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3836 getF32Constant(DAG, 0x3f949a29)); 3837 } else if (LimitFloatPrecision <= 12) { 3838 // For floating-point precision of 12: 3839 // 3840 // LogOfMantissa = 3841 // -1.7417939f + 3842 // (2.8212026f + 3843 // (-1.4699568f + 3844 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3845 // 3846 // error 0.000061011436, which is 14 bits 3847 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3848 getF32Constant(DAG, 0xbd67b6d6)); 3849 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3850 getF32Constant(DAG, 0x3ee4f4b8)); 3851 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3852 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3853 getF32Constant(DAG, 0x3fbc278b)); 3854 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3855 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3856 getF32Constant(DAG, 0x40348e95)); 3857 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3858 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3859 getF32Constant(DAG, 0x3fdef31a)); 3860 } else { // LimitFloatPrecision <= 18 3861 // For floating-point precision of 18: 3862 // 3863 // LogOfMantissa = 3864 // -2.1072184f + 3865 // (4.2372794f + 3866 // (-3.7029485f + 3867 // (2.2781945f + 3868 // (-0.87823314f + 3869 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3870 // 3871 // error 0.0000023660568, which is better than 18 bits 3872 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3873 getF32Constant(DAG, 0xbc91e5ac)); 3874 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3875 getF32Constant(DAG, 0x3e4350aa)); 3876 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3877 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3878 getF32Constant(DAG, 0x3f60d3e3)); 3879 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3880 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3881 getF32Constant(DAG, 0x4011cdf0)); 3882 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3883 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3884 getF32Constant(DAG, 0x406cfd1c)); 3885 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3886 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3887 getF32Constant(DAG, 0x408797cb)); 3888 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3889 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3890 getF32Constant(DAG, 0x4006dcab)); 3891 } 3892 3893 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 3894 } 3895 3896 // No special expansion. 3897 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 3898} 3899 3900/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 3901/// limited-precision mode. 3902static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3903 const TargetLowering &TLI) { 3904 if (Op.getValueType() == MVT::f32 && 3905 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3906 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3907 3908 // Get the exponent. 3909 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3910 3911 // Get the significand and build it into a floating-point number with 3912 // exponent of 1. 3913 SDValue X = GetSignificand(DAG, Op1, dl); 3914 3915 // Different possible minimax approximations of significand in 3916 // floating-point for various degrees of accuracy over [1,2]. 3917 SDValue Log2ofMantissa; 3918 if (LimitFloatPrecision <= 6) { 3919 // For floating-point precision of 6: 3920 // 3921 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3922 // 3923 // error 0.0049451742, which is more than 7 bits 3924 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3925 getF32Constant(DAG, 0xbeb08fe0)); 3926 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3927 getF32Constant(DAG, 0x40019463)); 3928 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3929 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3930 getF32Constant(DAG, 0x3fd6633d)); 3931 } else if (LimitFloatPrecision <= 12) { 3932 // For floating-point precision of 12: 3933 // 3934 // Log2ofMantissa = 3935 // -2.51285454f + 3936 // (4.07009056f + 3937 // (-2.12067489f + 3938 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3939 // 3940 // error 0.0000876136000, which is better than 13 bits 3941 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3942 getF32Constant(DAG, 0xbda7262e)); 3943 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3944 getF32Constant(DAG, 0x3f25280b)); 3945 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3946 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3947 getF32Constant(DAG, 0x4007b923)); 3948 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3949 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3950 getF32Constant(DAG, 0x40823e2f)); 3951 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3952 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3953 getF32Constant(DAG, 0x4020d29c)); 3954 } else { // LimitFloatPrecision <= 18 3955 // For floating-point precision of 18: 3956 // 3957 // Log2ofMantissa = 3958 // -3.0400495f + 3959 // (6.1129976f + 3960 // (-5.3420409f + 3961 // (3.2865683f + 3962 // (-1.2669343f + 3963 // (0.27515199f - 3964 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3965 // 3966 // error 0.0000018516, which is better than 18 bits 3967 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3968 getF32Constant(DAG, 0xbcd2769e)); 3969 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3970 getF32Constant(DAG, 0x3e8ce0b9)); 3971 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3972 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3973 getF32Constant(DAG, 0x3fa22ae7)); 3974 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3975 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3976 getF32Constant(DAG, 0x40525723)); 3977 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3978 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3979 getF32Constant(DAG, 0x40aaf200)); 3980 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3981 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3982 getF32Constant(DAG, 0x40c39dad)); 3983 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3984 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3985 getF32Constant(DAG, 0x4042902c)); 3986 } 3987 3988 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 3989 } 3990 3991 // No special expansion. 3992 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 3993} 3994 3995/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 3996/// limited-precision mode. 3997static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3998 const TargetLowering &TLI) { 3999 if (Op.getValueType() == MVT::f32 && 4000 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4001 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4002 4003 // Scale the exponent by log10(2) [0.30102999f]. 4004 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4005 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4006 getF32Constant(DAG, 0x3e9a209a)); 4007 4008 // Get the significand and build it into a floating-point number with 4009 // exponent of 1. 4010 SDValue X = GetSignificand(DAG, Op1, dl); 4011 4012 SDValue Log10ofMantissa; 4013 if (LimitFloatPrecision <= 6) { 4014 // For floating-point precision of 6: 4015 // 4016 // Log10ofMantissa = 4017 // -0.50419619f + 4018 // (0.60948995f - 0.10380950f * x) * x; 4019 // 4020 // error 0.0014886165, which is 6 bits 4021 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4022 getF32Constant(DAG, 0xbdd49a13)); 4023 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4024 getF32Constant(DAG, 0x3f1c0789)); 4025 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4026 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4027 getF32Constant(DAG, 0x3f011300)); 4028 } else if (LimitFloatPrecision <= 12) { 4029 // For floating-point precision of 12: 4030 // 4031 // Log10ofMantissa = 4032 // -0.64831180f + 4033 // (0.91751397f + 4034 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4035 // 4036 // error 0.00019228036, which is better than 12 bits 4037 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4038 getF32Constant(DAG, 0x3d431f31)); 4039 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4040 getF32Constant(DAG, 0x3ea21fb2)); 4041 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4042 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4043 getF32Constant(DAG, 0x3f6ae232)); 4044 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4045 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4046 getF32Constant(DAG, 0x3f25f7c3)); 4047 } else { // LimitFloatPrecision <= 18 4048 // For floating-point precision of 18: 4049 // 4050 // Log10ofMantissa = 4051 // -0.84299375f + 4052 // (1.5327582f + 4053 // (-1.0688956f + 4054 // (0.49102474f + 4055 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4056 // 4057 // error 0.0000037995730, which is better than 18 bits 4058 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4059 getF32Constant(DAG, 0x3c5d51ce)); 4060 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4061 getF32Constant(DAG, 0x3e00685a)); 4062 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4063 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4064 getF32Constant(DAG, 0x3efb6798)); 4065 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4066 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4067 getF32Constant(DAG, 0x3f88d192)); 4068 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4069 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4070 getF32Constant(DAG, 0x3fc4316c)); 4071 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4072 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4073 getF32Constant(DAG, 0x3f57ce70)); 4074 } 4075 4076 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4077 } 4078 4079 // No special expansion. 4080 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4081} 4082 4083/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4084/// limited-precision mode. 4085static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 4086 const TargetLowering &TLI) { 4087 if (Op.getValueType() == MVT::f32 && 4088 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4089 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4090 4091 // FractionalPartOfX = x - (float)IntegerPartOfX; 4092 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4093 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4094 4095 // IntegerPartOfX <<= 23; 4096 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4097 DAG.getConstant(23, TLI.getPointerTy())); 4098 4099 SDValue TwoToFractionalPartOfX; 4100 if (LimitFloatPrecision <= 6) { 4101 // For floating-point precision of 6: 4102 // 4103 // TwoToFractionalPartOfX = 4104 // 0.997535578f + 4105 // (0.735607626f + 0.252464424f * x) * x; 4106 // 4107 // error 0.0144103317, which is 6 bits 4108 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4109 getF32Constant(DAG, 0x3e814304)); 4110 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4111 getF32Constant(DAG, 0x3f3c50c8)); 4112 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4113 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4114 getF32Constant(DAG, 0x3f7f5e7e)); 4115 } else if (LimitFloatPrecision <= 12) { 4116 // For floating-point precision of 12: 4117 // 4118 // TwoToFractionalPartOfX = 4119 // 0.999892986f + 4120 // (0.696457318f + 4121 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4122 // 4123 // error 0.000107046256, which is 13 to 14 bits 4124 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4125 getF32Constant(DAG, 0x3da235e3)); 4126 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4127 getF32Constant(DAG, 0x3e65b8f3)); 4128 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4129 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4130 getF32Constant(DAG, 0x3f324b07)); 4131 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4132 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4133 getF32Constant(DAG, 0x3f7ff8fd)); 4134 } else { // LimitFloatPrecision <= 18 4135 // For floating-point precision of 18: 4136 // 4137 // TwoToFractionalPartOfX = 4138 // 0.999999982f + 4139 // (0.693148872f + 4140 // (0.240227044f + 4141 // (0.554906021e-1f + 4142 // (0.961591928e-2f + 4143 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4144 // error 2.47208000*10^(-7), which is better than 18 bits 4145 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4146 getF32Constant(DAG, 0x3924b03e)); 4147 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4148 getF32Constant(DAG, 0x3ab24b87)); 4149 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4150 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4151 getF32Constant(DAG, 0x3c1d8c17)); 4152 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4153 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4154 getF32Constant(DAG, 0x3d634a1d)); 4155 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4156 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4157 getF32Constant(DAG, 0x3e75fe14)); 4158 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4159 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4160 getF32Constant(DAG, 0x3f317234)); 4161 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4162 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4163 getF32Constant(DAG, 0x3f800000)); 4164 } 4165 4166 // Add the exponent into the result in integer domain. 4167 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4168 TwoToFractionalPartOfX); 4169 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4170 DAG.getNode(ISD::ADD, dl, MVT::i32, 4171 t13, IntegerPartOfX)); 4172 } 4173 4174 // No special expansion. 4175 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4176} 4177 4178/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4179/// limited-precision mode with x == 10.0f. 4180static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS, 4181 SelectionDAG &DAG, const TargetLowering &TLI) { 4182 bool IsExp10 = false; 4183 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4184 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4185 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4186 APFloat Ten(10.0f); 4187 IsExp10 = LHSC->isExactlyValue(Ten); 4188 } 4189 } 4190 4191 if (IsExp10) { 4192 // Put the exponent in the right bit position for later addition to the 4193 // final result: 4194 // 4195 // #define LOG2OF10 3.3219281f 4196 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4198 getF32Constant(DAG, 0x40549a78)); 4199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4200 4201 // FractionalPartOfX = x - (float)IntegerPartOfX; 4202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4203 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4204 4205 // IntegerPartOfX <<= 23; 4206 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4207 DAG.getConstant(23, TLI.getPointerTy())); 4208 4209 SDValue TwoToFractionalPartOfX; 4210 if (LimitFloatPrecision <= 6) { 4211 // For floating-point precision of 6: 4212 // 4213 // twoToFractionalPartOfX = 4214 // 0.997535578f + 4215 // (0.735607626f + 0.252464424f * x) * x; 4216 // 4217 // error 0.0144103317, which is 6 bits 4218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4219 getF32Constant(DAG, 0x3e814304)); 4220 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4221 getF32Constant(DAG, 0x3f3c50c8)); 4222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4223 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4224 getF32Constant(DAG, 0x3f7f5e7e)); 4225 } else if (LimitFloatPrecision <= 12) { 4226 // For floating-point precision of 12: 4227 // 4228 // TwoToFractionalPartOfX = 4229 // 0.999892986f + 4230 // (0.696457318f + 4231 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4232 // 4233 // error 0.000107046256, which is 13 to 14 bits 4234 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4235 getF32Constant(DAG, 0x3da235e3)); 4236 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4237 getF32Constant(DAG, 0x3e65b8f3)); 4238 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4239 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4240 getF32Constant(DAG, 0x3f324b07)); 4241 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4242 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4243 getF32Constant(DAG, 0x3f7ff8fd)); 4244 } else { // LimitFloatPrecision <= 18 4245 // For floating-point precision of 18: 4246 // 4247 // TwoToFractionalPartOfX = 4248 // 0.999999982f + 4249 // (0.693148872f + 4250 // (0.240227044f + 4251 // (0.554906021e-1f + 4252 // (0.961591928e-2f + 4253 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4254 // error 2.47208000*10^(-7), which is better than 18 bits 4255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4256 getF32Constant(DAG, 0x3924b03e)); 4257 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4258 getF32Constant(DAG, 0x3ab24b87)); 4259 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4260 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4261 getF32Constant(DAG, 0x3c1d8c17)); 4262 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4263 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4264 getF32Constant(DAG, 0x3d634a1d)); 4265 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4266 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4267 getF32Constant(DAG, 0x3e75fe14)); 4268 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4269 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4270 getF32Constant(DAG, 0x3f317234)); 4271 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4272 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4273 getF32Constant(DAG, 0x3f800000)); 4274 } 4275 4276 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4277 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4278 DAG.getNode(ISD::ADD, dl, MVT::i32, 4279 t13, IntegerPartOfX)); 4280 } 4281 4282 // No special expansion. 4283 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4284} 4285 4286 4287/// ExpandPowI - Expand a llvm.powi intrinsic. 4288static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4289 SelectionDAG &DAG) { 4290 // If RHS is a constant, we can expand this out to a multiplication tree, 4291 // otherwise we end up lowering to a call to __powidf2 (for example). When 4292 // optimizing for size, we only want to do this if the expansion would produce 4293 // a small number of multiplies, otherwise we do the full expansion. 4294 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4295 // Get the exponent as a positive value. 4296 unsigned Val = RHSC->getSExtValue(); 4297 if ((int)Val < 0) Val = -Val; 4298 4299 // powi(x, 0) -> 1.0 4300 if (Val == 0) 4301 return DAG.getConstantFP(1.0, LHS.getValueType()); 4302 4303 const Function *F = DAG.getMachineFunction().getFunction(); 4304 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 4305 Attribute::OptimizeForSize) || 4306 // If optimizing for size, don't insert too many multiplies. This 4307 // inserts up to 5 multiplies. 4308 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4309 // We use the simple binary decomposition method to generate the multiply 4310 // sequence. There are more optimal ways to do this (for example, 4311 // powi(x,15) generates one more multiply than it should), but this has 4312 // the benefit of being both really simple and much better than a libcall. 4313 SDValue Res; // Logically starts equal to 1.0 4314 SDValue CurSquare = LHS; 4315 while (Val) { 4316 if (Val & 1) { 4317 if (Res.getNode()) 4318 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4319 else 4320 Res = CurSquare; // 1.0*CurSquare. 4321 } 4322 4323 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4324 CurSquare, CurSquare); 4325 Val >>= 1; 4326 } 4327 4328 // If the original was negative, invert the result, producing 1/(x*x*x). 4329 if (RHSC->getSExtValue() < 0) 4330 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4331 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4332 return Res; 4333 } 4334 } 4335 4336 // Otherwise, expand to a libcall. 4337 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4338} 4339 4340// getTruncatedArgReg - Find underlying register used for an truncated 4341// argument. 4342static unsigned getTruncatedArgReg(const SDValue &N) { 4343 if (N.getOpcode() != ISD::TRUNCATE) 4344 return 0; 4345 4346 const SDValue &Ext = N.getOperand(0); 4347 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4348 const SDValue &CFR = Ext.getOperand(0); 4349 if (CFR.getOpcode() == ISD::CopyFromReg) 4350 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4351 if (CFR.getOpcode() == ISD::TRUNCATE) 4352 return getTruncatedArgReg(CFR); 4353 } 4354 return 0; 4355} 4356 4357/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4358/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4359/// At the end of instruction selection, they will be inserted to the entry BB. 4360bool 4361SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4362 int64_t Offset, 4363 const SDValue &N) { 4364 const Argument *Arg = dyn_cast<Argument>(V); 4365 if (!Arg) 4366 return false; 4367 4368 MachineFunction &MF = DAG.getMachineFunction(); 4369 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4370 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4371 4372 // Ignore inlined function arguments here. 4373 DIVariable DV(Variable); 4374 if (DV.isInlinedFnArgument(MF.getFunction())) 4375 return false; 4376 4377 unsigned Reg = 0; 4378 // Some arguments' frame index is recorded during argument lowering. 4379 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4380 if (Offset) 4381 Reg = TRI->getFrameRegister(MF); 4382 4383 if (!Reg && N.getNode()) { 4384 if (N.getOpcode() == ISD::CopyFromReg) 4385 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4386 else 4387 Reg = getTruncatedArgReg(N); 4388 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4389 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4390 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4391 if (PR) 4392 Reg = PR; 4393 } 4394 } 4395 4396 if (!Reg) { 4397 // Check if ValueMap has reg number. 4398 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4399 if (VMI != FuncInfo.ValueMap.end()) 4400 Reg = VMI->second; 4401 } 4402 4403 if (!Reg && N.getNode()) { 4404 // Check if frame index is available. 4405 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4406 if (FrameIndexSDNode *FINode = 4407 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4408 Reg = TRI->getFrameRegister(MF); 4409 Offset = FINode->getIndex(); 4410 } 4411 } 4412 4413 if (!Reg) 4414 return false; 4415 4416 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4417 TII->get(TargetOpcode::DBG_VALUE)) 4418 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4419 FuncInfo.ArgDbgValues.push_back(&*MIB); 4420 return true; 4421} 4422 4423// VisualStudio defines setjmp as _setjmp 4424#if defined(_MSC_VER) && defined(setjmp) && \ 4425 !defined(setjmp_undefined_for_msvc) 4426# pragma push_macro("setjmp") 4427# undef setjmp 4428# define setjmp_undefined_for_msvc 4429#endif 4430 4431/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4432/// we want to emit this as a call to a named external function, return the name 4433/// otherwise lower it and return null. 4434const char * 4435SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4436 DebugLoc dl = getCurDebugLoc(); 4437 SDValue Res; 4438 4439 switch (Intrinsic) { 4440 default: 4441 // By default, turn this into a target intrinsic node. 4442 visitTargetIntrinsic(I, Intrinsic); 4443 return 0; 4444 case Intrinsic::vastart: visitVAStart(I); return 0; 4445 case Intrinsic::vaend: visitVAEnd(I); return 0; 4446 case Intrinsic::vacopy: visitVACopy(I); return 0; 4447 case Intrinsic::returnaddress: 4448 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4449 getValue(I.getArgOperand(0)))); 4450 return 0; 4451 case Intrinsic::frameaddress: 4452 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4453 getValue(I.getArgOperand(0)))); 4454 return 0; 4455 case Intrinsic::setjmp: 4456 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4457 case Intrinsic::longjmp: 4458 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4459 case Intrinsic::memcpy: { 4460 // Assert for address < 256 since we support only user defined address 4461 // spaces. 4462 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4463 < 256 && 4464 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4465 < 256 && 4466 "Unknown address space"); 4467 SDValue Op1 = getValue(I.getArgOperand(0)); 4468 SDValue Op2 = getValue(I.getArgOperand(1)); 4469 SDValue Op3 = getValue(I.getArgOperand(2)); 4470 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4471 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4472 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4473 MachinePointerInfo(I.getArgOperand(0)), 4474 MachinePointerInfo(I.getArgOperand(1)))); 4475 return 0; 4476 } 4477 case Intrinsic::memset: { 4478 // Assert for address < 256 since we support only user defined address 4479 // spaces. 4480 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4481 < 256 && 4482 "Unknown address space"); 4483 SDValue Op1 = getValue(I.getArgOperand(0)); 4484 SDValue Op2 = getValue(I.getArgOperand(1)); 4485 SDValue Op3 = getValue(I.getArgOperand(2)); 4486 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4487 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4488 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4489 MachinePointerInfo(I.getArgOperand(0)))); 4490 return 0; 4491 } 4492 case Intrinsic::memmove: { 4493 // Assert for address < 256 since we support only user defined address 4494 // spaces. 4495 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4496 < 256 && 4497 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4498 < 256 && 4499 "Unknown address space"); 4500 SDValue Op1 = getValue(I.getArgOperand(0)); 4501 SDValue Op2 = getValue(I.getArgOperand(1)); 4502 SDValue Op3 = getValue(I.getArgOperand(2)); 4503 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4504 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4505 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4506 MachinePointerInfo(I.getArgOperand(0)), 4507 MachinePointerInfo(I.getArgOperand(1)))); 4508 return 0; 4509 } 4510 case Intrinsic::dbg_declare: { 4511 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4512 MDNode *Variable = DI.getVariable(); 4513 const Value *Address = DI.getAddress(); 4514 if (!Address || !DIVariable(Variable).Verify()) { 4515 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4516 return 0; 4517 } 4518 4519 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4520 // but do not always have a corresponding SDNode built. The SDNodeOrder 4521 // absolute, but not relative, values are different depending on whether 4522 // debug info exists. 4523 ++SDNodeOrder; 4524 4525 // Check if address has undef value. 4526 if (isa<UndefValue>(Address) || 4527 (Address->use_empty() && !isa<Argument>(Address))) { 4528 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4529 return 0; 4530 } 4531 4532 SDValue &N = NodeMap[Address]; 4533 if (!N.getNode() && isa<Argument>(Address)) 4534 // Check unused arguments map. 4535 N = UnusedArgNodeMap[Address]; 4536 SDDbgValue *SDV; 4537 if (N.getNode()) { 4538 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4539 Address = BCI->getOperand(0); 4540 // Parameters are handled specially. 4541 bool isParameter = 4542 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4543 isa<Argument>(Address)); 4544 4545 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4546 4547 if (isParameter && !AI) { 4548 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4549 if (FINode) 4550 // Byval parameter. We have a frame index at this point. 4551 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4552 0, dl, SDNodeOrder); 4553 else { 4554 // Address is an argument, so try to emit its dbg value using 4555 // virtual register info from the FuncInfo.ValueMap. 4556 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4557 return 0; 4558 } 4559 } else if (AI) 4560 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4561 0, dl, SDNodeOrder); 4562 else { 4563 // Can't do anything with other non-AI cases yet. 4564 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4565 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4566 DEBUG(Address->dump()); 4567 return 0; 4568 } 4569 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4570 } else { 4571 // If Address is an argument then try to emit its dbg value using 4572 // virtual register info from the FuncInfo.ValueMap. 4573 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4574 // If variable is pinned by a alloca in dominating bb then 4575 // use StaticAllocaMap. 4576 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4577 if (AI->getParent() != DI.getParent()) { 4578 DenseMap<const AllocaInst*, int>::iterator SI = 4579 FuncInfo.StaticAllocaMap.find(AI); 4580 if (SI != FuncInfo.StaticAllocaMap.end()) { 4581 SDV = DAG.getDbgValue(Variable, SI->second, 4582 0, dl, SDNodeOrder); 4583 DAG.AddDbgValue(SDV, 0, false); 4584 return 0; 4585 } 4586 } 4587 } 4588 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4589 } 4590 } 4591 return 0; 4592 } 4593 case Intrinsic::dbg_value: { 4594 const DbgValueInst &DI = cast<DbgValueInst>(I); 4595 if (!DIVariable(DI.getVariable()).Verify()) 4596 return 0; 4597 4598 MDNode *Variable = DI.getVariable(); 4599 uint64_t Offset = DI.getOffset(); 4600 const Value *V = DI.getValue(); 4601 if (!V) 4602 return 0; 4603 4604 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4605 // but do not always have a corresponding SDNode built. The SDNodeOrder 4606 // absolute, but not relative, values are different depending on whether 4607 // debug info exists. 4608 ++SDNodeOrder; 4609 SDDbgValue *SDV; 4610 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4611 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4612 DAG.AddDbgValue(SDV, 0, false); 4613 } else { 4614 // Do not use getValue() in here; we don't want to generate code at 4615 // this point if it hasn't been done yet. 4616 SDValue N = NodeMap[V]; 4617 if (!N.getNode() && isa<Argument>(V)) 4618 // Check unused arguments map. 4619 N = UnusedArgNodeMap[V]; 4620 if (N.getNode()) { 4621 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4622 SDV = DAG.getDbgValue(Variable, N.getNode(), 4623 N.getResNo(), Offset, dl, SDNodeOrder); 4624 DAG.AddDbgValue(SDV, N.getNode(), false); 4625 } 4626 } else if (!V->use_empty() ) { 4627 // Do not call getValue(V) yet, as we don't want to generate code. 4628 // Remember it for later. 4629 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4630 DanglingDebugInfoMap[V] = DDI; 4631 } else { 4632 // We may expand this to cover more cases. One case where we have no 4633 // data available is an unreferenced parameter. 4634 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4635 } 4636 } 4637 4638 // Build a debug info table entry. 4639 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4640 V = BCI->getOperand(0); 4641 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4642 // Don't handle byval struct arguments or VLAs, for example. 4643 if (!AI) { 4644 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4645 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4646 return 0; 4647 } 4648 DenseMap<const AllocaInst*, int>::iterator SI = 4649 FuncInfo.StaticAllocaMap.find(AI); 4650 if (SI == FuncInfo.StaticAllocaMap.end()) 4651 return 0; // VLAs. 4652 int FI = SI->second; 4653 4654 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4655 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4656 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4657 return 0; 4658 } 4659 4660 case Intrinsic::eh_typeid_for: { 4661 // Find the type id for the given typeinfo. 4662 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4663 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4664 Res = DAG.getConstant(TypeID, MVT::i32); 4665 setValue(&I, Res); 4666 return 0; 4667 } 4668 4669 case Intrinsic::eh_return_i32: 4670 case Intrinsic::eh_return_i64: 4671 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4672 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4673 MVT::Other, 4674 getControlRoot(), 4675 getValue(I.getArgOperand(0)), 4676 getValue(I.getArgOperand(1)))); 4677 return 0; 4678 case Intrinsic::eh_unwind_init: 4679 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4680 return 0; 4681 case Intrinsic::eh_dwarf_cfa: { 4682 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4683 TLI.getPointerTy()); 4684 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4685 TLI.getPointerTy(), 4686 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4687 TLI.getPointerTy()), 4688 CfaArg); 4689 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4690 TLI.getPointerTy(), 4691 DAG.getConstant(0, TLI.getPointerTy())); 4692 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4693 FA, Offset)); 4694 return 0; 4695 } 4696 case Intrinsic::eh_sjlj_callsite: { 4697 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4698 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4699 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4700 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4701 4702 MMI.setCurrentCallSite(CI->getZExtValue()); 4703 return 0; 4704 } 4705 case Intrinsic::eh_sjlj_functioncontext: { 4706 // Get and store the index of the function context. 4707 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4708 AllocaInst *FnCtx = 4709 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4710 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4711 MFI->setFunctionContextIndex(FI); 4712 return 0; 4713 } 4714 case Intrinsic::eh_sjlj_setjmp: { 4715 SDValue Ops[2]; 4716 Ops[0] = getRoot(); 4717 Ops[1] = getValue(I.getArgOperand(0)); 4718 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4719 DAG.getVTList(MVT::i32, MVT::Other), 4720 Ops, 2); 4721 setValue(&I, Op.getValue(0)); 4722 DAG.setRoot(Op.getValue(1)); 4723 return 0; 4724 } 4725 case Intrinsic::eh_sjlj_longjmp: { 4726 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4727 getRoot(), getValue(I.getArgOperand(0)))); 4728 return 0; 4729 } 4730 4731 case Intrinsic::x86_mmx_pslli_w: 4732 case Intrinsic::x86_mmx_pslli_d: 4733 case Intrinsic::x86_mmx_pslli_q: 4734 case Intrinsic::x86_mmx_psrli_w: 4735 case Intrinsic::x86_mmx_psrli_d: 4736 case Intrinsic::x86_mmx_psrli_q: 4737 case Intrinsic::x86_mmx_psrai_w: 4738 case Intrinsic::x86_mmx_psrai_d: { 4739 SDValue ShAmt = getValue(I.getArgOperand(1)); 4740 if (isa<ConstantSDNode>(ShAmt)) { 4741 visitTargetIntrinsic(I, Intrinsic); 4742 return 0; 4743 } 4744 unsigned NewIntrinsic = 0; 4745 EVT ShAmtVT = MVT::v2i32; 4746 switch (Intrinsic) { 4747 case Intrinsic::x86_mmx_pslli_w: 4748 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4749 break; 4750 case Intrinsic::x86_mmx_pslli_d: 4751 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4752 break; 4753 case Intrinsic::x86_mmx_pslli_q: 4754 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4755 break; 4756 case Intrinsic::x86_mmx_psrli_w: 4757 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4758 break; 4759 case Intrinsic::x86_mmx_psrli_d: 4760 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4761 break; 4762 case Intrinsic::x86_mmx_psrli_q: 4763 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4764 break; 4765 case Intrinsic::x86_mmx_psrai_w: 4766 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4767 break; 4768 case Intrinsic::x86_mmx_psrai_d: 4769 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4770 break; 4771 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4772 } 4773 4774 // The vector shift intrinsics with scalars uses 32b shift amounts but 4775 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4776 // to be zero. 4777 // We must do this early because v2i32 is not a legal type. 4778 SDValue ShOps[2]; 4779 ShOps[0] = ShAmt; 4780 ShOps[1] = DAG.getConstant(0, MVT::i32); 4781 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4782 EVT DestVT = TLI.getValueType(I.getType()); 4783 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4784 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4785 DAG.getConstant(NewIntrinsic, MVT::i32), 4786 getValue(I.getArgOperand(0)), ShAmt); 4787 setValue(&I, Res); 4788 return 0; 4789 } 4790 case Intrinsic::x86_avx_vinsertf128_pd_256: 4791 case Intrinsic::x86_avx_vinsertf128_ps_256: 4792 case Intrinsic::x86_avx_vinsertf128_si_256: 4793 case Intrinsic::x86_avx2_vinserti128: { 4794 EVT DestVT = TLI.getValueType(I.getType()); 4795 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4796 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4797 ElVT.getVectorNumElements(); 4798 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4799 getValue(I.getArgOperand(0)), 4800 getValue(I.getArgOperand(1)), 4801 DAG.getIntPtrConstant(Idx)); 4802 setValue(&I, Res); 4803 return 0; 4804 } 4805 case Intrinsic::x86_avx_vextractf128_pd_256: 4806 case Intrinsic::x86_avx_vextractf128_ps_256: 4807 case Intrinsic::x86_avx_vextractf128_si_256: 4808 case Intrinsic::x86_avx2_vextracti128: { 4809 EVT DestVT = TLI.getValueType(I.getType()); 4810 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4811 DestVT.getVectorNumElements(); 4812 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4813 getValue(I.getArgOperand(0)), 4814 DAG.getIntPtrConstant(Idx)); 4815 setValue(&I, Res); 4816 return 0; 4817 } 4818 case Intrinsic::convertff: 4819 case Intrinsic::convertfsi: 4820 case Intrinsic::convertfui: 4821 case Intrinsic::convertsif: 4822 case Intrinsic::convertuif: 4823 case Intrinsic::convertss: 4824 case Intrinsic::convertsu: 4825 case Intrinsic::convertus: 4826 case Intrinsic::convertuu: { 4827 ISD::CvtCode Code = ISD::CVT_INVALID; 4828 switch (Intrinsic) { 4829 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4830 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4831 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4832 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4833 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4834 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4835 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4836 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4837 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4838 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4839 } 4840 EVT DestVT = TLI.getValueType(I.getType()); 4841 const Value *Op1 = I.getArgOperand(0); 4842 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1), 4843 DAG.getValueType(DestVT), 4844 DAG.getValueType(getValue(Op1).getValueType()), 4845 getValue(I.getArgOperand(1)), 4846 getValue(I.getArgOperand(2)), 4847 Code); 4848 setValue(&I, Res); 4849 return 0; 4850 } 4851 case Intrinsic::powi: 4852 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4853 getValue(I.getArgOperand(1)), DAG)); 4854 return 0; 4855 case Intrinsic::log: 4856 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4857 return 0; 4858 case Intrinsic::log2: 4859 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4860 return 0; 4861 case Intrinsic::log10: 4862 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4863 return 0; 4864 case Intrinsic::exp: 4865 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4866 return 0; 4867 case Intrinsic::exp2: 4868 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4869 return 0; 4870 case Intrinsic::pow: 4871 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)), 4872 getValue(I.getArgOperand(1)), DAG, TLI)); 4873 return 0; 4874 case Intrinsic::sqrt: 4875 case Intrinsic::fabs: 4876 case Intrinsic::sin: 4877 case Intrinsic::cos: 4878 case Intrinsic::floor: 4879 case Intrinsic::ceil: 4880 case Intrinsic::trunc: 4881 case Intrinsic::rint: 4882 case Intrinsic::nearbyint: { 4883 unsigned Opcode; 4884 switch (Intrinsic) { 4885 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4886 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 4887 case Intrinsic::fabs: Opcode = ISD::FABS; break; 4888 case Intrinsic::sin: Opcode = ISD::FSIN; break; 4889 case Intrinsic::cos: Opcode = ISD::FCOS; break; 4890 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 4891 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 4892 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 4893 case Intrinsic::rint: Opcode = ISD::FRINT; break; 4894 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 4895 } 4896 4897 setValue(&I, DAG.getNode(Opcode, dl, 4898 getValue(I.getArgOperand(0)).getValueType(), 4899 getValue(I.getArgOperand(0)))); 4900 return 0; 4901 } 4902 case Intrinsic::fma: 4903 setValue(&I, DAG.getNode(ISD::FMA, dl, 4904 getValue(I.getArgOperand(0)).getValueType(), 4905 getValue(I.getArgOperand(0)), 4906 getValue(I.getArgOperand(1)), 4907 getValue(I.getArgOperand(2)))); 4908 return 0; 4909 case Intrinsic::fmuladd: { 4910 EVT VT = TLI.getValueType(I.getType()); 4911 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4912 TLI.isOperationLegalOrCustom(ISD::FMA, VT) && 4913 TLI.isFMAFasterThanMulAndAdd(VT)){ 4914 setValue(&I, DAG.getNode(ISD::FMA, dl, 4915 getValue(I.getArgOperand(0)).getValueType(), 4916 getValue(I.getArgOperand(0)), 4917 getValue(I.getArgOperand(1)), 4918 getValue(I.getArgOperand(2)))); 4919 } else { 4920 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4921 getValue(I.getArgOperand(0)).getValueType(), 4922 getValue(I.getArgOperand(0)), 4923 getValue(I.getArgOperand(1))); 4924 SDValue Add = DAG.getNode(ISD::FADD, dl, 4925 getValue(I.getArgOperand(0)).getValueType(), 4926 Mul, 4927 getValue(I.getArgOperand(2))); 4928 setValue(&I, Add); 4929 } 4930 return 0; 4931 } 4932 case Intrinsic::convert_to_fp16: 4933 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4934 MVT::i16, getValue(I.getArgOperand(0)))); 4935 return 0; 4936 case Intrinsic::convert_from_fp16: 4937 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4938 MVT::f32, getValue(I.getArgOperand(0)))); 4939 return 0; 4940 case Intrinsic::pcmarker: { 4941 SDValue Tmp = getValue(I.getArgOperand(0)); 4942 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4943 return 0; 4944 } 4945 case Intrinsic::readcyclecounter: { 4946 SDValue Op = getRoot(); 4947 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4948 DAG.getVTList(MVT::i64, MVT::Other), 4949 &Op, 1); 4950 setValue(&I, Res); 4951 DAG.setRoot(Res.getValue(1)); 4952 return 0; 4953 } 4954 case Intrinsic::bswap: 4955 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4956 getValue(I.getArgOperand(0)).getValueType(), 4957 getValue(I.getArgOperand(0)))); 4958 return 0; 4959 case Intrinsic::cttz: { 4960 SDValue Arg = getValue(I.getArgOperand(0)); 4961 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4962 EVT Ty = Arg.getValueType(); 4963 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4964 dl, Ty, Arg)); 4965 return 0; 4966 } 4967 case Intrinsic::ctlz: { 4968 SDValue Arg = getValue(I.getArgOperand(0)); 4969 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4970 EVT Ty = Arg.getValueType(); 4971 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4972 dl, Ty, Arg)); 4973 return 0; 4974 } 4975 case Intrinsic::ctpop: { 4976 SDValue Arg = getValue(I.getArgOperand(0)); 4977 EVT Ty = Arg.getValueType(); 4978 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4979 return 0; 4980 } 4981 case Intrinsic::stacksave: { 4982 SDValue Op = getRoot(); 4983 Res = DAG.getNode(ISD::STACKSAVE, dl, 4984 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4985 setValue(&I, Res); 4986 DAG.setRoot(Res.getValue(1)); 4987 return 0; 4988 } 4989 case Intrinsic::stackrestore: { 4990 Res = getValue(I.getArgOperand(0)); 4991 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4992 return 0; 4993 } 4994 case Intrinsic::stackprotector: { 4995 // Emit code into the DAG to store the stack guard onto the stack. 4996 MachineFunction &MF = DAG.getMachineFunction(); 4997 MachineFrameInfo *MFI = MF.getFrameInfo(); 4998 EVT PtrTy = TLI.getPointerTy(); 4999 5000 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5001 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5002 5003 int FI = FuncInfo.StaticAllocaMap[Slot]; 5004 MFI->setStackProtectorIndex(FI); 5005 5006 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5007 5008 // Store the stack protector onto the stack. 5009 Res = DAG.getStore(getRoot(), dl, Src, FIN, 5010 MachinePointerInfo::getFixedStack(FI), 5011 true, false, 0); 5012 setValue(&I, Res); 5013 DAG.setRoot(Res); 5014 return 0; 5015 } 5016 case Intrinsic::objectsize: { 5017 // If we don't know by now, we're never going to know. 5018 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5019 5020 assert(CI && "Non-constant type in __builtin_object_size?"); 5021 5022 SDValue Arg = getValue(I.getCalledValue()); 5023 EVT Ty = Arg.getValueType(); 5024 5025 if (CI->isZero()) 5026 Res = DAG.getConstant(-1ULL, Ty); 5027 else 5028 Res = DAG.getConstant(0, Ty); 5029 5030 setValue(&I, Res); 5031 return 0; 5032 } 5033 case Intrinsic::var_annotation: 5034 // Discard annotate attributes 5035 return 0; 5036 5037 case Intrinsic::init_trampoline: { 5038 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5039 5040 SDValue Ops[6]; 5041 Ops[0] = getRoot(); 5042 Ops[1] = getValue(I.getArgOperand(0)); 5043 Ops[2] = getValue(I.getArgOperand(1)); 5044 Ops[3] = getValue(I.getArgOperand(2)); 5045 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5046 Ops[5] = DAG.getSrcValue(F); 5047 5048 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5049 5050 DAG.setRoot(Res); 5051 return 0; 5052 } 5053 case Intrinsic::adjust_trampoline: { 5054 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5055 TLI.getPointerTy(), 5056 getValue(I.getArgOperand(0)))); 5057 return 0; 5058 } 5059 case Intrinsic::gcroot: 5060 if (GFI) { 5061 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5062 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5063 5064 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5065 GFI->addStackRoot(FI->getIndex(), TypeMap); 5066 } 5067 return 0; 5068 case Intrinsic::gcread: 5069 case Intrinsic::gcwrite: 5070 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5071 case Intrinsic::flt_rounds: 5072 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5073 return 0; 5074 5075 case Intrinsic::expect: { 5076 // Just replace __builtin_expect(exp, c) with EXP. 5077 setValue(&I, getValue(I.getArgOperand(0))); 5078 return 0; 5079 } 5080 5081 case Intrinsic::debugtrap: 5082 case Intrinsic::trap: { 5083 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5084 if (TrapFuncName.empty()) { 5085 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5086 ISD::TRAP : ISD::DEBUGTRAP; 5087 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot())); 5088 return 0; 5089 } 5090 TargetLowering::ArgListTy Args; 5091 TargetLowering:: 5092 CallLoweringInfo CLI(getRoot(), I.getType(), 5093 false, false, false, false, 0, CallingConv::C, 5094 /*isTailCall=*/false, 5095 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5096 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5097 Args, DAG, dl); 5098 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5099 DAG.setRoot(Result.second); 5100 return 0; 5101 } 5102 5103 case Intrinsic::uadd_with_overflow: 5104 case Intrinsic::sadd_with_overflow: 5105 case Intrinsic::usub_with_overflow: 5106 case Intrinsic::ssub_with_overflow: 5107 case Intrinsic::umul_with_overflow: 5108 case Intrinsic::smul_with_overflow: { 5109 ISD::NodeType Op; 5110 switch (Intrinsic) { 5111 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5112 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5113 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5114 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5115 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5116 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5117 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5118 } 5119 SDValue Op1 = getValue(I.getArgOperand(0)); 5120 SDValue Op2 = getValue(I.getArgOperand(1)); 5121 5122 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5123 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2)); 5124 return 0; 5125 } 5126 case Intrinsic::prefetch: { 5127 SDValue Ops[5]; 5128 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5129 Ops[0] = getRoot(); 5130 Ops[1] = getValue(I.getArgOperand(0)); 5131 Ops[2] = getValue(I.getArgOperand(1)); 5132 Ops[3] = getValue(I.getArgOperand(2)); 5133 Ops[4] = getValue(I.getArgOperand(3)); 5134 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5135 DAG.getVTList(MVT::Other), 5136 &Ops[0], 5, 5137 EVT::getIntegerVT(*Context, 8), 5138 MachinePointerInfo(I.getArgOperand(0)), 5139 0, /* align */ 5140 false, /* volatile */ 5141 rw==0, /* read */ 5142 rw==1)); /* write */ 5143 return 0; 5144 } 5145 case Intrinsic::lifetime_start: 5146 case Intrinsic::lifetime_end: { 5147 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5148 // Stack coloring is not enabled in O0, discard region information. 5149 if (TM.getOptLevel() == CodeGenOpt::None) 5150 return 0; 5151 5152 SmallVector<Value *, 4> Allocas; 5153 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5154 5155 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(), 5156 E = Allocas.end(); Object != E; ++Object) { 5157 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5158 5159 // Could not find an Alloca. 5160 if (!LifetimeObject) 5161 continue; 5162 5163 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5164 5165 SDValue Ops[2]; 5166 Ops[0] = getRoot(); 5167 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true); 5168 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5169 5170 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2); 5171 DAG.setRoot(Res); 5172 } 5173 } 5174 case Intrinsic::invariant_start: 5175 // Discard region information. 5176 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5177 return 0; 5178 case Intrinsic::invariant_end: 5179 // Discard region information. 5180 return 0; 5181 case Intrinsic::donothing: 5182 // ignore 5183 return 0; 5184 } 5185} 5186 5187void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5188 bool isTailCall, 5189 MachineBasicBlock *LandingPad) { 5190 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5191 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5192 Type *RetTy = FTy->getReturnType(); 5193 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5194 MCSymbol *BeginLabel = 0; 5195 5196 TargetLowering::ArgListTy Args; 5197 TargetLowering::ArgListEntry Entry; 5198 Args.reserve(CS.arg_size()); 5199 5200 // Check whether the function can return without sret-demotion. 5201 SmallVector<ISD::OutputArg, 4> Outs; 5202 GetReturnInfo(RetTy, CS.getAttributes(), Outs, TLI); 5203 5204 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5205 DAG.getMachineFunction(), 5206 FTy->isVarArg(), Outs, 5207 FTy->getContext()); 5208 5209 SDValue DemoteStackSlot; 5210 int DemoteStackIdx = -100; 5211 5212 if (!CanLowerReturn) { 5213 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize( 5214 FTy->getReturnType()); 5215 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment( 5216 FTy->getReturnType()); 5217 MachineFunction &MF = DAG.getMachineFunction(); 5218 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5219 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5220 5221 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5222 Entry.Node = DemoteStackSlot; 5223 Entry.Ty = StackSlotPtrType; 5224 Entry.isSExt = false; 5225 Entry.isZExt = false; 5226 Entry.isInReg = false; 5227 Entry.isSRet = true; 5228 Entry.isNest = false; 5229 Entry.isByVal = false; 5230 Entry.Alignment = Align; 5231 Args.push_back(Entry); 5232 RetTy = Type::getVoidTy(FTy->getContext()); 5233 } 5234 5235 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5236 i != e; ++i) { 5237 const Value *V = *i; 5238 5239 // Skip empty types 5240 if (V->getType()->isEmptyTy()) 5241 continue; 5242 5243 SDValue ArgNode = getValue(V); 5244 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5245 5246 unsigned attrInd = i - CS.arg_begin() + 1; 5247 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5248 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5249 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5250 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5251 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5252 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5253 Entry.Alignment = CS.getParamAlignment(attrInd); 5254 Args.push_back(Entry); 5255 } 5256 5257 if (LandingPad) { 5258 // Insert a label before the invoke call to mark the try range. This can be 5259 // used to detect deletion of the invoke via the MachineModuleInfo. 5260 BeginLabel = MMI.getContext().CreateTempSymbol(); 5261 5262 // For SjLj, keep track of which landing pads go with which invokes 5263 // so as to maintain the ordering of pads in the LSDA. 5264 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5265 if (CallSiteIndex) { 5266 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5267 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5268 5269 // Now that the call site is handled, stop tracking it. 5270 MMI.setCurrentCallSite(0); 5271 } 5272 5273 // Both PendingLoads and PendingExports must be flushed here; 5274 // this call might not return. 5275 (void)getRoot(); 5276 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5277 } 5278 5279 // Check if target-independent constraints permit a tail call here. 5280 // Target-dependent constraints are checked within TLI.LowerCallTo. 5281 if (isTailCall && !isInTailCallPosition(CS, TLI)) 5282 isTailCall = false; 5283 5284 TargetLowering:: 5285 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5286 getCurDebugLoc(), CS); 5287 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5288 assert((isTailCall || Result.second.getNode()) && 5289 "Non-null chain expected with non-tail call!"); 5290 assert((Result.second.getNode() || !Result.first.getNode()) && 5291 "Null value expected with tail call!"); 5292 if (Result.first.getNode()) { 5293 setValue(CS.getInstruction(), Result.first); 5294 } else if (!CanLowerReturn && Result.second.getNode()) { 5295 // The instruction result is the result of loading from the 5296 // hidden sret parameter. 5297 SmallVector<EVT, 1> PVTs; 5298 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5299 5300 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5301 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5302 EVT PtrVT = PVTs[0]; 5303 5304 SmallVector<EVT, 4> RetTys; 5305 SmallVector<uint64_t, 4> Offsets; 5306 RetTy = FTy->getReturnType(); 5307 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5308 5309 unsigned NumValues = RetTys.size(); 5310 SmallVector<SDValue, 4> Values(NumValues); 5311 SmallVector<SDValue, 4> Chains(NumValues); 5312 5313 for (unsigned i = 0; i < NumValues; ++i) { 5314 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5315 DemoteStackSlot, 5316 DAG.getConstant(Offsets[i], PtrVT)); 5317 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5318 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5319 false, false, false, 1); 5320 Values[i] = L; 5321 Chains[i] = L.getValue(1); 5322 } 5323 5324 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5325 MVT::Other, &Chains[0], NumValues); 5326 PendingLoads.push_back(Chain); 5327 5328 setValue(CS.getInstruction(), 5329 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5330 DAG.getVTList(&RetTys[0], RetTys.size()), 5331 &Values[0], Values.size())); 5332 } 5333 5334 // Assign order to nodes here. If the call does not produce a result, it won't 5335 // be mapped to a SDNode and visit() will not assign it an order number. 5336 if (!Result.second.getNode()) { 5337 // As a special case, a null chain means that a tail call has been emitted and 5338 // the DAG root is already updated. 5339 HasTailCall = true; 5340 ++SDNodeOrder; 5341 AssignOrderingToNode(DAG.getRoot().getNode()); 5342 } else { 5343 DAG.setRoot(Result.second); 5344 ++SDNodeOrder; 5345 AssignOrderingToNode(Result.second.getNode()); 5346 } 5347 5348 if (LandingPad) { 5349 // Insert a label at the end of the invoke call to mark the try range. This 5350 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5351 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5352 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5353 5354 // Inform MachineModuleInfo of range. 5355 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5356 } 5357} 5358 5359/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5360/// value is equal or not-equal to zero. 5361static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5362 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5363 UI != E; ++UI) { 5364 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5365 if (IC->isEquality()) 5366 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5367 if (C->isNullValue()) 5368 continue; 5369 // Unknown instruction. 5370 return false; 5371 } 5372 return true; 5373} 5374 5375static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5376 Type *LoadTy, 5377 SelectionDAGBuilder &Builder) { 5378 5379 // Check to see if this load can be trivially constant folded, e.g. if the 5380 // input is from a string literal. 5381 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5382 // Cast pointer to the type we really want to load. 5383 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5384 PointerType::getUnqual(LoadTy)); 5385 5386 if (const Constant *LoadCst = 5387 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5388 Builder.TD)) 5389 return Builder.getValue(LoadCst); 5390 } 5391 5392 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5393 // still constant memory, the input chain can be the entry node. 5394 SDValue Root; 5395 bool ConstantMemory = false; 5396 5397 // Do not serialize (non-volatile) loads of constant memory with anything. 5398 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5399 Root = Builder.DAG.getEntryNode(); 5400 ConstantMemory = true; 5401 } else { 5402 // Do not serialize non-volatile loads against each other. 5403 Root = Builder.DAG.getRoot(); 5404 } 5405 5406 SDValue Ptr = Builder.getValue(PtrVal); 5407 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5408 Ptr, MachinePointerInfo(PtrVal), 5409 false /*volatile*/, 5410 false /*nontemporal*/, 5411 false /*isinvariant*/, 1 /* align=1 */); 5412 5413 if (!ConstantMemory) 5414 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5415 return LoadVal; 5416} 5417 5418 5419/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5420/// If so, return true and lower it, otherwise return false and it will be 5421/// lowered like a normal call. 5422bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5423 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5424 if (I.getNumArgOperands() != 3) 5425 return false; 5426 5427 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5428 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5429 !I.getArgOperand(2)->getType()->isIntegerTy() || 5430 !I.getType()->isIntegerTy()) 5431 return false; 5432 5433 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5434 5435 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5436 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5437 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5438 bool ActuallyDoIt = true; 5439 MVT LoadVT; 5440 Type *LoadTy; 5441 switch (Size->getZExtValue()) { 5442 default: 5443 LoadVT = MVT::Other; 5444 LoadTy = 0; 5445 ActuallyDoIt = false; 5446 break; 5447 case 2: 5448 LoadVT = MVT::i16; 5449 LoadTy = Type::getInt16Ty(Size->getContext()); 5450 break; 5451 case 4: 5452 LoadVT = MVT::i32; 5453 LoadTy = Type::getInt32Ty(Size->getContext()); 5454 break; 5455 case 8: 5456 LoadVT = MVT::i64; 5457 LoadTy = Type::getInt64Ty(Size->getContext()); 5458 break; 5459 /* 5460 case 16: 5461 LoadVT = MVT::v4i32; 5462 LoadTy = Type::getInt32Ty(Size->getContext()); 5463 LoadTy = VectorType::get(LoadTy, 4); 5464 break; 5465 */ 5466 } 5467 5468 // This turns into unaligned loads. We only do this if the target natively 5469 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5470 // we'll only produce a small number of byte loads. 5471 5472 // Require that we can find a legal MVT, and only do this if the target 5473 // supports unaligned loads of that type. Expanding into byte loads would 5474 // bloat the code. 5475 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5476 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5477 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5478 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5479 ActuallyDoIt = false; 5480 } 5481 5482 if (ActuallyDoIt) { 5483 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5484 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5485 5486 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5487 ISD::SETNE); 5488 EVT CallVT = TLI.getValueType(I.getType(), true); 5489 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5490 return true; 5491 } 5492 } 5493 5494 5495 return false; 5496} 5497 5498/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5499/// operation (as expected), translate it to an SDNode with the specified opcode 5500/// and return true. 5501bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5502 unsigned Opcode) { 5503 // Sanity check that it really is a unary floating-point call. 5504 if (I.getNumArgOperands() != 1 || 5505 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5506 I.getType() != I.getArgOperand(0)->getType() || 5507 !I.onlyReadsMemory()) 5508 return false; 5509 5510 SDValue Tmp = getValue(I.getArgOperand(0)); 5511 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp)); 5512 return true; 5513} 5514 5515void SelectionDAGBuilder::visitCall(const CallInst &I) { 5516 // Handle inline assembly differently. 5517 if (isa<InlineAsm>(I.getCalledValue())) { 5518 visitInlineAsm(&I); 5519 return; 5520 } 5521 5522 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5523 ComputeUsesVAFloatArgument(I, &MMI); 5524 5525 const char *RenameFn = 0; 5526 if (Function *F = I.getCalledFunction()) { 5527 if (F->isDeclaration()) { 5528 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5529 if (unsigned IID = II->getIntrinsicID(F)) { 5530 RenameFn = visitIntrinsicCall(I, IID); 5531 if (!RenameFn) 5532 return; 5533 } 5534 } 5535 if (unsigned IID = F->getIntrinsicID()) { 5536 RenameFn = visitIntrinsicCall(I, IID); 5537 if (!RenameFn) 5538 return; 5539 } 5540 } 5541 5542 // Check for well-known libc/libm calls. If the function is internal, it 5543 // can't be a library call. 5544 LibFunc::Func Func; 5545 if (!F->hasLocalLinkage() && F->hasName() && 5546 LibInfo->getLibFunc(F->getName(), Func) && 5547 LibInfo->hasOptimizedCodeGen(Func)) { 5548 switch (Func) { 5549 default: break; 5550 case LibFunc::copysign: 5551 case LibFunc::copysignf: 5552 case LibFunc::copysignl: 5553 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5554 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5555 I.getType() == I.getArgOperand(0)->getType() && 5556 I.getType() == I.getArgOperand(1)->getType() && 5557 I.onlyReadsMemory()) { 5558 SDValue LHS = getValue(I.getArgOperand(0)); 5559 SDValue RHS = getValue(I.getArgOperand(1)); 5560 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5561 LHS.getValueType(), LHS, RHS)); 5562 return; 5563 } 5564 break; 5565 case LibFunc::fabs: 5566 case LibFunc::fabsf: 5567 case LibFunc::fabsl: 5568 if (visitUnaryFloatCall(I, ISD::FABS)) 5569 return; 5570 break; 5571 case LibFunc::sin: 5572 case LibFunc::sinf: 5573 case LibFunc::sinl: 5574 if (visitUnaryFloatCall(I, ISD::FSIN)) 5575 return; 5576 break; 5577 case LibFunc::cos: 5578 case LibFunc::cosf: 5579 case LibFunc::cosl: 5580 if (visitUnaryFloatCall(I, ISD::FCOS)) 5581 return; 5582 break; 5583 case LibFunc::sqrt: 5584 case LibFunc::sqrtf: 5585 case LibFunc::sqrtl: 5586 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5587 return; 5588 break; 5589 case LibFunc::floor: 5590 case LibFunc::floorf: 5591 case LibFunc::floorl: 5592 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5593 return; 5594 break; 5595 case LibFunc::nearbyint: 5596 case LibFunc::nearbyintf: 5597 case LibFunc::nearbyintl: 5598 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5599 return; 5600 break; 5601 case LibFunc::ceil: 5602 case LibFunc::ceilf: 5603 case LibFunc::ceill: 5604 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5605 return; 5606 break; 5607 case LibFunc::rint: 5608 case LibFunc::rintf: 5609 case LibFunc::rintl: 5610 if (visitUnaryFloatCall(I, ISD::FRINT)) 5611 return; 5612 break; 5613 case LibFunc::trunc: 5614 case LibFunc::truncf: 5615 case LibFunc::truncl: 5616 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5617 return; 5618 break; 5619 case LibFunc::log2: 5620 case LibFunc::log2f: 5621 case LibFunc::log2l: 5622 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5623 return; 5624 break; 5625 case LibFunc::exp2: 5626 case LibFunc::exp2f: 5627 case LibFunc::exp2l: 5628 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5629 return; 5630 break; 5631 case LibFunc::memcmp: 5632 if (visitMemCmpCall(I)) 5633 return; 5634 break; 5635 } 5636 } 5637 } 5638 5639 SDValue Callee; 5640 if (!RenameFn) 5641 Callee = getValue(I.getCalledValue()); 5642 else 5643 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5644 5645 // Check if we can potentially perform a tail call. More detailed checking is 5646 // be done within LowerCallTo, after more information about the call is known. 5647 LowerCallTo(&I, Callee, I.isTailCall()); 5648} 5649 5650namespace { 5651 5652/// AsmOperandInfo - This contains information for each constraint that we are 5653/// lowering. 5654class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5655public: 5656 /// CallOperand - If this is the result output operand or a clobber 5657 /// this is null, otherwise it is the incoming operand to the CallInst. 5658 /// This gets modified as the asm is processed. 5659 SDValue CallOperand; 5660 5661 /// AssignedRegs - If this is a register or register class operand, this 5662 /// contains the set of register corresponding to the operand. 5663 RegsForValue AssignedRegs; 5664 5665 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5666 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5667 } 5668 5669 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5670 /// corresponds to. If there is no Value* for this operand, it returns 5671 /// MVT::Other. 5672 EVT getCallOperandValEVT(LLVMContext &Context, 5673 const TargetLowering &TLI, 5674 const DataLayout *TD) const { 5675 if (CallOperandVal == 0) return MVT::Other; 5676 5677 if (isa<BasicBlock>(CallOperandVal)) 5678 return TLI.getPointerTy(); 5679 5680 llvm::Type *OpTy = CallOperandVal->getType(); 5681 5682 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5683 // If this is an indirect operand, the operand is a pointer to the 5684 // accessed type. 5685 if (isIndirect) { 5686 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5687 if (!PtrTy) 5688 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5689 OpTy = PtrTy->getElementType(); 5690 } 5691 5692 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5693 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5694 if (STy->getNumElements() == 1) 5695 OpTy = STy->getElementType(0); 5696 5697 // If OpTy is not a single value, it may be a struct/union that we 5698 // can tile with integers. 5699 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5700 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5701 switch (BitSize) { 5702 default: break; 5703 case 1: 5704 case 8: 5705 case 16: 5706 case 32: 5707 case 64: 5708 case 128: 5709 OpTy = IntegerType::get(Context, BitSize); 5710 break; 5711 } 5712 } 5713 5714 return TLI.getValueType(OpTy, true); 5715 } 5716}; 5717 5718typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5719 5720} // end anonymous namespace 5721 5722/// GetRegistersForValue - Assign registers (virtual or physical) for the 5723/// specified operand. We prefer to assign virtual registers, to allow the 5724/// register allocator to handle the assignment process. However, if the asm 5725/// uses features that we can't model on machineinstrs, we have SDISel do the 5726/// allocation. This produces generally horrible, but correct, code. 5727/// 5728/// OpInfo describes the operand. 5729/// 5730static void GetRegistersForValue(SelectionDAG &DAG, 5731 const TargetLowering &TLI, 5732 DebugLoc DL, 5733 SDISelAsmOperandInfo &OpInfo) { 5734 LLVMContext &Context = *DAG.getContext(); 5735 5736 MachineFunction &MF = DAG.getMachineFunction(); 5737 SmallVector<unsigned, 4> Regs; 5738 5739 // If this is a constraint for a single physreg, or a constraint for a 5740 // register class, find it. 5741 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5742 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5743 OpInfo.ConstraintVT); 5744 5745 unsigned NumRegs = 1; 5746 if (OpInfo.ConstraintVT != MVT::Other) { 5747 // If this is a FP input in an integer register (or visa versa) insert a bit 5748 // cast of the input value. More generally, handle any case where the input 5749 // value disagrees with the register class we plan to stick this in. 5750 if (OpInfo.Type == InlineAsm::isInput && 5751 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5752 // Try to convert to the first EVT that the reg class contains. If the 5753 // types are identical size, use a bitcast to convert (e.g. two differing 5754 // vector types). 5755 MVT RegVT = *PhysReg.second->vt_begin(); 5756 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5757 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5758 RegVT, OpInfo.CallOperand); 5759 OpInfo.ConstraintVT = RegVT; 5760 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5761 // If the input is a FP value and we want it in FP registers, do a 5762 // bitcast to the corresponding integer type. This turns an f64 value 5763 // into i64, which can be passed with two i32 values on a 32-bit 5764 // machine. 5765 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); 5766 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5767 RegVT, OpInfo.CallOperand); 5768 OpInfo.ConstraintVT = RegVT; 5769 } 5770 } 5771 5772 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5773 } 5774 5775 MVT RegVT; 5776 EVT ValueVT = OpInfo.ConstraintVT; 5777 5778 // If this is a constraint for a specific physical register, like {r17}, 5779 // assign it now. 5780 if (unsigned AssignedReg = PhysReg.first) { 5781 const TargetRegisterClass *RC = PhysReg.second; 5782 if (OpInfo.ConstraintVT == MVT::Other) 5783 ValueVT = *RC->vt_begin(); 5784 5785 // Get the actual register value type. This is important, because the user 5786 // may have asked for (e.g.) the AX register in i32 type. We need to 5787 // remember that AX is actually i16 to get the right extension. 5788 RegVT = *RC->vt_begin(); 5789 5790 // This is a explicit reference to a physical register. 5791 Regs.push_back(AssignedReg); 5792 5793 // If this is an expanded reference, add the rest of the regs to Regs. 5794 if (NumRegs != 1) { 5795 TargetRegisterClass::iterator I = RC->begin(); 5796 for (; *I != AssignedReg; ++I) 5797 assert(I != RC->end() && "Didn't find reg!"); 5798 5799 // Already added the first reg. 5800 --NumRegs; ++I; 5801 for (; NumRegs; --NumRegs, ++I) { 5802 assert(I != RC->end() && "Ran out of registers to allocate!"); 5803 Regs.push_back(*I); 5804 } 5805 } 5806 5807 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5808 return; 5809 } 5810 5811 // Otherwise, if this was a reference to an LLVM register class, create vregs 5812 // for this reference. 5813 if (const TargetRegisterClass *RC = PhysReg.second) { 5814 RegVT = *RC->vt_begin(); 5815 if (OpInfo.ConstraintVT == MVT::Other) 5816 ValueVT = RegVT; 5817 5818 // Create the appropriate number of virtual registers. 5819 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5820 for (; NumRegs; --NumRegs) 5821 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5822 5823 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5824 return; 5825 } 5826 5827 // Otherwise, we couldn't allocate enough registers for this. 5828} 5829 5830/// visitInlineAsm - Handle a call to an InlineAsm object. 5831/// 5832void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5833 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5834 5835 /// ConstraintOperands - Information about all of the constraints. 5836 SDISelAsmOperandInfoVector ConstraintOperands; 5837 5838 TargetLowering::AsmOperandInfoVector 5839 TargetConstraints = TLI.ParseConstraints(CS); 5840 5841 bool hasMemory = false; 5842 5843 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5844 unsigned ResNo = 0; // ResNo - The result number of the next output. 5845 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5846 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5847 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5848 5849 MVT OpVT = MVT::Other; 5850 5851 // Compute the value type for each operand. 5852 switch (OpInfo.Type) { 5853 case InlineAsm::isOutput: 5854 // Indirect outputs just consume an argument. 5855 if (OpInfo.isIndirect) { 5856 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5857 break; 5858 } 5859 5860 // The return value of the call is this value. As such, there is no 5861 // corresponding argument. 5862 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5863 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5864 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo)); 5865 } else { 5866 assert(ResNo == 0 && "Asm only has one result!"); 5867 OpVT = TLI.getSimpleValueType(CS.getType()); 5868 } 5869 ++ResNo; 5870 break; 5871 case InlineAsm::isInput: 5872 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5873 break; 5874 case InlineAsm::isClobber: 5875 // Nothing to do. 5876 break; 5877 } 5878 5879 // If this is an input or an indirect output, process the call argument. 5880 // BasicBlocks are labels, currently appearing only in asm's. 5881 if (OpInfo.CallOperandVal) { 5882 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5883 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5884 } else { 5885 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5886 } 5887 5888 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD). 5889 getSimpleVT(); 5890 } 5891 5892 OpInfo.ConstraintVT = OpVT; 5893 5894 // Indirect operand accesses access memory. 5895 if (OpInfo.isIndirect) 5896 hasMemory = true; 5897 else { 5898 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5899 TargetLowering::ConstraintType 5900 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5901 if (CType == TargetLowering::C_Memory) { 5902 hasMemory = true; 5903 break; 5904 } 5905 } 5906 } 5907 } 5908 5909 SDValue Chain, Flag; 5910 5911 // We won't need to flush pending loads if this asm doesn't touch 5912 // memory and is nonvolatile. 5913 if (hasMemory || IA->hasSideEffects()) 5914 Chain = getRoot(); 5915 else 5916 Chain = DAG.getRoot(); 5917 5918 // Second pass over the constraints: compute which constraint option to use 5919 // and assign registers to constraints that want a specific physreg. 5920 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5921 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5922 5923 // If this is an output operand with a matching input operand, look up the 5924 // matching input. If their types mismatch, e.g. one is an integer, the 5925 // other is floating point, or their sizes are different, flag it as an 5926 // error. 5927 if (OpInfo.hasMatchingInput()) { 5928 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5929 5930 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5931 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5932 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5933 OpInfo.ConstraintVT); 5934 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5935 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5936 Input.ConstraintVT); 5937 if ((OpInfo.ConstraintVT.isInteger() != 5938 Input.ConstraintVT.isInteger()) || 5939 (MatchRC.second != InputRC.second)) { 5940 report_fatal_error("Unsupported asm: input constraint" 5941 " with a matching output constraint of" 5942 " incompatible type!"); 5943 } 5944 Input.ConstraintVT = OpInfo.ConstraintVT; 5945 } 5946 } 5947 5948 // Compute the constraint code and ConstraintType to use. 5949 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5950 5951 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5952 OpInfo.Type == InlineAsm::isClobber) 5953 continue; 5954 5955 // If this is a memory input, and if the operand is not indirect, do what we 5956 // need to to provide an address for the memory input. 5957 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5958 !OpInfo.isIndirect) { 5959 assert((OpInfo.isMultipleAlternative || 5960 (OpInfo.Type == InlineAsm::isInput)) && 5961 "Can only indirectify direct input operands!"); 5962 5963 // Memory operands really want the address of the value. If we don't have 5964 // an indirect input, put it in the constpool if we can, otherwise spill 5965 // it to a stack slot. 5966 // TODO: This isn't quite right. We need to handle these according to 5967 // the addressing mode that the constraint wants. Also, this may take 5968 // an additional register for the computation and we don't want that 5969 // either. 5970 5971 // If the operand is a float, integer, or vector constant, spill to a 5972 // constant pool entry to get its address. 5973 const Value *OpVal = OpInfo.CallOperandVal; 5974 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5975 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5976 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5977 TLI.getPointerTy()); 5978 } else { 5979 // Otherwise, create a stack slot and emit a store to it before the 5980 // asm. 5981 Type *Ty = OpVal->getType(); 5982 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 5983 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty); 5984 MachineFunction &MF = DAG.getMachineFunction(); 5985 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5986 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5987 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5988 OpInfo.CallOperand, StackSlot, 5989 MachinePointerInfo::getFixedStack(SSFI), 5990 false, false, 0); 5991 OpInfo.CallOperand = StackSlot; 5992 } 5993 5994 // There is no longer a Value* corresponding to this operand. 5995 OpInfo.CallOperandVal = 0; 5996 5997 // It is now an indirect operand. 5998 OpInfo.isIndirect = true; 5999 } 6000 6001 // If this constraint is for a specific register, allocate it before 6002 // anything else. 6003 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6004 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6005 } 6006 6007 // Second pass - Loop over all of the operands, assigning virtual or physregs 6008 // to register class operands. 6009 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6010 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6011 6012 // C_Register operands have already been allocated, Other/Memory don't need 6013 // to be. 6014 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6015 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6016 } 6017 6018 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6019 std::vector<SDValue> AsmNodeOperands; 6020 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6021 AsmNodeOperands.push_back( 6022 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6023 TLI.getPointerTy())); 6024 6025 // If we have a !srcloc metadata node associated with it, we want to attach 6026 // this to the ultimately generated inline asm machineinstr. To do this, we 6027 // pass in the third operand as this (potentially null) inline asm MDNode. 6028 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6029 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6030 6031 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6032 // bits as operand 3. 6033 unsigned ExtraInfo = 0; 6034 if (IA->hasSideEffects()) 6035 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6036 if (IA->isAlignStack()) 6037 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6038 // Set the asm dialect. 6039 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6040 6041 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6042 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6043 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6044 6045 // Compute the constraint code and ConstraintType to use. 6046 TLI.ComputeConstraintToUse(OpInfo, SDValue()); 6047 6048 // Ideally, we would only check against memory constraints. However, the 6049 // meaning of an other constraint can be target-specific and we can't easily 6050 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6051 // for other constriants as well. 6052 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6053 OpInfo.ConstraintType == TargetLowering::C_Other) { 6054 if (OpInfo.Type == InlineAsm::isInput) 6055 ExtraInfo |= InlineAsm::Extra_MayLoad; 6056 else if (OpInfo.Type == InlineAsm::isOutput) 6057 ExtraInfo |= InlineAsm::Extra_MayStore; 6058 else if (OpInfo.Type == InlineAsm::isClobber) 6059 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 6060 } 6061 } 6062 6063 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6064 TLI.getPointerTy())); 6065 6066 // Loop over all of the inputs, copying the operand values into the 6067 // appropriate registers and processing the output regs. 6068 RegsForValue RetValRegs; 6069 6070 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6071 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6072 6073 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6074 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6075 6076 switch (OpInfo.Type) { 6077 case InlineAsm::isOutput: { 6078 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6079 OpInfo.ConstraintType != TargetLowering::C_Register) { 6080 // Memory output, or 'other' output (e.g. 'X' constraint). 6081 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6082 6083 // Add information to the INLINEASM node to know about this output. 6084 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6085 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6086 TLI.getPointerTy())); 6087 AsmNodeOperands.push_back(OpInfo.CallOperand); 6088 break; 6089 } 6090 6091 // Otherwise, this is a register or register class output. 6092 6093 // Copy the output from the appropriate register. Find a register that 6094 // we can use. 6095 if (OpInfo.AssignedRegs.Regs.empty()) { 6096 LLVMContext &Ctx = *DAG.getContext(); 6097 Ctx.emitError(CS.getInstruction(), 6098 "couldn't allocate output register for constraint '" + 6099 Twine(OpInfo.ConstraintCode) + "'"); 6100 break; 6101 } 6102 6103 // If this is an indirect operand, store through the pointer after the 6104 // asm. 6105 if (OpInfo.isIndirect) { 6106 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6107 OpInfo.CallOperandVal)); 6108 } else { 6109 // This is the result value of the call. 6110 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6111 // Concatenate this output onto the outputs list. 6112 RetValRegs.append(OpInfo.AssignedRegs); 6113 } 6114 6115 // Add information to the INLINEASM node to know that this register is 6116 // set. 6117 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6118 InlineAsm::Kind_RegDefEarlyClobber : 6119 InlineAsm::Kind_RegDef, 6120 false, 6121 0, 6122 DAG, 6123 AsmNodeOperands); 6124 break; 6125 } 6126 case InlineAsm::isInput: { 6127 SDValue InOperandVal = OpInfo.CallOperand; 6128 6129 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6130 // If this is required to match an output register we have already set, 6131 // just use its register. 6132 unsigned OperandNo = OpInfo.getMatchedOperand(); 6133 6134 // Scan until we find the definition we already emitted of this operand. 6135 // When we find it, create a RegsForValue operand. 6136 unsigned CurOp = InlineAsm::Op_FirstOperand; 6137 for (; OperandNo; --OperandNo) { 6138 // Advance to the next operand. 6139 unsigned OpFlag = 6140 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6141 assert((InlineAsm::isRegDefKind(OpFlag) || 6142 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6143 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6144 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6145 } 6146 6147 unsigned OpFlag = 6148 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6149 if (InlineAsm::isRegDefKind(OpFlag) || 6150 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6151 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6152 if (OpInfo.isIndirect) { 6153 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6154 LLVMContext &Ctx = *DAG.getContext(); 6155 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6156 " don't know how to handle tied " 6157 "indirect register inputs"); 6158 } 6159 6160 RegsForValue MatchedRegs; 6161 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6162 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6163 MatchedRegs.RegVTs.push_back(RegVT); 6164 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6165 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6166 i != e; ++i) 6167 MatchedRegs.Regs.push_back 6168 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6169 6170 // Use the produced MatchedRegs object to 6171 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6172 Chain, &Flag, CS.getInstruction()); 6173 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6174 true, OpInfo.getMatchedOperand(), 6175 DAG, AsmNodeOperands); 6176 break; 6177 } 6178 6179 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6180 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6181 "Unexpected number of operands"); 6182 // Add information to the INLINEASM node to know about this input. 6183 // See InlineAsm.h isUseOperandTiedToDef. 6184 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6185 OpInfo.getMatchedOperand()); 6186 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6187 TLI.getPointerTy())); 6188 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6189 break; 6190 } 6191 6192 // Treat indirect 'X' constraint as memory. 6193 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6194 OpInfo.isIndirect) 6195 OpInfo.ConstraintType = TargetLowering::C_Memory; 6196 6197 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6198 std::vector<SDValue> Ops; 6199 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6200 Ops, DAG); 6201 if (Ops.empty()) { 6202 LLVMContext &Ctx = *DAG.getContext(); 6203 Ctx.emitError(CS.getInstruction(), 6204 "invalid operand for inline asm constraint '" + 6205 Twine(OpInfo.ConstraintCode) + "'"); 6206 break; 6207 } 6208 6209 // Add information to the INLINEASM node to know about this input. 6210 unsigned ResOpType = 6211 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6212 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6213 TLI.getPointerTy())); 6214 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6215 break; 6216 } 6217 6218 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6219 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6220 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6221 "Memory operands expect pointer values"); 6222 6223 // Add information to the INLINEASM node to know about this input. 6224 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6225 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6226 TLI.getPointerTy())); 6227 AsmNodeOperands.push_back(InOperandVal); 6228 break; 6229 } 6230 6231 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6232 OpInfo.ConstraintType == TargetLowering::C_Register) && 6233 "Unknown constraint type!"); 6234 6235 // TODO: Support this. 6236 if (OpInfo.isIndirect) { 6237 LLVMContext &Ctx = *DAG.getContext(); 6238 Ctx.emitError(CS.getInstruction(), 6239 "Don't know how to handle indirect register inputs yet " 6240 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6241 break; 6242 } 6243 6244 // Copy the input into the appropriate registers. 6245 if (OpInfo.AssignedRegs.Regs.empty()) { 6246 LLVMContext &Ctx = *DAG.getContext(); 6247 Ctx.emitError(CS.getInstruction(), 6248 "couldn't allocate input reg for constraint '" + 6249 Twine(OpInfo.ConstraintCode) + "'"); 6250 break; 6251 } 6252 6253 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6254 Chain, &Flag, CS.getInstruction()); 6255 6256 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6257 DAG, AsmNodeOperands); 6258 break; 6259 } 6260 case InlineAsm::isClobber: { 6261 // Add the clobbered value to the operand list, so that the register 6262 // allocator is aware that the physreg got clobbered. 6263 if (!OpInfo.AssignedRegs.Regs.empty()) 6264 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6265 false, 0, DAG, 6266 AsmNodeOperands); 6267 break; 6268 } 6269 } 6270 } 6271 6272 // Finish up input operands. Set the input chain and add the flag last. 6273 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6274 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6275 6276 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6277 DAG.getVTList(MVT::Other, MVT::Glue), 6278 &AsmNodeOperands[0], AsmNodeOperands.size()); 6279 Flag = Chain.getValue(1); 6280 6281 // If this asm returns a register value, copy the result from that register 6282 // and set it as the value of the call. 6283 if (!RetValRegs.Regs.empty()) { 6284 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6285 Chain, &Flag, CS.getInstruction()); 6286 6287 // FIXME: Why don't we do this for inline asms with MRVs? 6288 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6289 EVT ResultType = TLI.getValueType(CS.getType()); 6290 6291 // If any of the results of the inline asm is a vector, it may have the 6292 // wrong width/num elts. This can happen for register classes that can 6293 // contain multiple different value types. The preg or vreg allocated may 6294 // not have the same VT as was expected. Convert it to the right type 6295 // with bit_convert. 6296 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6297 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6298 ResultType, Val); 6299 6300 } else if (ResultType != Val.getValueType() && 6301 ResultType.isInteger() && Val.getValueType().isInteger()) { 6302 // If a result value was tied to an input value, the computed result may 6303 // have a wider width than the expected result. Extract the relevant 6304 // portion. 6305 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6306 } 6307 6308 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6309 } 6310 6311 setValue(CS.getInstruction(), Val); 6312 // Don't need to use this as a chain in this case. 6313 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6314 return; 6315 } 6316 6317 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6318 6319 // Process indirect outputs, first output all of the flagged copies out of 6320 // physregs. 6321 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6322 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6323 const Value *Ptr = IndirectStoresToEmit[i].second; 6324 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6325 Chain, &Flag, IA); 6326 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6327 } 6328 6329 // Emit the non-flagged stores from the physregs. 6330 SmallVector<SDValue, 8> OutChains; 6331 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6332 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6333 StoresToEmit[i].first, 6334 getValue(StoresToEmit[i].second), 6335 MachinePointerInfo(StoresToEmit[i].second), 6336 false, false, 0); 6337 OutChains.push_back(Val); 6338 } 6339 6340 if (!OutChains.empty()) 6341 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6342 &OutChains[0], OutChains.size()); 6343 6344 DAG.setRoot(Chain); 6345} 6346 6347void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6348 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6349 MVT::Other, getRoot(), 6350 getValue(I.getArgOperand(0)), 6351 DAG.getSrcValue(I.getArgOperand(0)))); 6352} 6353 6354void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6355 const DataLayout &TD = *TLI.getDataLayout(); 6356 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6357 getRoot(), getValue(I.getOperand(0)), 6358 DAG.getSrcValue(I.getOperand(0)), 6359 TD.getABITypeAlignment(I.getType())); 6360 setValue(&I, V); 6361 DAG.setRoot(V.getValue(1)); 6362} 6363 6364void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6365 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6366 MVT::Other, getRoot(), 6367 getValue(I.getArgOperand(0)), 6368 DAG.getSrcValue(I.getArgOperand(0)))); 6369} 6370 6371void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6372 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6373 MVT::Other, getRoot(), 6374 getValue(I.getArgOperand(0)), 6375 getValue(I.getArgOperand(1)), 6376 DAG.getSrcValue(I.getArgOperand(0)), 6377 DAG.getSrcValue(I.getArgOperand(1)))); 6378} 6379 6380/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6381/// implementation, which just calls LowerCall. 6382/// FIXME: When all targets are 6383/// migrated to using LowerCall, this hook should be integrated into SDISel. 6384std::pair<SDValue, SDValue> 6385TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6386 // Handle all of the outgoing arguments. 6387 CLI.Outs.clear(); 6388 CLI.OutVals.clear(); 6389 ArgListTy &Args = CLI.Args; 6390 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6391 SmallVector<EVT, 4> ValueVTs; 6392 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6393 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6394 Value != NumValues; ++Value) { 6395 EVT VT = ValueVTs[Value]; 6396 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6397 SDValue Op = SDValue(Args[i].Node.getNode(), 6398 Args[i].Node.getResNo() + Value); 6399 ISD::ArgFlagsTy Flags; 6400 unsigned OriginalAlignment = 6401 getDataLayout()->getABITypeAlignment(ArgTy); 6402 6403 if (Args[i].isZExt) 6404 Flags.setZExt(); 6405 if (Args[i].isSExt) 6406 Flags.setSExt(); 6407 if (Args[i].isInReg) 6408 Flags.setInReg(); 6409 if (Args[i].isSRet) 6410 Flags.setSRet(); 6411 if (Args[i].isByVal) { 6412 Flags.setByVal(); 6413 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6414 Type *ElementTy = Ty->getElementType(); 6415 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 6416 // For ByVal, alignment should come from FE. BE will guess if this 6417 // info is not there but there are cases it cannot get right. 6418 unsigned FrameAlign; 6419 if (Args[i].Alignment) 6420 FrameAlign = Args[i].Alignment; 6421 else 6422 FrameAlign = getByValTypeAlignment(ElementTy); 6423 Flags.setByValAlign(FrameAlign); 6424 } 6425 if (Args[i].isNest) 6426 Flags.setNest(); 6427 Flags.setOrigAlign(OriginalAlignment); 6428 6429 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6430 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6431 SmallVector<SDValue, 4> Parts(NumParts); 6432 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6433 6434 if (Args[i].isSExt) 6435 ExtendKind = ISD::SIGN_EXTEND; 6436 else if (Args[i].isZExt) 6437 ExtendKind = ISD::ZERO_EXTEND; 6438 6439 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6440 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 6441 6442 for (unsigned j = 0; j != NumParts; ++j) { 6443 // if it isn't first piece, alignment must be 1 6444 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6445 i < CLI.NumFixedArgs, 6446 i, j*Parts[j].getValueType().getStoreSize()); 6447 if (NumParts > 1 && j == 0) 6448 MyFlags.Flags.setSplit(); 6449 else if (j != 0) 6450 MyFlags.Flags.setOrigAlign(1); 6451 6452 CLI.Outs.push_back(MyFlags); 6453 CLI.OutVals.push_back(Parts[j]); 6454 } 6455 } 6456 } 6457 6458 // Handle the incoming return values from the call. 6459 CLI.Ins.clear(); 6460 SmallVector<EVT, 4> RetTys; 6461 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6462 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6463 EVT VT = RetTys[I]; 6464 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6465 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6466 for (unsigned i = 0; i != NumRegs; ++i) { 6467 ISD::InputArg MyFlags; 6468 MyFlags.VT = RegisterVT; 6469 MyFlags.Used = CLI.IsReturnValueUsed; 6470 if (CLI.RetSExt) 6471 MyFlags.Flags.setSExt(); 6472 if (CLI.RetZExt) 6473 MyFlags.Flags.setZExt(); 6474 if (CLI.IsInReg) 6475 MyFlags.Flags.setInReg(); 6476 CLI.Ins.push_back(MyFlags); 6477 } 6478 } 6479 6480 SmallVector<SDValue, 4> InVals; 6481 CLI.Chain = LowerCall(CLI, InVals); 6482 6483 // Verify that the target's LowerCall behaved as expected. 6484 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6485 "LowerCall didn't return a valid chain!"); 6486 assert((!CLI.IsTailCall || InVals.empty()) && 6487 "LowerCall emitted a return value for a tail call!"); 6488 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6489 "LowerCall didn't emit the correct number of values!"); 6490 6491 // For a tail call, the return value is merely live-out and there aren't 6492 // any nodes in the DAG representing it. Return a special value to 6493 // indicate that a tail call has been emitted and no more Instructions 6494 // should be processed in the current block. 6495 if (CLI.IsTailCall) { 6496 CLI.DAG.setRoot(CLI.Chain); 6497 return std::make_pair(SDValue(), SDValue()); 6498 } 6499 6500 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6501 assert(InVals[i].getNode() && 6502 "LowerCall emitted a null value!"); 6503 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6504 "LowerCall emitted a value with the wrong type!"); 6505 }); 6506 6507 // Collect the legal value parts into potentially illegal values 6508 // that correspond to the original function's return values. 6509 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6510 if (CLI.RetSExt) 6511 AssertOp = ISD::AssertSext; 6512 else if (CLI.RetZExt) 6513 AssertOp = ISD::AssertZext; 6514 SmallVector<SDValue, 4> ReturnValues; 6515 unsigned CurReg = 0; 6516 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6517 EVT VT = RetTys[I]; 6518 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6519 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6520 6521 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6522 NumRegs, RegisterVT, VT, NULL, 6523 AssertOp)); 6524 CurReg += NumRegs; 6525 } 6526 6527 // For a function returning void, there is no return value. We can't create 6528 // such a node, so we just return a null return value in that case. In 6529 // that case, nothing will actually look at the value. 6530 if (ReturnValues.empty()) 6531 return std::make_pair(SDValue(), CLI.Chain); 6532 6533 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6534 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6535 &ReturnValues[0], ReturnValues.size()); 6536 return std::make_pair(Res, CLI.Chain); 6537} 6538 6539void TargetLowering::LowerOperationWrapper(SDNode *N, 6540 SmallVectorImpl<SDValue> &Results, 6541 SelectionDAG &DAG) const { 6542 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6543 if (Res.getNode()) 6544 Results.push_back(Res); 6545} 6546 6547SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6548 llvm_unreachable("LowerOperation not implemented for this target!"); 6549} 6550 6551void 6552SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6553 SDValue Op = getNonRegisterValue(V); 6554 assert((Op.getOpcode() != ISD::CopyFromReg || 6555 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6556 "Copy from a reg to the same reg!"); 6557 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6558 6559 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6560 SDValue Chain = DAG.getEntryNode(); 6561 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V); 6562 PendingExports.push_back(Chain); 6563} 6564 6565#include "llvm/CodeGen/SelectionDAGISel.h" 6566 6567/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6568/// entry block, return true. This includes arguments used by switches, since 6569/// the switch may expand into multiple basic blocks. 6570static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6571 // With FastISel active, we may be splitting blocks, so force creation 6572 // of virtual registers for all non-dead arguments. 6573 if (FastISel) 6574 return A->use_empty(); 6575 6576 const BasicBlock *Entry = A->getParent()->begin(); 6577 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6578 UI != E; ++UI) { 6579 const User *U = *UI; 6580 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6581 return false; // Use not in entry block. 6582 } 6583 return true; 6584} 6585 6586void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6587 // If this is the entry block, emit arguments. 6588 const Function &F = *LLVMBB->getParent(); 6589 SelectionDAG &DAG = SDB->DAG; 6590 DebugLoc dl = SDB->getCurDebugLoc(); 6591 const DataLayout *TD = TLI.getDataLayout(); 6592 SmallVector<ISD::InputArg, 16> Ins; 6593 6594 // Check whether the function can return without sret-demotion. 6595 SmallVector<ISD::OutputArg, 4> Outs; 6596 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 6597 6598 if (!FuncInfo->CanLowerReturn) { 6599 // Put in an sret pointer parameter before all the other parameters. 6600 SmallVector<EVT, 1> ValueVTs; 6601 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6602 6603 // NOTE: Assuming that a pointer will never break down to more than one VT 6604 // or one register. 6605 ISD::ArgFlagsTy Flags; 6606 Flags.setSRet(); 6607 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6608 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); 6609 Ins.push_back(RetArg); 6610 } 6611 6612 // Set up the incoming argument description vector. 6613 unsigned Idx = 1; 6614 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6615 I != E; ++I, ++Idx) { 6616 SmallVector<EVT, 4> ValueVTs; 6617 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6618 bool isArgValueUsed = !I->use_empty(); 6619 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6620 Value != NumValues; ++Value) { 6621 EVT VT = ValueVTs[Value]; 6622 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6623 ISD::ArgFlagsTy Flags; 6624 unsigned OriginalAlignment = 6625 TD->getABITypeAlignment(ArgTy); 6626 6627 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6628 Flags.setZExt(); 6629 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6630 Flags.setSExt(); 6631 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) 6632 Flags.setInReg(); 6633 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet)) 6634 Flags.setSRet(); 6635 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) { 6636 Flags.setByVal(); 6637 PointerType *Ty = cast<PointerType>(I->getType()); 6638 Type *ElementTy = Ty->getElementType(); 6639 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6640 // For ByVal, alignment should be passed from FE. BE will guess if 6641 // this info is not there but there are cases it cannot get right. 6642 unsigned FrameAlign; 6643 if (F.getParamAlignment(Idx)) 6644 FrameAlign = F.getParamAlignment(Idx); 6645 else 6646 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6647 Flags.setByValAlign(FrameAlign); 6648 } 6649 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) 6650 Flags.setNest(); 6651 Flags.setOrigAlign(OriginalAlignment); 6652 6653 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6654 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6655 for (unsigned i = 0; i != NumRegs; ++i) { 6656 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, 6657 Idx-1, i*RegisterVT.getStoreSize()); 6658 if (NumRegs > 1 && i == 0) 6659 MyFlags.Flags.setSplit(); 6660 // if it isn't first piece, alignment must be 1 6661 else if (i > 0) 6662 MyFlags.Flags.setOrigAlign(1); 6663 Ins.push_back(MyFlags); 6664 } 6665 } 6666 } 6667 6668 // Call the target to set up the argument values. 6669 SmallVector<SDValue, 8> InVals; 6670 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6671 F.isVarArg(), Ins, 6672 dl, DAG, InVals); 6673 6674 // Verify that the target's LowerFormalArguments behaved as expected. 6675 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6676 "LowerFormalArguments didn't return a valid chain!"); 6677 assert(InVals.size() == Ins.size() && 6678 "LowerFormalArguments didn't emit the correct number of values!"); 6679 DEBUG({ 6680 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6681 assert(InVals[i].getNode() && 6682 "LowerFormalArguments emitted a null value!"); 6683 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6684 "LowerFormalArguments emitted a value with the wrong type!"); 6685 } 6686 }); 6687 6688 // Update the DAG with the new chain value resulting from argument lowering. 6689 DAG.setRoot(NewRoot); 6690 6691 // Set up the argument values. 6692 unsigned i = 0; 6693 Idx = 1; 6694 if (!FuncInfo->CanLowerReturn) { 6695 // Create a virtual register for the sret pointer, and put in a copy 6696 // from the sret argument into it. 6697 SmallVector<EVT, 1> ValueVTs; 6698 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6699 MVT VT = ValueVTs[0].getSimpleVT(); 6700 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6701 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6702 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6703 RegVT, VT, NULL, AssertOp); 6704 6705 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6706 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6707 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6708 FuncInfo->DemoteRegister = SRetReg; 6709 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6710 SRetReg, ArgValue); 6711 DAG.setRoot(NewRoot); 6712 6713 // i indexes lowered arguments. Bump it past the hidden sret argument. 6714 // Idx indexes LLVM arguments. Don't touch it. 6715 ++i; 6716 } 6717 6718 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6719 ++I, ++Idx) { 6720 SmallVector<SDValue, 4> ArgValues; 6721 SmallVector<EVT, 4> ValueVTs; 6722 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6723 unsigned NumValues = ValueVTs.size(); 6724 6725 // If this argument is unused then remember its value. It is used to generate 6726 // debugging information. 6727 if (I->use_empty() && NumValues) 6728 SDB->setUnusedArgValue(I, InVals[i]); 6729 6730 for (unsigned Val = 0; Val != NumValues; ++Val) { 6731 EVT VT = ValueVTs[Val]; 6732 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6733 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6734 6735 if (!I->use_empty()) { 6736 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6737 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6738 AssertOp = ISD::AssertSext; 6739 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6740 AssertOp = ISD::AssertZext; 6741 6742 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6743 NumParts, PartVT, VT, 6744 NULL, AssertOp)); 6745 } 6746 6747 i += NumParts; 6748 } 6749 6750 // We don't need to do anything else for unused arguments. 6751 if (ArgValues.empty()) 6752 continue; 6753 6754 // Note down frame index. 6755 if (FrameIndexSDNode *FI = 6756 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6757 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6758 6759 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6760 SDB->getCurDebugLoc()); 6761 6762 SDB->setValue(I, Res); 6763 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6764 if (LoadSDNode *LNode = 6765 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6766 if (FrameIndexSDNode *FI = 6767 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6768 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6769 } 6770 6771 // If this argument is live outside of the entry block, insert a copy from 6772 // wherever we got it to the vreg that other BB's will reference it as. 6773 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6774 // If we can, though, try to skip creating an unnecessary vreg. 6775 // FIXME: This isn't very clean... it would be nice to make this more 6776 // general. It's also subtly incompatible with the hacks FastISel 6777 // uses with vregs. 6778 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6779 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6780 FuncInfo->ValueMap[I] = Reg; 6781 continue; 6782 } 6783 } 6784 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6785 FuncInfo->InitializeRegForValue(I); 6786 SDB->CopyToExportRegsIfNeeded(I); 6787 } 6788 } 6789 6790 assert(i == InVals.size() && "Argument register count mismatch!"); 6791 6792 // Finally, if the target has anything special to do, allow it to do so. 6793 // FIXME: this should insert code into the DAG! 6794 EmitFunctionEntryCode(); 6795} 6796 6797/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6798/// ensure constants are generated when needed. Remember the virtual registers 6799/// that need to be added to the Machine PHI nodes as input. We cannot just 6800/// directly add them, because expansion might result in multiple MBB's for one 6801/// BB. As such, the start of the BB might correspond to a different MBB than 6802/// the end. 6803/// 6804void 6805SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6806 const TerminatorInst *TI = LLVMBB->getTerminator(); 6807 6808 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6809 6810 // Check successor nodes' PHI nodes that expect a constant to be available 6811 // from this block. 6812 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6813 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6814 if (!isa<PHINode>(SuccBB->begin())) continue; 6815 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6816 6817 // If this terminator has multiple identical successors (common for 6818 // switches), only handle each succ once. 6819 if (!SuccsHandled.insert(SuccMBB)) continue; 6820 6821 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6822 6823 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6824 // nodes and Machine PHI nodes, but the incoming operands have not been 6825 // emitted yet. 6826 for (BasicBlock::const_iterator I = SuccBB->begin(); 6827 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6828 // Ignore dead phi's. 6829 if (PN->use_empty()) continue; 6830 6831 // Skip empty types 6832 if (PN->getType()->isEmptyTy()) 6833 continue; 6834 6835 unsigned Reg; 6836 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6837 6838 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6839 unsigned &RegOut = ConstantsOut[C]; 6840 if (RegOut == 0) { 6841 RegOut = FuncInfo.CreateRegs(C->getType()); 6842 CopyValueToVirtualRegister(C, RegOut); 6843 } 6844 Reg = RegOut; 6845 } else { 6846 DenseMap<const Value *, unsigned>::iterator I = 6847 FuncInfo.ValueMap.find(PHIOp); 6848 if (I != FuncInfo.ValueMap.end()) 6849 Reg = I->second; 6850 else { 6851 assert(isa<AllocaInst>(PHIOp) && 6852 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6853 "Didn't codegen value into a register!??"); 6854 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6855 CopyValueToVirtualRegister(PHIOp, Reg); 6856 } 6857 } 6858 6859 // Remember that this register needs to added to the machine PHI node as 6860 // the input for this MBB. 6861 SmallVector<EVT, 4> ValueVTs; 6862 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6863 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6864 EVT VT = ValueVTs[vti]; 6865 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6866 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6867 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6868 Reg += NumRegisters; 6869 } 6870 } 6871 } 6872 ConstantsOut.clear(); 6873} 6874