SelectionDAGBuilder.cpp revision 0bcbd1df7a204e1e512f1a27066d725309de1b13
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DebugInfo.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Function.h" 27#include "llvm/GlobalVariable.h" 28#include "llvm/InlineAsm.h" 29#include "llvm/Instructions.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/IntrinsicInst.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Module.h" 34#include "llvm/CodeGen/Analysis.h" 35#include "llvm/CodeGen/FastISel.h" 36#include "llvm/CodeGen/FunctionLoweringInfo.h" 37#include "llvm/CodeGen/GCStrategy.h" 38#include "llvm/CodeGen/GCMetadata.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineFrameInfo.h" 41#include "llvm/CodeGen/MachineInstrBuilder.h" 42#include "llvm/CodeGen/MachineJumpTableInfo.h" 43#include "llvm/CodeGen/MachineModuleInfo.h" 44#include "llvm/CodeGen/MachineRegisterInfo.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/IntegersSubsetMapping.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static const unsigned MaxParallelChains = 64; 88 89static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 90 const SDValue *Parts, unsigned NumParts, 91 EVT PartVT, EVT ValueVT); 92 93/// getCopyFromParts - Create a value that contains the specified legal parts 94/// combined into the value they represent. If the parts combine to a type 95/// larger then ValueVT then AssertOp can be used to specify whether the extra 96/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 97/// (ISD::AssertSext). 98static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 99 const SDValue *Parts, 100 unsigned NumParts, EVT PartVT, EVT ValueVT, 101 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 102 if (ValueVT.isVector()) 103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 104 105 assert(NumParts > 0 && "No parts to assemble!"); 106 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 107 SDValue Val = Parts[0]; 108 109 if (NumParts > 1) { 110 // Assemble the value from multiple parts. 111 if (ValueVT.isInteger()) { 112 unsigned PartBits = PartVT.getSizeInBits(); 113 unsigned ValueBits = ValueVT.getSizeInBits(); 114 115 // Assemble the power of 2 part. 116 unsigned RoundParts = NumParts & (NumParts - 1) ? 117 1 << Log2_32(NumParts) : NumParts; 118 unsigned RoundBits = PartBits * RoundParts; 119 EVT RoundVT = RoundBits == ValueBits ? 120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 121 SDValue Lo, Hi; 122 123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 124 125 if (RoundParts > 2) { 126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 127 PartVT, HalfVT); 128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 129 RoundParts / 2, PartVT, HalfVT); 130 } else { 131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 133 } 134 135 if (TLI.isBigEndian()) 136 std::swap(Lo, Hi); 137 138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 139 140 if (RoundParts < NumParts) { 141 // Assemble the trailing non-power-of-2 part. 142 unsigned OddParts = NumParts - RoundParts; 143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 144 Hi = getCopyFromParts(DAG, DL, 145 Parts + RoundParts, OddParts, PartVT, OddVT); 146 147 // Combine the round and odd parts. 148 Lo = Val; 149 if (TLI.isBigEndian()) 150 std::swap(Lo, Hi); 151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 154 DAG.getConstant(Lo.getValueType().getSizeInBits(), 155 TLI.getPointerTy())); 156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 158 } 159 } else if (PartVT.isFloatingPoint()) { 160 // FP split into multiple FP parts (for ppcf128) 161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 162 "Unexpected split"); 163 SDValue Lo, Hi; 164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 166 if (TLI.isBigEndian()) 167 std::swap(Lo, Hi); 168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 169 } else { 170 // FP split into integer parts (soft fp) 171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 172 !PartVT.isVector() && "Unexpected split"); 173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 175 } 176 } 177 178 // There is now one part, held in Val. Correct it to match ValueVT. 179 PartVT = Val.getValueType(); 180 181 if (PartVT == ValueVT) 182 return Val; 183 184 if (PartVT.isInteger() && ValueVT.isInteger()) { 185 if (ValueVT.bitsLT(PartVT)) { 186 // For a truncate, see if we have any information to 187 // indicate whether the truncated bits will always be 188 // zero or sign-extension. 189 if (AssertOp != ISD::DELETED_NODE) 190 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 191 DAG.getValueType(ValueVT)); 192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 193 } 194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 195 } 196 197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 198 // FP_ROUND's are always exact here. 199 if (ValueVT.bitsLT(Val.getValueType())) 200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 201 DAG.getTargetConstant(1, TLI.getPointerTy())); 202 203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 204 } 205 206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 208 209 llvm_unreachable("Unknown mismatch!"); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 357 ValueVT.isInteger() && 358 "Unknown mismatch!"); 359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 361 if (PartVT == MVT::x86mmx) 362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 363 } 364 } else if (PartBits == ValueVT.getSizeInBits()) { 365 // Different types of the same size. 366 assert(NumParts == 1 && PartVT != ValueVT); 367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 369 // If the parts cover less bits than value has, truncate the value. 370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 371 ValueVT.isInteger() && 372 "Unknown mismatch!"); 373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 375 if (PartVT == MVT::x86mmx) 376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 377 } 378 379 // The value may have changed - recompute ValueVT. 380 ValueVT = Val.getValueType(); 381 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 382 "Failed to tile the value with PartVT!"); 383 384 if (NumParts == 1) { 385 assert(PartVT == ValueVT && "Type conversion failed!"); 386 Parts[0] = Val; 387 return; 388 } 389 390 // Expand the value into multiple parts. 391 if (NumParts & (NumParts - 1)) { 392 // The number of parts is not a power of 2. Split off and copy the tail. 393 assert(PartVT.isInteger() && ValueVT.isInteger() && 394 "Do not know what to expand to!"); 395 unsigned RoundParts = 1 << Log2_32(NumParts); 396 unsigned RoundBits = RoundParts * PartBits; 397 unsigned OddParts = NumParts - RoundParts; 398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 399 DAG.getIntPtrConstant(RoundBits)); 400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 401 402 if (TLI.isBigEndian()) 403 // The odd parts were reversed by getCopyToParts - unreverse them. 404 std::reverse(Parts + RoundParts, Parts + NumParts); 405 406 NumParts = RoundParts; 407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 409 } 410 411 // The number of parts is a power of 2. Repeatedly bisect the value using 412 // EXTRACT_ELEMENT. 413 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 414 EVT::getIntegerVT(*DAG.getContext(), 415 ValueVT.getSizeInBits()), 416 Val); 417 418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 419 for (unsigned i = 0; i < NumParts; i += StepSize) { 420 unsigned ThisBits = StepSize * PartBits / 2; 421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 422 SDValue &Part0 = Parts[i]; 423 SDValue &Part1 = Parts[i+StepSize/2]; 424 425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 426 ThisVT, Part0, DAG.getIntPtrConstant(1)); 427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 428 ThisVT, Part0, DAG.getIntPtrConstant(0)); 429 430 if (ThisBits == PartBits && ThisVT != PartVT) { 431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 433 } 434 } 435 } 436 437 if (TLI.isBigEndian()) 438 std::reverse(Parts, Parts + OrigNumParts); 439} 440 441 442/// getCopyToPartsVector - Create a series of nodes that contain the specified 443/// value split into legal parts. 444static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 445 SDValue Val, SDValue *Parts, unsigned NumParts, 446 EVT PartVT) { 447 EVT ValueVT = Val.getValueType(); 448 assert(ValueVT.isVector() && "Not a vector"); 449 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 450 451 if (NumParts == 1) { 452 if (PartVT == ValueVT) { 453 // Nothing to do. 454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 455 // Bitconvert vector->vector case. 456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 457 } else if (PartVT.isVector() && 458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 460 EVT ElementVT = PartVT.getVectorElementType(); 461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 462 // undef elements. 463 SmallVector<SDValue, 16> Ops; 464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 466 ElementVT, Val, DAG.getIntPtrConstant(i))); 467 468 for (unsigned i = ValueVT.getVectorNumElements(), 469 e = PartVT.getVectorNumElements(); i != e; ++i) 470 Ops.push_back(DAG.getUNDEF(ElementVT)); 471 472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 473 474 // FIXME: Use CONCAT for 2x -> 4x. 475 476 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 478 } else if (PartVT.isVector() && 479 PartVT.getVectorElementType().bitsGE( 480 ValueVT.getVectorElementType()) && 481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 482 483 // Promoted vector extract 484 bool Smaller = PartVT.bitsLE(ValueVT); 485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 486 DL, PartVT, Val); 487 } else{ 488 // Vector -> scalar conversion. 489 assert(ValueVT.getVectorNumElements() == 1 && 490 "Only trivial vector-to-scalar conversions should get here!"); 491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 PartVT, Val, DAG.getIntPtrConstant(0)); 493 494 bool Smaller = ValueVT.bitsLE(PartVT); 495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 496 DL, PartVT, Val); 497 } 498 499 Parts[0] = Val; 500 return; 501 } 502 503 // Handle a multi-element vector. 504 EVT IntermediateVT, RegisterVT; 505 unsigned NumIntermediates; 506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 507 IntermediateVT, 508 NumIntermediates, RegisterVT); 509 unsigned NumElements = ValueVT.getVectorNumElements(); 510 511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 512 NumParts = NumRegs; // Silence a compiler warning. 513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 514 515 // Split the vector into intermediate operands. 516 SmallVector<SDValue, 8> Ops(NumIntermediates); 517 for (unsigned i = 0; i != NumIntermediates; ++i) { 518 if (IntermediateVT.isVector()) 519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 520 IntermediateVT, Val, 521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 522 else 523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 524 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 525 } 526 527 // Split the intermediate operands into legal parts. 528 if (NumParts == NumIntermediates) { 529 // If the register was not expanded, promote or copy the value, 530 // as appropriate. 531 for (unsigned i = 0; i != NumParts; ++i) 532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 533 } else if (NumParts > 0) { 534 // If the intermediate type was expanded, split each the value into 535 // legal parts. 536 assert(NumParts % NumIntermediates == 0 && 537 "Must expand into a divisible number of parts!"); 538 unsigned Factor = NumParts / NumIntermediates; 539 for (unsigned i = 0; i != NumIntermediates; ++i) 540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 541 } 542} 543 544 545 546 547namespace { 548 /// RegsForValue - This struct represents the registers (physical or virtual) 549 /// that a particular set of values is assigned, and the type information 550 /// about the value. The most common situation is to represent one value at a 551 /// time, but struct or array values are handled element-wise as multiple 552 /// values. The splitting of aggregates is performed recursively, so that we 553 /// never have aggregate-typed registers. The values at this point do not 554 /// necessarily have legal types, so each value may require one or more 555 /// registers of some legal type. 556 /// 557 struct RegsForValue { 558 /// ValueVTs - The value types of the values, which may not be legal, and 559 /// may need be promoted or synthesized from one or more registers. 560 /// 561 SmallVector<EVT, 4> ValueVTs; 562 563 /// RegVTs - The value types of the registers. This is the same size as 564 /// ValueVTs and it records, for each value, what the type of the assigned 565 /// register or registers are. (Individual values are never synthesized 566 /// from more than one type of register.) 567 /// 568 /// With virtual registers, the contents of RegVTs is redundant with TLI's 569 /// getRegisterType member function, however when with physical registers 570 /// it is necessary to have a separate record of the types. 571 /// 572 SmallVector<EVT, 4> RegVTs; 573 574 /// Regs - This list holds the registers assigned to the values. 575 /// Each legal or promoted value requires one register, and each 576 /// expanded value requires multiple registers. 577 /// 578 SmallVector<unsigned, 4> Regs; 579 580 RegsForValue() {} 581 582 RegsForValue(const SmallVector<unsigned, 4> ®s, 583 EVT regvt, EVT valuevt) 584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 585 586 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 587 unsigned Reg, Type *Ty) { 588 ComputeValueVTs(tli, Ty, ValueVTs); 589 590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 591 EVT ValueVT = ValueVTs[Value]; 592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 594 for (unsigned i = 0; i != NumRegs; ++i) 595 Regs.push_back(Reg + i); 596 RegVTs.push_back(RegisterVT); 597 Reg += NumRegs; 598 } 599 } 600 601 /// areValueTypesLegal - Return true if types of all the values are legal. 602 bool areValueTypesLegal(const TargetLowering &TLI) { 603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 604 EVT RegisterVT = RegVTs[Value]; 605 if (!TLI.isTypeLegal(RegisterVT)) 606 return false; 607 } 608 return true; 609 } 610 611 /// append - Add the specified values to this one. 612 void append(const RegsForValue &RHS) { 613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 615 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 616 } 617 618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 619 /// this value and returns the result as a ValueVTs value. This uses 620 /// Chain/Flag as the input and updates them for the output Chain/Flag. 621 /// If the Flag pointer is NULL, no flag is used. 622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 623 DebugLoc dl, 624 SDValue &Chain, SDValue *Flag) const; 625 626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 627 /// specified value into the registers specified by this object. This uses 628 /// Chain/Flag as the input and updates them for the output Chain/Flag. 629 /// If the Flag pointer is NULL, no flag is used. 630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 631 SDValue &Chain, SDValue *Flag) const; 632 633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 634 /// operand list. This adds the code marker, matching input operand index 635 /// (if applicable), and includes the number of values added into it. 636 void AddInlineAsmOperands(unsigned Kind, 637 bool HasMatching, unsigned MatchingIdx, 638 SelectionDAG &DAG, 639 std::vector<SDValue> &Ops) const; 640 }; 641} 642 643/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 644/// this value and returns the result as a ValueVT value. This uses 645/// Chain/Flag as the input and updates them for the output Chain/Flag. 646/// If the Flag pointer is NULL, no flag is used. 647SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 648 FunctionLoweringInfo &FuncInfo, 649 DebugLoc dl, 650 SDValue &Chain, SDValue *Flag) const { 651 // A Value with type {} or [0 x %t] needs no registers. 652 if (ValueVTs.empty()) 653 return SDValue(); 654 655 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 656 657 // Assemble the legal parts into the final values. 658 SmallVector<SDValue, 4> Values(ValueVTs.size()); 659 SmallVector<SDValue, 8> Parts; 660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 661 // Copy the legal parts from the registers. 662 EVT ValueVT = ValueVTs[Value]; 663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 664 EVT RegisterVT = RegVTs[Value]; 665 666 Parts.resize(NumRegs); 667 for (unsigned i = 0; i != NumRegs; ++i) { 668 SDValue P; 669 if (Flag == 0) { 670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 671 } else { 672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 673 *Flag = P.getValue(2); 674 } 675 676 Chain = P.getValue(1); 677 Parts[i] = P; 678 679 // If the source register was virtual and if we know something about it, 680 // add an assert node. 681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 682 !RegisterVT.isInteger() || RegisterVT.isVector()) 683 continue; 684 685 const FunctionLoweringInfo::LiveOutInfo *LOI = 686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 687 if (!LOI) 688 continue; 689 690 unsigned RegSize = RegisterVT.getSizeInBits(); 691 unsigned NumSignBits = LOI->NumSignBits; 692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 693 694 // FIXME: We capture more information than the dag can represent. For 695 // now, just use the tightest assertzext/assertsext possible. 696 bool isSExt = true; 697 EVT FromVT(MVT::Other); 698 if (NumSignBits == RegSize) 699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 700 else if (NumZeroBits >= RegSize-1) 701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 702 else if (NumSignBits > RegSize-8) 703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 704 else if (NumZeroBits >= RegSize-8) 705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 706 else if (NumSignBits > RegSize-16) 707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 708 else if (NumZeroBits >= RegSize-16) 709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 710 else if (NumSignBits > RegSize-32) 711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 712 else if (NumZeroBits >= RegSize-32) 713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 714 else 715 continue; 716 717 // Add an assertion node. 718 assert(FromVT != MVT::Other); 719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 720 RegisterVT, P, DAG.getValueType(FromVT)); 721 } 722 723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 724 NumRegs, RegisterVT, ValueVT); 725 Part += NumRegs; 726 Parts.clear(); 727 } 728 729 return DAG.getNode(ISD::MERGE_VALUES, dl, 730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 731 &Values[0], ValueVTs.size()); 732} 733 734/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 735/// specified value into the registers specified by this object. This uses 736/// Chain/Flag as the input and updates them for the output Chain/Flag. 737/// If the Flag pointer is NULL, no flag is used. 738void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 739 SDValue &Chain, SDValue *Flag) const { 740 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 741 742 // Get the list of the values's legal parts. 743 unsigned NumRegs = Regs.size(); 744 SmallVector<SDValue, 8> Parts(NumRegs); 745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 746 EVT ValueVT = ValueVTs[Value]; 747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 748 EVT RegisterVT = RegVTs[Value]; 749 750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 751 &Parts[Part], NumParts, RegisterVT); 752 Part += NumParts; 753 } 754 755 // Copy the parts into the registers. 756 SmallVector<SDValue, 8> Chains(NumRegs); 757 for (unsigned i = 0; i != NumRegs; ++i) { 758 SDValue Part; 759 if (Flag == 0) { 760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 761 } else { 762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 763 *Flag = Part.getValue(1); 764 } 765 766 Chains[i] = Part.getValue(0); 767 } 768 769 if (NumRegs == 1 || Flag) 770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 771 // flagged to it. That is the CopyToReg nodes and the user are considered 772 // a single scheduling unit. If we create a TokenFactor and return it as 773 // chain, then the TokenFactor is both a predecessor (operand) of the 774 // user as well as a successor (the TF operands are flagged to the user). 775 // c1, f1 = CopyToReg 776 // c2, f2 = CopyToReg 777 // c3 = TokenFactor c1, c2 778 // ... 779 // = op c3, ..., f2 780 Chain = Chains[NumRegs-1]; 781 else 782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 783} 784 785/// AddInlineAsmOperands - Add this value to the specified inlineasm node 786/// operand list. This adds the code marker and includes the number of 787/// values added into it. 788void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 789 unsigned MatchingIdx, 790 SelectionDAG &DAG, 791 std::vector<SDValue> &Ops) const { 792 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 793 794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 795 if (HasMatching) 796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 797 else if (!Regs.empty() && 798 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 799 // Put the register class of the virtual registers in the flag word. That 800 // way, later passes can recompute register class constraints for inline 801 // assembly as well as normal instructions. 802 // Don't do this for tied operands that can use the regclass information 803 // from the def. 804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 807 } 808 809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 810 Ops.push_back(Res); 811 812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 814 EVT RegisterVT = RegVTs[Value]; 815 for (unsigned i = 0; i != NumRegs; ++i) { 816 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 818 } 819 } 820} 821 822void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 823 const TargetLibraryInfo *li) { 824 AA = &aa; 825 GFI = gfi; 826 LibInfo = li; 827 TD = DAG.getTarget().getTargetData(); 828 LPadToCallSiteMap.clear(); 829} 830 831/// clear - Clear out the current SelectionDAG and the associated 832/// state and prepare this SelectionDAGBuilder object to be used 833/// for a new block. This doesn't clear out information about 834/// additional blocks that are needed to complete switch lowering 835/// or PHI node updating; that information is cleared out as it is 836/// consumed. 837void SelectionDAGBuilder::clear() { 838 NodeMap.clear(); 839 UnusedArgNodeMap.clear(); 840 PendingLoads.clear(); 841 PendingExports.clear(); 842 CurDebugLoc = DebugLoc(); 843 HasTailCall = false; 844} 845 846/// clearDanglingDebugInfo - Clear the dangling debug information 847/// map. This function is separated from the clear so that debug 848/// information that is dangling in a basic block can be properly 849/// resolved in a different basic block. This allows the 850/// SelectionDAG to resolve dangling debug information attached 851/// to PHI nodes. 852void SelectionDAGBuilder::clearDanglingDebugInfo() { 853 DanglingDebugInfoMap.clear(); 854} 855 856/// getRoot - Return the current virtual root of the Selection DAG, 857/// flushing any PendingLoad items. This must be done before emitting 858/// a store or any other node that may need to be ordered after any 859/// prior load instructions. 860/// 861SDValue SelectionDAGBuilder::getRoot() { 862 if (PendingLoads.empty()) 863 return DAG.getRoot(); 864 865 if (PendingLoads.size() == 1) { 866 SDValue Root = PendingLoads[0]; 867 DAG.setRoot(Root); 868 PendingLoads.clear(); 869 return Root; 870 } 871 872 // Otherwise, we have to make a token factor node. 873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 874 &PendingLoads[0], PendingLoads.size()); 875 PendingLoads.clear(); 876 DAG.setRoot(Root); 877 return Root; 878} 879 880/// getControlRoot - Similar to getRoot, but instead of flushing all the 881/// PendingLoad items, flush all the PendingExports items. It is necessary 882/// to do this before emitting a terminator instruction. 883/// 884SDValue SelectionDAGBuilder::getControlRoot() { 885 SDValue Root = DAG.getRoot(); 886 887 if (PendingExports.empty()) 888 return Root; 889 890 // Turn all of the CopyToReg chains into one factored node. 891 if (Root.getOpcode() != ISD::EntryToken) { 892 unsigned i = 0, e = PendingExports.size(); 893 for (; i != e; ++i) { 894 assert(PendingExports[i].getNode()->getNumOperands() > 1); 895 if (PendingExports[i].getNode()->getOperand(0) == Root) 896 break; // Don't add the root if we already indirectly depend on it. 897 } 898 899 if (i == e) 900 PendingExports.push_back(Root); 901 } 902 903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingExports[0], 905 PendingExports.size()); 906 PendingExports.clear(); 907 DAG.setRoot(Root); 908 return Root; 909} 910 911void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 913 DAG.AssignOrdering(Node, SDNodeOrder); 914 915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 916 AssignOrderingToNode(Node->getOperand(I).getNode()); 917} 918 919void SelectionDAGBuilder::visit(const Instruction &I) { 920 // Set up outgoing PHI node register values before emitting the terminator. 921 if (isa<TerminatorInst>(&I)) 922 HandlePHINodesInSuccessorBlocks(I.getParent()); 923 924 CurDebugLoc = I.getDebugLoc(); 925 926 visit(I.getOpcode(), I); 927 928 if (!isa<TerminatorInst>(&I) && !HasTailCall) 929 CopyToExportRegsIfNeeded(&I); 930 931 CurDebugLoc = DebugLoc(); 932} 933 934void SelectionDAGBuilder::visitPHI(const PHINode &) { 935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 936} 937 938void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 939 // Note: this doesn't use InstVisitor, because it has to work with 940 // ConstantExpr's in addition to instructions. 941 switch (Opcode) { 942 default: llvm_unreachable("Unknown instruction type encountered!"); 943 // Build the switch statement using the Instruction.def file. 944#define HANDLE_INST(NUM, OPCODE, CLASS) \ 945 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 946#include "llvm/Instruction.def" 947 } 948 949 // Assign the ordering to the freshly created DAG nodes. 950 if (NodeMap.count(&I)) { 951 ++SDNodeOrder; 952 AssignOrderingToNode(getValue(&I).getNode()); 953 } 954} 955 956// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 957// generate the debug data structures now that we've seen its definition. 958void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 959 SDValue Val) { 960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 961 if (DDI.getDI()) { 962 const DbgValueInst *DI = DDI.getDI(); 963 DebugLoc dl = DDI.getdl(); 964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 965 MDNode *Variable = DI->getVariable(); 966 uint64_t Offset = DI->getOffset(); 967 SDDbgValue *SDV; 968 if (Val.getNode()) { 969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 970 SDV = DAG.getDbgValue(Variable, Val.getNode(), 971 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 972 DAG.AddDbgValue(SDV, Val.getNode(), false); 973 } 974 } else 975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 976 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 977 } 978} 979 980/// getValue - Return an SDValue for the given Value. 981SDValue SelectionDAGBuilder::getValue(const Value *V) { 982 // If we already have an SDValue for this value, use it. It's important 983 // to do this first, so that we don't create a CopyFromReg if we already 984 // have a regular SDValue. 985 SDValue &N = NodeMap[V]; 986 if (N.getNode()) return N; 987 988 // If there's a virtual register allocated and initialized for this 989 // value, use it. 990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 991 if (It != FuncInfo.ValueMap.end()) { 992 unsigned InReg = It->second; 993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 994 SDValue Chain = DAG.getEntryNode(); 995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 996 resolveDanglingDebugInfo(V, N); 997 return N; 998 } 999 1000 // Otherwise create a new SDValue and remember it. 1001 SDValue Val = getValueImpl(V); 1002 NodeMap[V] = Val; 1003 resolveDanglingDebugInfo(V, Val); 1004 return Val; 1005} 1006 1007/// getNonRegisterValue - Return an SDValue for the given Value, but 1008/// don't look in FuncInfo.ValueMap for a virtual register. 1009SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1010 // If we already have an SDValue for this value, use it. 1011 SDValue &N = NodeMap[V]; 1012 if (N.getNode()) return N; 1013 1014 // Otherwise create a new SDValue and remember it. 1015 SDValue Val = getValueImpl(V); 1016 NodeMap[V] = Val; 1017 resolveDanglingDebugInfo(V, Val); 1018 return Val; 1019} 1020 1021/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1022/// Create an SDValue for the given value. 1023SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1024 if (const Constant *C = dyn_cast<Constant>(V)) { 1025 EVT VT = TLI.getValueType(V->getType(), true); 1026 1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1028 return DAG.getConstant(*CI, VT); 1029 1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1032 1033 if (isa<ConstantPointerNull>(C)) 1034 return DAG.getConstant(0, TLI.getPointerTy()); 1035 1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1037 return DAG.getConstantFP(*CFP, VT); 1038 1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1040 return DAG.getUNDEF(VT); 1041 1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1043 visit(CE->getOpcode(), *CE); 1044 SDValue N1 = NodeMap[V]; 1045 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1046 return N1; 1047 } 1048 1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1050 SmallVector<SDValue, 4> Constants; 1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1052 OI != OE; ++OI) { 1053 SDNode *Val = getValue(*OI).getNode(); 1054 // If the operand is an empty aggregate, there are no values. 1055 if (!Val) continue; 1056 // Add each leaf value from the operand to the Constants list 1057 // to form a flattened list of all the values. 1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1059 Constants.push_back(SDValue(Val, i)); 1060 } 1061 1062 return DAG.getMergeValues(&Constants[0], Constants.size(), 1063 getCurDebugLoc()); 1064 } 1065 1066 if (const ConstantDataSequential *CDS = 1067 dyn_cast<ConstantDataSequential>(C)) { 1068 SmallVector<SDValue, 4> Ops; 1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1071 // Add each leaf value from the operand to the Constants list 1072 // to form a flattened list of all the values. 1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1074 Ops.push_back(SDValue(Val, i)); 1075 } 1076 1077 if (isa<ArrayType>(CDS->getType())) 1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1080 VT, &Ops[0], Ops.size()); 1081 } 1082 1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1085 "Unknown struct or array constant!"); 1086 1087 SmallVector<EVT, 4> ValueVTs; 1088 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1089 unsigned NumElts = ValueVTs.size(); 1090 if (NumElts == 0) 1091 return SDValue(); // empty struct 1092 SmallVector<SDValue, 4> Constants(NumElts); 1093 for (unsigned i = 0; i != NumElts; ++i) { 1094 EVT EltVT = ValueVTs[i]; 1095 if (isa<UndefValue>(C)) 1096 Constants[i] = DAG.getUNDEF(EltVT); 1097 else if (EltVT.isFloatingPoint()) 1098 Constants[i] = DAG.getConstantFP(0, EltVT); 1099 else 1100 Constants[i] = DAG.getConstant(0, EltVT); 1101 } 1102 1103 return DAG.getMergeValues(&Constants[0], NumElts, 1104 getCurDebugLoc()); 1105 } 1106 1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1108 return DAG.getBlockAddress(BA, VT); 1109 1110 VectorType *VecTy = cast<VectorType>(V->getType()); 1111 unsigned NumElements = VecTy->getNumElements(); 1112 1113 // Now that we know the number and type of the elements, get that number of 1114 // elements into the Ops array based on what kind of constant it is. 1115 SmallVector<SDValue, 16> Ops; 1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1117 for (unsigned i = 0; i != NumElements; ++i) 1118 Ops.push_back(getValue(CV->getOperand(i))); 1119 } else { 1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1121 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1122 1123 SDValue Op; 1124 if (EltVT.isFloatingPoint()) 1125 Op = DAG.getConstantFP(0, EltVT); 1126 else 1127 Op = DAG.getConstant(0, EltVT); 1128 Ops.assign(NumElements, Op); 1129 } 1130 1131 // Create a BUILD_VECTOR node. 1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1133 VT, &Ops[0], Ops.size()); 1134 } 1135 1136 // If this is a static alloca, generate it as the frameindex instead of 1137 // computation. 1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1139 DenseMap<const AllocaInst*, int>::iterator SI = 1140 FuncInfo.StaticAllocaMap.find(AI); 1141 if (SI != FuncInfo.StaticAllocaMap.end()) 1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1143 } 1144 1145 // If this is an instruction which fast-isel has deferred, select it now. 1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1149 SDValue Chain = DAG.getEntryNode(); 1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1151 } 1152 1153 llvm_unreachable("Can't get register for value!"); 1154} 1155 1156void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1157 SDValue Chain = getControlRoot(); 1158 SmallVector<ISD::OutputArg, 8> Outs; 1159 SmallVector<SDValue, 8> OutVals; 1160 1161 if (!FuncInfo.CanLowerReturn) { 1162 unsigned DemoteReg = FuncInfo.DemoteRegister; 1163 const Function *F = I.getParent()->getParent(); 1164 1165 // Emit a store of the return value through the virtual register. 1166 // Leave Outs empty so that LowerReturn won't try to load return 1167 // registers the usual way. 1168 SmallVector<EVT, 1> PtrValueVTs; 1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1170 PtrValueVTs); 1171 1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1173 SDValue RetOp = getValue(I.getOperand(0)); 1174 1175 SmallVector<EVT, 4> ValueVTs; 1176 SmallVector<uint64_t, 4> Offsets; 1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1178 unsigned NumValues = ValueVTs.size(); 1179 1180 SmallVector<SDValue, 4> Chains(NumValues); 1181 for (unsigned i = 0; i != NumValues; ++i) { 1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1183 RetPtr.getValueType(), RetPtr, 1184 DAG.getIntPtrConstant(Offsets[i])); 1185 Chains[i] = 1186 DAG.getStore(Chain, getCurDebugLoc(), 1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1188 // FIXME: better loc info would be nice. 1189 Add, MachinePointerInfo(), false, false, 0); 1190 } 1191 1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1193 MVT::Other, &Chains[0], NumValues); 1194 } else if (I.getNumOperands() != 0) { 1195 SmallVector<EVT, 4> ValueVTs; 1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1197 unsigned NumValues = ValueVTs.size(); 1198 if (NumValues) { 1199 SDValue RetOp = getValue(I.getOperand(0)); 1200 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1201 EVT VT = ValueVTs[j]; 1202 1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1204 1205 const Function *F = I.getParent()->getParent(); 1206 if (F->paramHasAttr(0, Attribute::SExt)) 1207 ExtendKind = ISD::SIGN_EXTEND; 1208 else if (F->paramHasAttr(0, Attribute::ZExt)) 1209 ExtendKind = ISD::ZERO_EXTEND; 1210 1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1213 1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1216 SmallVector<SDValue, 4> Parts(NumParts); 1217 getCopyToParts(DAG, getCurDebugLoc(), 1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1219 &Parts[0], NumParts, PartVT, ExtendKind); 1220 1221 // 'inreg' on function refers to return value 1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1223 if (F->paramHasAttr(0, Attribute::InReg)) 1224 Flags.setInReg(); 1225 1226 // Propagate extension type if any 1227 if (ExtendKind == ISD::SIGN_EXTEND) 1228 Flags.setSExt(); 1229 else if (ExtendKind == ISD::ZERO_EXTEND) 1230 Flags.setZExt(); 1231 1232 for (unsigned i = 0; i < NumParts; ++i) { 1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1234 /*isfixed=*/true)); 1235 OutVals.push_back(Parts[i]); 1236 } 1237 } 1238 } 1239 } 1240 1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1242 CallingConv::ID CallConv = 1243 DAG.getMachineFunction().getFunction()->getCallingConv(); 1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1245 Outs, OutVals, getCurDebugLoc(), DAG); 1246 1247 // Verify that the target's LowerReturn behaved as expected. 1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1249 "LowerReturn didn't return a valid chain!"); 1250 1251 // Update the DAG with the new chain value resulting from return lowering. 1252 DAG.setRoot(Chain); 1253} 1254 1255/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1256/// created for it, emit nodes to copy the value into the virtual 1257/// registers. 1258void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1259 // Skip empty types 1260 if (V->getType()->isEmptyTy()) 1261 return; 1262 1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1264 if (VMI != FuncInfo.ValueMap.end()) { 1265 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1266 CopyValueToVirtualRegister(V, VMI->second); 1267 } 1268} 1269 1270/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1271/// the current basic block, add it to ValueMap now so that we'll get a 1272/// CopyTo/FromReg. 1273void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1274 // No need to export constants. 1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1276 1277 // Already exported? 1278 if (FuncInfo.isExportedInst(V)) return; 1279 1280 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1281 CopyValueToVirtualRegister(V, Reg); 1282} 1283 1284bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1285 const BasicBlock *FromBB) { 1286 // The operands of the setcc have to be in this block. We don't know 1287 // how to export them from some other block. 1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1289 // Can export from current BB. 1290 if (VI->getParent() == FromBB) 1291 return true; 1292 1293 // Is already exported, noop. 1294 return FuncInfo.isExportedInst(V); 1295 } 1296 1297 // If this is an argument, we can export it if the BB is the entry block or 1298 // if it is already exported. 1299 if (isa<Argument>(V)) { 1300 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1301 return true; 1302 1303 // Otherwise, can only export this if it is already exported. 1304 return FuncInfo.isExportedInst(V); 1305 } 1306 1307 // Otherwise, constants can always be exported. 1308 return true; 1309} 1310 1311/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1312uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1313 const MachineBasicBlock *Dst) const { 1314 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1315 if (!BPI) 1316 return 0; 1317 const BasicBlock *SrcBB = Src->getBasicBlock(); 1318 const BasicBlock *DstBB = Dst->getBasicBlock(); 1319 return BPI->getEdgeWeight(SrcBB, DstBB); 1320} 1321 1322void SelectionDAGBuilder:: 1323addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1324 uint32_t Weight /* = 0 */) { 1325 if (!Weight) 1326 Weight = getEdgeWeight(Src, Dst); 1327 Src->addSuccessor(Dst, Weight); 1328} 1329 1330 1331static bool InBlock(const Value *V, const BasicBlock *BB) { 1332 if (const Instruction *I = dyn_cast<Instruction>(V)) 1333 return I->getParent() == BB; 1334 return true; 1335} 1336 1337/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1338/// This function emits a branch and is used at the leaves of an OR or an 1339/// AND operator tree. 1340/// 1341void 1342SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1343 MachineBasicBlock *TBB, 1344 MachineBasicBlock *FBB, 1345 MachineBasicBlock *CurBB, 1346 MachineBasicBlock *SwitchBB) { 1347 const BasicBlock *BB = CurBB->getBasicBlock(); 1348 1349 // If the leaf of the tree is a comparison, merge the condition into 1350 // the caseblock. 1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1352 // The operands of the cmp have to be in this block. We don't know 1353 // how to export them from some other block. If this is the first block 1354 // of the sequence, no exporting is needed. 1355 if (CurBB == SwitchBB || 1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1358 ISD::CondCode Condition; 1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1360 Condition = getICmpCondCode(IC->getPredicate()); 1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1362 Condition = getFCmpCondCode(FC->getPredicate()); 1363 if (TM.Options.NoNaNsFPMath) 1364 Condition = getFCmpCodeWithoutNaN(Condition); 1365 } else { 1366 Condition = ISD::SETEQ; // silence warning. 1367 llvm_unreachable("Unknown compare instruction"); 1368 } 1369 1370 CaseBlock CB(Condition, BOp->getOperand(0), 1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1372 SwitchCases.push_back(CB); 1373 return; 1374 } 1375 } 1376 1377 // Create a CaseBlock record representing this branch. 1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1379 NULL, TBB, FBB, CurBB); 1380 SwitchCases.push_back(CB); 1381} 1382 1383/// FindMergedConditions - If Cond is an expression like 1384void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1385 MachineBasicBlock *TBB, 1386 MachineBasicBlock *FBB, 1387 MachineBasicBlock *CurBB, 1388 MachineBasicBlock *SwitchBB, 1389 unsigned Opc) { 1390 // If this node is not part of the or/and tree, emit it as a branch. 1391 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1394 BOp->getParent() != CurBB->getBasicBlock() || 1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1398 return; 1399 } 1400 1401 // Create TmpBB after CurBB. 1402 MachineFunction::iterator BBI = CurBB; 1403 MachineFunction &MF = DAG.getMachineFunction(); 1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1405 CurBB->getParent()->insert(++BBI, TmpBB); 1406 1407 if (Opc == Instruction::Or) { 1408 // Codegen X | Y as: 1409 // jmp_if_X TBB 1410 // jmp TmpBB 1411 // TmpBB: 1412 // jmp_if_Y TBB 1413 // jmp FBB 1414 // 1415 1416 // Emit the LHS condition. 1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1418 1419 // Emit the RHS condition into TmpBB. 1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1421 } else { 1422 assert(Opc == Instruction::And && "Unknown merge op!"); 1423 // Codegen X & Y as: 1424 // jmp_if_X TmpBB 1425 // jmp FBB 1426 // TmpBB: 1427 // jmp_if_Y TBB 1428 // jmp FBB 1429 // 1430 // This requires creation of TmpBB after CurBB. 1431 1432 // Emit the LHS condition. 1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1434 1435 // Emit the RHS condition into TmpBB. 1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1437 } 1438} 1439 1440/// If the set of cases should be emitted as a series of branches, return true. 1441/// If we should emit this as a bunch of and/or'd together conditions, return 1442/// false. 1443bool 1444SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1445 if (Cases.size() != 2) return true; 1446 1447 // If this is two comparisons of the same values or'd or and'd together, they 1448 // will get folded into a single comparison, so don't emit two blocks. 1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1450 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1451 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1453 return false; 1454 } 1455 1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1459 Cases[0].CC == Cases[1].CC && 1460 isa<Constant>(Cases[0].CmpRHS) && 1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1463 return false; 1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1465 return false; 1466 } 1467 1468 return true; 1469} 1470 1471void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1472 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1473 1474 // Update machine-CFG edges. 1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1476 1477 // Figure out which block is immediately after the current one. 1478 MachineBasicBlock *NextBlock = 0; 1479 MachineFunction::iterator BBI = BrMBB; 1480 if (++BBI != FuncInfo.MF->end()) 1481 NextBlock = BBI; 1482 1483 if (I.isUnconditional()) { 1484 // Update machine-CFG edges. 1485 BrMBB->addSuccessor(Succ0MBB); 1486 1487 // If this is not a fall-through branch, emit the branch. 1488 if (Succ0MBB != NextBlock) 1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1490 MVT::Other, getControlRoot(), 1491 DAG.getBasicBlock(Succ0MBB))); 1492 1493 return; 1494 } 1495 1496 // If this condition is one of the special cases we handle, do special stuff 1497 // now. 1498 const Value *CondVal = I.getCondition(); 1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1500 1501 // If this is a series of conditions that are or'd or and'd together, emit 1502 // this as a sequence of branches instead of setcc's with and/or operations. 1503 // As long as jumps are not expensive, this should improve performance. 1504 // For example, instead of something like: 1505 // cmp A, B 1506 // C = seteq 1507 // cmp D, E 1508 // F = setle 1509 // or C, F 1510 // jnz foo 1511 // Emit: 1512 // cmp A, B 1513 // je foo 1514 // cmp D, E 1515 // jle foo 1516 // 1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1518 if (!TLI.isJumpExpensive() && 1519 BOp->hasOneUse() && 1520 (BOp->getOpcode() == Instruction::And || 1521 BOp->getOpcode() == Instruction::Or)) { 1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1523 BOp->getOpcode()); 1524 // If the compares in later blocks need to use values not currently 1525 // exported from this block, export them now. This block should always 1526 // be the first entry. 1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1528 1529 // Allow some cases to be rejected. 1530 if (ShouldEmitAsBranches(SwitchCases)) { 1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1534 } 1535 1536 // Emit the branch for this block. 1537 visitSwitchCase(SwitchCases[0], BrMBB); 1538 SwitchCases.erase(SwitchCases.begin()); 1539 return; 1540 } 1541 1542 // Okay, we decided not to do this, remove any inserted MBB's and clear 1543 // SwitchCases. 1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1546 1547 SwitchCases.clear(); 1548 } 1549 } 1550 1551 // Create a CaseBlock record representing this branch. 1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1553 NULL, Succ0MBB, Succ1MBB, BrMBB); 1554 1555 // Use visitSwitchCase to actually insert the fast branch sequence for this 1556 // cond branch. 1557 visitSwitchCase(CB, BrMBB); 1558} 1559 1560/// visitSwitchCase - Emits the necessary code to represent a single node in 1561/// the binary search tree resulting from lowering a switch instruction. 1562void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1563 MachineBasicBlock *SwitchBB) { 1564 SDValue Cond; 1565 SDValue CondLHS = getValue(CB.CmpLHS); 1566 DebugLoc dl = getCurDebugLoc(); 1567 1568 // Build the setcc now. 1569 if (CB.CmpMHS == NULL) { 1570 // Fold "(X == true)" to X and "(X == false)" to !X to 1571 // handle common cases produced by branch lowering. 1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1573 CB.CC == ISD::SETEQ) 1574 Cond = CondLHS; 1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1576 CB.CC == ISD::SETEQ) { 1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1579 } else 1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1581 } else { 1582 assert(CB.CC == ISD::SETCC_INVALID && 1583 "Condition is undefined for to-the-range belonging check."); 1584 1585 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1586 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1587 1588 SDValue CmpOp = getValue(CB.CmpMHS); 1589 EVT VT = CmpOp.getValueType(); 1590 1591 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1592 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1593 ISD::SETULE); 1594 } else { 1595 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1596 VT, CmpOp, DAG.getConstant(Low, VT)); 1597 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1598 DAG.getConstant(High-Low, VT), ISD::SETULE); 1599 } 1600 } 1601 1602 // Update successor info 1603 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1604 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1605 1606 // Set NextBlock to be the MBB immediately after the current one, if any. 1607 // This is used to avoid emitting unnecessary branches to the next block. 1608 MachineBasicBlock *NextBlock = 0; 1609 MachineFunction::iterator BBI = SwitchBB; 1610 if (++BBI != FuncInfo.MF->end()) 1611 NextBlock = BBI; 1612 1613 // If the lhs block is the next block, invert the condition so that we can 1614 // fall through to the lhs instead of the rhs block. 1615 if (CB.TrueBB == NextBlock) { 1616 std::swap(CB.TrueBB, CB.FalseBB); 1617 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1618 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1619 } 1620 1621 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1622 MVT::Other, getControlRoot(), Cond, 1623 DAG.getBasicBlock(CB.TrueBB)); 1624 1625 // Insert the false branch. Do this even if it's a fall through branch, 1626 // this makes it easier to do DAG optimizations which require inverting 1627 // the branch condition. 1628 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1629 DAG.getBasicBlock(CB.FalseBB)); 1630 1631 DAG.setRoot(BrCond); 1632} 1633 1634/// visitJumpTable - Emit JumpTable node in the current MBB 1635void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1636 // Emit the code for the jump table 1637 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1638 EVT PTy = TLI.getPointerTy(); 1639 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1640 JT.Reg, PTy); 1641 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1642 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1643 MVT::Other, Index.getValue(1), 1644 Table, Index); 1645 DAG.setRoot(BrJumpTable); 1646} 1647 1648/// visitJumpTableHeader - This function emits necessary code to produce index 1649/// in the JumpTable from switch case. 1650void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1651 JumpTableHeader &JTH, 1652 MachineBasicBlock *SwitchBB) { 1653 // Subtract the lowest switch case value from the value being switched on and 1654 // conditional branch to default mbb if the result is greater than the 1655 // difference between smallest and largest cases. 1656 SDValue SwitchOp = getValue(JTH.SValue); 1657 EVT VT = SwitchOp.getValueType(); 1658 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1659 DAG.getConstant(JTH.First, VT)); 1660 1661 // The SDNode we just created, which holds the value being switched on minus 1662 // the smallest case value, needs to be copied to a virtual register so it 1663 // can be used as an index into the jump table in a subsequent basic block. 1664 // This value may be smaller or larger than the target's pointer type, and 1665 // therefore require extension or truncating. 1666 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1667 1668 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1669 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1670 JumpTableReg, SwitchOp); 1671 JT.Reg = JumpTableReg; 1672 1673 // Emit the range check for the jump table, and branch to the default block 1674 // for the switch statement if the value being switched on exceeds the largest 1675 // case in the switch. 1676 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1677 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1678 DAG.getConstant(JTH.Last-JTH.First,VT), 1679 ISD::SETUGT); 1680 1681 // Set NextBlock to be the MBB immediately after the current one, if any. 1682 // This is used to avoid emitting unnecessary branches to the next block. 1683 MachineBasicBlock *NextBlock = 0; 1684 MachineFunction::iterator BBI = SwitchBB; 1685 1686 if (++BBI != FuncInfo.MF->end()) 1687 NextBlock = BBI; 1688 1689 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1690 MVT::Other, CopyTo, CMP, 1691 DAG.getBasicBlock(JT.Default)); 1692 1693 if (JT.MBB != NextBlock) 1694 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1695 DAG.getBasicBlock(JT.MBB)); 1696 1697 DAG.setRoot(BrCond); 1698} 1699 1700/// visitBitTestHeader - This function emits necessary code to produce value 1701/// suitable for "bit tests" 1702void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1703 MachineBasicBlock *SwitchBB) { 1704 // Subtract the minimum value 1705 SDValue SwitchOp = getValue(B.SValue); 1706 EVT VT = SwitchOp.getValueType(); 1707 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1708 DAG.getConstant(B.First, VT)); 1709 1710 // Check range 1711 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1712 TLI.getSetCCResultType(Sub.getValueType()), 1713 Sub, DAG.getConstant(B.Range, VT), 1714 ISD::SETUGT); 1715 1716 // Determine the type of the test operands. 1717 bool UsePtrType = false; 1718 if (!TLI.isTypeLegal(VT)) 1719 UsePtrType = true; 1720 else { 1721 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1722 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1723 // Switch table case range are encoded into series of masks. 1724 // Just use pointer type, it's guaranteed to fit. 1725 UsePtrType = true; 1726 break; 1727 } 1728 } 1729 if (UsePtrType) { 1730 VT = TLI.getPointerTy(); 1731 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1732 } 1733 1734 B.RegVT = VT; 1735 B.Reg = FuncInfo.CreateReg(VT); 1736 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1737 B.Reg, Sub); 1738 1739 // Set NextBlock to be the MBB immediately after the current one, if any. 1740 // This is used to avoid emitting unnecessary branches to the next block. 1741 MachineBasicBlock *NextBlock = 0; 1742 MachineFunction::iterator BBI = SwitchBB; 1743 if (++BBI != FuncInfo.MF->end()) 1744 NextBlock = BBI; 1745 1746 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1747 1748 addSuccessorWithWeight(SwitchBB, B.Default); 1749 addSuccessorWithWeight(SwitchBB, MBB); 1750 1751 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1752 MVT::Other, CopyTo, RangeCmp, 1753 DAG.getBasicBlock(B.Default)); 1754 1755 if (MBB != NextBlock) 1756 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1757 DAG.getBasicBlock(MBB)); 1758 1759 DAG.setRoot(BrRange); 1760} 1761 1762/// visitBitTestCase - this function produces one "bit test" 1763void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1764 MachineBasicBlock* NextMBB, 1765 unsigned Reg, 1766 BitTestCase &B, 1767 MachineBasicBlock *SwitchBB) { 1768 EVT VT = BB.RegVT; 1769 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1770 Reg, VT); 1771 SDValue Cmp; 1772 unsigned PopCount = CountPopulation_64(B.Mask); 1773 if (PopCount == 1) { 1774 // Testing for a single bit; just compare the shift count with what it 1775 // would need to be to shift a 1 bit in that position. 1776 Cmp = DAG.getSetCC(getCurDebugLoc(), 1777 TLI.getSetCCResultType(VT), 1778 ShiftOp, 1779 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1780 ISD::SETEQ); 1781 } else if (PopCount == BB.Range) { 1782 // There is only one zero bit in the range, test for it directly. 1783 Cmp = DAG.getSetCC(getCurDebugLoc(), 1784 TLI.getSetCCResultType(VT), 1785 ShiftOp, 1786 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1787 ISD::SETNE); 1788 } else { 1789 // Make desired shift 1790 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1791 DAG.getConstant(1, VT), ShiftOp); 1792 1793 // Emit bit tests and jumps 1794 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1795 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1796 Cmp = DAG.getSetCC(getCurDebugLoc(), 1797 TLI.getSetCCResultType(VT), 1798 AndOp, DAG.getConstant(0, VT), 1799 ISD::SETNE); 1800 } 1801 1802 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1803 addSuccessorWithWeight(SwitchBB, NextMBB); 1804 1805 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 Cmp, DAG.getBasicBlock(B.TargetBB)); 1808 1809 // Set NextBlock to be the MBB immediately after the current one, if any. 1810 // This is used to avoid emitting unnecessary branches to the next block. 1811 MachineBasicBlock *NextBlock = 0; 1812 MachineFunction::iterator BBI = SwitchBB; 1813 if (++BBI != FuncInfo.MF->end()) 1814 NextBlock = BBI; 1815 1816 if (NextMBB != NextBlock) 1817 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1818 DAG.getBasicBlock(NextMBB)); 1819 1820 DAG.setRoot(BrAnd); 1821} 1822 1823void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1824 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1825 1826 // Retrieve successors. 1827 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1828 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1829 1830 const Value *Callee(I.getCalledValue()); 1831 if (isa<InlineAsm>(Callee)) 1832 visitInlineAsm(&I); 1833 else 1834 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1835 1836 // If the value of the invoke is used outside of its defining block, make it 1837 // available as a virtual register. 1838 CopyToExportRegsIfNeeded(&I); 1839 1840 // Update successor info 1841 addSuccessorWithWeight(InvokeMBB, Return); 1842 addSuccessorWithWeight(InvokeMBB, LandingPad); 1843 1844 // Drop into normal successor. 1845 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1846 MVT::Other, getControlRoot(), 1847 DAG.getBasicBlock(Return))); 1848} 1849 1850void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1851 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1852} 1853 1854void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1855 assert(FuncInfo.MBB->isLandingPad() && 1856 "Call to landingpad not in landing pad!"); 1857 1858 MachineBasicBlock *MBB = FuncInfo.MBB; 1859 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1860 AddLandingPadInfo(LP, MMI, MBB); 1861 1862 // If there aren't registers to copy the values into (e.g., during SjLj 1863 // exceptions), then don't bother to create these DAG nodes. 1864 if (TLI.getExceptionPointerRegister() == 0 && 1865 TLI.getExceptionSelectorRegister() == 0) 1866 return; 1867 1868 SmallVector<EVT, 2> ValueVTs; 1869 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1870 1871 // Insert the EXCEPTIONADDR instruction. 1872 assert(FuncInfo.MBB->isLandingPad() && 1873 "Call to eh.exception not in landing pad!"); 1874 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1875 SDValue Ops[2]; 1876 Ops[0] = DAG.getRoot(); 1877 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1878 SDValue Chain = Op1.getValue(1); 1879 1880 // Insert the EHSELECTION instruction. 1881 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1882 Ops[0] = Op1; 1883 Ops[1] = Chain; 1884 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1885 Chain = Op2.getValue(1); 1886 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1887 1888 Ops[0] = Op1; 1889 Ops[1] = Op2; 1890 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1891 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1892 &Ops[0], 2); 1893 1894 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1895 setValue(&LP, RetPair.first); 1896 DAG.setRoot(RetPair.second); 1897} 1898 1899/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1900/// small case ranges). 1901bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1902 CaseRecVector& WorkList, 1903 const Value* SV, 1904 MachineBasicBlock *Default, 1905 MachineBasicBlock *SwitchBB) { 1906 // Size is the number of Cases represented by this range. 1907 size_t Size = CR.Range.second - CR.Range.first; 1908 if (Size > 3) 1909 return false; 1910 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineBasicBlock *NextBlock = 0; 1917 MachineFunction::iterator BBI = CR.CaseBB; 1918 1919 if (++BBI != FuncInfo.MF->end()) 1920 NextBlock = BBI; 1921 1922 // If any two of the cases has the same destination, and if one value 1923 // is the same as the other, but has one bit unset that the other has set, 1924 // use bit manipulation to do two compares at once. For example: 1925 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1926 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1927 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1928 if (Size == 2 && CR.CaseBB == SwitchBB) { 1929 Case &Small = *CR.Range.first; 1930 Case &Big = *(CR.Range.second-1); 1931 1932 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1933 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1934 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1935 1936 // Check that there is only one bit different. 1937 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1938 (SmallValue | BigValue) == BigValue) { 1939 // Isolate the common bit. 1940 APInt CommonBit = BigValue & ~SmallValue; 1941 assert((SmallValue | CommonBit) == BigValue && 1942 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1943 1944 SDValue CondLHS = getValue(SV); 1945 EVT VT = CondLHS.getValueType(); 1946 DebugLoc DL = getCurDebugLoc(); 1947 1948 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1949 DAG.getConstant(CommonBit, VT)); 1950 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1951 Or, DAG.getConstant(BigValue, VT), 1952 ISD::SETEQ); 1953 1954 // Update successor info. 1955 addSuccessorWithWeight(SwitchBB, Small.BB); 1956 addSuccessorWithWeight(SwitchBB, Default); 1957 1958 // Insert the true branch. 1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1960 getControlRoot(), Cond, 1961 DAG.getBasicBlock(Small.BB)); 1962 1963 // Insert the false branch. 1964 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1965 DAG.getBasicBlock(Default)); 1966 1967 DAG.setRoot(BrCond); 1968 return true; 1969 } 1970 } 1971 } 1972 1973 // Order cases by weight so the most likely case will be checked first. 1974 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1975 if (BPI) { 1976 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 1977 uint32_t IWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1978 I->BB->getBasicBlock()); 1979 for (CaseItr J = CR.Range.first; J < I; ++J) { 1980 uint32_t JWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1981 J->BB->getBasicBlock()); 1982 if (IWeight > JWeight) 1983 std::swap(*I, *J); 1984 } 1985 } 1986 } 1987 // Rearrange the case blocks so that the last one falls through if possible. 1988 Case &BackCase = *(CR.Range.second-1); 1989 if (Size > 1 && 1990 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1991 // The last case block won't fall through into 'NextBlock' if we emit the 1992 // branches in this order. See if rearranging a case value would help. 1993 // We start at the bottom as it's the case with the least weight. 1994 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 1995 if (I->BB == NextBlock) { 1996 std::swap(*I, BackCase); 1997 break; 1998 } 1999 } 2000 } 2001 2002 // Create a CaseBlock record representing a conditional branch to 2003 // the Case's target mbb if the value being switched on SV is equal 2004 // to C. 2005 MachineBasicBlock *CurBlock = CR.CaseBB; 2006 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2007 MachineBasicBlock *FallThrough; 2008 if (I != E-1) { 2009 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2010 CurMF->insert(BBI, FallThrough); 2011 2012 // Put SV in a virtual register to make it available from the new blocks. 2013 ExportFromCurrentBlock(SV); 2014 } else { 2015 // If the last case doesn't match, go to the default block. 2016 FallThrough = Default; 2017 } 2018 2019 const Value *RHS, *LHS, *MHS; 2020 ISD::CondCode CC; 2021 if (I->High == I->Low) { 2022 // This is just small small case range :) containing exactly 1 case 2023 CC = ISD::SETEQ; 2024 LHS = SV; RHS = I->High; MHS = NULL; 2025 } else { 2026 CC = ISD::SETCC_INVALID; 2027 LHS = I->Low; MHS = SV; RHS = I->High; 2028 } 2029 2030 uint32_t ExtraWeight = I->ExtraWeight; 2031 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2032 /* me */ CurBlock, 2033 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2034 2035 // If emitting the first comparison, just call visitSwitchCase to emit the 2036 // code into the current block. Otherwise, push the CaseBlock onto the 2037 // vector to be later processed by SDISel, and insert the node's MBB 2038 // before the next MBB. 2039 if (CurBlock == SwitchBB) 2040 visitSwitchCase(CB, SwitchBB); 2041 else 2042 SwitchCases.push_back(CB); 2043 2044 CurBlock = FallThrough; 2045 } 2046 2047 return true; 2048} 2049 2050static inline bool areJTsAllowed(const TargetLowering &TLI) { 2051 return !TLI.getTargetMachine().Options.DisableJumpTables && 2052 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2053 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2054} 2055 2056static APInt ComputeRange(const APInt &First, const APInt &Last) { 2057 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2058 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2059 return (LastExt - FirstExt + 1ULL); 2060} 2061 2062/// handleJTSwitchCase - Emit jumptable for current switch case range 2063bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2064 CaseRecVector &WorkList, 2065 const Value *SV, 2066 MachineBasicBlock *Default, 2067 MachineBasicBlock *SwitchBB) { 2068 Case& FrontCase = *CR.Range.first; 2069 Case& BackCase = *(CR.Range.second-1); 2070 2071 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2072 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2073 2074 APInt TSize(First.getBitWidth(), 0); 2075 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2076 TSize += I->size(); 2077 2078 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2079 return false; 2080 2081 APInt Range = ComputeRange(First, Last); 2082 // The density is TSize / Range. Require at least 40%. 2083 // It should not be possible for IntTSize to saturate for sane code, but make 2084 // sure we handle Range saturation correctly. 2085 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2086 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2087 if (IntTSize * 10 < IntRange * 4) 2088 return false; 2089 2090 DEBUG(dbgs() << "Lowering jump table\n" 2091 << "First entry: " << First << ". Last entry: " << Last << '\n' 2092 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2093 2094 // Get the MachineFunction which holds the current MBB. This is used when 2095 // inserting any additional MBBs necessary to represent the switch. 2096 MachineFunction *CurMF = FuncInfo.MF; 2097 2098 // Figure out which block is immediately after the current one. 2099 MachineFunction::iterator BBI = CR.CaseBB; 2100 ++BBI; 2101 2102 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2103 2104 // Create a new basic block to hold the code for loading the address 2105 // of the jump table, and jumping to it. Update successor information; 2106 // we will either branch to the default case for the switch, or the jump 2107 // table. 2108 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2109 CurMF->insert(BBI, JumpTableBB); 2110 2111 addSuccessorWithWeight(CR.CaseBB, Default); 2112 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2113 2114 // Build a vector of destination BBs, corresponding to each target 2115 // of the jump table. If the value of the jump table slot corresponds to 2116 // a case statement, push the case's BB onto the vector, otherwise, push 2117 // the default BB. 2118 std::vector<MachineBasicBlock*> DestBBs; 2119 APInt TEI = First; 2120 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2121 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2122 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2123 2124 if (Low.ule(TEI) && TEI.ule(High)) { 2125 DestBBs.push_back(I->BB); 2126 if (TEI==High) 2127 ++I; 2128 } else { 2129 DestBBs.push_back(Default); 2130 } 2131 } 2132 2133 // Update successor info. Add one edge to each unique successor. 2134 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2135 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2136 E = DestBBs.end(); I != E; ++I) { 2137 if (!SuccsHandled[(*I)->getNumber()]) { 2138 SuccsHandled[(*I)->getNumber()] = true; 2139 addSuccessorWithWeight(JumpTableBB, *I); 2140 } 2141 } 2142 2143 // Create a jump table index for this jump table. 2144 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2145 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2146 ->createJumpTableIndex(DestBBs); 2147 2148 // Set the jump table information so that we can codegen it as a second 2149 // MachineBasicBlock 2150 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2151 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2152 if (CR.CaseBB == SwitchBB) 2153 visitJumpTableHeader(JT, JTH, SwitchBB); 2154 2155 JTCases.push_back(JumpTableBlock(JTH, JT)); 2156 return true; 2157} 2158 2159/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2160/// 2 subtrees. 2161bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2162 CaseRecVector& WorkList, 2163 const Value* SV, 2164 MachineBasicBlock *Default, 2165 MachineBasicBlock *SwitchBB) { 2166 // Get the MachineFunction which holds the current MBB. This is used when 2167 // inserting any additional MBBs necessary to represent the switch. 2168 MachineFunction *CurMF = FuncInfo.MF; 2169 2170 // Figure out which block is immediately after the current one. 2171 MachineFunction::iterator BBI = CR.CaseBB; 2172 ++BBI; 2173 2174 Case& FrontCase = *CR.Range.first; 2175 Case& BackCase = *(CR.Range.second-1); 2176 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2177 2178 // Size is the number of Cases represented by this range. 2179 unsigned Size = CR.Range.second - CR.Range.first; 2180 2181 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2182 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2183 double FMetric = 0; 2184 CaseItr Pivot = CR.Range.first + Size/2; 2185 2186 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2187 // (heuristically) allow us to emit JumpTable's later. 2188 APInt TSize(First.getBitWidth(), 0); 2189 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2190 I!=E; ++I) 2191 TSize += I->size(); 2192 2193 APInt LSize = FrontCase.size(); 2194 APInt RSize = TSize-LSize; 2195 DEBUG(dbgs() << "Selecting best pivot: \n" 2196 << "First: " << First << ", Last: " << Last <<'\n' 2197 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2198 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2199 J!=E; ++I, ++J) { 2200 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2201 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2202 APInt Range = ComputeRange(LEnd, RBegin); 2203 assert((Range - 2ULL).isNonNegative() && 2204 "Invalid case distance"); 2205 // Use volatile double here to avoid excess precision issues on some hosts, 2206 // e.g. that use 80-bit X87 registers. 2207 volatile double LDensity = 2208 (double)LSize.roundToDouble() / 2209 (LEnd - First + 1ULL).roundToDouble(); 2210 volatile double RDensity = 2211 (double)RSize.roundToDouble() / 2212 (Last - RBegin + 1ULL).roundToDouble(); 2213 double Metric = Range.logBase2()*(LDensity+RDensity); 2214 // Should always split in some non-trivial place 2215 DEBUG(dbgs() <<"=>Step\n" 2216 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2217 << "LDensity: " << LDensity 2218 << ", RDensity: " << RDensity << '\n' 2219 << "Metric: " << Metric << '\n'); 2220 if (FMetric < Metric) { 2221 Pivot = J; 2222 FMetric = Metric; 2223 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2224 } 2225 2226 LSize += J->size(); 2227 RSize -= J->size(); 2228 } 2229 if (areJTsAllowed(TLI)) { 2230 // If our case is dense we *really* should handle it earlier! 2231 assert((FMetric > 0) && "Should handle dense range earlier!"); 2232 } else { 2233 Pivot = CR.Range.first + Size/2; 2234 } 2235 2236 CaseRange LHSR(CR.Range.first, Pivot); 2237 CaseRange RHSR(Pivot, CR.Range.second); 2238 const Constant *C = Pivot->Low; 2239 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2240 2241 // We know that we branch to the LHS if the Value being switched on is 2242 // less than the Pivot value, C. We use this to optimize our binary 2243 // tree a bit, by recognizing that if SV is greater than or equal to the 2244 // LHS's Case Value, and that Case Value is exactly one less than the 2245 // Pivot's Value, then we can branch directly to the LHS's Target, 2246 // rather than creating a leaf node for it. 2247 if ((LHSR.second - LHSR.first) == 1 && 2248 LHSR.first->High == CR.GE && 2249 cast<ConstantInt>(C)->getValue() == 2250 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2251 TrueBB = LHSR.first->BB; 2252 } else { 2253 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2254 CurMF->insert(BBI, TrueBB); 2255 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2256 2257 // Put SV in a virtual register to make it available from the new blocks. 2258 ExportFromCurrentBlock(SV); 2259 } 2260 2261 // Similar to the optimization above, if the Value being switched on is 2262 // known to be less than the Constant CR.LT, and the current Case Value 2263 // is CR.LT - 1, then we can branch directly to the target block for 2264 // the current Case Value, rather than emitting a RHS leaf node for it. 2265 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2266 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2267 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2268 FalseBB = RHSR.first->BB; 2269 } else { 2270 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2271 CurMF->insert(BBI, FalseBB); 2272 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2273 2274 // Put SV in a virtual register to make it available from the new blocks. 2275 ExportFromCurrentBlock(SV); 2276 } 2277 2278 // Create a CaseBlock record representing a conditional branch to 2279 // the LHS node if the value being switched on SV is less than C. 2280 // Otherwise, branch to LHS. 2281 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2282 2283 if (CR.CaseBB == SwitchBB) 2284 visitSwitchCase(CB, SwitchBB); 2285 else 2286 SwitchCases.push_back(CB); 2287 2288 return true; 2289} 2290 2291/// handleBitTestsSwitchCase - if current case range has few destination and 2292/// range span less, than machine word bitwidth, encode case range into series 2293/// of masks and emit bit tests with these masks. 2294bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2295 CaseRecVector& WorkList, 2296 const Value* SV, 2297 MachineBasicBlock* Default, 2298 MachineBasicBlock *SwitchBB){ 2299 EVT PTy = TLI.getPointerTy(); 2300 unsigned IntPtrBits = PTy.getSizeInBits(); 2301 2302 Case& FrontCase = *CR.Range.first; 2303 Case& BackCase = *(CR.Range.second-1); 2304 2305 // Get the MachineFunction which holds the current MBB. This is used when 2306 // inserting any additional MBBs necessary to represent the switch. 2307 MachineFunction *CurMF = FuncInfo.MF; 2308 2309 // If target does not have legal shift left, do not emit bit tests at all. 2310 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2311 return false; 2312 2313 size_t numCmps = 0; 2314 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2315 I!=E; ++I) { 2316 // Single case counts one, case range - two. 2317 numCmps += (I->Low == I->High ? 1 : 2); 2318 } 2319 2320 // Count unique destinations 2321 SmallSet<MachineBasicBlock*, 4> Dests; 2322 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2323 Dests.insert(I->BB); 2324 if (Dests.size() > 3) 2325 // Don't bother the code below, if there are too much unique destinations 2326 return false; 2327 } 2328 DEBUG(dbgs() << "Total number of unique destinations: " 2329 << Dests.size() << '\n' 2330 << "Total number of comparisons: " << numCmps << '\n'); 2331 2332 // Compute span of values. 2333 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2334 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2335 APInt cmpRange = maxValue - minValue; 2336 2337 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2338 << "Low bound: " << minValue << '\n' 2339 << "High bound: " << maxValue << '\n'); 2340 2341 if (cmpRange.uge(IntPtrBits) || 2342 (!(Dests.size() == 1 && numCmps >= 3) && 2343 !(Dests.size() == 2 && numCmps >= 5) && 2344 !(Dests.size() >= 3 && numCmps >= 6))) 2345 return false; 2346 2347 DEBUG(dbgs() << "Emitting bit tests\n"); 2348 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2349 2350 // Optimize the case where all the case values fit in a 2351 // word without having to subtract minValue. In this case, 2352 // we can optimize away the subtraction. 2353 if (maxValue.ult(IntPtrBits)) { 2354 cmpRange = maxValue; 2355 } else { 2356 lowBound = minValue; 2357 } 2358 2359 CaseBitsVector CasesBits; 2360 unsigned i, count = 0; 2361 2362 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2363 MachineBasicBlock* Dest = I->BB; 2364 for (i = 0; i < count; ++i) 2365 if (Dest == CasesBits[i].BB) 2366 break; 2367 2368 if (i == count) { 2369 assert((count < 3) && "Too much destinations to test!"); 2370 CasesBits.push_back(CaseBits(0, Dest, 0)); 2371 count++; 2372 } 2373 2374 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2375 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2376 2377 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2378 uint64_t hi = (highValue - lowBound).getZExtValue(); 2379 2380 for (uint64_t j = lo; j <= hi; j++) { 2381 CasesBits[i].Mask |= 1ULL << j; 2382 CasesBits[i].Bits++; 2383 } 2384 2385 } 2386 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2387 2388 BitTestInfo BTC; 2389 2390 // Figure out which block is immediately after the current one. 2391 MachineFunction::iterator BBI = CR.CaseBB; 2392 ++BBI; 2393 2394 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2395 2396 DEBUG(dbgs() << "Cases:\n"); 2397 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2398 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2399 << ", Bits: " << CasesBits[i].Bits 2400 << ", BB: " << CasesBits[i].BB << '\n'); 2401 2402 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2403 CurMF->insert(BBI, CaseBB); 2404 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2405 CaseBB, 2406 CasesBits[i].BB)); 2407 2408 // Put SV in a virtual register to make it available from the new blocks. 2409 ExportFromCurrentBlock(SV); 2410 } 2411 2412 BitTestBlock BTB(lowBound, cmpRange, SV, 2413 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2414 CR.CaseBB, Default, BTC); 2415 2416 if (CR.CaseBB == SwitchBB) 2417 visitBitTestHeader(BTB, SwitchBB); 2418 2419 BitTestCases.push_back(BTB); 2420 2421 return true; 2422} 2423 2424/// Clusterify - Transform simple list of Cases into list of CaseRange's 2425size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2426 const SwitchInst& SI) { 2427 2428 /// Use a shorter form of declaration, and also 2429 /// show the we want to use CRSBuilder as Clusterifier. 2430 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2431 2432 Clusterifier TheClusterifier; 2433 2434 // Start with "simple" cases 2435 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2436 i != e; ++i) { 2437 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2438 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2439 2440 TheClusterifier.add(i.getCaseValueEx(), SMBB); 2441 } 2442 2443 TheClusterifier.optimize(); 2444 2445 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2446 size_t numCmps = 0; 2447 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2448 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2449 Clusterifier::Cluster &C = *i; 2450 unsigned W = 0; 2451 if (BPI) { 2452 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock()); 2453 if (!W) 2454 W = 16; 2455 W *= C.first.Weight; 2456 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W); 2457 } 2458 2459 // FIXME: Currently work with ConstantInt based numbers. 2460 // Changing it to APInt based is a pretty heavy for this commit. 2461 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2462 C.first.getHigh().toConstantInt(), C.second, W)); 2463 2464 if (C.first.getLow() != C.first.getHigh()) 2465 // A range counts double, since it requires two compares. 2466 ++numCmps; 2467 } 2468 2469 return numCmps; 2470} 2471 2472void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2473 MachineBasicBlock *Last) { 2474 // Update JTCases. 2475 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2476 if (JTCases[i].first.HeaderBB == First) 2477 JTCases[i].first.HeaderBB = Last; 2478 2479 // Update BitTestCases. 2480 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2481 if (BitTestCases[i].Parent == First) 2482 BitTestCases[i].Parent = Last; 2483} 2484 2485void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2486 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2487 2488 // Figure out which block is immediately after the current one. 2489 MachineBasicBlock *NextBlock = 0; 2490 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2491 2492 // If there is only the default destination, branch to it if it is not the 2493 // next basic block. Otherwise, just fall through. 2494 if (!SI.getNumCases()) { 2495 // Update machine-CFG edges. 2496 2497 // If this is not a fall-through branch, emit the branch. 2498 SwitchMBB->addSuccessor(Default); 2499 if (Default != NextBlock) 2500 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2501 MVT::Other, getControlRoot(), 2502 DAG.getBasicBlock(Default))); 2503 2504 return; 2505 } 2506 2507 // If there are any non-default case statements, create a vector of Cases 2508 // representing each one, and sort the vector so that we can efficiently 2509 // create a binary search tree from them. 2510 CaseVector Cases; 2511 size_t numCmps = Clusterify(Cases, SI); 2512 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2513 << ". Total compares: " << numCmps << '\n'); 2514 (void)numCmps; 2515 2516 // Get the Value to be switched on and default basic blocks, which will be 2517 // inserted into CaseBlock records, representing basic blocks in the binary 2518 // search tree. 2519 const Value *SV = SI.getCondition(); 2520 2521 // Push the initial CaseRec onto the worklist 2522 CaseRecVector WorkList; 2523 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2524 CaseRange(Cases.begin(),Cases.end()))); 2525 2526 while (!WorkList.empty()) { 2527 // Grab a record representing a case range to process off the worklist 2528 CaseRec CR = WorkList.back(); 2529 WorkList.pop_back(); 2530 2531 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2532 continue; 2533 2534 // If the range has few cases (two or less) emit a series of specific 2535 // tests. 2536 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2537 continue; 2538 2539 // If the switch has more than 5 blocks, and at least 40% dense, and the 2540 // target supports indirect branches, then emit a jump table rather than 2541 // lowering the switch to a binary tree of conditional branches. 2542 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2543 continue; 2544 2545 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2546 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2547 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2548 } 2549} 2550 2551void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2552 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2553 2554 // Update machine-CFG edges with unique successors. 2555 SmallVector<BasicBlock*, 32> succs; 2556 succs.reserve(I.getNumSuccessors()); 2557 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2558 succs.push_back(I.getSuccessor(i)); 2559 array_pod_sort(succs.begin(), succs.end()); 2560 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2561 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2562 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2563 addSuccessorWithWeight(IndirectBrMBB, Succ); 2564 } 2565 2566 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2567 MVT::Other, getControlRoot(), 2568 getValue(I.getAddress()))); 2569} 2570 2571void SelectionDAGBuilder::visitFSub(const User &I) { 2572 // -0.0 - X --> fneg 2573 Type *Ty = I.getType(); 2574 if (isa<Constant>(I.getOperand(0)) && 2575 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2576 SDValue Op2 = getValue(I.getOperand(1)); 2577 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2578 Op2.getValueType(), Op2)); 2579 return; 2580 } 2581 2582 visitBinary(I, ISD::FSUB); 2583} 2584 2585void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2586 SDValue Op1 = getValue(I.getOperand(0)); 2587 SDValue Op2 = getValue(I.getOperand(1)); 2588 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2589 Op1.getValueType(), Op1, Op2)); 2590} 2591 2592void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2593 SDValue Op1 = getValue(I.getOperand(0)); 2594 SDValue Op2 = getValue(I.getOperand(1)); 2595 2596 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2597 2598 // Coerce the shift amount to the right type if we can. 2599 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2600 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2601 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2602 DebugLoc DL = getCurDebugLoc(); 2603 2604 // If the operand is smaller than the shift count type, promote it. 2605 if (ShiftSize > Op2Size) 2606 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2607 2608 // If the operand is larger than the shift count type but the shift 2609 // count type has enough bits to represent any shift value, truncate 2610 // it now. This is a common case and it exposes the truncate to 2611 // optimization early. 2612 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2613 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2614 // Otherwise we'll need to temporarily settle for some other convenient 2615 // type. Type legalization will make adjustments once the shiftee is split. 2616 else 2617 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2618 } 2619 2620 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2621 Op1.getValueType(), Op1, Op2)); 2622} 2623 2624void SelectionDAGBuilder::visitSDiv(const User &I) { 2625 SDValue Op1 = getValue(I.getOperand(0)); 2626 SDValue Op2 = getValue(I.getOperand(1)); 2627 2628 // Turn exact SDivs into multiplications. 2629 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2630 // exact bit. 2631 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2632 !isa<ConstantSDNode>(Op1) && 2633 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2634 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2635 else 2636 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2637 Op1, Op2)); 2638} 2639 2640void SelectionDAGBuilder::visitICmp(const User &I) { 2641 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2642 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2643 predicate = IC->getPredicate(); 2644 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2645 predicate = ICmpInst::Predicate(IC->getPredicate()); 2646 SDValue Op1 = getValue(I.getOperand(0)); 2647 SDValue Op2 = getValue(I.getOperand(1)); 2648 ISD::CondCode Opcode = getICmpCondCode(predicate); 2649 2650 EVT DestVT = TLI.getValueType(I.getType()); 2651 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2652} 2653 2654void SelectionDAGBuilder::visitFCmp(const User &I) { 2655 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2656 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2657 predicate = FC->getPredicate(); 2658 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2659 predicate = FCmpInst::Predicate(FC->getPredicate()); 2660 SDValue Op1 = getValue(I.getOperand(0)); 2661 SDValue Op2 = getValue(I.getOperand(1)); 2662 ISD::CondCode Condition = getFCmpCondCode(predicate); 2663 if (TM.Options.NoNaNsFPMath) 2664 Condition = getFCmpCodeWithoutNaN(Condition); 2665 EVT DestVT = TLI.getValueType(I.getType()); 2666 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2667} 2668 2669void SelectionDAGBuilder::visitSelect(const User &I) { 2670 SmallVector<EVT, 4> ValueVTs; 2671 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2672 unsigned NumValues = ValueVTs.size(); 2673 if (NumValues == 0) return; 2674 2675 SmallVector<SDValue, 4> Values(NumValues); 2676 SDValue Cond = getValue(I.getOperand(0)); 2677 SDValue TrueVal = getValue(I.getOperand(1)); 2678 SDValue FalseVal = getValue(I.getOperand(2)); 2679 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2680 ISD::VSELECT : ISD::SELECT; 2681 2682 for (unsigned i = 0; i != NumValues; ++i) 2683 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2684 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2685 Cond, 2686 SDValue(TrueVal.getNode(), 2687 TrueVal.getResNo() + i), 2688 SDValue(FalseVal.getNode(), 2689 FalseVal.getResNo() + i)); 2690 2691 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2692 DAG.getVTList(&ValueVTs[0], NumValues), 2693 &Values[0], NumValues)); 2694} 2695 2696void SelectionDAGBuilder::visitTrunc(const User &I) { 2697 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2698 SDValue N = getValue(I.getOperand(0)); 2699 EVT DestVT = TLI.getValueType(I.getType()); 2700 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2701} 2702 2703void SelectionDAGBuilder::visitZExt(const User &I) { 2704 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2705 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2706 SDValue N = getValue(I.getOperand(0)); 2707 EVT DestVT = TLI.getValueType(I.getType()); 2708 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2709} 2710 2711void SelectionDAGBuilder::visitSExt(const User &I) { 2712 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2713 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2714 SDValue N = getValue(I.getOperand(0)); 2715 EVT DestVT = TLI.getValueType(I.getType()); 2716 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2717} 2718 2719void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2720 // FPTrunc is never a no-op cast, no need to check 2721 SDValue N = getValue(I.getOperand(0)); 2722 EVT DestVT = TLI.getValueType(I.getType()); 2723 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2724 DestVT, N, 2725 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2726} 2727 2728void SelectionDAGBuilder::visitFPExt(const User &I){ 2729 // FPExt is never a no-op cast, no need to check 2730 SDValue N = getValue(I.getOperand(0)); 2731 EVT DestVT = TLI.getValueType(I.getType()); 2732 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2733} 2734 2735void SelectionDAGBuilder::visitFPToUI(const User &I) { 2736 // FPToUI is never a no-op cast, no need to check 2737 SDValue N = getValue(I.getOperand(0)); 2738 EVT DestVT = TLI.getValueType(I.getType()); 2739 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2740} 2741 2742void SelectionDAGBuilder::visitFPToSI(const User &I) { 2743 // FPToSI is never a no-op cast, no need to check 2744 SDValue N = getValue(I.getOperand(0)); 2745 EVT DestVT = TLI.getValueType(I.getType()); 2746 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2747} 2748 2749void SelectionDAGBuilder::visitUIToFP(const User &I) { 2750 // UIToFP is never a no-op cast, no need to check 2751 SDValue N = getValue(I.getOperand(0)); 2752 EVT DestVT = TLI.getValueType(I.getType()); 2753 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2754} 2755 2756void SelectionDAGBuilder::visitSIToFP(const User &I){ 2757 // SIToFP is never a no-op cast, no need to check 2758 SDValue N = getValue(I.getOperand(0)); 2759 EVT DestVT = TLI.getValueType(I.getType()); 2760 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2761} 2762 2763void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2764 // What to do depends on the size of the integer and the size of the pointer. 2765 // We can either truncate, zero extend, or no-op, accordingly. 2766 SDValue N = getValue(I.getOperand(0)); 2767 EVT DestVT = TLI.getValueType(I.getType()); 2768 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2769} 2770 2771void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2772 // What to do depends on the size of the integer and the size of the pointer. 2773 // We can either truncate, zero extend, or no-op, accordingly. 2774 SDValue N = getValue(I.getOperand(0)); 2775 EVT DestVT = TLI.getValueType(I.getType()); 2776 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2777} 2778 2779void SelectionDAGBuilder::visitBitCast(const User &I) { 2780 SDValue N = getValue(I.getOperand(0)); 2781 EVT DestVT = TLI.getValueType(I.getType()); 2782 2783 // BitCast assures us that source and destination are the same size so this is 2784 // either a BITCAST or a no-op. 2785 if (DestVT != N.getValueType()) 2786 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2787 DestVT, N)); // convert types. 2788 else 2789 setValue(&I, N); // noop cast. 2790} 2791 2792void SelectionDAGBuilder::visitInsertElement(const User &I) { 2793 SDValue InVec = getValue(I.getOperand(0)); 2794 SDValue InVal = getValue(I.getOperand(1)); 2795 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2796 TLI.getPointerTy(), 2797 getValue(I.getOperand(2))); 2798 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2799 TLI.getValueType(I.getType()), 2800 InVec, InVal, InIdx)); 2801} 2802 2803void SelectionDAGBuilder::visitExtractElement(const User &I) { 2804 SDValue InVec = getValue(I.getOperand(0)); 2805 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2806 TLI.getPointerTy(), 2807 getValue(I.getOperand(1))); 2808 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2809 TLI.getValueType(I.getType()), InVec, InIdx)); 2810} 2811 2812// Utility for visitShuffleVector - Return true if every element in Mask, 2813// beginning from position Pos and ending in Pos+Size, falls within the 2814// specified sequential range [L, L+Pos). or is undef. 2815static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2816 unsigned Pos, unsigned Size, int Low) { 2817 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2818 if (Mask[i] >= 0 && Mask[i] != Low) 2819 return false; 2820 return true; 2821} 2822 2823void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2824 SDValue Src1 = getValue(I.getOperand(0)); 2825 SDValue Src2 = getValue(I.getOperand(1)); 2826 2827 SmallVector<int, 8> Mask; 2828 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2829 unsigned MaskNumElts = Mask.size(); 2830 2831 EVT VT = TLI.getValueType(I.getType()); 2832 EVT SrcVT = Src1.getValueType(); 2833 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2834 2835 if (SrcNumElts == MaskNumElts) { 2836 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2837 &Mask[0])); 2838 return; 2839 } 2840 2841 // Normalize the shuffle vector since mask and vector length don't match. 2842 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2843 // Mask is longer than the source vectors and is a multiple of the source 2844 // vectors. We can use concatenate vector to make the mask and vectors 2845 // lengths match. 2846 if (SrcNumElts*2 == MaskNumElts) { 2847 // First check for Src1 in low and Src2 in high 2848 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2849 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2850 // The shuffle is concatenating two vectors together. 2851 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2852 VT, Src1, Src2)); 2853 return; 2854 } 2855 // Then check for Src2 in low and Src1 in high 2856 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2857 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2858 // The shuffle is concatenating two vectors together. 2859 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2860 VT, Src2, Src1)); 2861 return; 2862 } 2863 } 2864 2865 // Pad both vectors with undefs to make them the same length as the mask. 2866 unsigned NumConcat = MaskNumElts / SrcNumElts; 2867 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2868 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2869 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2870 2871 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2872 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2873 MOps1[0] = Src1; 2874 MOps2[0] = Src2; 2875 2876 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2877 getCurDebugLoc(), VT, 2878 &MOps1[0], NumConcat); 2879 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2880 getCurDebugLoc(), VT, 2881 &MOps2[0], NumConcat); 2882 2883 // Readjust mask for new input vector length. 2884 SmallVector<int, 8> MappedOps; 2885 for (unsigned i = 0; i != MaskNumElts; ++i) { 2886 int Idx = Mask[i]; 2887 if (Idx >= (int)SrcNumElts) 2888 Idx -= SrcNumElts - MaskNumElts; 2889 MappedOps.push_back(Idx); 2890 } 2891 2892 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2893 &MappedOps[0])); 2894 return; 2895 } 2896 2897 if (SrcNumElts > MaskNumElts) { 2898 // Analyze the access pattern of the vector to see if we can extract 2899 // two subvectors and do the shuffle. The analysis is done by calculating 2900 // the range of elements the mask access on both vectors. 2901 int MinRange[2] = { static_cast<int>(SrcNumElts), 2902 static_cast<int>(SrcNumElts)}; 2903 int MaxRange[2] = {-1, -1}; 2904 2905 for (unsigned i = 0; i != MaskNumElts; ++i) { 2906 int Idx = Mask[i]; 2907 unsigned Input = 0; 2908 if (Idx < 0) 2909 continue; 2910 2911 if (Idx >= (int)SrcNumElts) { 2912 Input = 1; 2913 Idx -= SrcNumElts; 2914 } 2915 if (Idx > MaxRange[Input]) 2916 MaxRange[Input] = Idx; 2917 if (Idx < MinRange[Input]) 2918 MinRange[Input] = Idx; 2919 } 2920 2921 // Check if the access is smaller than the vector size and can we find 2922 // a reasonable extract index. 2923 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2924 // Extract. 2925 int StartIdx[2]; // StartIdx to extract from 2926 for (unsigned Input = 0; Input < 2; ++Input) { 2927 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2928 RangeUse[Input] = 0; // Unused 2929 StartIdx[Input] = 0; 2930 continue; 2931 } 2932 2933 // Find a good start index that is a multiple of the mask length. Then 2934 // see if the rest of the elements are in range. 2935 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2936 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2937 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2938 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2939 } 2940 2941 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2942 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2943 return; 2944 } 2945 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2946 // Extract appropriate subvector and generate a vector shuffle 2947 for (unsigned Input = 0; Input < 2; ++Input) { 2948 SDValue &Src = Input == 0 ? Src1 : Src2; 2949 if (RangeUse[Input] == 0) 2950 Src = DAG.getUNDEF(VT); 2951 else 2952 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2953 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2954 } 2955 2956 // Calculate new mask. 2957 SmallVector<int, 8> MappedOps; 2958 for (unsigned i = 0; i != MaskNumElts; ++i) { 2959 int Idx = Mask[i]; 2960 if (Idx >= 0) { 2961 if (Idx < (int)SrcNumElts) 2962 Idx -= StartIdx[0]; 2963 else 2964 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2965 } 2966 MappedOps.push_back(Idx); 2967 } 2968 2969 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2970 &MappedOps[0])); 2971 return; 2972 } 2973 } 2974 2975 // We can't use either concat vectors or extract subvectors so fall back to 2976 // replacing the shuffle with extract and build vector. 2977 // to insert and build vector. 2978 EVT EltVT = VT.getVectorElementType(); 2979 EVT PtrVT = TLI.getPointerTy(); 2980 SmallVector<SDValue,8> Ops; 2981 for (unsigned i = 0; i != MaskNumElts; ++i) { 2982 int Idx = Mask[i]; 2983 SDValue Res; 2984 2985 if (Idx < 0) { 2986 Res = DAG.getUNDEF(EltVT); 2987 } else { 2988 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 2989 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 2990 2991 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2992 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 2993 } 2994 2995 Ops.push_back(Res); 2996 } 2997 2998 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2999 VT, &Ops[0], Ops.size())); 3000} 3001 3002void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3003 const Value *Op0 = I.getOperand(0); 3004 const Value *Op1 = I.getOperand(1); 3005 Type *AggTy = I.getType(); 3006 Type *ValTy = Op1->getType(); 3007 bool IntoUndef = isa<UndefValue>(Op0); 3008 bool FromUndef = isa<UndefValue>(Op1); 3009 3010 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3011 3012 SmallVector<EVT, 4> AggValueVTs; 3013 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3014 SmallVector<EVT, 4> ValValueVTs; 3015 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3016 3017 unsigned NumAggValues = AggValueVTs.size(); 3018 unsigned NumValValues = ValValueVTs.size(); 3019 SmallVector<SDValue, 4> Values(NumAggValues); 3020 3021 SDValue Agg = getValue(Op0); 3022 unsigned i = 0; 3023 // Copy the beginning value(s) from the original aggregate. 3024 for (; i != LinearIndex; ++i) 3025 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3026 SDValue(Agg.getNode(), Agg.getResNo() + i); 3027 // Copy values from the inserted value(s). 3028 if (NumValValues) { 3029 SDValue Val = getValue(Op1); 3030 for (; i != LinearIndex + NumValValues; ++i) 3031 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3032 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3033 } 3034 // Copy remaining value(s) from the original aggregate. 3035 for (; i != NumAggValues; ++i) 3036 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3037 SDValue(Agg.getNode(), Agg.getResNo() + i); 3038 3039 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3040 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3041 &Values[0], NumAggValues)); 3042} 3043 3044void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3045 const Value *Op0 = I.getOperand(0); 3046 Type *AggTy = Op0->getType(); 3047 Type *ValTy = I.getType(); 3048 bool OutOfUndef = isa<UndefValue>(Op0); 3049 3050 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3051 3052 SmallVector<EVT, 4> ValValueVTs; 3053 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3054 3055 unsigned NumValValues = ValValueVTs.size(); 3056 3057 // Ignore a extractvalue that produces an empty object 3058 if (!NumValValues) { 3059 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3060 return; 3061 } 3062 3063 SmallVector<SDValue, 4> Values(NumValValues); 3064 3065 SDValue Agg = getValue(Op0); 3066 // Copy out the selected value(s). 3067 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3068 Values[i - LinearIndex] = 3069 OutOfUndef ? 3070 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3071 SDValue(Agg.getNode(), Agg.getResNo() + i); 3072 3073 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3074 DAG.getVTList(&ValValueVTs[0], NumValValues), 3075 &Values[0], NumValValues)); 3076} 3077 3078void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3079 SDValue N = getValue(I.getOperand(0)); 3080 // Note that the pointer operand may be a vector of pointers. Take the scalar 3081 // element which holds a pointer. 3082 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3083 3084 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3085 OI != E; ++OI) { 3086 const Value *Idx = *OI; 3087 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3088 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3089 if (Field) { 3090 // N = N + Offset 3091 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3092 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3093 DAG.getIntPtrConstant(Offset)); 3094 } 3095 3096 Ty = StTy->getElementType(Field); 3097 } else { 3098 Ty = cast<SequentialType>(Ty)->getElementType(); 3099 3100 // If this is a constant subscript, handle it quickly. 3101 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3102 if (CI->isZero()) continue; 3103 uint64_t Offs = 3104 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3105 SDValue OffsVal; 3106 EVT PTy = TLI.getPointerTy(); 3107 unsigned PtrBits = PTy.getSizeInBits(); 3108 if (PtrBits < 64) 3109 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3110 TLI.getPointerTy(), 3111 DAG.getConstant(Offs, MVT::i64)); 3112 else 3113 OffsVal = DAG.getIntPtrConstant(Offs); 3114 3115 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3116 OffsVal); 3117 continue; 3118 } 3119 3120 // N = N + Idx * ElementSize; 3121 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3122 TD->getTypeAllocSize(Ty)); 3123 SDValue IdxN = getValue(Idx); 3124 3125 // If the index is smaller or larger than intptr_t, truncate or extend 3126 // it. 3127 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3128 3129 // If this is a multiply by a power of two, turn it into a shl 3130 // immediately. This is a very common case. 3131 if (ElementSize != 1) { 3132 if (ElementSize.isPowerOf2()) { 3133 unsigned Amt = ElementSize.logBase2(); 3134 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3135 N.getValueType(), IdxN, 3136 DAG.getConstant(Amt, IdxN.getValueType())); 3137 } else { 3138 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3139 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3140 N.getValueType(), IdxN, Scale); 3141 } 3142 } 3143 3144 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3145 N.getValueType(), N, IdxN); 3146 } 3147 } 3148 3149 setValue(&I, N); 3150} 3151 3152void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3153 // If this is a fixed sized alloca in the entry block of the function, 3154 // allocate it statically on the stack. 3155 if (FuncInfo.StaticAllocaMap.count(&I)) 3156 return; // getValue will auto-populate this. 3157 3158 Type *Ty = I.getAllocatedType(); 3159 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3160 unsigned Align = 3161 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3162 I.getAlignment()); 3163 3164 SDValue AllocSize = getValue(I.getArraySize()); 3165 3166 EVT IntPtr = TLI.getPointerTy(); 3167 if (AllocSize.getValueType() != IntPtr) 3168 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3169 3170 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3171 AllocSize, 3172 DAG.getConstant(TySize, IntPtr)); 3173 3174 // Handle alignment. If the requested alignment is less than or equal to 3175 // the stack alignment, ignore it. If the size is greater than or equal to 3176 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3177 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3178 if (Align <= StackAlign) 3179 Align = 0; 3180 3181 // Round the size of the allocation up to the stack alignment size 3182 // by add SA-1 to the size. 3183 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3184 AllocSize.getValueType(), AllocSize, 3185 DAG.getIntPtrConstant(StackAlign-1)); 3186 3187 // Mask out the low bits for alignment purposes. 3188 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3189 AllocSize.getValueType(), AllocSize, 3190 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3191 3192 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3193 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3194 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3195 VTs, Ops, 3); 3196 setValue(&I, DSA); 3197 DAG.setRoot(DSA.getValue(1)); 3198 3199 // Inform the Frame Information that we have just allocated a variable-sized 3200 // object. 3201 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3202} 3203 3204void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3205 if (I.isAtomic()) 3206 return visitAtomicLoad(I); 3207 3208 const Value *SV = I.getOperand(0); 3209 SDValue Ptr = getValue(SV); 3210 3211 Type *Ty = I.getType(); 3212 3213 bool isVolatile = I.isVolatile(); 3214 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3215 bool isInvariant = I.getMetadata("invariant.load") != 0; 3216 unsigned Alignment = I.getAlignment(); 3217 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3218 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3219 3220 SmallVector<EVT, 4> ValueVTs; 3221 SmallVector<uint64_t, 4> Offsets; 3222 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3223 unsigned NumValues = ValueVTs.size(); 3224 if (NumValues == 0) 3225 return; 3226 3227 SDValue Root; 3228 bool ConstantMemory = false; 3229 if (I.isVolatile() || NumValues > MaxParallelChains) 3230 // Serialize volatile loads with other side effects. 3231 Root = getRoot(); 3232 else if (AA->pointsToConstantMemory( 3233 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3234 // Do not serialize (non-volatile) loads of constant memory with anything. 3235 Root = DAG.getEntryNode(); 3236 ConstantMemory = true; 3237 } else { 3238 // Do not serialize non-volatile loads against each other. 3239 Root = DAG.getRoot(); 3240 } 3241 3242 SmallVector<SDValue, 4> Values(NumValues); 3243 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3244 NumValues)); 3245 EVT PtrVT = Ptr.getValueType(); 3246 unsigned ChainI = 0; 3247 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3248 // Serializing loads here may result in excessive register pressure, and 3249 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3250 // could recover a bit by hoisting nodes upward in the chain by recognizing 3251 // they are side-effect free or do not alias. The optimizer should really 3252 // avoid this case by converting large object/array copies to llvm.memcpy 3253 // (MaxParallelChains should always remain as failsafe). 3254 if (ChainI == MaxParallelChains) { 3255 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3256 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3257 MVT::Other, &Chains[0], ChainI); 3258 Root = Chain; 3259 ChainI = 0; 3260 } 3261 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3262 PtrVT, Ptr, 3263 DAG.getConstant(Offsets[i], PtrVT)); 3264 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3265 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3266 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3267 Ranges); 3268 3269 Values[i] = L; 3270 Chains[ChainI] = L.getValue(1); 3271 } 3272 3273 if (!ConstantMemory) { 3274 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3275 MVT::Other, &Chains[0], ChainI); 3276 if (isVolatile) 3277 DAG.setRoot(Chain); 3278 else 3279 PendingLoads.push_back(Chain); 3280 } 3281 3282 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3283 DAG.getVTList(&ValueVTs[0], NumValues), 3284 &Values[0], NumValues)); 3285} 3286 3287void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3288 if (I.isAtomic()) 3289 return visitAtomicStore(I); 3290 3291 const Value *SrcV = I.getOperand(0); 3292 const Value *PtrV = I.getOperand(1); 3293 3294 SmallVector<EVT, 4> ValueVTs; 3295 SmallVector<uint64_t, 4> Offsets; 3296 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3297 unsigned NumValues = ValueVTs.size(); 3298 if (NumValues == 0) 3299 return; 3300 3301 // Get the lowered operands. Note that we do this after 3302 // checking if NumResults is zero, because with zero results 3303 // the operands won't have values in the map. 3304 SDValue Src = getValue(SrcV); 3305 SDValue Ptr = getValue(PtrV); 3306 3307 SDValue Root = getRoot(); 3308 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3309 NumValues)); 3310 EVT PtrVT = Ptr.getValueType(); 3311 bool isVolatile = I.isVolatile(); 3312 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3313 unsigned Alignment = I.getAlignment(); 3314 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3315 3316 unsigned ChainI = 0; 3317 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3318 // See visitLoad comments. 3319 if (ChainI == MaxParallelChains) { 3320 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3321 MVT::Other, &Chains[0], ChainI); 3322 Root = Chain; 3323 ChainI = 0; 3324 } 3325 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3326 DAG.getConstant(Offsets[i], PtrVT)); 3327 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3328 SDValue(Src.getNode(), Src.getResNo() + i), 3329 Add, MachinePointerInfo(PtrV, Offsets[i]), 3330 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3331 Chains[ChainI] = St; 3332 } 3333 3334 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3335 MVT::Other, &Chains[0], ChainI); 3336 ++SDNodeOrder; 3337 AssignOrderingToNode(StoreNode.getNode()); 3338 DAG.setRoot(StoreNode); 3339} 3340 3341static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3342 SynchronizationScope Scope, 3343 bool Before, DebugLoc dl, 3344 SelectionDAG &DAG, 3345 const TargetLowering &TLI) { 3346 // Fence, if necessary 3347 if (Before) { 3348 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3349 Order = Release; 3350 else if (Order == Acquire || Order == Monotonic) 3351 return Chain; 3352 } else { 3353 if (Order == AcquireRelease) 3354 Order = Acquire; 3355 else if (Order == Release || Order == Monotonic) 3356 return Chain; 3357 } 3358 SDValue Ops[3]; 3359 Ops[0] = Chain; 3360 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3361 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3362 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3363} 3364 3365void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3366 DebugLoc dl = getCurDebugLoc(); 3367 AtomicOrdering Order = I.getOrdering(); 3368 SynchronizationScope Scope = I.getSynchScope(); 3369 3370 SDValue InChain = getRoot(); 3371 3372 if (TLI.getInsertFencesForAtomic()) 3373 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3374 DAG, TLI); 3375 3376 SDValue L = 3377 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3378 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3379 InChain, 3380 getValue(I.getPointerOperand()), 3381 getValue(I.getCompareOperand()), 3382 getValue(I.getNewValOperand()), 3383 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3384 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3385 Scope); 3386 3387 SDValue OutChain = L.getValue(1); 3388 3389 if (TLI.getInsertFencesForAtomic()) 3390 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3391 DAG, TLI); 3392 3393 setValue(&I, L); 3394 DAG.setRoot(OutChain); 3395} 3396 3397void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3398 DebugLoc dl = getCurDebugLoc(); 3399 ISD::NodeType NT; 3400 switch (I.getOperation()) { 3401 default: llvm_unreachable("Unknown atomicrmw operation"); 3402 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3403 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3404 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3405 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3406 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3407 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3408 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3409 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3410 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3411 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3412 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3413 } 3414 AtomicOrdering Order = I.getOrdering(); 3415 SynchronizationScope Scope = I.getSynchScope(); 3416 3417 SDValue InChain = getRoot(); 3418 3419 if (TLI.getInsertFencesForAtomic()) 3420 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3421 DAG, TLI); 3422 3423 SDValue L = 3424 DAG.getAtomic(NT, dl, 3425 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3426 InChain, 3427 getValue(I.getPointerOperand()), 3428 getValue(I.getValOperand()), 3429 I.getPointerOperand(), 0 /* Alignment */, 3430 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3431 Scope); 3432 3433 SDValue OutChain = L.getValue(1); 3434 3435 if (TLI.getInsertFencesForAtomic()) 3436 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3437 DAG, TLI); 3438 3439 setValue(&I, L); 3440 DAG.setRoot(OutChain); 3441} 3442 3443void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3444 DebugLoc dl = getCurDebugLoc(); 3445 SDValue Ops[3]; 3446 Ops[0] = getRoot(); 3447 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3448 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3449 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3450} 3451 3452void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3453 DebugLoc dl = getCurDebugLoc(); 3454 AtomicOrdering Order = I.getOrdering(); 3455 SynchronizationScope Scope = I.getSynchScope(); 3456 3457 SDValue InChain = getRoot(); 3458 3459 EVT VT = EVT::getEVT(I.getType()); 3460 3461 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3462 report_fatal_error("Cannot generate unaligned atomic load"); 3463 3464 SDValue L = 3465 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3466 getValue(I.getPointerOperand()), 3467 I.getPointerOperand(), I.getAlignment(), 3468 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3469 Scope); 3470 3471 SDValue OutChain = L.getValue(1); 3472 3473 if (TLI.getInsertFencesForAtomic()) 3474 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3475 DAG, TLI); 3476 3477 setValue(&I, L); 3478 DAG.setRoot(OutChain); 3479} 3480 3481void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3482 DebugLoc dl = getCurDebugLoc(); 3483 3484 AtomicOrdering Order = I.getOrdering(); 3485 SynchronizationScope Scope = I.getSynchScope(); 3486 3487 SDValue InChain = getRoot(); 3488 3489 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3490 3491 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3492 report_fatal_error("Cannot generate unaligned atomic store"); 3493 3494 if (TLI.getInsertFencesForAtomic()) 3495 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3496 DAG, TLI); 3497 3498 SDValue OutChain = 3499 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3500 InChain, 3501 getValue(I.getPointerOperand()), 3502 getValue(I.getValueOperand()), 3503 I.getPointerOperand(), I.getAlignment(), 3504 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3505 Scope); 3506 3507 if (TLI.getInsertFencesForAtomic()) 3508 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3509 DAG, TLI); 3510 3511 DAG.setRoot(OutChain); 3512} 3513 3514/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3515/// node. 3516void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3517 unsigned Intrinsic) { 3518 bool HasChain = !I.doesNotAccessMemory(); 3519 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3520 3521 // Build the operand list. 3522 SmallVector<SDValue, 8> Ops; 3523 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3524 if (OnlyLoad) { 3525 // We don't need to serialize loads against other loads. 3526 Ops.push_back(DAG.getRoot()); 3527 } else { 3528 Ops.push_back(getRoot()); 3529 } 3530 } 3531 3532 // Info is set by getTgtMemInstrinsic 3533 TargetLowering::IntrinsicInfo Info; 3534 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3535 3536 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3537 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3538 Info.opc == ISD::INTRINSIC_W_CHAIN) 3539 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3540 3541 // Add all operands of the call to the operand list. 3542 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3543 SDValue Op = getValue(I.getArgOperand(i)); 3544 Ops.push_back(Op); 3545 } 3546 3547 SmallVector<EVT, 4> ValueVTs; 3548 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3549 3550 if (HasChain) 3551 ValueVTs.push_back(MVT::Other); 3552 3553 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3554 3555 // Create the node. 3556 SDValue Result; 3557 if (IsTgtIntrinsic) { 3558 // This is target intrinsic that touches memory 3559 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3560 VTs, &Ops[0], Ops.size(), 3561 Info.memVT, 3562 MachinePointerInfo(Info.ptrVal, Info.offset), 3563 Info.align, Info.vol, 3564 Info.readMem, Info.writeMem); 3565 } else if (!HasChain) { 3566 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3567 VTs, &Ops[0], Ops.size()); 3568 } else if (!I.getType()->isVoidTy()) { 3569 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3570 VTs, &Ops[0], Ops.size()); 3571 } else { 3572 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3573 VTs, &Ops[0], Ops.size()); 3574 } 3575 3576 if (HasChain) { 3577 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3578 if (OnlyLoad) 3579 PendingLoads.push_back(Chain); 3580 else 3581 DAG.setRoot(Chain); 3582 } 3583 3584 if (!I.getType()->isVoidTy()) { 3585 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3586 EVT VT = TLI.getValueType(PTy); 3587 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3588 } 3589 3590 setValue(&I, Result); 3591 } else { 3592 // Assign order to result here. If the intrinsic does not produce a result, 3593 // it won't be mapped to a SDNode and visit() will not assign it an order 3594 // number. 3595 ++SDNodeOrder; 3596 AssignOrderingToNode(Result.getNode()); 3597 } 3598} 3599 3600/// GetSignificand - Get the significand and build it into a floating-point 3601/// number with exponent of 1: 3602/// 3603/// Op = (Op & 0x007fffff) | 0x3f800000; 3604/// 3605/// where Op is the hexidecimal representation of floating point value. 3606static SDValue 3607GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3608 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3609 DAG.getConstant(0x007fffff, MVT::i32)); 3610 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3611 DAG.getConstant(0x3f800000, MVT::i32)); 3612 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3613} 3614 3615/// GetExponent - Get the exponent: 3616/// 3617/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3618/// 3619/// where Op is the hexidecimal representation of floating point value. 3620static SDValue 3621GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3622 DebugLoc dl) { 3623 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3624 DAG.getConstant(0x7f800000, MVT::i32)); 3625 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3626 DAG.getConstant(23, TLI.getPointerTy())); 3627 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3628 DAG.getConstant(127, MVT::i32)); 3629 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3630} 3631 3632/// getF32Constant - Get 32-bit floating point constant. 3633static SDValue 3634getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3635 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3636} 3637 3638/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3639/// limited-precision mode. 3640void 3641SelectionDAGBuilder::visitExp(const CallInst &I) { 3642 SDValue result; 3643 DebugLoc dl = getCurDebugLoc(); 3644 3645 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3646 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3647 SDValue Op = getValue(I.getArgOperand(0)); 3648 3649 // Put the exponent in the right bit position for later addition to the 3650 // final result: 3651 // 3652 // #define LOG2OFe 1.4426950f 3653 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3654 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3655 getF32Constant(DAG, 0x3fb8aa3b)); 3656 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3657 3658 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3659 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3660 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3661 3662 // IntegerPartOfX <<= 23; 3663 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3664 DAG.getConstant(23, TLI.getPointerTy())); 3665 3666 if (LimitFloatPrecision <= 6) { 3667 // For floating-point precision of 6: 3668 // 3669 // TwoToFractionalPartOfX = 3670 // 0.997535578f + 3671 // (0.735607626f + 0.252464424f * x) * x; 3672 // 3673 // error 0.0144103317, which is 6 bits 3674 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3675 getF32Constant(DAG, 0x3e814304)); 3676 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3677 getF32Constant(DAG, 0x3f3c50c8)); 3678 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3679 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3680 getF32Constant(DAG, 0x3f7f5e7e)); 3681 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3682 3683 // Add the exponent into the result in integer domain. 3684 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3685 TwoToFracPartOfX, IntegerPartOfX); 3686 3687 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3688 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3689 // For floating-point precision of 12: 3690 // 3691 // TwoToFractionalPartOfX = 3692 // 0.999892986f + 3693 // (0.696457318f + 3694 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3695 // 3696 // 0.000107046256 error, which is 13 to 14 bits 3697 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3698 getF32Constant(DAG, 0x3da235e3)); 3699 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3700 getF32Constant(DAG, 0x3e65b8f3)); 3701 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3702 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3703 getF32Constant(DAG, 0x3f324b07)); 3704 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3705 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3706 getF32Constant(DAG, 0x3f7ff8fd)); 3707 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3708 3709 // Add the exponent into the result in integer domain. 3710 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3711 TwoToFracPartOfX, IntegerPartOfX); 3712 3713 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3714 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3715 // For floating-point precision of 18: 3716 // 3717 // TwoToFractionalPartOfX = 3718 // 0.999999982f + 3719 // (0.693148872f + 3720 // (0.240227044f + 3721 // (0.554906021e-1f + 3722 // (0.961591928e-2f + 3723 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3724 // 3725 // error 2.47208000*10^(-7), which is better than 18 bits 3726 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3727 getF32Constant(DAG, 0x3924b03e)); 3728 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3729 getF32Constant(DAG, 0x3ab24b87)); 3730 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3731 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3732 getF32Constant(DAG, 0x3c1d8c17)); 3733 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3734 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3735 getF32Constant(DAG, 0x3d634a1d)); 3736 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3737 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3738 getF32Constant(DAG, 0x3e75fe14)); 3739 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3740 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3741 getF32Constant(DAG, 0x3f317234)); 3742 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3743 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3744 getF32Constant(DAG, 0x3f800000)); 3745 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3746 MVT::i32, t13); 3747 3748 // Add the exponent into the result in integer domain. 3749 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3750 TwoToFracPartOfX, IntegerPartOfX); 3751 3752 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3753 } 3754 } else { 3755 // No special expansion. 3756 result = DAG.getNode(ISD::FEXP, dl, 3757 getValue(I.getArgOperand(0)).getValueType(), 3758 getValue(I.getArgOperand(0))); 3759 } 3760 3761 setValue(&I, result); 3762} 3763 3764/// visitLog - Lower a log intrinsic. Handles the special sequences for 3765/// limited-precision mode. 3766void 3767SelectionDAGBuilder::visitLog(const CallInst &I) { 3768 SDValue result; 3769 DebugLoc dl = getCurDebugLoc(); 3770 3771 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3772 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3773 SDValue Op = getValue(I.getArgOperand(0)); 3774 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3775 3776 // Scale the exponent by log(2) [0.69314718f]. 3777 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3778 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3779 getF32Constant(DAG, 0x3f317218)); 3780 3781 // Get the significand and build it into a floating-point number with 3782 // exponent of 1. 3783 SDValue X = GetSignificand(DAG, Op1, dl); 3784 3785 if (LimitFloatPrecision <= 6) { 3786 // For floating-point precision of 6: 3787 // 3788 // LogofMantissa = 3789 // -1.1609546f + 3790 // (1.4034025f - 0.23903021f * x) * x; 3791 // 3792 // error 0.0034276066, which is better than 8 bits 3793 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3794 getF32Constant(DAG, 0xbe74c456)); 3795 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3796 getF32Constant(DAG, 0x3fb3a2b1)); 3797 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3798 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3799 getF32Constant(DAG, 0x3f949a29)); 3800 3801 result = DAG.getNode(ISD::FADD, dl, 3802 MVT::f32, LogOfExponent, LogOfMantissa); 3803 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3804 // For floating-point precision of 12: 3805 // 3806 // LogOfMantissa = 3807 // -1.7417939f + 3808 // (2.8212026f + 3809 // (-1.4699568f + 3810 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3811 // 3812 // error 0.000061011436, which is 14 bits 3813 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3814 getF32Constant(DAG, 0xbd67b6d6)); 3815 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3816 getF32Constant(DAG, 0x3ee4f4b8)); 3817 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3818 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3819 getF32Constant(DAG, 0x3fbc278b)); 3820 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3821 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3822 getF32Constant(DAG, 0x40348e95)); 3823 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3824 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3825 getF32Constant(DAG, 0x3fdef31a)); 3826 3827 result = DAG.getNode(ISD::FADD, dl, 3828 MVT::f32, LogOfExponent, LogOfMantissa); 3829 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3830 // For floating-point precision of 18: 3831 // 3832 // LogOfMantissa = 3833 // -2.1072184f + 3834 // (4.2372794f + 3835 // (-3.7029485f + 3836 // (2.2781945f + 3837 // (-0.87823314f + 3838 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3839 // 3840 // error 0.0000023660568, which is better than 18 bits 3841 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3842 getF32Constant(DAG, 0xbc91e5ac)); 3843 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3844 getF32Constant(DAG, 0x3e4350aa)); 3845 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3846 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3847 getF32Constant(DAG, 0x3f60d3e3)); 3848 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3849 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3850 getF32Constant(DAG, 0x4011cdf0)); 3851 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3852 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3853 getF32Constant(DAG, 0x406cfd1c)); 3854 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3855 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3856 getF32Constant(DAG, 0x408797cb)); 3857 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3858 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3859 getF32Constant(DAG, 0x4006dcab)); 3860 3861 result = DAG.getNode(ISD::FADD, dl, 3862 MVT::f32, LogOfExponent, LogOfMantissa); 3863 } 3864 } else { 3865 // No special expansion. 3866 result = DAG.getNode(ISD::FLOG, dl, 3867 getValue(I.getArgOperand(0)).getValueType(), 3868 getValue(I.getArgOperand(0))); 3869 } 3870 3871 setValue(&I, result); 3872} 3873 3874/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3875/// limited-precision mode. 3876void 3877SelectionDAGBuilder::visitLog2(const CallInst &I) { 3878 SDValue result; 3879 DebugLoc dl = getCurDebugLoc(); 3880 3881 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3882 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3883 SDValue Op = getValue(I.getArgOperand(0)); 3884 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3885 3886 // Get the exponent. 3887 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3888 3889 // Get the significand and build it into a floating-point number with 3890 // exponent of 1. 3891 SDValue X = GetSignificand(DAG, Op1, dl); 3892 3893 // Different possible minimax approximations of significand in 3894 // floating-point for various degrees of accuracy over [1,2]. 3895 if (LimitFloatPrecision <= 6) { 3896 // For floating-point precision of 6: 3897 // 3898 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3899 // 3900 // error 0.0049451742, which is more than 7 bits 3901 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3902 getF32Constant(DAG, 0xbeb08fe0)); 3903 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3904 getF32Constant(DAG, 0x40019463)); 3905 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3906 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3907 getF32Constant(DAG, 0x3fd6633d)); 3908 3909 result = DAG.getNode(ISD::FADD, dl, 3910 MVT::f32, LogOfExponent, Log2ofMantissa); 3911 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3912 // For floating-point precision of 12: 3913 // 3914 // Log2ofMantissa = 3915 // -2.51285454f + 3916 // (4.07009056f + 3917 // (-2.12067489f + 3918 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3919 // 3920 // error 0.0000876136000, which is better than 13 bits 3921 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3922 getF32Constant(DAG, 0xbda7262e)); 3923 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3924 getF32Constant(DAG, 0x3f25280b)); 3925 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3926 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3927 getF32Constant(DAG, 0x4007b923)); 3928 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3929 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3930 getF32Constant(DAG, 0x40823e2f)); 3931 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3932 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3933 getF32Constant(DAG, 0x4020d29c)); 3934 3935 result = DAG.getNode(ISD::FADD, dl, 3936 MVT::f32, LogOfExponent, Log2ofMantissa); 3937 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3938 // For floating-point precision of 18: 3939 // 3940 // Log2ofMantissa = 3941 // -3.0400495f + 3942 // (6.1129976f + 3943 // (-5.3420409f + 3944 // (3.2865683f + 3945 // (-1.2669343f + 3946 // (0.27515199f - 3947 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3948 // 3949 // error 0.0000018516, which is better than 18 bits 3950 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3951 getF32Constant(DAG, 0xbcd2769e)); 3952 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3953 getF32Constant(DAG, 0x3e8ce0b9)); 3954 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3955 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3956 getF32Constant(DAG, 0x3fa22ae7)); 3957 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3958 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3959 getF32Constant(DAG, 0x40525723)); 3960 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3961 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3962 getF32Constant(DAG, 0x40aaf200)); 3963 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3964 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3965 getF32Constant(DAG, 0x40c39dad)); 3966 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3967 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3968 getF32Constant(DAG, 0x4042902c)); 3969 3970 result = DAG.getNode(ISD::FADD, dl, 3971 MVT::f32, LogOfExponent, Log2ofMantissa); 3972 } 3973 } else { 3974 // No special expansion. 3975 result = DAG.getNode(ISD::FLOG2, dl, 3976 getValue(I.getArgOperand(0)).getValueType(), 3977 getValue(I.getArgOperand(0))); 3978 } 3979 3980 setValue(&I, result); 3981} 3982 3983/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3984/// limited-precision mode. 3985void 3986SelectionDAGBuilder::visitLog10(const CallInst &I) { 3987 SDValue result; 3988 DebugLoc dl = getCurDebugLoc(); 3989 3990 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3991 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3992 SDValue Op = getValue(I.getArgOperand(0)); 3993 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3994 3995 // Scale the exponent by log10(2) [0.30102999f]. 3996 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3997 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3998 getF32Constant(DAG, 0x3e9a209a)); 3999 4000 // Get the significand and build it into a floating-point number with 4001 // exponent of 1. 4002 SDValue X = GetSignificand(DAG, Op1, dl); 4003 4004 if (LimitFloatPrecision <= 6) { 4005 // For floating-point precision of 6: 4006 // 4007 // Log10ofMantissa = 4008 // -0.50419619f + 4009 // (0.60948995f - 0.10380950f * x) * x; 4010 // 4011 // error 0.0014886165, which is 6 bits 4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4013 getF32Constant(DAG, 0xbdd49a13)); 4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4015 getF32Constant(DAG, 0x3f1c0789)); 4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4017 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4018 getF32Constant(DAG, 0x3f011300)); 4019 4020 result = DAG.getNode(ISD::FADD, dl, 4021 MVT::f32, LogOfExponent, Log10ofMantissa); 4022 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4023 // For floating-point precision of 12: 4024 // 4025 // Log10ofMantissa = 4026 // -0.64831180f + 4027 // (0.91751397f + 4028 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4029 // 4030 // error 0.00019228036, which is better than 12 bits 4031 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4032 getF32Constant(DAG, 0x3d431f31)); 4033 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4034 getF32Constant(DAG, 0x3ea21fb2)); 4035 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4036 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4037 getF32Constant(DAG, 0x3f6ae232)); 4038 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4039 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4040 getF32Constant(DAG, 0x3f25f7c3)); 4041 4042 result = DAG.getNode(ISD::FADD, dl, 4043 MVT::f32, LogOfExponent, Log10ofMantissa); 4044 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4045 // For floating-point precision of 18: 4046 // 4047 // Log10ofMantissa = 4048 // -0.84299375f + 4049 // (1.5327582f + 4050 // (-1.0688956f + 4051 // (0.49102474f + 4052 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4053 // 4054 // error 0.0000037995730, which is better than 18 bits 4055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4056 getF32Constant(DAG, 0x3c5d51ce)); 4057 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4058 getF32Constant(DAG, 0x3e00685a)); 4059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4060 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4061 getF32Constant(DAG, 0x3efb6798)); 4062 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4063 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4064 getF32Constant(DAG, 0x3f88d192)); 4065 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4066 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4067 getF32Constant(DAG, 0x3fc4316c)); 4068 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4069 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4070 getF32Constant(DAG, 0x3f57ce70)); 4071 4072 result = DAG.getNode(ISD::FADD, dl, 4073 MVT::f32, LogOfExponent, Log10ofMantissa); 4074 } 4075 } else { 4076 // No special expansion. 4077 result = DAG.getNode(ISD::FLOG10, dl, 4078 getValue(I.getArgOperand(0)).getValueType(), 4079 getValue(I.getArgOperand(0))); 4080 } 4081 4082 setValue(&I, result); 4083} 4084 4085/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4086/// limited-precision mode. 4087void 4088SelectionDAGBuilder::visitExp2(const CallInst &I) { 4089 SDValue result; 4090 DebugLoc dl = getCurDebugLoc(); 4091 4092 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4093 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4094 SDValue Op = getValue(I.getArgOperand(0)); 4095 4096 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4097 4098 // FractionalPartOfX = x - (float)IntegerPartOfX; 4099 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4100 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4101 4102 // IntegerPartOfX <<= 23; 4103 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4104 DAG.getConstant(23, TLI.getPointerTy())); 4105 4106 if (LimitFloatPrecision <= 6) { 4107 // For floating-point precision of 6: 4108 // 4109 // TwoToFractionalPartOfX = 4110 // 0.997535578f + 4111 // (0.735607626f + 0.252464424f * x) * x; 4112 // 4113 // error 0.0144103317, which is 6 bits 4114 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4115 getF32Constant(DAG, 0x3e814304)); 4116 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4117 getF32Constant(DAG, 0x3f3c50c8)); 4118 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4119 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4120 getF32Constant(DAG, 0x3f7f5e7e)); 4121 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4122 SDValue TwoToFractionalPartOfX = 4123 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4124 4125 result = DAG.getNode(ISD::BITCAST, dl, 4126 MVT::f32, TwoToFractionalPartOfX); 4127 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4128 // For floating-point precision of 12: 4129 // 4130 // TwoToFractionalPartOfX = 4131 // 0.999892986f + 4132 // (0.696457318f + 4133 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4134 // 4135 // error 0.000107046256, which is 13 to 14 bits 4136 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4137 getF32Constant(DAG, 0x3da235e3)); 4138 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4139 getF32Constant(DAG, 0x3e65b8f3)); 4140 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4141 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4142 getF32Constant(DAG, 0x3f324b07)); 4143 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4144 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4145 getF32Constant(DAG, 0x3f7ff8fd)); 4146 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4147 SDValue TwoToFractionalPartOfX = 4148 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4149 4150 result = DAG.getNode(ISD::BITCAST, dl, 4151 MVT::f32, TwoToFractionalPartOfX); 4152 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4153 // For floating-point precision of 18: 4154 // 4155 // TwoToFractionalPartOfX = 4156 // 0.999999982f + 4157 // (0.693148872f + 4158 // (0.240227044f + 4159 // (0.554906021e-1f + 4160 // (0.961591928e-2f + 4161 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4162 // error 2.47208000*10^(-7), which is better than 18 bits 4163 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4164 getF32Constant(DAG, 0x3924b03e)); 4165 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4166 getF32Constant(DAG, 0x3ab24b87)); 4167 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4168 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4169 getF32Constant(DAG, 0x3c1d8c17)); 4170 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4171 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4172 getF32Constant(DAG, 0x3d634a1d)); 4173 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4174 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4175 getF32Constant(DAG, 0x3e75fe14)); 4176 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4177 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4178 getF32Constant(DAG, 0x3f317234)); 4179 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4180 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4181 getF32Constant(DAG, 0x3f800000)); 4182 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4183 SDValue TwoToFractionalPartOfX = 4184 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4185 4186 result = DAG.getNode(ISD::BITCAST, dl, 4187 MVT::f32, TwoToFractionalPartOfX); 4188 } 4189 } else { 4190 // No special expansion. 4191 result = DAG.getNode(ISD::FEXP2, dl, 4192 getValue(I.getArgOperand(0)).getValueType(), 4193 getValue(I.getArgOperand(0))); 4194 } 4195 4196 setValue(&I, result); 4197} 4198 4199/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4200/// limited-precision mode with x == 10.0f. 4201void 4202SelectionDAGBuilder::visitPow(const CallInst &I) { 4203 SDValue result; 4204 const Value *Val = I.getArgOperand(0); 4205 DebugLoc dl = getCurDebugLoc(); 4206 bool IsExp10 = false; 4207 4208 if (getValue(Val).getValueType() == MVT::f32 && 4209 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4210 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4211 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4212 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4213 APFloat Ten(10.0f); 4214 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4215 } 4216 } 4217 } 4218 4219 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4220 SDValue Op = getValue(I.getArgOperand(1)); 4221 4222 // Put the exponent in the right bit position for later addition to the 4223 // final result: 4224 // 4225 // #define LOG2OF10 3.3219281f 4226 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4227 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4228 getF32Constant(DAG, 0x40549a78)); 4229 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4230 4231 // FractionalPartOfX = x - (float)IntegerPartOfX; 4232 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4233 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4234 4235 // IntegerPartOfX <<= 23; 4236 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4237 DAG.getConstant(23, TLI.getPointerTy())); 4238 4239 if (LimitFloatPrecision <= 6) { 4240 // For floating-point precision of 6: 4241 // 4242 // twoToFractionalPartOfX = 4243 // 0.997535578f + 4244 // (0.735607626f + 0.252464424f * x) * x; 4245 // 4246 // error 0.0144103317, which is 6 bits 4247 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4248 getF32Constant(DAG, 0x3e814304)); 4249 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4250 getF32Constant(DAG, 0x3f3c50c8)); 4251 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4252 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4253 getF32Constant(DAG, 0x3f7f5e7e)); 4254 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4255 SDValue TwoToFractionalPartOfX = 4256 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4257 4258 result = DAG.getNode(ISD::BITCAST, dl, 4259 MVT::f32, TwoToFractionalPartOfX); 4260 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4261 // For floating-point precision of 12: 4262 // 4263 // TwoToFractionalPartOfX = 4264 // 0.999892986f + 4265 // (0.696457318f + 4266 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4267 // 4268 // error 0.000107046256, which is 13 to 14 bits 4269 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4270 getF32Constant(DAG, 0x3da235e3)); 4271 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4272 getF32Constant(DAG, 0x3e65b8f3)); 4273 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4274 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4275 getF32Constant(DAG, 0x3f324b07)); 4276 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4277 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4278 getF32Constant(DAG, 0x3f7ff8fd)); 4279 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4280 SDValue TwoToFractionalPartOfX = 4281 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4282 4283 result = DAG.getNode(ISD::BITCAST, dl, 4284 MVT::f32, TwoToFractionalPartOfX); 4285 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4286 // For floating-point precision of 18: 4287 // 4288 // TwoToFractionalPartOfX = 4289 // 0.999999982f + 4290 // (0.693148872f + 4291 // (0.240227044f + 4292 // (0.554906021e-1f + 4293 // (0.961591928e-2f + 4294 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4295 // error 2.47208000*10^(-7), which is better than 18 bits 4296 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4297 getF32Constant(DAG, 0x3924b03e)); 4298 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4299 getF32Constant(DAG, 0x3ab24b87)); 4300 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4301 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4302 getF32Constant(DAG, 0x3c1d8c17)); 4303 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4304 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4305 getF32Constant(DAG, 0x3d634a1d)); 4306 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4307 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4308 getF32Constant(DAG, 0x3e75fe14)); 4309 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4310 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4311 getF32Constant(DAG, 0x3f317234)); 4312 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4313 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4314 getF32Constant(DAG, 0x3f800000)); 4315 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4316 SDValue TwoToFractionalPartOfX = 4317 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4318 4319 result = DAG.getNode(ISD::BITCAST, dl, 4320 MVT::f32, TwoToFractionalPartOfX); 4321 } 4322 } else { 4323 // No special expansion. 4324 result = DAG.getNode(ISD::FPOW, dl, 4325 getValue(I.getArgOperand(0)).getValueType(), 4326 getValue(I.getArgOperand(0)), 4327 getValue(I.getArgOperand(1))); 4328 } 4329 4330 setValue(&I, result); 4331} 4332 4333 4334/// ExpandPowI - Expand a llvm.powi intrinsic. 4335static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4336 SelectionDAG &DAG) { 4337 // If RHS is a constant, we can expand this out to a multiplication tree, 4338 // otherwise we end up lowering to a call to __powidf2 (for example). When 4339 // optimizing for size, we only want to do this if the expansion would produce 4340 // a small number of multiplies, otherwise we do the full expansion. 4341 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4342 // Get the exponent as a positive value. 4343 unsigned Val = RHSC->getSExtValue(); 4344 if ((int)Val < 0) Val = -Val; 4345 4346 // powi(x, 0) -> 1.0 4347 if (Val == 0) 4348 return DAG.getConstantFP(1.0, LHS.getValueType()); 4349 4350 const Function *F = DAG.getMachineFunction().getFunction(); 4351 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4352 // If optimizing for size, don't insert too many multiplies. This 4353 // inserts up to 5 multiplies. 4354 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4355 // We use the simple binary decomposition method to generate the multiply 4356 // sequence. There are more optimal ways to do this (for example, 4357 // powi(x,15) generates one more multiply than it should), but this has 4358 // the benefit of being both really simple and much better than a libcall. 4359 SDValue Res; // Logically starts equal to 1.0 4360 SDValue CurSquare = LHS; 4361 while (Val) { 4362 if (Val & 1) { 4363 if (Res.getNode()) 4364 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4365 else 4366 Res = CurSquare; // 1.0*CurSquare. 4367 } 4368 4369 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4370 CurSquare, CurSquare); 4371 Val >>= 1; 4372 } 4373 4374 // If the original was negative, invert the result, producing 1/(x*x*x). 4375 if (RHSC->getSExtValue() < 0) 4376 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4377 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4378 return Res; 4379 } 4380 } 4381 4382 // Otherwise, expand to a libcall. 4383 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4384} 4385 4386// getTruncatedArgReg - Find underlying register used for an truncated 4387// argument. 4388static unsigned getTruncatedArgReg(const SDValue &N) { 4389 if (N.getOpcode() != ISD::TRUNCATE) 4390 return 0; 4391 4392 const SDValue &Ext = N.getOperand(0); 4393 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4394 const SDValue &CFR = Ext.getOperand(0); 4395 if (CFR.getOpcode() == ISD::CopyFromReg) 4396 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4397 if (CFR.getOpcode() == ISD::TRUNCATE) 4398 return getTruncatedArgReg(CFR); 4399 } 4400 return 0; 4401} 4402 4403/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4404/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4405/// At the end of instruction selection, they will be inserted to the entry BB. 4406bool 4407SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4408 int64_t Offset, 4409 const SDValue &N) { 4410 const Argument *Arg = dyn_cast<Argument>(V); 4411 if (!Arg) 4412 return false; 4413 4414 MachineFunction &MF = DAG.getMachineFunction(); 4415 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4416 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4417 4418 // Ignore inlined function arguments here. 4419 DIVariable DV(Variable); 4420 if (DV.isInlinedFnArgument(MF.getFunction())) 4421 return false; 4422 4423 unsigned Reg = 0; 4424 // Some arguments' frame index is recorded during argument lowering. 4425 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4426 if (Offset) 4427 Reg = TRI->getFrameRegister(MF); 4428 4429 if (!Reg && N.getNode()) { 4430 if (N.getOpcode() == ISD::CopyFromReg) 4431 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4432 else 4433 Reg = getTruncatedArgReg(N); 4434 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4435 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4436 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4437 if (PR) 4438 Reg = PR; 4439 } 4440 } 4441 4442 if (!Reg) { 4443 // Check if ValueMap has reg number. 4444 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4445 if (VMI != FuncInfo.ValueMap.end()) 4446 Reg = VMI->second; 4447 } 4448 4449 if (!Reg && N.getNode()) { 4450 // Check if frame index is available. 4451 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4452 if (FrameIndexSDNode *FINode = 4453 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4454 Reg = TRI->getFrameRegister(MF); 4455 Offset = FINode->getIndex(); 4456 } 4457 } 4458 4459 if (!Reg) 4460 return false; 4461 4462 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4463 TII->get(TargetOpcode::DBG_VALUE)) 4464 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4465 FuncInfo.ArgDbgValues.push_back(&*MIB); 4466 return true; 4467} 4468 4469// VisualStudio defines setjmp as _setjmp 4470#if defined(_MSC_VER) && defined(setjmp) && \ 4471 !defined(setjmp_undefined_for_msvc) 4472# pragma push_macro("setjmp") 4473# undef setjmp 4474# define setjmp_undefined_for_msvc 4475#endif 4476 4477/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4478/// we want to emit this as a call to a named external function, return the name 4479/// otherwise lower it and return null. 4480const char * 4481SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4482 DebugLoc dl = getCurDebugLoc(); 4483 SDValue Res; 4484 4485 switch (Intrinsic) { 4486 default: 4487 // By default, turn this into a target intrinsic node. 4488 visitTargetIntrinsic(I, Intrinsic); 4489 return 0; 4490 case Intrinsic::vastart: visitVAStart(I); return 0; 4491 case Intrinsic::vaend: visitVAEnd(I); return 0; 4492 case Intrinsic::vacopy: visitVACopy(I); return 0; 4493 case Intrinsic::returnaddress: 4494 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4495 getValue(I.getArgOperand(0)))); 4496 return 0; 4497 case Intrinsic::frameaddress: 4498 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4499 getValue(I.getArgOperand(0)))); 4500 return 0; 4501 case Intrinsic::setjmp: 4502 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4503 case Intrinsic::longjmp: 4504 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4505 case Intrinsic::memcpy: { 4506 // Assert for address < 256 since we support only user defined address 4507 // spaces. 4508 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4509 < 256 && 4510 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4511 < 256 && 4512 "Unknown address space"); 4513 SDValue Op1 = getValue(I.getArgOperand(0)); 4514 SDValue Op2 = getValue(I.getArgOperand(1)); 4515 SDValue Op3 = getValue(I.getArgOperand(2)); 4516 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4517 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4518 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4519 MachinePointerInfo(I.getArgOperand(0)), 4520 MachinePointerInfo(I.getArgOperand(1)))); 4521 return 0; 4522 } 4523 case Intrinsic::memset: { 4524 // Assert for address < 256 since we support only user defined address 4525 // spaces. 4526 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4527 < 256 && 4528 "Unknown address space"); 4529 SDValue Op1 = getValue(I.getArgOperand(0)); 4530 SDValue Op2 = getValue(I.getArgOperand(1)); 4531 SDValue Op3 = getValue(I.getArgOperand(2)); 4532 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4533 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4534 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4535 MachinePointerInfo(I.getArgOperand(0)))); 4536 return 0; 4537 } 4538 case Intrinsic::memmove: { 4539 // Assert for address < 256 since we support only user defined address 4540 // spaces. 4541 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4542 < 256 && 4543 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4544 < 256 && 4545 "Unknown address space"); 4546 SDValue Op1 = getValue(I.getArgOperand(0)); 4547 SDValue Op2 = getValue(I.getArgOperand(1)); 4548 SDValue Op3 = getValue(I.getArgOperand(2)); 4549 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4550 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4551 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4552 MachinePointerInfo(I.getArgOperand(0)), 4553 MachinePointerInfo(I.getArgOperand(1)))); 4554 return 0; 4555 } 4556 case Intrinsic::dbg_declare: { 4557 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4558 MDNode *Variable = DI.getVariable(); 4559 const Value *Address = DI.getAddress(); 4560 if (!Address || !DIVariable(Variable).Verify()) { 4561 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4562 return 0; 4563 } 4564 4565 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4566 // but do not always have a corresponding SDNode built. The SDNodeOrder 4567 // absolute, but not relative, values are different depending on whether 4568 // debug info exists. 4569 ++SDNodeOrder; 4570 4571 // Check if address has undef value. 4572 if (isa<UndefValue>(Address) || 4573 (Address->use_empty() && !isa<Argument>(Address))) { 4574 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4575 return 0; 4576 } 4577 4578 SDValue &N = NodeMap[Address]; 4579 if (!N.getNode() && isa<Argument>(Address)) 4580 // Check unused arguments map. 4581 N = UnusedArgNodeMap[Address]; 4582 SDDbgValue *SDV; 4583 if (N.getNode()) { 4584 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4585 Address = BCI->getOperand(0); 4586 // Parameters are handled specially. 4587 bool isParameter = 4588 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4589 isa<Argument>(Address)); 4590 4591 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4592 4593 if (isParameter && !AI) { 4594 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4595 if (FINode) 4596 // Byval parameter. We have a frame index at this point. 4597 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4598 0, dl, SDNodeOrder); 4599 else { 4600 // Address is an argument, so try to emit its dbg value using 4601 // virtual register info from the FuncInfo.ValueMap. 4602 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4603 return 0; 4604 } 4605 } else if (AI) 4606 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4607 0, dl, SDNodeOrder); 4608 else { 4609 // Can't do anything with other non-AI cases yet. 4610 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4611 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4612 DEBUG(Address->dump()); 4613 return 0; 4614 } 4615 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4616 } else { 4617 // If Address is an argument then try to emit its dbg value using 4618 // virtual register info from the FuncInfo.ValueMap. 4619 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4620 // If variable is pinned by a alloca in dominating bb then 4621 // use StaticAllocaMap. 4622 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4623 if (AI->getParent() != DI.getParent()) { 4624 DenseMap<const AllocaInst*, int>::iterator SI = 4625 FuncInfo.StaticAllocaMap.find(AI); 4626 if (SI != FuncInfo.StaticAllocaMap.end()) { 4627 SDV = DAG.getDbgValue(Variable, SI->second, 4628 0, dl, SDNodeOrder); 4629 DAG.AddDbgValue(SDV, 0, false); 4630 return 0; 4631 } 4632 } 4633 } 4634 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4635 } 4636 } 4637 return 0; 4638 } 4639 case Intrinsic::dbg_value: { 4640 const DbgValueInst &DI = cast<DbgValueInst>(I); 4641 if (!DIVariable(DI.getVariable()).Verify()) 4642 return 0; 4643 4644 MDNode *Variable = DI.getVariable(); 4645 uint64_t Offset = DI.getOffset(); 4646 const Value *V = DI.getValue(); 4647 if (!V) 4648 return 0; 4649 4650 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4651 // but do not always have a corresponding SDNode built. The SDNodeOrder 4652 // absolute, but not relative, values are different depending on whether 4653 // debug info exists. 4654 ++SDNodeOrder; 4655 SDDbgValue *SDV; 4656 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4657 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4658 DAG.AddDbgValue(SDV, 0, false); 4659 } else { 4660 // Do not use getValue() in here; we don't want to generate code at 4661 // this point if it hasn't been done yet. 4662 SDValue N = NodeMap[V]; 4663 if (!N.getNode() && isa<Argument>(V)) 4664 // Check unused arguments map. 4665 N = UnusedArgNodeMap[V]; 4666 if (N.getNode()) { 4667 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4668 SDV = DAG.getDbgValue(Variable, N.getNode(), 4669 N.getResNo(), Offset, dl, SDNodeOrder); 4670 DAG.AddDbgValue(SDV, N.getNode(), false); 4671 } 4672 } else if (!V->use_empty() ) { 4673 // Do not call getValue(V) yet, as we don't want to generate code. 4674 // Remember it for later. 4675 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4676 DanglingDebugInfoMap[V] = DDI; 4677 } else { 4678 // We may expand this to cover more cases. One case where we have no 4679 // data available is an unreferenced parameter. 4680 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4681 } 4682 } 4683 4684 // Build a debug info table entry. 4685 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4686 V = BCI->getOperand(0); 4687 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4688 // Don't handle byval struct arguments or VLAs, for example. 4689 if (!AI) { 4690 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4691 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4692 return 0; 4693 } 4694 DenseMap<const AllocaInst*, int>::iterator SI = 4695 FuncInfo.StaticAllocaMap.find(AI); 4696 if (SI == FuncInfo.StaticAllocaMap.end()) 4697 return 0; // VLAs. 4698 int FI = SI->second; 4699 4700 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4701 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4702 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4703 return 0; 4704 } 4705 4706 case Intrinsic::eh_typeid_for: { 4707 // Find the type id for the given typeinfo. 4708 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4709 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4710 Res = DAG.getConstant(TypeID, MVT::i32); 4711 setValue(&I, Res); 4712 return 0; 4713 } 4714 4715 case Intrinsic::eh_return_i32: 4716 case Intrinsic::eh_return_i64: 4717 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4718 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4719 MVT::Other, 4720 getControlRoot(), 4721 getValue(I.getArgOperand(0)), 4722 getValue(I.getArgOperand(1)))); 4723 return 0; 4724 case Intrinsic::eh_unwind_init: 4725 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4726 return 0; 4727 case Intrinsic::eh_dwarf_cfa: { 4728 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4729 TLI.getPointerTy()); 4730 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4731 TLI.getPointerTy(), 4732 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4733 TLI.getPointerTy()), 4734 CfaArg); 4735 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4736 TLI.getPointerTy(), 4737 DAG.getConstant(0, TLI.getPointerTy())); 4738 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4739 FA, Offset)); 4740 return 0; 4741 } 4742 case Intrinsic::eh_sjlj_callsite: { 4743 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4744 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4745 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4746 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4747 4748 MMI.setCurrentCallSite(CI->getZExtValue()); 4749 return 0; 4750 } 4751 case Intrinsic::eh_sjlj_functioncontext: { 4752 // Get and store the index of the function context. 4753 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4754 AllocaInst *FnCtx = 4755 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4756 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4757 MFI->setFunctionContextIndex(FI); 4758 return 0; 4759 } 4760 case Intrinsic::eh_sjlj_setjmp: { 4761 SDValue Ops[2]; 4762 Ops[0] = getRoot(); 4763 Ops[1] = getValue(I.getArgOperand(0)); 4764 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4765 DAG.getVTList(MVT::i32, MVT::Other), 4766 Ops, 2); 4767 setValue(&I, Op.getValue(0)); 4768 DAG.setRoot(Op.getValue(1)); 4769 return 0; 4770 } 4771 case Intrinsic::eh_sjlj_longjmp: { 4772 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4773 getRoot(), getValue(I.getArgOperand(0)))); 4774 return 0; 4775 } 4776 4777 case Intrinsic::x86_mmx_pslli_w: 4778 case Intrinsic::x86_mmx_pslli_d: 4779 case Intrinsic::x86_mmx_pslli_q: 4780 case Intrinsic::x86_mmx_psrli_w: 4781 case Intrinsic::x86_mmx_psrli_d: 4782 case Intrinsic::x86_mmx_psrli_q: 4783 case Intrinsic::x86_mmx_psrai_w: 4784 case Intrinsic::x86_mmx_psrai_d: { 4785 SDValue ShAmt = getValue(I.getArgOperand(1)); 4786 if (isa<ConstantSDNode>(ShAmt)) { 4787 visitTargetIntrinsic(I, Intrinsic); 4788 return 0; 4789 } 4790 unsigned NewIntrinsic = 0; 4791 EVT ShAmtVT = MVT::v2i32; 4792 switch (Intrinsic) { 4793 case Intrinsic::x86_mmx_pslli_w: 4794 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4795 break; 4796 case Intrinsic::x86_mmx_pslli_d: 4797 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4798 break; 4799 case Intrinsic::x86_mmx_pslli_q: 4800 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4801 break; 4802 case Intrinsic::x86_mmx_psrli_w: 4803 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4804 break; 4805 case Intrinsic::x86_mmx_psrli_d: 4806 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4807 break; 4808 case Intrinsic::x86_mmx_psrli_q: 4809 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4810 break; 4811 case Intrinsic::x86_mmx_psrai_w: 4812 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4813 break; 4814 case Intrinsic::x86_mmx_psrai_d: 4815 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4816 break; 4817 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4818 } 4819 4820 // The vector shift intrinsics with scalars uses 32b shift amounts but 4821 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4822 // to be zero. 4823 // We must do this early because v2i32 is not a legal type. 4824 DebugLoc dl = getCurDebugLoc(); 4825 SDValue ShOps[2]; 4826 ShOps[0] = ShAmt; 4827 ShOps[1] = DAG.getConstant(0, MVT::i32); 4828 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4829 EVT DestVT = TLI.getValueType(I.getType()); 4830 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4831 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4832 DAG.getConstant(NewIntrinsic, MVT::i32), 4833 getValue(I.getArgOperand(0)), ShAmt); 4834 setValue(&I, Res); 4835 return 0; 4836 } 4837 case Intrinsic::x86_avx_vinsertf128_pd_256: 4838 case Intrinsic::x86_avx_vinsertf128_ps_256: 4839 case Intrinsic::x86_avx_vinsertf128_si_256: 4840 case Intrinsic::x86_avx2_vinserti128: { 4841 DebugLoc dl = getCurDebugLoc(); 4842 EVT DestVT = TLI.getValueType(I.getType()); 4843 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4844 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4845 ElVT.getVectorNumElements(); 4846 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4847 getValue(I.getArgOperand(0)), 4848 getValue(I.getArgOperand(1)), 4849 DAG.getConstant(Idx, MVT::i32)); 4850 setValue(&I, Res); 4851 return 0; 4852 } 4853 case Intrinsic::convertff: 4854 case Intrinsic::convertfsi: 4855 case Intrinsic::convertfui: 4856 case Intrinsic::convertsif: 4857 case Intrinsic::convertuif: 4858 case Intrinsic::convertss: 4859 case Intrinsic::convertsu: 4860 case Intrinsic::convertus: 4861 case Intrinsic::convertuu: { 4862 ISD::CvtCode Code = ISD::CVT_INVALID; 4863 switch (Intrinsic) { 4864 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4865 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4866 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4867 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4868 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4869 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4870 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4871 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4872 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4873 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4874 } 4875 EVT DestVT = TLI.getValueType(I.getType()); 4876 const Value *Op1 = I.getArgOperand(0); 4877 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4878 DAG.getValueType(DestVT), 4879 DAG.getValueType(getValue(Op1).getValueType()), 4880 getValue(I.getArgOperand(1)), 4881 getValue(I.getArgOperand(2)), 4882 Code); 4883 setValue(&I, Res); 4884 return 0; 4885 } 4886 case Intrinsic::sqrt: 4887 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4888 getValue(I.getArgOperand(0)).getValueType(), 4889 getValue(I.getArgOperand(0)))); 4890 return 0; 4891 case Intrinsic::powi: 4892 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4893 getValue(I.getArgOperand(1)), DAG)); 4894 return 0; 4895 case Intrinsic::sin: 4896 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4897 getValue(I.getArgOperand(0)).getValueType(), 4898 getValue(I.getArgOperand(0)))); 4899 return 0; 4900 case Intrinsic::cos: 4901 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4902 getValue(I.getArgOperand(0)).getValueType(), 4903 getValue(I.getArgOperand(0)))); 4904 return 0; 4905 case Intrinsic::log: 4906 visitLog(I); 4907 return 0; 4908 case Intrinsic::log2: 4909 visitLog2(I); 4910 return 0; 4911 case Intrinsic::log10: 4912 visitLog10(I); 4913 return 0; 4914 case Intrinsic::exp: 4915 visitExp(I); 4916 return 0; 4917 case Intrinsic::exp2: 4918 visitExp2(I); 4919 return 0; 4920 case Intrinsic::pow: 4921 visitPow(I); 4922 return 0; 4923 case Intrinsic::fabs: 4924 setValue(&I, DAG.getNode(ISD::FABS, dl, 4925 getValue(I.getArgOperand(0)).getValueType(), 4926 getValue(I.getArgOperand(0)))); 4927 return 0; 4928 case Intrinsic::fma: 4929 setValue(&I, DAG.getNode(ISD::FMA, dl, 4930 getValue(I.getArgOperand(0)).getValueType(), 4931 getValue(I.getArgOperand(0)), 4932 getValue(I.getArgOperand(1)), 4933 getValue(I.getArgOperand(2)))); 4934 return 0; 4935 case Intrinsic::fmuladd: { 4936 EVT VT = TLI.getValueType(I.getType()); 4937 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4938 TLI.isOperationLegal(ISD::FMA, VT) && 4939 TLI.isFMAFasterThanMulAndAdd(VT)){ 4940 setValue(&I, DAG.getNode(ISD::FMA, dl, 4941 getValue(I.getArgOperand(0)).getValueType(), 4942 getValue(I.getArgOperand(0)), 4943 getValue(I.getArgOperand(1)), 4944 getValue(I.getArgOperand(2)))); 4945 } else { 4946 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4947 getValue(I.getArgOperand(0)).getValueType(), 4948 getValue(I.getArgOperand(0)), 4949 getValue(I.getArgOperand(1))); 4950 SDValue Add = DAG.getNode(ISD::FADD, dl, 4951 getValue(I.getArgOperand(0)).getValueType(), 4952 Mul, 4953 getValue(I.getArgOperand(2))); 4954 setValue(&I, Add); 4955 } 4956 return 0; 4957 } 4958 case Intrinsic::convert_to_fp16: 4959 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4960 MVT::i16, getValue(I.getArgOperand(0)))); 4961 return 0; 4962 case Intrinsic::convert_from_fp16: 4963 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4964 MVT::f32, getValue(I.getArgOperand(0)))); 4965 return 0; 4966 case Intrinsic::pcmarker: { 4967 SDValue Tmp = getValue(I.getArgOperand(0)); 4968 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4969 return 0; 4970 } 4971 case Intrinsic::readcyclecounter: { 4972 SDValue Op = getRoot(); 4973 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4974 DAG.getVTList(MVT::i64, MVT::Other), 4975 &Op, 1); 4976 setValue(&I, Res); 4977 DAG.setRoot(Res.getValue(1)); 4978 return 0; 4979 } 4980 case Intrinsic::bswap: 4981 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4982 getValue(I.getArgOperand(0)).getValueType(), 4983 getValue(I.getArgOperand(0)))); 4984 return 0; 4985 case Intrinsic::cttz: { 4986 SDValue Arg = getValue(I.getArgOperand(0)); 4987 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4988 EVT Ty = Arg.getValueType(); 4989 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4990 dl, Ty, Arg)); 4991 return 0; 4992 } 4993 case Intrinsic::ctlz: { 4994 SDValue Arg = getValue(I.getArgOperand(0)); 4995 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4996 EVT Ty = Arg.getValueType(); 4997 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4998 dl, Ty, Arg)); 4999 return 0; 5000 } 5001 case Intrinsic::ctpop: { 5002 SDValue Arg = getValue(I.getArgOperand(0)); 5003 EVT Ty = Arg.getValueType(); 5004 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 5005 return 0; 5006 } 5007 case Intrinsic::stacksave: { 5008 SDValue Op = getRoot(); 5009 Res = DAG.getNode(ISD::STACKSAVE, dl, 5010 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 5011 setValue(&I, Res); 5012 DAG.setRoot(Res.getValue(1)); 5013 return 0; 5014 } 5015 case Intrinsic::stackrestore: { 5016 Res = getValue(I.getArgOperand(0)); 5017 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 5018 return 0; 5019 } 5020 case Intrinsic::stackprotector: { 5021 // Emit code into the DAG to store the stack guard onto the stack. 5022 MachineFunction &MF = DAG.getMachineFunction(); 5023 MachineFrameInfo *MFI = MF.getFrameInfo(); 5024 EVT PtrTy = TLI.getPointerTy(); 5025 5026 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5027 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5028 5029 int FI = FuncInfo.StaticAllocaMap[Slot]; 5030 MFI->setStackProtectorIndex(FI); 5031 5032 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5033 5034 // Store the stack protector onto the stack. 5035 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5036 MachinePointerInfo::getFixedStack(FI), 5037 true, false, 0); 5038 setValue(&I, Res); 5039 DAG.setRoot(Res); 5040 return 0; 5041 } 5042 case Intrinsic::objectsize: { 5043 // If we don't know by now, we're never going to know. 5044 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5045 5046 assert(CI && "Non-constant type in __builtin_object_size?"); 5047 5048 SDValue Arg = getValue(I.getCalledValue()); 5049 EVT Ty = Arg.getValueType(); 5050 5051 if (CI->isZero()) 5052 Res = DAG.getConstant(-1ULL, Ty); 5053 else 5054 Res = DAG.getConstant(0, Ty); 5055 5056 setValue(&I, Res); 5057 return 0; 5058 } 5059 case Intrinsic::var_annotation: 5060 // Discard annotate attributes 5061 return 0; 5062 5063 case Intrinsic::init_trampoline: { 5064 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5065 5066 SDValue Ops[6]; 5067 Ops[0] = getRoot(); 5068 Ops[1] = getValue(I.getArgOperand(0)); 5069 Ops[2] = getValue(I.getArgOperand(1)); 5070 Ops[3] = getValue(I.getArgOperand(2)); 5071 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5072 Ops[5] = DAG.getSrcValue(F); 5073 5074 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5075 5076 DAG.setRoot(Res); 5077 return 0; 5078 } 5079 case Intrinsic::adjust_trampoline: { 5080 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5081 TLI.getPointerTy(), 5082 getValue(I.getArgOperand(0)))); 5083 return 0; 5084 } 5085 case Intrinsic::gcroot: 5086 if (GFI) { 5087 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5088 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5089 5090 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5091 GFI->addStackRoot(FI->getIndex(), TypeMap); 5092 } 5093 return 0; 5094 case Intrinsic::gcread: 5095 case Intrinsic::gcwrite: 5096 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5097 case Intrinsic::flt_rounds: 5098 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5099 return 0; 5100 5101 case Intrinsic::expect: { 5102 // Just replace __builtin_expect(exp, c) with EXP. 5103 setValue(&I, getValue(I.getArgOperand(0))); 5104 return 0; 5105 } 5106 5107 case Intrinsic::trap: { 5108 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5109 if (TrapFuncName.empty()) { 5110 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5111 return 0; 5112 } 5113 TargetLowering::ArgListTy Args; 5114 TargetLowering:: 5115 CallLoweringInfo CLI(getRoot(), I.getType(), 5116 false, false, false, false, 0, CallingConv::C, 5117 /*isTailCall=*/false, 5118 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5119 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5120 Args, DAG, getCurDebugLoc()); 5121 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5122 DAG.setRoot(Result.second); 5123 return 0; 5124 } 5125 case Intrinsic::debugtrap: { 5126 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot())); 5127 return 0; 5128 } 5129 case Intrinsic::uadd_with_overflow: 5130 case Intrinsic::sadd_with_overflow: 5131 case Intrinsic::usub_with_overflow: 5132 case Intrinsic::ssub_with_overflow: 5133 case Intrinsic::umul_with_overflow: 5134 case Intrinsic::smul_with_overflow: { 5135 ISD::NodeType Op; 5136 switch (Intrinsic) { 5137 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5138 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5139 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5140 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5141 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5142 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5143 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5144 } 5145 SDValue Op1 = getValue(I.getArgOperand(0)); 5146 SDValue Op2 = getValue(I.getArgOperand(1)); 5147 5148 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5149 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 5150 return 0; 5151 } 5152 case Intrinsic::prefetch: { 5153 SDValue Ops[5]; 5154 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5155 Ops[0] = getRoot(); 5156 Ops[1] = getValue(I.getArgOperand(0)); 5157 Ops[2] = getValue(I.getArgOperand(1)); 5158 Ops[3] = getValue(I.getArgOperand(2)); 5159 Ops[4] = getValue(I.getArgOperand(3)); 5160 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5161 DAG.getVTList(MVT::Other), 5162 &Ops[0], 5, 5163 EVT::getIntegerVT(*Context, 8), 5164 MachinePointerInfo(I.getArgOperand(0)), 5165 0, /* align */ 5166 false, /* volatile */ 5167 rw==0, /* read */ 5168 rw==1)); /* write */ 5169 return 0; 5170 } 5171 5172 case Intrinsic::invariant_start: 5173 case Intrinsic::lifetime_start: 5174 // Discard region information. 5175 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5176 return 0; 5177 case Intrinsic::invariant_end: 5178 case Intrinsic::lifetime_end: 5179 // Discard region information. 5180 return 0; 5181 } 5182} 5183 5184void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5185 bool isTailCall, 5186 MachineBasicBlock *LandingPad) { 5187 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5188 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5189 Type *RetTy = FTy->getReturnType(); 5190 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5191 MCSymbol *BeginLabel = 0; 5192 5193 TargetLowering::ArgListTy Args; 5194 TargetLowering::ArgListEntry Entry; 5195 Args.reserve(CS.arg_size()); 5196 5197 // Check whether the function can return without sret-demotion. 5198 SmallVector<ISD::OutputArg, 4> Outs; 5199 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5200 Outs, TLI); 5201 5202 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5203 DAG.getMachineFunction(), 5204 FTy->isVarArg(), Outs, 5205 FTy->getContext()); 5206 5207 SDValue DemoteStackSlot; 5208 int DemoteStackIdx = -100; 5209 5210 if (!CanLowerReturn) { 5211 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5212 FTy->getReturnType()); 5213 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5214 FTy->getReturnType()); 5215 MachineFunction &MF = DAG.getMachineFunction(); 5216 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5217 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5218 5219 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5220 Entry.Node = DemoteStackSlot; 5221 Entry.Ty = StackSlotPtrType; 5222 Entry.isSExt = false; 5223 Entry.isZExt = false; 5224 Entry.isInReg = false; 5225 Entry.isSRet = true; 5226 Entry.isNest = false; 5227 Entry.isByVal = false; 5228 Entry.Alignment = Align; 5229 Args.push_back(Entry); 5230 RetTy = Type::getVoidTy(FTy->getContext()); 5231 } 5232 5233 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5234 i != e; ++i) { 5235 const Value *V = *i; 5236 5237 // Skip empty types 5238 if (V->getType()->isEmptyTy()) 5239 continue; 5240 5241 SDValue ArgNode = getValue(V); 5242 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5243 5244 unsigned attrInd = i - CS.arg_begin() + 1; 5245 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5246 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5247 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5248 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5249 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5250 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5251 Entry.Alignment = CS.getParamAlignment(attrInd); 5252 Args.push_back(Entry); 5253 } 5254 5255 if (LandingPad) { 5256 // Insert a label before the invoke call to mark the try range. This can be 5257 // used to detect deletion of the invoke via the MachineModuleInfo. 5258 BeginLabel = MMI.getContext().CreateTempSymbol(); 5259 5260 // For SjLj, keep track of which landing pads go with which invokes 5261 // so as to maintain the ordering of pads in the LSDA. 5262 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5263 if (CallSiteIndex) { 5264 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5265 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5266 5267 // Now that the call site is handled, stop tracking it. 5268 MMI.setCurrentCallSite(0); 5269 } 5270 5271 // Both PendingLoads and PendingExports must be flushed here; 5272 // this call might not return. 5273 (void)getRoot(); 5274 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5275 } 5276 5277 // Check if target-independent constraints permit a tail call here. 5278 // Target-dependent constraints are checked within TLI.LowerCallTo. 5279 if (isTailCall && 5280 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5281 isTailCall = false; 5282 5283 // If there's a possibility that fast-isel has already selected some amount 5284 // of the current basic block, don't emit a tail call. 5285 if (isTailCall && TM.Options.EnableFastISel) 5286 isTailCall = false; 5287 5288 TargetLowering:: 5289 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5290 getCurDebugLoc(), CS); 5291 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5292 assert((isTailCall || Result.second.getNode()) && 5293 "Non-null chain expected with non-tail call!"); 5294 assert((Result.second.getNode() || !Result.first.getNode()) && 5295 "Null value expected with tail call!"); 5296 if (Result.first.getNode()) { 5297 setValue(CS.getInstruction(), Result.first); 5298 } else if (!CanLowerReturn && Result.second.getNode()) { 5299 // The instruction result is the result of loading from the 5300 // hidden sret parameter. 5301 SmallVector<EVT, 1> PVTs; 5302 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5303 5304 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5305 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5306 EVT PtrVT = PVTs[0]; 5307 5308 SmallVector<EVT, 4> RetTys; 5309 SmallVector<uint64_t, 4> Offsets; 5310 RetTy = FTy->getReturnType(); 5311 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5312 5313 unsigned NumValues = RetTys.size(); 5314 SmallVector<SDValue, 4> Values(NumValues); 5315 SmallVector<SDValue, 4> Chains(NumValues); 5316 5317 for (unsigned i = 0; i < NumValues; ++i) { 5318 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5319 DemoteStackSlot, 5320 DAG.getConstant(Offsets[i], PtrVT)); 5321 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5322 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5323 false, false, false, 1); 5324 Values[i] = L; 5325 Chains[i] = L.getValue(1); 5326 } 5327 5328 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5329 MVT::Other, &Chains[0], NumValues); 5330 PendingLoads.push_back(Chain); 5331 5332 setValue(CS.getInstruction(), 5333 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5334 DAG.getVTList(&RetTys[0], RetTys.size()), 5335 &Values[0], Values.size())); 5336 } 5337 5338 // Assign order to nodes here. If the call does not produce a result, it won't 5339 // be mapped to a SDNode and visit() will not assign it an order number. 5340 if (!Result.second.getNode()) { 5341 // As a special case, a null chain means that a tail call has been emitted and 5342 // the DAG root is already updated. 5343 HasTailCall = true; 5344 ++SDNodeOrder; 5345 AssignOrderingToNode(DAG.getRoot().getNode()); 5346 } else { 5347 DAG.setRoot(Result.second); 5348 ++SDNodeOrder; 5349 AssignOrderingToNode(Result.second.getNode()); 5350 } 5351 5352 if (LandingPad) { 5353 // Insert a label at the end of the invoke call to mark the try range. This 5354 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5355 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5356 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5357 5358 // Inform MachineModuleInfo of range. 5359 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5360 } 5361} 5362 5363/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5364/// value is equal or not-equal to zero. 5365static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5366 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5367 UI != E; ++UI) { 5368 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5369 if (IC->isEquality()) 5370 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5371 if (C->isNullValue()) 5372 continue; 5373 // Unknown instruction. 5374 return false; 5375 } 5376 return true; 5377} 5378 5379static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5380 Type *LoadTy, 5381 SelectionDAGBuilder &Builder) { 5382 5383 // Check to see if this load can be trivially constant folded, e.g. if the 5384 // input is from a string literal. 5385 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5386 // Cast pointer to the type we really want to load. 5387 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5388 PointerType::getUnqual(LoadTy)); 5389 5390 if (const Constant *LoadCst = 5391 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5392 Builder.TD)) 5393 return Builder.getValue(LoadCst); 5394 } 5395 5396 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5397 // still constant memory, the input chain can be the entry node. 5398 SDValue Root; 5399 bool ConstantMemory = false; 5400 5401 // Do not serialize (non-volatile) loads of constant memory with anything. 5402 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5403 Root = Builder.DAG.getEntryNode(); 5404 ConstantMemory = true; 5405 } else { 5406 // Do not serialize non-volatile loads against each other. 5407 Root = Builder.DAG.getRoot(); 5408 } 5409 5410 SDValue Ptr = Builder.getValue(PtrVal); 5411 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5412 Ptr, MachinePointerInfo(PtrVal), 5413 false /*volatile*/, 5414 false /*nontemporal*/, 5415 false /*isinvariant*/, 1 /* align=1 */); 5416 5417 if (!ConstantMemory) 5418 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5419 return LoadVal; 5420} 5421 5422 5423/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5424/// If so, return true and lower it, otherwise return false and it will be 5425/// lowered like a normal call. 5426bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5427 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5428 if (I.getNumArgOperands() != 3) 5429 return false; 5430 5431 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5432 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5433 !I.getArgOperand(2)->getType()->isIntegerTy() || 5434 !I.getType()->isIntegerTy()) 5435 return false; 5436 5437 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5438 5439 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5440 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5441 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5442 bool ActuallyDoIt = true; 5443 MVT LoadVT; 5444 Type *LoadTy; 5445 switch (Size->getZExtValue()) { 5446 default: 5447 LoadVT = MVT::Other; 5448 LoadTy = 0; 5449 ActuallyDoIt = false; 5450 break; 5451 case 2: 5452 LoadVT = MVT::i16; 5453 LoadTy = Type::getInt16Ty(Size->getContext()); 5454 break; 5455 case 4: 5456 LoadVT = MVT::i32; 5457 LoadTy = Type::getInt32Ty(Size->getContext()); 5458 break; 5459 case 8: 5460 LoadVT = MVT::i64; 5461 LoadTy = Type::getInt64Ty(Size->getContext()); 5462 break; 5463 /* 5464 case 16: 5465 LoadVT = MVT::v4i32; 5466 LoadTy = Type::getInt32Ty(Size->getContext()); 5467 LoadTy = VectorType::get(LoadTy, 4); 5468 break; 5469 */ 5470 } 5471 5472 // This turns into unaligned loads. We only do this if the target natively 5473 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5474 // we'll only produce a small number of byte loads. 5475 5476 // Require that we can find a legal MVT, and only do this if the target 5477 // supports unaligned loads of that type. Expanding into byte loads would 5478 // bloat the code. 5479 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5480 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5481 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5482 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5483 ActuallyDoIt = false; 5484 } 5485 5486 if (ActuallyDoIt) { 5487 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5488 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5489 5490 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5491 ISD::SETNE); 5492 EVT CallVT = TLI.getValueType(I.getType(), true); 5493 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5494 return true; 5495 } 5496 } 5497 5498 5499 return false; 5500} 5501 5502 5503void SelectionDAGBuilder::visitCall(const CallInst &I) { 5504 // Handle inline assembly differently. 5505 if (isa<InlineAsm>(I.getCalledValue())) { 5506 visitInlineAsm(&I); 5507 return; 5508 } 5509 5510 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5511 ComputeUsesVAFloatArgument(I, &MMI); 5512 5513 const char *RenameFn = 0; 5514 if (Function *F = I.getCalledFunction()) { 5515 if (F->isDeclaration()) { 5516 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5517 if (unsigned IID = II->getIntrinsicID(F)) { 5518 RenameFn = visitIntrinsicCall(I, IID); 5519 if (!RenameFn) 5520 return; 5521 } 5522 } 5523 if (unsigned IID = F->getIntrinsicID()) { 5524 RenameFn = visitIntrinsicCall(I, IID); 5525 if (!RenameFn) 5526 return; 5527 } 5528 } 5529 5530 // Check for well-known libc/libm calls. If the function is internal, it 5531 // can't be a library call. 5532 if (!F->hasLocalLinkage() && F->hasName()) { 5533 StringRef Name = F->getName(); 5534 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5535 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5536 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5537 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5538 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5539 I.getType() == I.getArgOperand(0)->getType() && 5540 I.getType() == I.getArgOperand(1)->getType()) { 5541 SDValue LHS = getValue(I.getArgOperand(0)); 5542 SDValue RHS = getValue(I.getArgOperand(1)); 5543 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5544 LHS.getValueType(), LHS, RHS)); 5545 return; 5546 } 5547 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5548 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5549 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5550 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5551 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5552 I.getType() == I.getArgOperand(0)->getType()) { 5553 SDValue Tmp = getValue(I.getArgOperand(0)); 5554 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5555 Tmp.getValueType(), Tmp)); 5556 return; 5557 } 5558 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5559 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5560 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5561 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5562 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5563 I.getType() == I.getArgOperand(0)->getType() && 5564 I.onlyReadsMemory()) { 5565 SDValue Tmp = getValue(I.getArgOperand(0)); 5566 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5567 Tmp.getValueType(), Tmp)); 5568 return; 5569 } 5570 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5571 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5572 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5573 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5574 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5575 I.getType() == I.getArgOperand(0)->getType() && 5576 I.onlyReadsMemory()) { 5577 SDValue Tmp = getValue(I.getArgOperand(0)); 5578 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5579 Tmp.getValueType(), Tmp)); 5580 return; 5581 } 5582 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5583 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5584 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5585 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5586 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5587 I.getType() == I.getArgOperand(0)->getType() && 5588 I.onlyReadsMemory()) { 5589 SDValue Tmp = getValue(I.getArgOperand(0)); 5590 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5591 Tmp.getValueType(), Tmp)); 5592 return; 5593 } 5594 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5595 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5596 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5597 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5598 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5599 I.getType() == I.getArgOperand(0)->getType()) { 5600 SDValue Tmp = getValue(I.getArgOperand(0)); 5601 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5602 Tmp.getValueType(), Tmp)); 5603 return; 5604 } 5605 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5606 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5607 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5608 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5609 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5610 I.getType() == I.getArgOperand(0)->getType()) { 5611 SDValue Tmp = getValue(I.getArgOperand(0)); 5612 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5613 Tmp.getValueType(), Tmp)); 5614 return; 5615 } 5616 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5617 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5618 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5619 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5620 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5621 I.getType() == I.getArgOperand(0)->getType()) { 5622 SDValue Tmp = getValue(I.getArgOperand(0)); 5623 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5624 Tmp.getValueType(), Tmp)); 5625 return; 5626 } 5627 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5628 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5629 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5630 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5631 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5632 I.getType() == I.getArgOperand(0)->getType()) { 5633 SDValue Tmp = getValue(I.getArgOperand(0)); 5634 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5635 Tmp.getValueType(), Tmp)); 5636 return; 5637 } 5638 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5639 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5640 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5641 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5642 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5643 I.getType() == I.getArgOperand(0)->getType()) { 5644 SDValue Tmp = getValue(I.getArgOperand(0)); 5645 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5646 Tmp.getValueType(), Tmp)); 5647 return; 5648 } 5649 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5650 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5651 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5652 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5653 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5654 I.getType() == I.getArgOperand(0)->getType() && 5655 I.onlyReadsMemory()) { 5656 SDValue Tmp = getValue(I.getArgOperand(0)); 5657 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5658 Tmp.getValueType(), Tmp)); 5659 return; 5660 } 5661 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5662 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5663 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5664 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5665 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5666 I.getType() == I.getArgOperand(0)->getType() && 5667 I.onlyReadsMemory()) { 5668 SDValue Tmp = getValue(I.getArgOperand(0)); 5669 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5670 Tmp.getValueType(), Tmp)); 5671 return; 5672 } 5673 } else if (Name == "memcmp") { 5674 if (visitMemCmpCall(I)) 5675 return; 5676 } 5677 } 5678 } 5679 5680 SDValue Callee; 5681 if (!RenameFn) 5682 Callee = getValue(I.getCalledValue()); 5683 else 5684 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5685 5686 // Check if we can potentially perform a tail call. More detailed checking is 5687 // be done within LowerCallTo, after more information about the call is known. 5688 LowerCallTo(&I, Callee, I.isTailCall()); 5689} 5690 5691namespace { 5692 5693/// AsmOperandInfo - This contains information for each constraint that we are 5694/// lowering. 5695class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5696public: 5697 /// CallOperand - If this is the result output operand or a clobber 5698 /// this is null, otherwise it is the incoming operand to the CallInst. 5699 /// This gets modified as the asm is processed. 5700 SDValue CallOperand; 5701 5702 /// AssignedRegs - If this is a register or register class operand, this 5703 /// contains the set of register corresponding to the operand. 5704 RegsForValue AssignedRegs; 5705 5706 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5707 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5708 } 5709 5710 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5711 /// corresponds to. If there is no Value* for this operand, it returns 5712 /// MVT::Other. 5713 EVT getCallOperandValEVT(LLVMContext &Context, 5714 const TargetLowering &TLI, 5715 const TargetData *TD) const { 5716 if (CallOperandVal == 0) return MVT::Other; 5717 5718 if (isa<BasicBlock>(CallOperandVal)) 5719 return TLI.getPointerTy(); 5720 5721 llvm::Type *OpTy = CallOperandVal->getType(); 5722 5723 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5724 // If this is an indirect operand, the operand is a pointer to the 5725 // accessed type. 5726 if (isIndirect) { 5727 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5728 if (!PtrTy) 5729 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5730 OpTy = PtrTy->getElementType(); 5731 } 5732 5733 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5734 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5735 if (STy->getNumElements() == 1) 5736 OpTy = STy->getElementType(0); 5737 5738 // If OpTy is not a single value, it may be a struct/union that we 5739 // can tile with integers. 5740 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5741 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5742 switch (BitSize) { 5743 default: break; 5744 case 1: 5745 case 8: 5746 case 16: 5747 case 32: 5748 case 64: 5749 case 128: 5750 OpTy = IntegerType::get(Context, BitSize); 5751 break; 5752 } 5753 } 5754 5755 return TLI.getValueType(OpTy, true); 5756 } 5757}; 5758 5759typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5760 5761} // end anonymous namespace 5762 5763/// GetRegistersForValue - Assign registers (virtual or physical) for the 5764/// specified operand. We prefer to assign virtual registers, to allow the 5765/// register allocator to handle the assignment process. However, if the asm 5766/// uses features that we can't model on machineinstrs, we have SDISel do the 5767/// allocation. This produces generally horrible, but correct, code. 5768/// 5769/// OpInfo describes the operand. 5770/// 5771static void GetRegistersForValue(SelectionDAG &DAG, 5772 const TargetLowering &TLI, 5773 DebugLoc DL, 5774 SDISelAsmOperandInfo &OpInfo) { 5775 LLVMContext &Context = *DAG.getContext(); 5776 5777 MachineFunction &MF = DAG.getMachineFunction(); 5778 SmallVector<unsigned, 4> Regs; 5779 5780 // If this is a constraint for a single physreg, or a constraint for a 5781 // register class, find it. 5782 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5783 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5784 OpInfo.ConstraintVT); 5785 5786 unsigned NumRegs = 1; 5787 if (OpInfo.ConstraintVT != MVT::Other) { 5788 // If this is a FP input in an integer register (or visa versa) insert a bit 5789 // cast of the input value. More generally, handle any case where the input 5790 // value disagrees with the register class we plan to stick this in. 5791 if (OpInfo.Type == InlineAsm::isInput && 5792 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5793 // Try to convert to the first EVT that the reg class contains. If the 5794 // types are identical size, use a bitcast to convert (e.g. two differing 5795 // vector types). 5796 EVT RegVT = *PhysReg.second->vt_begin(); 5797 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5798 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5799 RegVT, OpInfo.CallOperand); 5800 OpInfo.ConstraintVT = RegVT; 5801 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5802 // If the input is a FP value and we want it in FP registers, do a 5803 // bitcast to the corresponding integer type. This turns an f64 value 5804 // into i64, which can be passed with two i32 values on a 32-bit 5805 // machine. 5806 RegVT = EVT::getIntegerVT(Context, 5807 OpInfo.ConstraintVT.getSizeInBits()); 5808 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5809 RegVT, OpInfo.CallOperand); 5810 OpInfo.ConstraintVT = RegVT; 5811 } 5812 } 5813 5814 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5815 } 5816 5817 EVT RegVT; 5818 EVT ValueVT = OpInfo.ConstraintVT; 5819 5820 // If this is a constraint for a specific physical register, like {r17}, 5821 // assign it now. 5822 if (unsigned AssignedReg = PhysReg.first) { 5823 const TargetRegisterClass *RC = PhysReg.second; 5824 if (OpInfo.ConstraintVT == MVT::Other) 5825 ValueVT = *RC->vt_begin(); 5826 5827 // Get the actual register value type. This is important, because the user 5828 // may have asked for (e.g.) the AX register in i32 type. We need to 5829 // remember that AX is actually i16 to get the right extension. 5830 RegVT = *RC->vt_begin(); 5831 5832 // This is a explicit reference to a physical register. 5833 Regs.push_back(AssignedReg); 5834 5835 // If this is an expanded reference, add the rest of the regs to Regs. 5836 if (NumRegs != 1) { 5837 TargetRegisterClass::iterator I = RC->begin(); 5838 for (; *I != AssignedReg; ++I) 5839 assert(I != RC->end() && "Didn't find reg!"); 5840 5841 // Already added the first reg. 5842 --NumRegs; ++I; 5843 for (; NumRegs; --NumRegs, ++I) { 5844 assert(I != RC->end() && "Ran out of registers to allocate!"); 5845 Regs.push_back(*I); 5846 } 5847 } 5848 5849 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5850 return; 5851 } 5852 5853 // Otherwise, if this was a reference to an LLVM register class, create vregs 5854 // for this reference. 5855 if (const TargetRegisterClass *RC = PhysReg.second) { 5856 RegVT = *RC->vt_begin(); 5857 if (OpInfo.ConstraintVT == MVT::Other) 5858 ValueVT = RegVT; 5859 5860 // Create the appropriate number of virtual registers. 5861 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5862 for (; NumRegs; --NumRegs) 5863 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5864 5865 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5866 return; 5867 } 5868 5869 // Otherwise, we couldn't allocate enough registers for this. 5870} 5871 5872/// visitInlineAsm - Handle a call to an InlineAsm object. 5873/// 5874void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5875 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5876 5877 /// ConstraintOperands - Information about all of the constraints. 5878 SDISelAsmOperandInfoVector ConstraintOperands; 5879 5880 TargetLowering::AsmOperandInfoVector 5881 TargetConstraints = TLI.ParseConstraints(CS); 5882 5883 bool hasMemory = false; 5884 5885 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5886 unsigned ResNo = 0; // ResNo - The result number of the next output. 5887 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5888 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5889 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5890 5891 EVT OpVT = MVT::Other; 5892 5893 // Compute the value type for each operand. 5894 switch (OpInfo.Type) { 5895 case InlineAsm::isOutput: 5896 // Indirect outputs just consume an argument. 5897 if (OpInfo.isIndirect) { 5898 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5899 break; 5900 } 5901 5902 // The return value of the call is this value. As such, there is no 5903 // corresponding argument. 5904 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5905 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5906 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5907 } else { 5908 assert(ResNo == 0 && "Asm only has one result!"); 5909 OpVT = TLI.getValueType(CS.getType()); 5910 } 5911 ++ResNo; 5912 break; 5913 case InlineAsm::isInput: 5914 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5915 break; 5916 case InlineAsm::isClobber: 5917 // Nothing to do. 5918 break; 5919 } 5920 5921 // If this is an input or an indirect output, process the call argument. 5922 // BasicBlocks are labels, currently appearing only in asm's. 5923 if (OpInfo.CallOperandVal) { 5924 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5925 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5926 } else { 5927 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5928 } 5929 5930 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5931 } 5932 5933 OpInfo.ConstraintVT = OpVT; 5934 5935 // Indirect operand accesses access memory. 5936 if (OpInfo.isIndirect) 5937 hasMemory = true; 5938 else { 5939 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5940 TargetLowering::ConstraintType 5941 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5942 if (CType == TargetLowering::C_Memory) { 5943 hasMemory = true; 5944 break; 5945 } 5946 } 5947 } 5948 } 5949 5950 SDValue Chain, Flag; 5951 5952 // We won't need to flush pending loads if this asm doesn't touch 5953 // memory and is nonvolatile. 5954 if (hasMemory || IA->hasSideEffects()) 5955 Chain = getRoot(); 5956 else 5957 Chain = DAG.getRoot(); 5958 5959 // Second pass over the constraints: compute which constraint option to use 5960 // and assign registers to constraints that want a specific physreg. 5961 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5962 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5963 5964 // If this is an output operand with a matching input operand, look up the 5965 // matching input. If their types mismatch, e.g. one is an integer, the 5966 // other is floating point, or their sizes are different, flag it as an 5967 // error. 5968 if (OpInfo.hasMatchingInput()) { 5969 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5970 5971 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5972 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5973 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5974 OpInfo.ConstraintVT); 5975 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5976 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5977 Input.ConstraintVT); 5978 if ((OpInfo.ConstraintVT.isInteger() != 5979 Input.ConstraintVT.isInteger()) || 5980 (MatchRC.second != InputRC.second)) { 5981 report_fatal_error("Unsupported asm: input constraint" 5982 " with a matching output constraint of" 5983 " incompatible type!"); 5984 } 5985 Input.ConstraintVT = OpInfo.ConstraintVT; 5986 } 5987 } 5988 5989 // Compute the constraint code and ConstraintType to use. 5990 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5991 5992 // If this is a memory input, and if the operand is not indirect, do what we 5993 // need to to provide an address for the memory input. 5994 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5995 !OpInfo.isIndirect) { 5996 assert((OpInfo.isMultipleAlternative || 5997 (OpInfo.Type == InlineAsm::isInput)) && 5998 "Can only indirectify direct input operands!"); 5999 6000 // Memory operands really want the address of the value. If we don't have 6001 // an indirect input, put it in the constpool if we can, otherwise spill 6002 // it to a stack slot. 6003 // TODO: This isn't quite right. We need to handle these according to 6004 // the addressing mode that the constraint wants. Also, this may take 6005 // an additional register for the computation and we don't want that 6006 // either. 6007 6008 // If the operand is a float, integer, or vector constant, spill to a 6009 // constant pool entry to get its address. 6010 const Value *OpVal = OpInfo.CallOperandVal; 6011 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6012 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6013 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6014 TLI.getPointerTy()); 6015 } else { 6016 // Otherwise, create a stack slot and emit a store to it before the 6017 // asm. 6018 Type *Ty = OpVal->getType(); 6019 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6020 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6021 MachineFunction &MF = DAG.getMachineFunction(); 6022 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6023 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6024 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6025 OpInfo.CallOperand, StackSlot, 6026 MachinePointerInfo::getFixedStack(SSFI), 6027 false, false, 0); 6028 OpInfo.CallOperand = StackSlot; 6029 } 6030 6031 // There is no longer a Value* corresponding to this operand. 6032 OpInfo.CallOperandVal = 0; 6033 6034 // It is now an indirect operand. 6035 OpInfo.isIndirect = true; 6036 } 6037 6038 // If this constraint is for a specific register, allocate it before 6039 // anything else. 6040 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6041 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6042 } 6043 6044 // Second pass - Loop over all of the operands, assigning virtual or physregs 6045 // to register class operands. 6046 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6047 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6048 6049 // C_Register operands have already been allocated, Other/Memory don't need 6050 // to be. 6051 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6052 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6053 } 6054 6055 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6056 std::vector<SDValue> AsmNodeOperands; 6057 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6058 AsmNodeOperands.push_back( 6059 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6060 TLI.getPointerTy())); 6061 6062 // If we have a !srcloc metadata node associated with it, we want to attach 6063 // this to the ultimately generated inline asm machineinstr. To do this, we 6064 // pass in the third operand as this (potentially null) inline asm MDNode. 6065 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6066 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6067 6068 // Remember the HasSideEffect and AlignStack bits as operand 3. 6069 unsigned ExtraInfo = 0; 6070 if (IA->hasSideEffects()) 6071 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6072 if (IA->isAlignStack()) 6073 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6074 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6075 TLI.getPointerTy())); 6076 6077 // Loop over all of the inputs, copying the operand values into the 6078 // appropriate registers and processing the output regs. 6079 RegsForValue RetValRegs; 6080 6081 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6082 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6083 6084 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6085 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6086 6087 switch (OpInfo.Type) { 6088 case InlineAsm::isOutput: { 6089 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6090 OpInfo.ConstraintType != TargetLowering::C_Register) { 6091 // Memory output, or 'other' output (e.g. 'X' constraint). 6092 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6093 6094 // Add information to the INLINEASM node to know about this output. 6095 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6096 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6097 TLI.getPointerTy())); 6098 AsmNodeOperands.push_back(OpInfo.CallOperand); 6099 break; 6100 } 6101 6102 // Otherwise, this is a register or register class output. 6103 6104 // Copy the output from the appropriate register. Find a register that 6105 // we can use. 6106 if (OpInfo.AssignedRegs.Regs.empty()) { 6107 LLVMContext &Ctx = *DAG.getContext(); 6108 Ctx.emitError(CS.getInstruction(), 6109 "couldn't allocate output register for constraint '" + 6110 Twine(OpInfo.ConstraintCode) + "'"); 6111 break; 6112 } 6113 6114 // If this is an indirect operand, store through the pointer after the 6115 // asm. 6116 if (OpInfo.isIndirect) { 6117 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6118 OpInfo.CallOperandVal)); 6119 } else { 6120 // This is the result value of the call. 6121 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6122 // Concatenate this output onto the outputs list. 6123 RetValRegs.append(OpInfo.AssignedRegs); 6124 } 6125 6126 // Add information to the INLINEASM node to know that this register is 6127 // set. 6128 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6129 InlineAsm::Kind_RegDefEarlyClobber : 6130 InlineAsm::Kind_RegDef, 6131 false, 6132 0, 6133 DAG, 6134 AsmNodeOperands); 6135 break; 6136 } 6137 case InlineAsm::isInput: { 6138 SDValue InOperandVal = OpInfo.CallOperand; 6139 6140 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6141 // If this is required to match an output register we have already set, 6142 // just use its register. 6143 unsigned OperandNo = OpInfo.getMatchedOperand(); 6144 6145 // Scan until we find the definition we already emitted of this operand. 6146 // When we find it, create a RegsForValue operand. 6147 unsigned CurOp = InlineAsm::Op_FirstOperand; 6148 for (; OperandNo; --OperandNo) { 6149 // Advance to the next operand. 6150 unsigned OpFlag = 6151 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6152 assert((InlineAsm::isRegDefKind(OpFlag) || 6153 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6154 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6155 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6156 } 6157 6158 unsigned OpFlag = 6159 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6160 if (InlineAsm::isRegDefKind(OpFlag) || 6161 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6162 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6163 if (OpInfo.isIndirect) { 6164 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6165 LLVMContext &Ctx = *DAG.getContext(); 6166 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6167 " don't know how to handle tied " 6168 "indirect register inputs"); 6169 } 6170 6171 RegsForValue MatchedRegs; 6172 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6173 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6174 MatchedRegs.RegVTs.push_back(RegVT); 6175 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6176 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6177 i != e; ++i) 6178 MatchedRegs.Regs.push_back 6179 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6180 6181 // Use the produced MatchedRegs object to 6182 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6183 Chain, &Flag); 6184 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6185 true, OpInfo.getMatchedOperand(), 6186 DAG, AsmNodeOperands); 6187 break; 6188 } 6189 6190 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6191 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6192 "Unexpected number of operands"); 6193 // Add information to the INLINEASM node to know about this input. 6194 // See InlineAsm.h isUseOperandTiedToDef. 6195 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6196 OpInfo.getMatchedOperand()); 6197 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6198 TLI.getPointerTy())); 6199 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6200 break; 6201 } 6202 6203 // Treat indirect 'X' constraint as memory. 6204 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6205 OpInfo.isIndirect) 6206 OpInfo.ConstraintType = TargetLowering::C_Memory; 6207 6208 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6209 std::vector<SDValue> Ops; 6210 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6211 Ops, DAG); 6212 if (Ops.empty()) { 6213 LLVMContext &Ctx = *DAG.getContext(); 6214 Ctx.emitError(CS.getInstruction(), 6215 "invalid operand for inline asm constraint '" + 6216 Twine(OpInfo.ConstraintCode) + "'"); 6217 break; 6218 } 6219 6220 // Add information to the INLINEASM node to know about this input. 6221 unsigned ResOpType = 6222 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6223 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6224 TLI.getPointerTy())); 6225 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6226 break; 6227 } 6228 6229 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6230 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6231 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6232 "Memory operands expect pointer values"); 6233 6234 // Add information to the INLINEASM node to know about this input. 6235 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6236 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6237 TLI.getPointerTy())); 6238 AsmNodeOperands.push_back(InOperandVal); 6239 break; 6240 } 6241 6242 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6243 OpInfo.ConstraintType == TargetLowering::C_Register) && 6244 "Unknown constraint type!"); 6245 assert(!OpInfo.isIndirect && 6246 "Don't know how to handle indirect register inputs yet!"); 6247 6248 // Copy the input into the appropriate registers. 6249 if (OpInfo.AssignedRegs.Regs.empty()) { 6250 LLVMContext &Ctx = *DAG.getContext(); 6251 Ctx.emitError(CS.getInstruction(), 6252 "couldn't allocate input reg for constraint '" + 6253 Twine(OpInfo.ConstraintCode) + "'"); 6254 break; 6255 } 6256 6257 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6258 Chain, &Flag); 6259 6260 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6261 DAG, AsmNodeOperands); 6262 break; 6263 } 6264 case InlineAsm::isClobber: { 6265 // Add the clobbered value to the operand list, so that the register 6266 // allocator is aware that the physreg got clobbered. 6267 if (!OpInfo.AssignedRegs.Regs.empty()) 6268 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6269 false, 0, DAG, 6270 AsmNodeOperands); 6271 break; 6272 } 6273 } 6274 } 6275 6276 // Finish up input operands. Set the input chain and add the flag last. 6277 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6278 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6279 6280 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6281 DAG.getVTList(MVT::Other, MVT::Glue), 6282 &AsmNodeOperands[0], AsmNodeOperands.size()); 6283 Flag = Chain.getValue(1); 6284 6285 // If this asm returns a register value, copy the result from that register 6286 // and set it as the value of the call. 6287 if (!RetValRegs.Regs.empty()) { 6288 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6289 Chain, &Flag); 6290 6291 // FIXME: Why don't we do this for inline asms with MRVs? 6292 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6293 EVT ResultType = TLI.getValueType(CS.getType()); 6294 6295 // If any of the results of the inline asm is a vector, it may have the 6296 // wrong width/num elts. This can happen for register classes that can 6297 // contain multiple different value types. The preg or vreg allocated may 6298 // not have the same VT as was expected. Convert it to the right type 6299 // with bit_convert. 6300 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6301 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6302 ResultType, Val); 6303 6304 } else if (ResultType != Val.getValueType() && 6305 ResultType.isInteger() && Val.getValueType().isInteger()) { 6306 // If a result value was tied to an input value, the computed result may 6307 // have a wider width than the expected result. Extract the relevant 6308 // portion. 6309 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6310 } 6311 6312 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6313 } 6314 6315 setValue(CS.getInstruction(), Val); 6316 // Don't need to use this as a chain in this case. 6317 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6318 return; 6319 } 6320 6321 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6322 6323 // Process indirect outputs, first output all of the flagged copies out of 6324 // physregs. 6325 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6326 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6327 const Value *Ptr = IndirectStoresToEmit[i].second; 6328 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6329 Chain, &Flag); 6330 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6331 } 6332 6333 // Emit the non-flagged stores from the physregs. 6334 SmallVector<SDValue, 8> OutChains; 6335 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6336 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6337 StoresToEmit[i].first, 6338 getValue(StoresToEmit[i].second), 6339 MachinePointerInfo(StoresToEmit[i].second), 6340 false, false, 0); 6341 OutChains.push_back(Val); 6342 } 6343 6344 if (!OutChains.empty()) 6345 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6346 &OutChains[0], OutChains.size()); 6347 6348 DAG.setRoot(Chain); 6349} 6350 6351void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6352 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6353 MVT::Other, getRoot(), 6354 getValue(I.getArgOperand(0)), 6355 DAG.getSrcValue(I.getArgOperand(0)))); 6356} 6357 6358void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6359 const TargetData &TD = *TLI.getTargetData(); 6360 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6361 getRoot(), getValue(I.getOperand(0)), 6362 DAG.getSrcValue(I.getOperand(0)), 6363 TD.getABITypeAlignment(I.getType())); 6364 setValue(&I, V); 6365 DAG.setRoot(V.getValue(1)); 6366} 6367 6368void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6369 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6370 MVT::Other, getRoot(), 6371 getValue(I.getArgOperand(0)), 6372 DAG.getSrcValue(I.getArgOperand(0)))); 6373} 6374 6375void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6376 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6377 MVT::Other, getRoot(), 6378 getValue(I.getArgOperand(0)), 6379 getValue(I.getArgOperand(1)), 6380 DAG.getSrcValue(I.getArgOperand(0)), 6381 DAG.getSrcValue(I.getArgOperand(1)))); 6382} 6383 6384/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6385/// implementation, which just calls LowerCall. 6386/// FIXME: When all targets are 6387/// migrated to using LowerCall, this hook should be integrated into SDISel. 6388std::pair<SDValue, SDValue> 6389TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6390 // Handle all of the outgoing arguments. 6391 CLI.Outs.clear(); 6392 CLI.OutVals.clear(); 6393 ArgListTy &Args = CLI.Args; 6394 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6395 SmallVector<EVT, 4> ValueVTs; 6396 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6397 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6398 Value != NumValues; ++Value) { 6399 EVT VT = ValueVTs[Value]; 6400 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6401 SDValue Op = SDValue(Args[i].Node.getNode(), 6402 Args[i].Node.getResNo() + Value); 6403 ISD::ArgFlagsTy Flags; 6404 unsigned OriginalAlignment = 6405 getTargetData()->getABITypeAlignment(ArgTy); 6406 6407 if (Args[i].isZExt) 6408 Flags.setZExt(); 6409 if (Args[i].isSExt) 6410 Flags.setSExt(); 6411 if (Args[i].isInReg) 6412 Flags.setInReg(); 6413 if (Args[i].isSRet) 6414 Flags.setSRet(); 6415 if (Args[i].isByVal) { 6416 Flags.setByVal(); 6417 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6418 Type *ElementTy = Ty->getElementType(); 6419 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6420 // For ByVal, alignment should come from FE. BE will guess if this 6421 // info is not there but there are cases it cannot get right. 6422 unsigned FrameAlign; 6423 if (Args[i].Alignment) 6424 FrameAlign = Args[i].Alignment; 6425 else 6426 FrameAlign = getByValTypeAlignment(ElementTy); 6427 Flags.setByValAlign(FrameAlign); 6428 } 6429 if (Args[i].isNest) 6430 Flags.setNest(); 6431 Flags.setOrigAlign(OriginalAlignment); 6432 6433 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6434 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6435 SmallVector<SDValue, 4> Parts(NumParts); 6436 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6437 6438 if (Args[i].isSExt) 6439 ExtendKind = ISD::SIGN_EXTEND; 6440 else if (Args[i].isZExt) 6441 ExtendKind = ISD::ZERO_EXTEND; 6442 6443 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6444 PartVT, ExtendKind); 6445 6446 for (unsigned j = 0; j != NumParts; ++j) { 6447 // if it isn't first piece, alignment must be 1 6448 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6449 i < CLI.NumFixedArgs); 6450 if (NumParts > 1 && j == 0) 6451 MyFlags.Flags.setSplit(); 6452 else if (j != 0) 6453 MyFlags.Flags.setOrigAlign(1); 6454 6455 CLI.Outs.push_back(MyFlags); 6456 CLI.OutVals.push_back(Parts[j]); 6457 } 6458 } 6459 } 6460 6461 // Handle the incoming return values from the call. 6462 CLI.Ins.clear(); 6463 SmallVector<EVT, 4> RetTys; 6464 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6465 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6466 EVT VT = RetTys[I]; 6467 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6468 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6469 for (unsigned i = 0; i != NumRegs; ++i) { 6470 ISD::InputArg MyFlags; 6471 MyFlags.VT = RegisterVT.getSimpleVT(); 6472 MyFlags.Used = CLI.IsReturnValueUsed; 6473 if (CLI.RetSExt) 6474 MyFlags.Flags.setSExt(); 6475 if (CLI.RetZExt) 6476 MyFlags.Flags.setZExt(); 6477 if (CLI.IsInReg) 6478 MyFlags.Flags.setInReg(); 6479 CLI.Ins.push_back(MyFlags); 6480 } 6481 } 6482 6483 SmallVector<SDValue, 4> InVals; 6484 CLI.Chain = LowerCall(CLI, InVals); 6485 6486 // Verify that the target's LowerCall behaved as expected. 6487 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6488 "LowerCall didn't return a valid chain!"); 6489 assert((!CLI.IsTailCall || InVals.empty()) && 6490 "LowerCall emitted a return value for a tail call!"); 6491 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6492 "LowerCall didn't emit the correct number of values!"); 6493 6494 // For a tail call, the return value is merely live-out and there aren't 6495 // any nodes in the DAG representing it. Return a special value to 6496 // indicate that a tail call has been emitted and no more Instructions 6497 // should be processed in the current block. 6498 if (CLI.IsTailCall) { 6499 CLI.DAG.setRoot(CLI.Chain); 6500 return std::make_pair(SDValue(), SDValue()); 6501 } 6502 6503 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6504 assert(InVals[i].getNode() && 6505 "LowerCall emitted a null value!"); 6506 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6507 "LowerCall emitted a value with the wrong type!"); 6508 }); 6509 6510 // Collect the legal value parts into potentially illegal values 6511 // that correspond to the original function's return values. 6512 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6513 if (CLI.RetSExt) 6514 AssertOp = ISD::AssertSext; 6515 else if (CLI.RetZExt) 6516 AssertOp = ISD::AssertZext; 6517 SmallVector<SDValue, 4> ReturnValues; 6518 unsigned CurReg = 0; 6519 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6520 EVT VT = RetTys[I]; 6521 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6522 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6523 6524 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6525 NumRegs, RegisterVT, VT, 6526 AssertOp)); 6527 CurReg += NumRegs; 6528 } 6529 6530 // For a function returning void, there is no return value. We can't create 6531 // such a node, so we just return a null return value in that case. In 6532 // that case, nothing will actually look at the value. 6533 if (ReturnValues.empty()) 6534 return std::make_pair(SDValue(), CLI.Chain); 6535 6536 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6537 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6538 &ReturnValues[0], ReturnValues.size()); 6539 return std::make_pair(Res, CLI.Chain); 6540} 6541 6542void TargetLowering::LowerOperationWrapper(SDNode *N, 6543 SmallVectorImpl<SDValue> &Results, 6544 SelectionDAG &DAG) const { 6545 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6546 if (Res.getNode()) 6547 Results.push_back(Res); 6548} 6549 6550SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6551 llvm_unreachable("LowerOperation not implemented for this target!"); 6552} 6553 6554void 6555SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6556 SDValue Op = getNonRegisterValue(V); 6557 assert((Op.getOpcode() != ISD::CopyFromReg || 6558 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6559 "Copy from a reg to the same reg!"); 6560 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6561 6562 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6563 SDValue Chain = DAG.getEntryNode(); 6564 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6565 PendingExports.push_back(Chain); 6566} 6567 6568#include "llvm/CodeGen/SelectionDAGISel.h" 6569 6570/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6571/// entry block, return true. This includes arguments used by switches, since 6572/// the switch may expand into multiple basic blocks. 6573static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6574 // With FastISel active, we may be splitting blocks, so force creation 6575 // of virtual registers for all non-dead arguments. 6576 if (FastISel) 6577 return A->use_empty(); 6578 6579 const BasicBlock *Entry = A->getParent()->begin(); 6580 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6581 UI != E; ++UI) { 6582 const User *U = *UI; 6583 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6584 return false; // Use not in entry block. 6585 } 6586 return true; 6587} 6588 6589void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6590 // If this is the entry block, emit arguments. 6591 const Function &F = *LLVMBB->getParent(); 6592 SelectionDAG &DAG = SDB->DAG; 6593 DebugLoc dl = SDB->getCurDebugLoc(); 6594 const TargetData *TD = TLI.getTargetData(); 6595 SmallVector<ISD::InputArg, 16> Ins; 6596 6597 // Check whether the function can return without sret-demotion. 6598 SmallVector<ISD::OutputArg, 4> Outs; 6599 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6600 Outs, TLI); 6601 6602 if (!FuncInfo->CanLowerReturn) { 6603 // Put in an sret pointer parameter before all the other parameters. 6604 SmallVector<EVT, 1> ValueVTs; 6605 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6606 6607 // NOTE: Assuming that a pointer will never break down to more than one VT 6608 // or one register. 6609 ISD::ArgFlagsTy Flags; 6610 Flags.setSRet(); 6611 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6612 ISD::InputArg RetArg(Flags, RegisterVT, true); 6613 Ins.push_back(RetArg); 6614 } 6615 6616 // Set up the incoming argument description vector. 6617 unsigned Idx = 1; 6618 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6619 I != E; ++I, ++Idx) { 6620 SmallVector<EVT, 4> ValueVTs; 6621 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6622 bool isArgValueUsed = !I->use_empty(); 6623 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6624 Value != NumValues; ++Value) { 6625 EVT VT = ValueVTs[Value]; 6626 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6627 ISD::ArgFlagsTy Flags; 6628 unsigned OriginalAlignment = 6629 TD->getABITypeAlignment(ArgTy); 6630 6631 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6632 Flags.setZExt(); 6633 if (F.paramHasAttr(Idx, Attribute::SExt)) 6634 Flags.setSExt(); 6635 if (F.paramHasAttr(Idx, Attribute::InReg)) 6636 Flags.setInReg(); 6637 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6638 Flags.setSRet(); 6639 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6640 Flags.setByVal(); 6641 PointerType *Ty = cast<PointerType>(I->getType()); 6642 Type *ElementTy = Ty->getElementType(); 6643 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6644 // For ByVal, alignment should be passed from FE. BE will guess if 6645 // this info is not there but there are cases it cannot get right. 6646 unsigned FrameAlign; 6647 if (F.getParamAlignment(Idx)) 6648 FrameAlign = F.getParamAlignment(Idx); 6649 else 6650 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6651 Flags.setByValAlign(FrameAlign); 6652 } 6653 if (F.paramHasAttr(Idx, Attribute::Nest)) 6654 Flags.setNest(); 6655 Flags.setOrigAlign(OriginalAlignment); 6656 6657 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6658 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6659 for (unsigned i = 0; i != NumRegs; ++i) { 6660 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6661 if (NumRegs > 1 && i == 0) 6662 MyFlags.Flags.setSplit(); 6663 // if it isn't first piece, alignment must be 1 6664 else if (i > 0) 6665 MyFlags.Flags.setOrigAlign(1); 6666 Ins.push_back(MyFlags); 6667 } 6668 } 6669 } 6670 6671 // Call the target to set up the argument values. 6672 SmallVector<SDValue, 8> InVals; 6673 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6674 F.isVarArg(), Ins, 6675 dl, DAG, InVals); 6676 6677 // Verify that the target's LowerFormalArguments behaved as expected. 6678 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6679 "LowerFormalArguments didn't return a valid chain!"); 6680 assert(InVals.size() == Ins.size() && 6681 "LowerFormalArguments didn't emit the correct number of values!"); 6682 DEBUG({ 6683 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6684 assert(InVals[i].getNode() && 6685 "LowerFormalArguments emitted a null value!"); 6686 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6687 "LowerFormalArguments emitted a value with the wrong type!"); 6688 } 6689 }); 6690 6691 // Update the DAG with the new chain value resulting from argument lowering. 6692 DAG.setRoot(NewRoot); 6693 6694 // Set up the argument values. 6695 unsigned i = 0; 6696 Idx = 1; 6697 if (!FuncInfo->CanLowerReturn) { 6698 // Create a virtual register for the sret pointer, and put in a copy 6699 // from the sret argument into it. 6700 SmallVector<EVT, 1> ValueVTs; 6701 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6702 EVT VT = ValueVTs[0]; 6703 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6704 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6705 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6706 RegVT, VT, AssertOp); 6707 6708 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6709 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6710 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6711 FuncInfo->DemoteRegister = SRetReg; 6712 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6713 SRetReg, ArgValue); 6714 DAG.setRoot(NewRoot); 6715 6716 // i indexes lowered arguments. Bump it past the hidden sret argument. 6717 // Idx indexes LLVM arguments. Don't touch it. 6718 ++i; 6719 } 6720 6721 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6722 ++I, ++Idx) { 6723 SmallVector<SDValue, 4> ArgValues; 6724 SmallVector<EVT, 4> ValueVTs; 6725 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6726 unsigned NumValues = ValueVTs.size(); 6727 6728 // If this argument is unused then remember its value. It is used to generate 6729 // debugging information. 6730 if (I->use_empty() && NumValues) 6731 SDB->setUnusedArgValue(I, InVals[i]); 6732 6733 for (unsigned Val = 0; Val != NumValues; ++Val) { 6734 EVT VT = ValueVTs[Val]; 6735 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6736 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6737 6738 if (!I->use_empty()) { 6739 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6740 if (F.paramHasAttr(Idx, Attribute::SExt)) 6741 AssertOp = ISD::AssertSext; 6742 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6743 AssertOp = ISD::AssertZext; 6744 6745 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6746 NumParts, PartVT, VT, 6747 AssertOp)); 6748 } 6749 6750 i += NumParts; 6751 } 6752 6753 // We don't need to do anything else for unused arguments. 6754 if (ArgValues.empty()) 6755 continue; 6756 6757 // Note down frame index. 6758 if (FrameIndexSDNode *FI = 6759 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6760 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6761 6762 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6763 SDB->getCurDebugLoc()); 6764 6765 SDB->setValue(I, Res); 6766 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6767 if (LoadSDNode *LNode = 6768 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6769 if (FrameIndexSDNode *FI = 6770 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6771 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6772 } 6773 6774 // If this argument is live outside of the entry block, insert a copy from 6775 // wherever we got it to the vreg that other BB's will reference it as. 6776 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6777 // If we can, though, try to skip creating an unnecessary vreg. 6778 // FIXME: This isn't very clean... it would be nice to make this more 6779 // general. It's also subtly incompatible with the hacks FastISel 6780 // uses with vregs. 6781 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6782 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6783 FuncInfo->ValueMap[I] = Reg; 6784 continue; 6785 } 6786 } 6787 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6788 FuncInfo->InitializeRegForValue(I); 6789 SDB->CopyToExportRegsIfNeeded(I); 6790 } 6791 } 6792 6793 assert(i == InVals.size() && "Argument register count mismatch!"); 6794 6795 // Finally, if the target has anything special to do, allow it to do so. 6796 // FIXME: this should insert code into the DAG! 6797 EmitFunctionEntryCode(); 6798} 6799 6800/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6801/// ensure constants are generated when needed. Remember the virtual registers 6802/// that need to be added to the Machine PHI nodes as input. We cannot just 6803/// directly add them, because expansion might result in multiple MBB's for one 6804/// BB. As such, the start of the BB might correspond to a different MBB than 6805/// the end. 6806/// 6807void 6808SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6809 const TerminatorInst *TI = LLVMBB->getTerminator(); 6810 6811 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6812 6813 // Check successor nodes' PHI nodes that expect a constant to be available 6814 // from this block. 6815 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6816 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6817 if (!isa<PHINode>(SuccBB->begin())) continue; 6818 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6819 6820 // If this terminator has multiple identical successors (common for 6821 // switches), only handle each succ once. 6822 if (!SuccsHandled.insert(SuccMBB)) continue; 6823 6824 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6825 6826 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6827 // nodes and Machine PHI nodes, but the incoming operands have not been 6828 // emitted yet. 6829 for (BasicBlock::const_iterator I = SuccBB->begin(); 6830 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6831 // Ignore dead phi's. 6832 if (PN->use_empty()) continue; 6833 6834 // Skip empty types 6835 if (PN->getType()->isEmptyTy()) 6836 continue; 6837 6838 unsigned Reg; 6839 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6840 6841 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6842 unsigned &RegOut = ConstantsOut[C]; 6843 if (RegOut == 0) { 6844 RegOut = FuncInfo.CreateRegs(C->getType()); 6845 CopyValueToVirtualRegister(C, RegOut); 6846 } 6847 Reg = RegOut; 6848 } else { 6849 DenseMap<const Value *, unsigned>::iterator I = 6850 FuncInfo.ValueMap.find(PHIOp); 6851 if (I != FuncInfo.ValueMap.end()) 6852 Reg = I->second; 6853 else { 6854 assert(isa<AllocaInst>(PHIOp) && 6855 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6856 "Didn't codegen value into a register!??"); 6857 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6858 CopyValueToVirtualRegister(PHIOp, Reg); 6859 } 6860 } 6861 6862 // Remember that this register needs to added to the machine PHI node as 6863 // the input for this MBB. 6864 SmallVector<EVT, 4> ValueVTs; 6865 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6866 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6867 EVT VT = ValueVTs[vti]; 6868 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6869 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6870 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6871 Reg += NumRegisters; 6872 } 6873 } 6874 } 6875 ConstantsOut.clear(); 6876} 6877