SelectionDAGBuilder.cpp revision 0dadb15927b912c98918e8a9e7466af77062149f
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/ConstantFolding.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/Module.h" 32#include "llvm/CodeGen/Analysis.h" 33#include "llvm/CodeGen/FastISel.h" 34#include "llvm/CodeGen/FunctionLoweringInfo.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 74 const SDValue *Parts, unsigned NumParts, 75 EVT PartVT, EVT ValueVT); 76 77/// getCopyFromParts - Create a value that contains the specified legal parts 78/// combined into the value they represent. If the parts combine to a type 79/// larger then ValueVT then AssertOp can be used to specify whether the extra 80/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 81/// (ISD::AssertSext). 82static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 83 const SDValue *Parts, 84 unsigned NumParts, EVT PartVT, EVT ValueVT, 85 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 86 if (ValueVT.isVector()) 87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 88 89 assert(NumParts > 0 && "No parts to assemble!"); 90 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 91 SDValue Val = Parts[0]; 92 93 if (NumParts > 1) { 94 // Assemble the value from multiple parts. 95 if (ValueVT.isInteger()) { 96 unsigned PartBits = PartVT.getSizeInBits(); 97 unsigned ValueBits = ValueVT.getSizeInBits(); 98 99 // Assemble the power of 2 part. 100 unsigned RoundParts = NumParts & (NumParts - 1) ? 101 1 << Log2_32(NumParts) : NumParts; 102 unsigned RoundBits = PartBits * RoundParts; 103 EVT RoundVT = RoundBits == ValueBits ? 104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 105 SDValue Lo, Hi; 106 107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 108 109 if (RoundParts > 2) { 110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 111 PartVT, HalfVT); 112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 113 RoundParts / 2, PartVT, HalfVT); 114 } else { 115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); 116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); 117 } 118 119 if (TLI.isBigEndian()) 120 std::swap(Lo, Hi); 121 122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 123 124 if (RoundParts < NumParts) { 125 // Assemble the trailing non-power-of-2 part. 126 unsigned OddParts = NumParts - RoundParts; 127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 128 Hi = getCopyFromParts(DAG, DL, 129 Parts + RoundParts, OddParts, PartVT, OddVT); 130 131 // Combine the round and odd parts. 132 Lo = Val; 133 if (TLI.isBigEndian()) 134 std::swap(Lo, Hi); 135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 138 DAG.getConstant(Lo.getValueType().getSizeInBits(), 139 TLI.getPointerTy())); 140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 142 } 143 } else if (PartVT.isFloatingPoint()) { 144 // FP split into multiple FP parts (for ppcf128) 145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 146 "Unexpected split"); 147 SDValue Lo, Hi; 148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); 149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); 150 if (TLI.isBigEndian()) 151 std::swap(Lo, Hi); 152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 153 } else { 154 // FP split into integer parts (soft fp) 155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 156 !PartVT.isVector() && "Unexpected split"); 157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 159 } 160 } 161 162 // There is now one part, held in Val. Correct it to match ValueVT. 163 PartVT = Val.getValueType(); 164 165 if (PartVT == ValueVT) 166 return Val; 167 168 if (PartVT.isInteger() && ValueVT.isInteger()) { 169 if (ValueVT.bitsLT(PartVT)) { 170 // For a truncate, see if we have any information to 171 // indicate whether the truncated bits will always be 172 // zero or sign-extension. 173 if (AssertOp != ISD::DELETED_NODE) 174 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 175 DAG.getValueType(ValueVT)); 176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 177 } 178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 179 } 180 181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 182 // FP_ROUND's are always exact here. 183 if (ValueVT.bitsLT(Val.getValueType())) 184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 185 DAG.getIntPtrConstant(1)); 186 187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 188 } 189 190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 192 193 llvm_unreachable("Unknown mismatch!"); 194 return SDValue(); 195} 196 197/// getCopyFromParts - Create a value that contains the specified legal parts 198/// combined into the value they represent. If the parts combine to a type 199/// larger then ValueVT then AssertOp can be used to specify whether the extra 200/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 201/// (ISD::AssertSext). 202static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 203 const SDValue *Parts, unsigned NumParts, 204 EVT PartVT, EVT ValueVT) { 205 assert(ValueVT.isVector() && "Not a vector value"); 206 assert(NumParts > 0 && "No parts to assemble!"); 207 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 208 SDValue Val = Parts[0]; 209 210 // Handle a multi-element vector. 211 if (NumParts > 1) { 212 EVT IntermediateVT, RegisterVT; 213 unsigned NumIntermediates; 214 unsigned NumRegs = 215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 216 NumIntermediates, RegisterVT); 217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 218 NumParts = NumRegs; // Silence a compiler warning. 219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 220 assert(RegisterVT == Parts[0].getValueType() && 221 "Part type doesn't match part!"); 222 223 // Assemble the parts into intermediate operands. 224 SmallVector<SDValue, 8> Ops(NumIntermediates); 225 if (NumIntermediates == NumParts) { 226 // If the register was not expanded, truncate or copy the value, 227 // as appropriate. 228 for (unsigned i = 0; i != NumParts; ++i) 229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 230 PartVT, IntermediateVT); 231 } else if (NumParts > 0) { 232 // If the intermediate type was expanded, build the intermediate 233 // operands from the parts. 234 assert(NumParts % NumIntermediates == 0 && 235 "Must expand into a divisible number of parts!"); 236 unsigned Factor = NumParts / NumIntermediates; 237 for (unsigned i = 0; i != NumIntermediates; ++i) 238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 239 PartVT, IntermediateVT); 240 } 241 242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 243 // intermediate operands. 244 Val = DAG.getNode(IntermediateVT.isVector() ? 245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 246 ValueVT, &Ops[0], NumIntermediates); 247 } 248 249 // There is now one part, held in Val. Correct it to match ValueVT. 250 PartVT = Val.getValueType(); 251 252 if (PartVT == ValueVT) 253 return Val; 254 255 if (PartVT.isVector()) { 256 // If the element type of the source/dest vectors are the same, but the 257 // parts vector has more elements than the value vector, then we have a 258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 259 // elements we want. 260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 262 "Cannot narrow, it would be a lossy transformation"); 263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 264 DAG.getIntPtrConstant(0)); 265 } 266 267 // Vector/Vector bitcast. 268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 269 } 270 271 assert(ValueVT.getVectorElementType() == PartVT && 272 ValueVT.getVectorNumElements() == 1 && 273 "Only trivial scalar-to-vector conversions should get here!"); 274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 275} 276 277 278 279 280static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 281 SDValue Val, SDValue *Parts, unsigned NumParts, 282 EVT PartVT); 283 284/// getCopyToParts - Create a series of nodes that contain the specified value 285/// split into legal parts. If the parts contain more bits than Val, then, for 286/// integers, ExtendKind can be used to specify how to generate the extra bits. 287static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 288 SDValue Val, SDValue *Parts, unsigned NumParts, 289 EVT PartVT, 290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 291 EVT ValueVT = Val.getValueType(); 292 293 // Handle the vector case separately. 294 if (ValueVT.isVector()) 295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 296 297 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 298 unsigned PartBits = PartVT.getSizeInBits(); 299 unsigned OrigNumParts = NumParts; 300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 301 302 if (NumParts == 0) 303 return; 304 305 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 306 if (PartVT == ValueVT) { 307 assert(NumParts == 1 && "No-op copy with multiple parts!"); 308 Parts[0] = Val; 309 return; 310 } 311 312 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 313 // If the parts cover more bits than the value has, promote the value. 314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 315 assert(NumParts == 1 && "Do not know what to promote to!"); 316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 317 } else { 318 assert(PartVT.isInteger() && ValueVT.isInteger() && 319 "Unknown mismatch!"); 320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 322 } 323 } else if (PartBits == ValueVT.getSizeInBits()) { 324 // Different types of the same size. 325 assert(NumParts == 1 && PartVT != ValueVT); 326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 328 // If the parts cover less bits than value has, truncate the value. 329 assert(PartVT.isInteger() && ValueVT.isInteger() && 330 "Unknown mismatch!"); 331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 333 } 334 335 // The value may have changed - recompute ValueVT. 336 ValueVT = Val.getValueType(); 337 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 338 "Failed to tile the value with PartVT!"); 339 340 if (NumParts == 1) { 341 assert(PartVT == ValueVT && "Type conversion failed!"); 342 Parts[0] = Val; 343 return; 344 } 345 346 // Expand the value into multiple parts. 347 if (NumParts & (NumParts - 1)) { 348 // The number of parts is not a power of 2. Split off and copy the tail. 349 assert(PartVT.isInteger() && ValueVT.isInteger() && 350 "Do not know what to expand to!"); 351 unsigned RoundParts = 1 << Log2_32(NumParts); 352 unsigned RoundBits = RoundParts * PartBits; 353 unsigned OddParts = NumParts - RoundParts; 354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 355 DAG.getIntPtrConstant(RoundBits)); 356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 357 358 if (TLI.isBigEndian()) 359 // The odd parts were reversed by getCopyToParts - unreverse them. 360 std::reverse(Parts + RoundParts, Parts + NumParts); 361 362 NumParts = RoundParts; 363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 365 } 366 367 // The number of parts is a power of 2. Repeatedly bisect the value using 368 // EXTRACT_ELEMENT. 369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, 370 EVT::getIntegerVT(*DAG.getContext(), 371 ValueVT.getSizeInBits()), 372 Val); 373 374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 375 for (unsigned i = 0; i < NumParts; i += StepSize) { 376 unsigned ThisBits = StepSize * PartBits / 2; 377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 378 SDValue &Part0 = Parts[i]; 379 SDValue &Part1 = Parts[i+StepSize/2]; 380 381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 382 ThisVT, Part0, DAG.getIntPtrConstant(1)); 383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 384 ThisVT, Part0, DAG.getIntPtrConstant(0)); 385 386 if (ThisBits == PartBits && ThisVT != PartVT) { 387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); 388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); 389 } 390 } 391 } 392 393 if (TLI.isBigEndian()) 394 std::reverse(Parts, Parts + OrigNumParts); 395} 396 397 398/// getCopyToPartsVector - Create a series of nodes that contain the specified 399/// value split into legal parts. 400static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 401 SDValue Val, SDValue *Parts, unsigned NumParts, 402 EVT PartVT) { 403 EVT ValueVT = Val.getValueType(); 404 assert(ValueVT.isVector() && "Not a vector"); 405 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 406 407 if (NumParts == 1) { 408 if (PartVT == ValueVT) { 409 // Nothing to do. 410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 411 // Bitconvert vector->vector case. 412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 413 } else if (PartVT.isVector() && 414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 416 EVT ElementVT = PartVT.getVectorElementType(); 417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 418 // undef elements. 419 SmallVector<SDValue, 16> Ops; 420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 422 ElementVT, Val, DAG.getIntPtrConstant(i))); 423 424 for (unsigned i = ValueVT.getVectorNumElements(), 425 e = PartVT.getVectorNumElements(); i != e; ++i) 426 Ops.push_back(DAG.getUNDEF(ElementVT)); 427 428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 429 430 // FIXME: Use CONCAT for 2x -> 4x. 431 432 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 434 } else { 435 // Vector -> scalar conversion. 436 assert(ValueVT.getVectorElementType() == PartVT && 437 ValueVT.getVectorNumElements() == 1 && 438 "Only trivial vector-to-scalar conversions should get here!"); 439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 PartVT, Val, DAG.getIntPtrConstant(0)); 441 } 442 443 Parts[0] = Val; 444 return; 445 } 446 447 // Handle a multi-element vector. 448 EVT IntermediateVT, RegisterVT; 449 unsigned NumIntermediates; 450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 451 IntermediateVT, 452 NumIntermediates, RegisterVT); 453 unsigned NumElements = ValueVT.getVectorNumElements(); 454 455 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 456 NumParts = NumRegs; // Silence a compiler warning. 457 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 458 459 // Split the vector into intermediate operands. 460 SmallVector<SDValue, 8> Ops(NumIntermediates); 461 for (unsigned i = 0; i != NumIntermediates; ++i) { 462 if (IntermediateVT.isVector()) 463 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 464 IntermediateVT, Val, 465 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 466 else 467 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 468 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 469 } 470 471 // Split the intermediate operands into legal parts. 472 if (NumParts == NumIntermediates) { 473 // If the register was not expanded, promote or copy the value, 474 // as appropriate. 475 for (unsigned i = 0; i != NumParts; ++i) 476 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 477 } else if (NumParts > 0) { 478 // If the intermediate type was expanded, split each the value into 479 // legal parts. 480 assert(NumParts % NumIntermediates == 0 && 481 "Must expand into a divisible number of parts!"); 482 unsigned Factor = NumParts / NumIntermediates; 483 for (unsigned i = 0; i != NumIntermediates; ++i) 484 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 485 } 486} 487 488 489 490 491namespace { 492 /// RegsForValue - This struct represents the registers (physical or virtual) 493 /// that a particular set of values is assigned, and the type information 494 /// about the value. The most common situation is to represent one value at a 495 /// time, but struct or array values are handled element-wise as multiple 496 /// values. The splitting of aggregates is performed recursively, so that we 497 /// never have aggregate-typed registers. The values at this point do not 498 /// necessarily have legal types, so each value may require one or more 499 /// registers of some legal type. 500 /// 501 struct RegsForValue { 502 /// ValueVTs - The value types of the values, which may not be legal, and 503 /// may need be promoted or synthesized from one or more registers. 504 /// 505 SmallVector<EVT, 4> ValueVTs; 506 507 /// RegVTs - The value types of the registers. This is the same size as 508 /// ValueVTs and it records, for each value, what the type of the assigned 509 /// register or registers are. (Individual values are never synthesized 510 /// from more than one type of register.) 511 /// 512 /// With virtual registers, the contents of RegVTs is redundant with TLI's 513 /// getRegisterType member function, however when with physical registers 514 /// it is necessary to have a separate record of the types. 515 /// 516 SmallVector<EVT, 4> RegVTs; 517 518 /// Regs - This list holds the registers assigned to the values. 519 /// Each legal or promoted value requires one register, and each 520 /// expanded value requires multiple registers. 521 /// 522 SmallVector<unsigned, 4> Regs; 523 524 RegsForValue() {} 525 526 RegsForValue(const SmallVector<unsigned, 4> ®s, 527 EVT regvt, EVT valuevt) 528 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 529 530 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 531 unsigned Reg, const Type *Ty) { 532 ComputeValueVTs(tli, Ty, ValueVTs); 533 534 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 535 EVT ValueVT = ValueVTs[Value]; 536 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 537 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 538 for (unsigned i = 0; i != NumRegs; ++i) 539 Regs.push_back(Reg + i); 540 RegVTs.push_back(RegisterVT); 541 Reg += NumRegs; 542 } 543 } 544 545 /// areValueTypesLegal - Return true if types of all the values are legal. 546 bool areValueTypesLegal(const TargetLowering &TLI) { 547 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 548 EVT RegisterVT = RegVTs[Value]; 549 if (!TLI.isTypeLegal(RegisterVT)) 550 return false; 551 } 552 return true; 553 } 554 555 /// append - Add the specified values to this one. 556 void append(const RegsForValue &RHS) { 557 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 558 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 559 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 560 } 561 562 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 563 /// this value and returns the result as a ValueVTs value. This uses 564 /// Chain/Flag as the input and updates them for the output Chain/Flag. 565 /// If the Flag pointer is NULL, no flag is used. 566 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 567 DebugLoc dl, 568 SDValue &Chain, SDValue *Flag) const; 569 570 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 571 /// specified value into the registers specified by this object. This uses 572 /// Chain/Flag as the input and updates them for the output Chain/Flag. 573 /// If the Flag pointer is NULL, no flag is used. 574 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 575 SDValue &Chain, SDValue *Flag) const; 576 577 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 578 /// operand list. This adds the code marker, matching input operand index 579 /// (if applicable), and includes the number of values added into it. 580 void AddInlineAsmOperands(unsigned Kind, 581 bool HasMatching, unsigned MatchingIdx, 582 SelectionDAG &DAG, 583 std::vector<SDValue> &Ops) const; 584 }; 585} 586 587/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 588/// this value and returns the result as a ValueVT value. This uses 589/// Chain/Flag as the input and updates them for the output Chain/Flag. 590/// If the Flag pointer is NULL, no flag is used. 591SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 592 FunctionLoweringInfo &FuncInfo, 593 DebugLoc dl, 594 SDValue &Chain, SDValue *Flag) const { 595 // A Value with type {} or [0 x %t] needs no registers. 596 if (ValueVTs.empty()) 597 return SDValue(); 598 599 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 600 601 // Assemble the legal parts into the final values. 602 SmallVector<SDValue, 4> Values(ValueVTs.size()); 603 SmallVector<SDValue, 8> Parts; 604 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 605 // Copy the legal parts from the registers. 606 EVT ValueVT = ValueVTs[Value]; 607 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 608 EVT RegisterVT = RegVTs[Value]; 609 610 Parts.resize(NumRegs); 611 for (unsigned i = 0; i != NumRegs; ++i) { 612 SDValue P; 613 if (Flag == 0) { 614 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 615 } else { 616 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 617 *Flag = P.getValue(2); 618 } 619 620 Chain = P.getValue(1); 621 622 // If the source register was virtual and if we know something about it, 623 // add an assert node. 624 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 625 RegisterVT.isInteger() && !RegisterVT.isVector()) { 626 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 627 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 628 const FunctionLoweringInfo::LiveOutInfo &LOI = 629 FuncInfo.LiveOutRegInfo[SlotNo]; 630 631 unsigned RegSize = RegisterVT.getSizeInBits(); 632 unsigned NumSignBits = LOI.NumSignBits; 633 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 634 635 // FIXME: We capture more information than the dag can represent. For 636 // now, just use the tightest assertzext/assertsext possible. 637 bool isSExt = true; 638 EVT FromVT(MVT::Other); 639 if (NumSignBits == RegSize) 640 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 641 else if (NumZeroBits >= RegSize-1) 642 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 643 else if (NumSignBits > RegSize-8) 644 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 645 else if (NumZeroBits >= RegSize-8) 646 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 647 else if (NumSignBits > RegSize-16) 648 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 649 else if (NumZeroBits >= RegSize-16) 650 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 651 else if (NumSignBits > RegSize-32) 652 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 653 else if (NumZeroBits >= RegSize-32) 654 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 655 656 if (FromVT != MVT::Other) 657 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 658 RegisterVT, P, DAG.getValueType(FromVT)); 659 } 660 } 661 662 Parts[i] = P; 663 } 664 665 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 666 NumRegs, RegisterVT, ValueVT); 667 Part += NumRegs; 668 Parts.clear(); 669 } 670 671 return DAG.getNode(ISD::MERGE_VALUES, dl, 672 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 673 &Values[0], ValueVTs.size()); 674} 675 676/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 677/// specified value into the registers specified by this object. This uses 678/// Chain/Flag as the input and updates them for the output Chain/Flag. 679/// If the Flag pointer is NULL, no flag is used. 680void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 681 SDValue &Chain, SDValue *Flag) const { 682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 683 684 // Get the list of the values's legal parts. 685 unsigned NumRegs = Regs.size(); 686 SmallVector<SDValue, 8> Parts(NumRegs); 687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 EVT RegisterVT = RegVTs[Value]; 691 692 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 693 &Parts[Part], NumParts, RegisterVT); 694 Part += NumParts; 695 } 696 697 // Copy the parts into the registers. 698 SmallVector<SDValue, 8> Chains(NumRegs); 699 for (unsigned i = 0; i != NumRegs; ++i) { 700 SDValue Part; 701 if (Flag == 0) { 702 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 703 } else { 704 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 705 *Flag = Part.getValue(1); 706 } 707 708 Chains[i] = Part.getValue(0); 709 } 710 711 if (NumRegs == 1 || Flag) 712 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 713 // flagged to it. That is the CopyToReg nodes and the user are considered 714 // a single scheduling unit. If we create a TokenFactor and return it as 715 // chain, then the TokenFactor is both a predecessor (operand) of the 716 // user as well as a successor (the TF operands are flagged to the user). 717 // c1, f1 = CopyToReg 718 // c2, f2 = CopyToReg 719 // c3 = TokenFactor c1, c2 720 // ... 721 // = op c3, ..., f2 722 Chain = Chains[NumRegs-1]; 723 else 724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 725} 726 727/// AddInlineAsmOperands - Add this value to the specified inlineasm node 728/// operand list. This adds the code marker and includes the number of 729/// values added into it. 730void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 731 unsigned MatchingIdx, 732 SelectionDAG &DAG, 733 std::vector<SDValue> &Ops) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 737 if (HasMatching) 738 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 739 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 740 Ops.push_back(Res); 741 742 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 743 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 744 EVT RegisterVT = RegVTs[Value]; 745 for (unsigned i = 0; i != NumRegs; ++i) { 746 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 747 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 748 } 749 } 750} 751 752void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 753 AA = &aa; 754 GFI = gfi; 755 TD = DAG.getTarget().getTargetData(); 756} 757 758/// clear - Clear out the current SelectionDAG and the associated 759/// state and prepare this SelectionDAGBuilder object to be used 760/// for a new block. This doesn't clear out information about 761/// additional blocks that are needed to complete switch lowering 762/// or PHI node updating; that information is cleared out as it is 763/// consumed. 764void SelectionDAGBuilder::clear() { 765 NodeMap.clear(); 766 UnusedArgNodeMap.clear(); 767 PendingLoads.clear(); 768 PendingExports.clear(); 769 DanglingDebugInfoMap.clear(); 770 CurDebugLoc = DebugLoc(); 771 HasTailCall = false; 772} 773 774/// getRoot - Return the current virtual root of the Selection DAG, 775/// flushing any PendingLoad items. This must be done before emitting 776/// a store or any other node that may need to be ordered after any 777/// prior load instructions. 778/// 779SDValue SelectionDAGBuilder::getRoot() { 780 if (PendingLoads.empty()) 781 return DAG.getRoot(); 782 783 if (PendingLoads.size() == 1) { 784 SDValue Root = PendingLoads[0]; 785 DAG.setRoot(Root); 786 PendingLoads.clear(); 787 return Root; 788 } 789 790 // Otherwise, we have to make a token factor node. 791 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 792 &PendingLoads[0], PendingLoads.size()); 793 PendingLoads.clear(); 794 DAG.setRoot(Root); 795 return Root; 796} 797 798/// getControlRoot - Similar to getRoot, but instead of flushing all the 799/// PendingLoad items, flush all the PendingExports items. It is necessary 800/// to do this before emitting a terminator instruction. 801/// 802SDValue SelectionDAGBuilder::getControlRoot() { 803 SDValue Root = DAG.getRoot(); 804 805 if (PendingExports.empty()) 806 return Root; 807 808 // Turn all of the CopyToReg chains into one factored node. 809 if (Root.getOpcode() != ISD::EntryToken) { 810 unsigned i = 0, e = PendingExports.size(); 811 for (; i != e; ++i) { 812 assert(PendingExports[i].getNode()->getNumOperands() > 1); 813 if (PendingExports[i].getNode()->getOperand(0) == Root) 814 break; // Don't add the root if we already indirectly depend on it. 815 } 816 817 if (i == e) 818 PendingExports.push_back(Root); 819 } 820 821 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 822 &PendingExports[0], 823 PendingExports.size()); 824 PendingExports.clear(); 825 DAG.setRoot(Root); 826 return Root; 827} 828 829void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 830 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 831 DAG.AssignOrdering(Node, SDNodeOrder); 832 833 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 834 AssignOrderingToNode(Node->getOperand(I).getNode()); 835} 836 837void SelectionDAGBuilder::visit(const Instruction &I) { 838 // Set up outgoing PHI node register values before emitting the terminator. 839 if (isa<TerminatorInst>(&I)) 840 HandlePHINodesInSuccessorBlocks(I.getParent()); 841 842 CurDebugLoc = I.getDebugLoc(); 843 844 visit(I.getOpcode(), I); 845 846 if (!isa<TerminatorInst>(&I) && !HasTailCall) 847 CopyToExportRegsIfNeeded(&I); 848 849 CurDebugLoc = DebugLoc(); 850} 851 852void SelectionDAGBuilder::visitPHI(const PHINode &) { 853 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 854} 855 856void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 857 // Note: this doesn't use InstVisitor, because it has to work with 858 // ConstantExpr's in addition to instructions. 859 switch (Opcode) { 860 default: llvm_unreachable("Unknown instruction type encountered!"); 861 // Build the switch statement using the Instruction.def file. 862#define HANDLE_INST(NUM, OPCODE, CLASS) \ 863 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 864#include "llvm/Instruction.def" 865 } 866 867 // Assign the ordering to the freshly created DAG nodes. 868 if (NodeMap.count(&I)) { 869 ++SDNodeOrder; 870 AssignOrderingToNode(getValue(&I).getNode()); 871 } 872} 873 874// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 875// generate the debug data structures now that we've seen its definition. 876void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 877 SDValue Val) { 878 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 879 if (DDI.getDI()) { 880 const DbgValueInst *DI = DDI.getDI(); 881 DebugLoc dl = DDI.getdl(); 882 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 883 MDNode *Variable = DI->getVariable(); 884 uint64_t Offset = DI->getOffset(); 885 SDDbgValue *SDV; 886 if (Val.getNode()) { 887 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 888 SDV = DAG.getDbgValue(Variable, Val.getNode(), 889 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 890 DAG.AddDbgValue(SDV, Val.getNode(), false); 891 } 892 } else { 893 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 894 Offset, dl, SDNodeOrder); 895 DAG.AddDbgValue(SDV, 0, false); 896 } 897 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 898 } 899} 900 901// getValue - Return an SDValue for the given Value. 902SDValue SelectionDAGBuilder::getValue(const Value *V) { 903 // If we already have an SDValue for this value, use it. It's important 904 // to do this first, so that we don't create a CopyFromReg if we already 905 // have a regular SDValue. 906 SDValue &N = NodeMap[V]; 907 if (N.getNode()) return N; 908 909 // If there's a virtual register allocated and initialized for this 910 // value, use it. 911 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 912 if (It != FuncInfo.ValueMap.end()) { 913 unsigned InReg = It->second; 914 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 915 SDValue Chain = DAG.getEntryNode(); 916 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 917 } 918 919 // Otherwise create a new SDValue and remember it. 920 SDValue Val = getValueImpl(V); 921 NodeMap[V] = Val; 922 resolveDanglingDebugInfo(V, Val); 923 return Val; 924} 925 926/// getNonRegisterValue - Return an SDValue for the given Value, but 927/// don't look in FuncInfo.ValueMap for a virtual register. 928SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 929 // If we already have an SDValue for this value, use it. 930 SDValue &N = NodeMap[V]; 931 if (N.getNode()) return N; 932 933 // Otherwise create a new SDValue and remember it. 934 SDValue Val = getValueImpl(V); 935 NodeMap[V] = Val; 936 resolveDanglingDebugInfo(V, Val); 937 return Val; 938} 939 940/// getValueImpl - Helper function for getValue and getNonRegisterValue. 941/// Create an SDValue for the given value. 942SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 943 if (const Constant *C = dyn_cast<Constant>(V)) { 944 EVT VT = TLI.getValueType(V->getType(), true); 945 946 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 947 return DAG.getConstant(*CI, VT); 948 949 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 950 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 951 952 if (isa<ConstantPointerNull>(C)) 953 return DAG.getConstant(0, TLI.getPointerTy()); 954 955 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 956 return DAG.getConstantFP(*CFP, VT); 957 958 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 959 return DAG.getUNDEF(VT); 960 961 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 962 visit(CE->getOpcode(), *CE); 963 SDValue N1 = NodeMap[V]; 964 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 965 return N1; 966 } 967 968 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 969 SmallVector<SDValue, 4> Constants; 970 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 971 OI != OE; ++OI) { 972 SDNode *Val = getValue(*OI).getNode(); 973 // If the operand is an empty aggregate, there are no values. 974 if (!Val) continue; 975 // Add each leaf value from the operand to the Constants list 976 // to form a flattened list of all the values. 977 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 978 Constants.push_back(SDValue(Val, i)); 979 } 980 981 return DAG.getMergeValues(&Constants[0], Constants.size(), 982 getCurDebugLoc()); 983 } 984 985 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 986 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 987 "Unknown struct or array constant!"); 988 989 SmallVector<EVT, 4> ValueVTs; 990 ComputeValueVTs(TLI, C->getType(), ValueVTs); 991 unsigned NumElts = ValueVTs.size(); 992 if (NumElts == 0) 993 return SDValue(); // empty struct 994 SmallVector<SDValue, 4> Constants(NumElts); 995 for (unsigned i = 0; i != NumElts; ++i) { 996 EVT EltVT = ValueVTs[i]; 997 if (isa<UndefValue>(C)) 998 Constants[i] = DAG.getUNDEF(EltVT); 999 else if (EltVT.isFloatingPoint()) 1000 Constants[i] = DAG.getConstantFP(0, EltVT); 1001 else 1002 Constants[i] = DAG.getConstant(0, EltVT); 1003 } 1004 1005 return DAG.getMergeValues(&Constants[0], NumElts, 1006 getCurDebugLoc()); 1007 } 1008 1009 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1010 return DAG.getBlockAddress(BA, VT); 1011 1012 const VectorType *VecTy = cast<VectorType>(V->getType()); 1013 unsigned NumElements = VecTy->getNumElements(); 1014 1015 // Now that we know the number and type of the elements, get that number of 1016 // elements into the Ops array based on what kind of constant it is. 1017 SmallVector<SDValue, 16> Ops; 1018 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1019 for (unsigned i = 0; i != NumElements; ++i) 1020 Ops.push_back(getValue(CP->getOperand(i))); 1021 } else { 1022 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1023 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1024 1025 SDValue Op; 1026 if (EltVT.isFloatingPoint()) 1027 Op = DAG.getConstantFP(0, EltVT); 1028 else 1029 Op = DAG.getConstant(0, EltVT); 1030 Ops.assign(NumElements, Op); 1031 } 1032 1033 // Create a BUILD_VECTOR node. 1034 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1035 VT, &Ops[0], Ops.size()); 1036 } 1037 1038 // If this is a static alloca, generate it as the frameindex instead of 1039 // computation. 1040 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1041 DenseMap<const AllocaInst*, int>::iterator SI = 1042 FuncInfo.StaticAllocaMap.find(AI); 1043 if (SI != FuncInfo.StaticAllocaMap.end()) 1044 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1045 } 1046 1047 // If this is an instruction which fast-isel has deferred, select it now. 1048 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1049 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1050 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1051 SDValue Chain = DAG.getEntryNode(); 1052 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1053 } 1054 1055 llvm_unreachable("Can't get register for value!"); 1056 return SDValue(); 1057} 1058 1059void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1060 SDValue Chain = getControlRoot(); 1061 SmallVector<ISD::OutputArg, 8> Outs; 1062 SmallVector<SDValue, 8> OutVals; 1063 1064 if (!FuncInfo.CanLowerReturn) { 1065 unsigned DemoteReg = FuncInfo.DemoteRegister; 1066 const Function *F = I.getParent()->getParent(); 1067 1068 // Emit a store of the return value through the virtual register. 1069 // Leave Outs empty so that LowerReturn won't try to load return 1070 // registers the usual way. 1071 SmallVector<EVT, 1> PtrValueVTs; 1072 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1073 PtrValueVTs); 1074 1075 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1076 SDValue RetOp = getValue(I.getOperand(0)); 1077 1078 SmallVector<EVT, 4> ValueVTs; 1079 SmallVector<uint64_t, 4> Offsets; 1080 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1081 unsigned NumValues = ValueVTs.size(); 1082 1083 SmallVector<SDValue, 4> Chains(NumValues); 1084 for (unsigned i = 0; i != NumValues; ++i) { 1085 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1086 RetPtr.getValueType(), RetPtr, 1087 DAG.getIntPtrConstant(Offsets[i])); 1088 Chains[i] = 1089 DAG.getStore(Chain, getCurDebugLoc(), 1090 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1091 // FIXME: better loc info would be nice. 1092 Add, MachinePointerInfo(), false, false, 0); 1093 } 1094 1095 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1096 MVT::Other, &Chains[0], NumValues); 1097 } else if (I.getNumOperands() != 0) { 1098 SmallVector<EVT, 4> ValueVTs; 1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1100 unsigned NumValues = ValueVTs.size(); 1101 if (NumValues) { 1102 SDValue RetOp = getValue(I.getOperand(0)); 1103 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1104 EVT VT = ValueVTs[j]; 1105 1106 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1107 1108 const Function *F = I.getParent()->getParent(); 1109 if (F->paramHasAttr(0, Attribute::SExt)) 1110 ExtendKind = ISD::SIGN_EXTEND; 1111 else if (F->paramHasAttr(0, Attribute::ZExt)) 1112 ExtendKind = ISD::ZERO_EXTEND; 1113 1114 // FIXME: C calling convention requires the return type to be promoted 1115 // to at least 32-bit. But this is not necessary for non-C calling 1116 // conventions. The frontend should mark functions whose return values 1117 // require promoting with signext or zeroext attributes. 1118 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1119 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1120 if (VT.bitsLT(MinVT)) 1121 VT = MinVT; 1122 } 1123 1124 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1125 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1126 SmallVector<SDValue, 4> Parts(NumParts); 1127 getCopyToParts(DAG, getCurDebugLoc(), 1128 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1129 &Parts[0], NumParts, PartVT, ExtendKind); 1130 1131 // 'inreg' on function refers to return value 1132 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1133 if (F->paramHasAttr(0, Attribute::InReg)) 1134 Flags.setInReg(); 1135 1136 // Propagate extension type if any 1137 if (F->paramHasAttr(0, Attribute::SExt)) 1138 Flags.setSExt(); 1139 else if (F->paramHasAttr(0, Attribute::ZExt)) 1140 Flags.setZExt(); 1141 1142 for (unsigned i = 0; i < NumParts; ++i) { 1143 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1144 /*isfixed=*/true)); 1145 OutVals.push_back(Parts[i]); 1146 } 1147 } 1148 } 1149 } 1150 1151 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1152 CallingConv::ID CallConv = 1153 DAG.getMachineFunction().getFunction()->getCallingConv(); 1154 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1155 Outs, OutVals, getCurDebugLoc(), DAG); 1156 1157 // Verify that the target's LowerReturn behaved as expected. 1158 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1159 "LowerReturn didn't return a valid chain!"); 1160 1161 // Update the DAG with the new chain value resulting from return lowering. 1162 DAG.setRoot(Chain); 1163} 1164 1165/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1166/// created for it, emit nodes to copy the value into the virtual 1167/// registers. 1168void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1169 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1170 if (VMI != FuncInfo.ValueMap.end()) { 1171 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1172 CopyValueToVirtualRegister(V, VMI->second); 1173 } 1174} 1175 1176/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1177/// the current basic block, add it to ValueMap now so that we'll get a 1178/// CopyTo/FromReg. 1179void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1180 // No need to export constants. 1181 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1182 1183 // Already exported? 1184 if (FuncInfo.isExportedInst(V)) return; 1185 1186 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1187 CopyValueToVirtualRegister(V, Reg); 1188} 1189 1190bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1191 const BasicBlock *FromBB) { 1192 // The operands of the setcc have to be in this block. We don't know 1193 // how to export them from some other block. 1194 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1195 // Can export from current BB. 1196 if (VI->getParent() == FromBB) 1197 return true; 1198 1199 // Is already exported, noop. 1200 return FuncInfo.isExportedInst(V); 1201 } 1202 1203 // If this is an argument, we can export it if the BB is the entry block or 1204 // if it is already exported. 1205 if (isa<Argument>(V)) { 1206 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1207 return true; 1208 1209 // Otherwise, can only export this if it is already exported. 1210 return FuncInfo.isExportedInst(V); 1211 } 1212 1213 // Otherwise, constants can always be exported. 1214 return true; 1215} 1216 1217static bool InBlock(const Value *V, const BasicBlock *BB) { 1218 if (const Instruction *I = dyn_cast<Instruction>(V)) 1219 return I->getParent() == BB; 1220 return true; 1221} 1222 1223/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1224/// This function emits a branch and is used at the leaves of an OR or an 1225/// AND operator tree. 1226/// 1227void 1228SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1229 MachineBasicBlock *TBB, 1230 MachineBasicBlock *FBB, 1231 MachineBasicBlock *CurBB, 1232 MachineBasicBlock *SwitchBB) { 1233 const BasicBlock *BB = CurBB->getBasicBlock(); 1234 1235 // If the leaf of the tree is a comparison, merge the condition into 1236 // the caseblock. 1237 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1238 // The operands of the cmp have to be in this block. We don't know 1239 // how to export them from some other block. If this is the first block 1240 // of the sequence, no exporting is needed. 1241 if (CurBB == SwitchBB || 1242 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1243 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1244 ISD::CondCode Condition; 1245 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1246 Condition = getICmpCondCode(IC->getPredicate()); 1247 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1248 Condition = getFCmpCondCode(FC->getPredicate()); 1249 } else { 1250 Condition = ISD::SETEQ; // silence warning. 1251 llvm_unreachable("Unknown compare instruction"); 1252 } 1253 1254 CaseBlock CB(Condition, BOp->getOperand(0), 1255 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1256 SwitchCases.push_back(CB); 1257 return; 1258 } 1259 } 1260 1261 // Create a CaseBlock record representing this branch. 1262 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1263 NULL, TBB, FBB, CurBB); 1264 SwitchCases.push_back(CB); 1265} 1266 1267/// FindMergedConditions - If Cond is an expression like 1268void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1269 MachineBasicBlock *TBB, 1270 MachineBasicBlock *FBB, 1271 MachineBasicBlock *CurBB, 1272 MachineBasicBlock *SwitchBB, 1273 unsigned Opc) { 1274 // If this node is not part of the or/and tree, emit it as a branch. 1275 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1276 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1277 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1278 BOp->getParent() != CurBB->getBasicBlock() || 1279 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1280 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1281 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1282 return; 1283 } 1284 1285 // Create TmpBB after CurBB. 1286 MachineFunction::iterator BBI = CurBB; 1287 MachineFunction &MF = DAG.getMachineFunction(); 1288 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1289 CurBB->getParent()->insert(++BBI, TmpBB); 1290 1291 if (Opc == Instruction::Or) { 1292 // Codegen X | Y as: 1293 // jmp_if_X TBB 1294 // jmp TmpBB 1295 // TmpBB: 1296 // jmp_if_Y TBB 1297 // jmp FBB 1298 // 1299 1300 // Emit the LHS condition. 1301 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1302 1303 // Emit the RHS condition into TmpBB. 1304 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1305 } else { 1306 assert(Opc == Instruction::And && "Unknown merge op!"); 1307 // Codegen X & Y as: 1308 // jmp_if_X TmpBB 1309 // jmp FBB 1310 // TmpBB: 1311 // jmp_if_Y TBB 1312 // jmp FBB 1313 // 1314 // This requires creation of TmpBB after CurBB. 1315 1316 // Emit the LHS condition. 1317 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1318 1319 // Emit the RHS condition into TmpBB. 1320 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1321 } 1322} 1323 1324/// If the set of cases should be emitted as a series of branches, return true. 1325/// If we should emit this as a bunch of and/or'd together conditions, return 1326/// false. 1327bool 1328SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1329 if (Cases.size() != 2) return true; 1330 1331 // If this is two comparisons of the same values or'd or and'd together, they 1332 // will get folded into a single comparison, so don't emit two blocks. 1333 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1334 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1335 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1336 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1337 return false; 1338 } 1339 1340 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1341 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1342 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1343 Cases[0].CC == Cases[1].CC && 1344 isa<Constant>(Cases[0].CmpRHS) && 1345 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1346 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1347 return false; 1348 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1349 return false; 1350 } 1351 1352 return true; 1353} 1354 1355void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1356 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1357 1358 // Update machine-CFG edges. 1359 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1360 1361 // Figure out which block is immediately after the current one. 1362 MachineBasicBlock *NextBlock = 0; 1363 MachineFunction::iterator BBI = BrMBB; 1364 if (++BBI != FuncInfo.MF->end()) 1365 NextBlock = BBI; 1366 1367 if (I.isUnconditional()) { 1368 // Update machine-CFG edges. 1369 BrMBB->addSuccessor(Succ0MBB); 1370 1371 // If this is not a fall-through branch, emit the branch. 1372 if (Succ0MBB != NextBlock) 1373 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1374 MVT::Other, getControlRoot(), 1375 DAG.getBasicBlock(Succ0MBB))); 1376 1377 return; 1378 } 1379 1380 // If this condition is one of the special cases we handle, do special stuff 1381 // now. 1382 const Value *CondVal = I.getCondition(); 1383 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1384 1385 // If this is a series of conditions that are or'd or and'd together, emit 1386 // this as a sequence of branches instead of setcc's with and/or operations. 1387 // For example, instead of something like: 1388 // cmp A, B 1389 // C = seteq 1390 // cmp D, E 1391 // F = setle 1392 // or C, F 1393 // jnz foo 1394 // Emit: 1395 // cmp A, B 1396 // je foo 1397 // cmp D, E 1398 // jle foo 1399 // 1400 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1401 if (BOp->hasOneUse() && 1402 (BOp->getOpcode() == Instruction::And || 1403 BOp->getOpcode() == Instruction::Or)) { 1404 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1405 BOp->getOpcode()); 1406 // If the compares in later blocks need to use values not currently 1407 // exported from this block, export them now. This block should always 1408 // be the first entry. 1409 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1410 1411 // Allow some cases to be rejected. 1412 if (ShouldEmitAsBranches(SwitchCases)) { 1413 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1414 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1415 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1416 } 1417 1418 // Emit the branch for this block. 1419 visitSwitchCase(SwitchCases[0], BrMBB); 1420 SwitchCases.erase(SwitchCases.begin()); 1421 return; 1422 } 1423 1424 // Okay, we decided not to do this, remove any inserted MBB's and clear 1425 // SwitchCases. 1426 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1427 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1428 1429 SwitchCases.clear(); 1430 } 1431 } 1432 1433 // Create a CaseBlock record representing this branch. 1434 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1435 NULL, Succ0MBB, Succ1MBB, BrMBB); 1436 1437 // Use visitSwitchCase to actually insert the fast branch sequence for this 1438 // cond branch. 1439 visitSwitchCase(CB, BrMBB); 1440} 1441 1442/// visitSwitchCase - Emits the necessary code to represent a single node in 1443/// the binary search tree resulting from lowering a switch instruction. 1444void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1445 MachineBasicBlock *SwitchBB) { 1446 SDValue Cond; 1447 SDValue CondLHS = getValue(CB.CmpLHS); 1448 DebugLoc dl = getCurDebugLoc(); 1449 1450 // Build the setcc now. 1451 if (CB.CmpMHS == NULL) { 1452 // Fold "(X == true)" to X and "(X == false)" to !X to 1453 // handle common cases produced by branch lowering. 1454 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1455 CB.CC == ISD::SETEQ) 1456 Cond = CondLHS; 1457 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1458 CB.CC == ISD::SETEQ) { 1459 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1460 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1461 } else 1462 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1463 } else { 1464 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1465 1466 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1467 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1468 1469 SDValue CmpOp = getValue(CB.CmpMHS); 1470 EVT VT = CmpOp.getValueType(); 1471 1472 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1473 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1474 ISD::SETLE); 1475 } else { 1476 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1477 VT, CmpOp, DAG.getConstant(Low, VT)); 1478 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1479 DAG.getConstant(High-Low, VT), ISD::SETULE); 1480 } 1481 } 1482 1483 // Update successor info 1484 SwitchBB->addSuccessor(CB.TrueBB); 1485 SwitchBB->addSuccessor(CB.FalseBB); 1486 1487 // Set NextBlock to be the MBB immediately after the current one, if any. 1488 // This is used to avoid emitting unnecessary branches to the next block. 1489 MachineBasicBlock *NextBlock = 0; 1490 MachineFunction::iterator BBI = SwitchBB; 1491 if (++BBI != FuncInfo.MF->end()) 1492 NextBlock = BBI; 1493 1494 // If the lhs block is the next block, invert the condition so that we can 1495 // fall through to the lhs instead of the rhs block. 1496 if (CB.TrueBB == NextBlock) { 1497 std::swap(CB.TrueBB, CB.FalseBB); 1498 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1499 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1500 } 1501 1502 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1503 MVT::Other, getControlRoot(), Cond, 1504 DAG.getBasicBlock(CB.TrueBB)); 1505 1506 // Insert the false branch. Do this even if it's a fall through branch, 1507 // this makes it easier to do DAG optimizations which require inverting 1508 // the branch condition. 1509 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1510 DAG.getBasicBlock(CB.FalseBB)); 1511 1512 DAG.setRoot(BrCond); 1513} 1514 1515/// visitJumpTable - Emit JumpTable node in the current MBB 1516void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1517 // Emit the code for the jump table 1518 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1519 EVT PTy = TLI.getPointerTy(); 1520 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1521 JT.Reg, PTy); 1522 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1523 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1524 MVT::Other, Index.getValue(1), 1525 Table, Index); 1526 DAG.setRoot(BrJumpTable); 1527} 1528 1529/// visitJumpTableHeader - This function emits necessary code to produce index 1530/// in the JumpTable from switch case. 1531void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1532 JumpTableHeader &JTH, 1533 MachineBasicBlock *SwitchBB) { 1534 // Subtract the lowest switch case value from the value being switched on and 1535 // conditional branch to default mbb if the result is greater than the 1536 // difference between smallest and largest cases. 1537 SDValue SwitchOp = getValue(JTH.SValue); 1538 EVT VT = SwitchOp.getValueType(); 1539 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1540 DAG.getConstant(JTH.First, VT)); 1541 1542 // The SDNode we just created, which holds the value being switched on minus 1543 // the smallest case value, needs to be copied to a virtual register so it 1544 // can be used as an index into the jump table in a subsequent basic block. 1545 // This value may be smaller or larger than the target's pointer type, and 1546 // therefore require extension or truncating. 1547 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1548 1549 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1550 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1551 JumpTableReg, SwitchOp); 1552 JT.Reg = JumpTableReg; 1553 1554 // Emit the range check for the jump table, and branch to the default block 1555 // for the switch statement if the value being switched on exceeds the largest 1556 // case in the switch. 1557 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1558 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1559 DAG.getConstant(JTH.Last-JTH.First,VT), 1560 ISD::SETUGT); 1561 1562 // Set NextBlock to be the MBB immediately after the current one, if any. 1563 // This is used to avoid emitting unnecessary branches to the next block. 1564 MachineBasicBlock *NextBlock = 0; 1565 MachineFunction::iterator BBI = SwitchBB; 1566 1567 if (++BBI != FuncInfo.MF->end()) 1568 NextBlock = BBI; 1569 1570 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1571 MVT::Other, CopyTo, CMP, 1572 DAG.getBasicBlock(JT.Default)); 1573 1574 if (JT.MBB != NextBlock) 1575 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1576 DAG.getBasicBlock(JT.MBB)); 1577 1578 DAG.setRoot(BrCond); 1579} 1580 1581/// visitBitTestHeader - This function emits necessary code to produce value 1582/// suitable for "bit tests" 1583void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1584 MachineBasicBlock *SwitchBB) { 1585 // Subtract the minimum value 1586 SDValue SwitchOp = getValue(B.SValue); 1587 EVT VT = SwitchOp.getValueType(); 1588 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1589 DAG.getConstant(B.First, VT)); 1590 1591 // Check range 1592 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1593 TLI.getSetCCResultType(Sub.getValueType()), 1594 Sub, DAG.getConstant(B.Range, VT), 1595 ISD::SETUGT); 1596 1597 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1598 TLI.getPointerTy()); 1599 1600 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1601 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1602 B.Reg, ShiftOp); 1603 1604 // Set NextBlock to be the MBB immediately after the current one, if any. 1605 // This is used to avoid emitting unnecessary branches to the next block. 1606 MachineBasicBlock *NextBlock = 0; 1607 MachineFunction::iterator BBI = SwitchBB; 1608 if (++BBI != FuncInfo.MF->end()) 1609 NextBlock = BBI; 1610 1611 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1612 1613 SwitchBB->addSuccessor(B.Default); 1614 SwitchBB->addSuccessor(MBB); 1615 1616 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1617 MVT::Other, CopyTo, RangeCmp, 1618 DAG.getBasicBlock(B.Default)); 1619 1620 if (MBB != NextBlock) 1621 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1622 DAG.getBasicBlock(MBB)); 1623 1624 DAG.setRoot(BrRange); 1625} 1626 1627/// visitBitTestCase - this function produces one "bit test" 1628void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1629 unsigned Reg, 1630 BitTestCase &B, 1631 MachineBasicBlock *SwitchBB) { 1632 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1633 TLI.getPointerTy()); 1634 SDValue Cmp; 1635 if (CountPopulation_64(B.Mask) == 1) { 1636 // Testing for a single bit; just compare the shift count with what it 1637 // would need to be to shift a 1 bit in that position. 1638 Cmp = DAG.getSetCC(getCurDebugLoc(), 1639 TLI.getSetCCResultType(ShiftOp.getValueType()), 1640 ShiftOp, 1641 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1642 TLI.getPointerTy()), 1643 ISD::SETEQ); 1644 } else { 1645 // Make desired shift 1646 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1647 TLI.getPointerTy(), 1648 DAG.getConstant(1, TLI.getPointerTy()), 1649 ShiftOp); 1650 1651 // Emit bit tests and jumps 1652 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1653 TLI.getPointerTy(), SwitchVal, 1654 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1655 Cmp = DAG.getSetCC(getCurDebugLoc(), 1656 TLI.getSetCCResultType(AndOp.getValueType()), 1657 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1658 ISD::SETNE); 1659 } 1660 1661 SwitchBB->addSuccessor(B.TargetBB); 1662 SwitchBB->addSuccessor(NextMBB); 1663 1664 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1665 MVT::Other, getControlRoot(), 1666 Cmp, DAG.getBasicBlock(B.TargetBB)); 1667 1668 // Set NextBlock to be the MBB immediately after the current one, if any. 1669 // This is used to avoid emitting unnecessary branches to the next block. 1670 MachineBasicBlock *NextBlock = 0; 1671 MachineFunction::iterator BBI = SwitchBB; 1672 if (++BBI != FuncInfo.MF->end()) 1673 NextBlock = BBI; 1674 1675 if (NextMBB != NextBlock) 1676 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1677 DAG.getBasicBlock(NextMBB)); 1678 1679 DAG.setRoot(BrAnd); 1680} 1681 1682void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1683 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1684 1685 // Retrieve successors. 1686 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1687 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1688 1689 const Value *Callee(I.getCalledValue()); 1690 if (isa<InlineAsm>(Callee)) 1691 visitInlineAsm(&I); 1692 else 1693 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1694 1695 // If the value of the invoke is used outside of its defining block, make it 1696 // available as a virtual register. 1697 CopyToExportRegsIfNeeded(&I); 1698 1699 // Update successor info 1700 InvokeMBB->addSuccessor(Return); 1701 InvokeMBB->addSuccessor(LandingPad); 1702 1703 // Drop into normal successor. 1704 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1705 MVT::Other, getControlRoot(), 1706 DAG.getBasicBlock(Return))); 1707} 1708 1709void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1710} 1711 1712/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1713/// small case ranges). 1714bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1715 CaseRecVector& WorkList, 1716 const Value* SV, 1717 MachineBasicBlock *Default, 1718 MachineBasicBlock *SwitchBB) { 1719 Case& BackCase = *(CR.Range.second-1); 1720 1721 // Size is the number of Cases represented by this range. 1722 size_t Size = CR.Range.second - CR.Range.first; 1723 if (Size > 3) 1724 return false; 1725 1726 // Get the MachineFunction which holds the current MBB. This is used when 1727 // inserting any additional MBBs necessary to represent the switch. 1728 MachineFunction *CurMF = FuncInfo.MF; 1729 1730 // Figure out which block is immediately after the current one. 1731 MachineBasicBlock *NextBlock = 0; 1732 MachineFunction::iterator BBI = CR.CaseBB; 1733 1734 if (++BBI != FuncInfo.MF->end()) 1735 NextBlock = BBI; 1736 1737 // TODO: If any two of the cases has the same destination, and if one value 1738 // is the same as the other, but has one bit unset that the other has set, 1739 // use bit manipulation to do two compares at once. For example: 1740 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1741 1742 // Rearrange the case blocks so that the last one falls through if possible. 1743 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1744 // The last case block won't fall through into 'NextBlock' if we emit the 1745 // branches in this order. See if rearranging a case value would help. 1746 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1747 if (I->BB == NextBlock) { 1748 std::swap(*I, BackCase); 1749 break; 1750 } 1751 } 1752 } 1753 1754 // Create a CaseBlock record representing a conditional branch to 1755 // the Case's target mbb if the value being switched on SV is equal 1756 // to C. 1757 MachineBasicBlock *CurBlock = CR.CaseBB; 1758 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1759 MachineBasicBlock *FallThrough; 1760 if (I != E-1) { 1761 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1762 CurMF->insert(BBI, FallThrough); 1763 1764 // Put SV in a virtual register to make it available from the new blocks. 1765 ExportFromCurrentBlock(SV); 1766 } else { 1767 // If the last case doesn't match, go to the default block. 1768 FallThrough = Default; 1769 } 1770 1771 const Value *RHS, *LHS, *MHS; 1772 ISD::CondCode CC; 1773 if (I->High == I->Low) { 1774 // This is just small small case range :) containing exactly 1 case 1775 CC = ISD::SETEQ; 1776 LHS = SV; RHS = I->High; MHS = NULL; 1777 } else { 1778 CC = ISD::SETLE; 1779 LHS = I->Low; MHS = SV; RHS = I->High; 1780 } 1781 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1782 1783 // If emitting the first comparison, just call visitSwitchCase to emit the 1784 // code into the current block. Otherwise, push the CaseBlock onto the 1785 // vector to be later processed by SDISel, and insert the node's MBB 1786 // before the next MBB. 1787 if (CurBlock == SwitchBB) 1788 visitSwitchCase(CB, SwitchBB); 1789 else 1790 SwitchCases.push_back(CB); 1791 1792 CurBlock = FallThrough; 1793 } 1794 1795 return true; 1796} 1797 1798static inline bool areJTsAllowed(const TargetLowering &TLI) { 1799 return !DisableJumpTables && 1800 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1801 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1802} 1803 1804static APInt ComputeRange(const APInt &First, const APInt &Last) { 1805 APInt LastExt(Last), FirstExt(First); 1806 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1807 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1808 return (LastExt - FirstExt + 1ULL); 1809} 1810 1811/// handleJTSwitchCase - Emit jumptable for current switch case range 1812bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1813 CaseRecVector& WorkList, 1814 const Value* SV, 1815 MachineBasicBlock* Default, 1816 MachineBasicBlock *SwitchBB) { 1817 Case& FrontCase = *CR.Range.first; 1818 Case& BackCase = *(CR.Range.second-1); 1819 1820 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1821 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1822 1823 APInt TSize(First.getBitWidth(), 0); 1824 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1825 I!=E; ++I) 1826 TSize += I->size(); 1827 1828 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1829 return false; 1830 1831 APInt Range = ComputeRange(First, Last); 1832 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1833 if (Density < 0.4) 1834 return false; 1835 1836 DEBUG(dbgs() << "Lowering jump table\n" 1837 << "First entry: " << First << ". Last entry: " << Last << '\n' 1838 << "Range: " << Range 1839 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1840 1841 // Get the MachineFunction which holds the current MBB. This is used when 1842 // inserting any additional MBBs necessary to represent the switch. 1843 MachineFunction *CurMF = FuncInfo.MF; 1844 1845 // Figure out which block is immediately after the current one. 1846 MachineFunction::iterator BBI = CR.CaseBB; 1847 ++BBI; 1848 1849 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1850 1851 // Create a new basic block to hold the code for loading the address 1852 // of the jump table, and jumping to it. Update successor information; 1853 // we will either branch to the default case for the switch, or the jump 1854 // table. 1855 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1856 CurMF->insert(BBI, JumpTableBB); 1857 CR.CaseBB->addSuccessor(Default); 1858 CR.CaseBB->addSuccessor(JumpTableBB); 1859 1860 // Build a vector of destination BBs, corresponding to each target 1861 // of the jump table. If the value of the jump table slot corresponds to 1862 // a case statement, push the case's BB onto the vector, otherwise, push 1863 // the default BB. 1864 std::vector<MachineBasicBlock*> DestBBs; 1865 APInt TEI = First; 1866 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1867 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1868 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1869 1870 if (Low.sle(TEI) && TEI.sle(High)) { 1871 DestBBs.push_back(I->BB); 1872 if (TEI==High) 1873 ++I; 1874 } else { 1875 DestBBs.push_back(Default); 1876 } 1877 } 1878 1879 // Update successor info. Add one edge to each unique successor. 1880 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1881 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1882 E = DestBBs.end(); I != E; ++I) { 1883 if (!SuccsHandled[(*I)->getNumber()]) { 1884 SuccsHandled[(*I)->getNumber()] = true; 1885 JumpTableBB->addSuccessor(*I); 1886 } 1887 } 1888 1889 // Create a jump table index for this jump table. 1890 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1891 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1892 ->createJumpTableIndex(DestBBs); 1893 1894 // Set the jump table information so that we can codegen it as a second 1895 // MachineBasicBlock 1896 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1897 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1898 if (CR.CaseBB == SwitchBB) 1899 visitJumpTableHeader(JT, JTH, SwitchBB); 1900 1901 JTCases.push_back(JumpTableBlock(JTH, JT)); 1902 1903 return true; 1904} 1905 1906/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1907/// 2 subtrees. 1908bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1909 CaseRecVector& WorkList, 1910 const Value* SV, 1911 MachineBasicBlock *Default, 1912 MachineBasicBlock *SwitchBB) { 1913 // Get the MachineFunction which holds the current MBB. This is used when 1914 // inserting any additional MBBs necessary to represent the switch. 1915 MachineFunction *CurMF = FuncInfo.MF; 1916 1917 // Figure out which block is immediately after the current one. 1918 MachineFunction::iterator BBI = CR.CaseBB; 1919 ++BBI; 1920 1921 Case& FrontCase = *CR.Range.first; 1922 Case& BackCase = *(CR.Range.second-1); 1923 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1924 1925 // Size is the number of Cases represented by this range. 1926 unsigned Size = CR.Range.second - CR.Range.first; 1927 1928 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1929 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1930 double FMetric = 0; 1931 CaseItr Pivot = CR.Range.first + Size/2; 1932 1933 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1934 // (heuristically) allow us to emit JumpTable's later. 1935 APInt TSize(First.getBitWidth(), 0); 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1937 I!=E; ++I) 1938 TSize += I->size(); 1939 1940 APInt LSize = FrontCase.size(); 1941 APInt RSize = TSize-LSize; 1942 DEBUG(dbgs() << "Selecting best pivot: \n" 1943 << "First: " << First << ", Last: " << Last <<'\n' 1944 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1945 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1946 J!=E; ++I, ++J) { 1947 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1948 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1949 APInt Range = ComputeRange(LEnd, RBegin); 1950 assert((Range - 2ULL).isNonNegative() && 1951 "Invalid case distance"); 1952 double LDensity = (double)LSize.roundToDouble() / 1953 (LEnd - First + 1ULL).roundToDouble(); 1954 double RDensity = (double)RSize.roundToDouble() / 1955 (Last - RBegin + 1ULL).roundToDouble(); 1956 double Metric = Range.logBase2()*(LDensity+RDensity); 1957 // Should always split in some non-trivial place 1958 DEBUG(dbgs() <<"=>Step\n" 1959 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1960 << "LDensity: " << LDensity 1961 << ", RDensity: " << RDensity << '\n' 1962 << "Metric: " << Metric << '\n'); 1963 if (FMetric < Metric) { 1964 Pivot = J; 1965 FMetric = Metric; 1966 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1967 } 1968 1969 LSize += J->size(); 1970 RSize -= J->size(); 1971 } 1972 if (areJTsAllowed(TLI)) { 1973 // If our case is dense we *really* should handle it earlier! 1974 assert((FMetric > 0) && "Should handle dense range earlier!"); 1975 } else { 1976 Pivot = CR.Range.first + Size/2; 1977 } 1978 1979 CaseRange LHSR(CR.Range.first, Pivot); 1980 CaseRange RHSR(Pivot, CR.Range.second); 1981 Constant *C = Pivot->Low; 1982 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1983 1984 // We know that we branch to the LHS if the Value being switched on is 1985 // less than the Pivot value, C. We use this to optimize our binary 1986 // tree a bit, by recognizing that if SV is greater than or equal to the 1987 // LHS's Case Value, and that Case Value is exactly one less than the 1988 // Pivot's Value, then we can branch directly to the LHS's Target, 1989 // rather than creating a leaf node for it. 1990 if ((LHSR.second - LHSR.first) == 1 && 1991 LHSR.first->High == CR.GE && 1992 cast<ConstantInt>(C)->getValue() == 1993 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1994 TrueBB = LHSR.first->BB; 1995 } else { 1996 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1997 CurMF->insert(BBI, TrueBB); 1998 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1999 2000 // Put SV in a virtual register to make it available from the new blocks. 2001 ExportFromCurrentBlock(SV); 2002 } 2003 2004 // Similar to the optimization above, if the Value being switched on is 2005 // known to be less than the Constant CR.LT, and the current Case Value 2006 // is CR.LT - 1, then we can branch directly to the target block for 2007 // the current Case Value, rather than emitting a RHS leaf node for it. 2008 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2009 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2010 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2011 FalseBB = RHSR.first->BB; 2012 } else { 2013 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2014 CurMF->insert(BBI, FalseBB); 2015 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2016 2017 // Put SV in a virtual register to make it available from the new blocks. 2018 ExportFromCurrentBlock(SV); 2019 } 2020 2021 // Create a CaseBlock record representing a conditional branch to 2022 // the LHS node if the value being switched on SV is less than C. 2023 // Otherwise, branch to LHS. 2024 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2025 2026 if (CR.CaseBB == SwitchBB) 2027 visitSwitchCase(CB, SwitchBB); 2028 else 2029 SwitchCases.push_back(CB); 2030 2031 return true; 2032} 2033 2034/// handleBitTestsSwitchCase - if current case range has few destination and 2035/// range span less, than machine word bitwidth, encode case range into series 2036/// of masks and emit bit tests with these masks. 2037bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2038 CaseRecVector& WorkList, 2039 const Value* SV, 2040 MachineBasicBlock* Default, 2041 MachineBasicBlock *SwitchBB){ 2042 EVT PTy = TLI.getPointerTy(); 2043 unsigned IntPtrBits = PTy.getSizeInBits(); 2044 2045 Case& FrontCase = *CR.Range.first; 2046 Case& BackCase = *(CR.Range.second-1); 2047 2048 // Get the MachineFunction which holds the current MBB. This is used when 2049 // inserting any additional MBBs necessary to represent the switch. 2050 MachineFunction *CurMF = FuncInfo.MF; 2051 2052 // If target does not have legal shift left, do not emit bit tests at all. 2053 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2054 return false; 2055 2056 size_t numCmps = 0; 2057 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2058 I!=E; ++I) { 2059 // Single case counts one, case range - two. 2060 numCmps += (I->Low == I->High ? 1 : 2); 2061 } 2062 2063 // Count unique destinations 2064 SmallSet<MachineBasicBlock*, 4> Dests; 2065 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2066 Dests.insert(I->BB); 2067 if (Dests.size() > 3) 2068 // Don't bother the code below, if there are too much unique destinations 2069 return false; 2070 } 2071 DEBUG(dbgs() << "Total number of unique destinations: " 2072 << Dests.size() << '\n' 2073 << "Total number of comparisons: " << numCmps << '\n'); 2074 2075 // Compute span of values. 2076 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2077 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2078 APInt cmpRange = maxValue - minValue; 2079 2080 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2081 << "Low bound: " << minValue << '\n' 2082 << "High bound: " << maxValue << '\n'); 2083 2084 if (cmpRange.uge(IntPtrBits) || 2085 (!(Dests.size() == 1 && numCmps >= 3) && 2086 !(Dests.size() == 2 && numCmps >= 5) && 2087 !(Dests.size() >= 3 && numCmps >= 6))) 2088 return false; 2089 2090 DEBUG(dbgs() << "Emitting bit tests\n"); 2091 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2092 2093 // Optimize the case where all the case values fit in a 2094 // word without having to subtract minValue. In this case, 2095 // we can optimize away the subtraction. 2096 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2097 cmpRange = maxValue; 2098 } else { 2099 lowBound = minValue; 2100 } 2101 2102 CaseBitsVector CasesBits; 2103 unsigned i, count = 0; 2104 2105 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2106 MachineBasicBlock* Dest = I->BB; 2107 for (i = 0; i < count; ++i) 2108 if (Dest == CasesBits[i].BB) 2109 break; 2110 2111 if (i == count) { 2112 assert((count < 3) && "Too much destinations to test!"); 2113 CasesBits.push_back(CaseBits(0, Dest, 0)); 2114 count++; 2115 } 2116 2117 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2118 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2119 2120 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2121 uint64_t hi = (highValue - lowBound).getZExtValue(); 2122 2123 for (uint64_t j = lo; j <= hi; j++) { 2124 CasesBits[i].Mask |= 1ULL << j; 2125 CasesBits[i].Bits++; 2126 } 2127 2128 } 2129 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2130 2131 BitTestInfo BTC; 2132 2133 // Figure out which block is immediately after the current one. 2134 MachineFunction::iterator BBI = CR.CaseBB; 2135 ++BBI; 2136 2137 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2138 2139 DEBUG(dbgs() << "Cases:\n"); 2140 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2141 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2142 << ", Bits: " << CasesBits[i].Bits 2143 << ", BB: " << CasesBits[i].BB << '\n'); 2144 2145 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2146 CurMF->insert(BBI, CaseBB); 2147 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2148 CaseBB, 2149 CasesBits[i].BB)); 2150 2151 // Put SV in a virtual register to make it available from the new blocks. 2152 ExportFromCurrentBlock(SV); 2153 } 2154 2155 BitTestBlock BTB(lowBound, cmpRange, SV, 2156 -1U, (CR.CaseBB == SwitchBB), 2157 CR.CaseBB, Default, BTC); 2158 2159 if (CR.CaseBB == SwitchBB) 2160 visitBitTestHeader(BTB, SwitchBB); 2161 2162 BitTestCases.push_back(BTB); 2163 2164 return true; 2165} 2166 2167/// Clusterify - Transform simple list of Cases into list of CaseRange's 2168size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2169 const SwitchInst& SI) { 2170 size_t numCmps = 0; 2171 2172 // Start with "simple" cases 2173 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2174 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2175 Cases.push_back(Case(SI.getSuccessorValue(i), 2176 SI.getSuccessorValue(i), 2177 SMBB)); 2178 } 2179 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2180 2181 // Merge case into clusters 2182 if (Cases.size() >= 2) 2183 // Must recompute end() each iteration because it may be 2184 // invalidated by erase if we hold on to it 2185 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2186 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2187 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2188 MachineBasicBlock* nextBB = J->BB; 2189 MachineBasicBlock* currentBB = I->BB; 2190 2191 // If the two neighboring cases go to the same destination, merge them 2192 // into a single case. 2193 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2194 I->High = J->High; 2195 J = Cases.erase(J); 2196 } else { 2197 I = J++; 2198 } 2199 } 2200 2201 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2202 if (I->Low != I->High) 2203 // A range counts double, since it requires two compares. 2204 ++numCmps; 2205 } 2206 2207 return numCmps; 2208} 2209 2210void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2211 MachineBasicBlock *Last) { 2212 // Update JTCases. 2213 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2214 if (JTCases[i].first.HeaderBB == First) 2215 JTCases[i].first.HeaderBB = Last; 2216 2217 // Update BitTestCases. 2218 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2219 if (BitTestCases[i].Parent == First) 2220 BitTestCases[i].Parent = Last; 2221} 2222 2223void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2224 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2225 2226 // Figure out which block is immediately after the current one. 2227 MachineBasicBlock *NextBlock = 0; 2228 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2229 2230 // If there is only the default destination, branch to it if it is not the 2231 // next basic block. Otherwise, just fall through. 2232 if (SI.getNumOperands() == 2) { 2233 // Update machine-CFG edges. 2234 2235 // If this is not a fall-through branch, emit the branch. 2236 SwitchMBB->addSuccessor(Default); 2237 if (Default != NextBlock) 2238 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2239 MVT::Other, getControlRoot(), 2240 DAG.getBasicBlock(Default))); 2241 2242 return; 2243 } 2244 2245 // If there are any non-default case statements, create a vector of Cases 2246 // representing each one, and sort the vector so that we can efficiently 2247 // create a binary search tree from them. 2248 CaseVector Cases; 2249 size_t numCmps = Clusterify(Cases, SI); 2250 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2251 << ". Total compares: " << numCmps << '\n'); 2252 numCmps = 0; 2253 2254 // Get the Value to be switched on and default basic blocks, which will be 2255 // inserted into CaseBlock records, representing basic blocks in the binary 2256 // search tree. 2257 const Value *SV = SI.getOperand(0); 2258 2259 // Push the initial CaseRec onto the worklist 2260 CaseRecVector WorkList; 2261 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2262 CaseRange(Cases.begin(),Cases.end()))); 2263 2264 while (!WorkList.empty()) { 2265 // Grab a record representing a case range to process off the worklist 2266 CaseRec CR = WorkList.back(); 2267 WorkList.pop_back(); 2268 2269 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2270 continue; 2271 2272 // If the range has few cases (two or less) emit a series of specific 2273 // tests. 2274 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2275 continue; 2276 2277 // If the switch has more than 5 blocks, and at least 40% dense, and the 2278 // target supports indirect branches, then emit a jump table rather than 2279 // lowering the switch to a binary tree of conditional branches. 2280 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2281 continue; 2282 2283 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2284 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2285 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2286 } 2287} 2288 2289void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2290 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2291 2292 // Update machine-CFG edges with unique successors. 2293 SmallVector<BasicBlock*, 32> succs; 2294 succs.reserve(I.getNumSuccessors()); 2295 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2296 succs.push_back(I.getSuccessor(i)); 2297 array_pod_sort(succs.begin(), succs.end()); 2298 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2299 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2300 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2301 2302 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2303 MVT::Other, getControlRoot(), 2304 getValue(I.getAddress()))); 2305} 2306 2307void SelectionDAGBuilder::visitFSub(const User &I) { 2308 // -0.0 - X --> fneg 2309 const Type *Ty = I.getType(); 2310 if (Ty->isVectorTy()) { 2311 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2312 const VectorType *DestTy = cast<VectorType>(I.getType()); 2313 const Type *ElTy = DestTy->getElementType(); 2314 unsigned VL = DestTy->getNumElements(); 2315 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2316 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2317 if (CV == CNZ) { 2318 SDValue Op2 = getValue(I.getOperand(1)); 2319 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2320 Op2.getValueType(), Op2)); 2321 return; 2322 } 2323 } 2324 } 2325 2326 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2327 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2328 SDValue Op2 = getValue(I.getOperand(1)); 2329 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2330 Op2.getValueType(), Op2)); 2331 return; 2332 } 2333 2334 visitBinary(I, ISD::FSUB); 2335} 2336 2337void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2338 SDValue Op1 = getValue(I.getOperand(0)); 2339 SDValue Op2 = getValue(I.getOperand(1)); 2340 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2341 Op1.getValueType(), Op1, Op2)); 2342} 2343 2344void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2345 SDValue Op1 = getValue(I.getOperand(0)); 2346 SDValue Op2 = getValue(I.getOperand(1)); 2347 if (!I.getType()->isVectorTy() && 2348 Op2.getValueType() != TLI.getShiftAmountTy()) { 2349 // If the operand is smaller than the shift count type, promote it. 2350 EVT PTy = TLI.getPointerTy(); 2351 EVT STy = TLI.getShiftAmountTy(); 2352 if (STy.bitsGT(Op2.getValueType())) 2353 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2354 TLI.getShiftAmountTy(), Op2); 2355 // If the operand is larger than the shift count type but the shift 2356 // count type has enough bits to represent any shift value, truncate 2357 // it now. This is a common case and it exposes the truncate to 2358 // optimization early. 2359 else if (STy.getSizeInBits() >= 2360 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2361 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2362 TLI.getShiftAmountTy(), Op2); 2363 // Otherwise we'll need to temporarily settle for some other 2364 // convenient type; type legalization will make adjustments as 2365 // needed. 2366 else if (PTy.bitsLT(Op2.getValueType())) 2367 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2368 TLI.getPointerTy(), Op2); 2369 else if (PTy.bitsGT(Op2.getValueType())) 2370 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2371 TLI.getPointerTy(), Op2); 2372 } 2373 2374 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2375 Op1.getValueType(), Op1, Op2)); 2376} 2377 2378void SelectionDAGBuilder::visitICmp(const User &I) { 2379 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2380 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2381 predicate = IC->getPredicate(); 2382 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2383 predicate = ICmpInst::Predicate(IC->getPredicate()); 2384 SDValue Op1 = getValue(I.getOperand(0)); 2385 SDValue Op2 = getValue(I.getOperand(1)); 2386 ISD::CondCode Opcode = getICmpCondCode(predicate); 2387 2388 EVT DestVT = TLI.getValueType(I.getType()); 2389 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2390} 2391 2392void SelectionDAGBuilder::visitFCmp(const User &I) { 2393 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2394 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2395 predicate = FC->getPredicate(); 2396 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2397 predicate = FCmpInst::Predicate(FC->getPredicate()); 2398 SDValue Op1 = getValue(I.getOperand(0)); 2399 SDValue Op2 = getValue(I.getOperand(1)); 2400 ISD::CondCode Condition = getFCmpCondCode(predicate); 2401 EVT DestVT = TLI.getValueType(I.getType()); 2402 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2403} 2404 2405void SelectionDAGBuilder::visitSelect(const User &I) { 2406 SmallVector<EVT, 4> ValueVTs; 2407 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2408 unsigned NumValues = ValueVTs.size(); 2409 if (NumValues == 0) return; 2410 2411 SmallVector<SDValue, 4> Values(NumValues); 2412 SDValue Cond = getValue(I.getOperand(0)); 2413 SDValue TrueVal = getValue(I.getOperand(1)); 2414 SDValue FalseVal = getValue(I.getOperand(2)); 2415 2416 for (unsigned i = 0; i != NumValues; ++i) 2417 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2418 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2419 Cond, 2420 SDValue(TrueVal.getNode(), 2421 TrueVal.getResNo() + i), 2422 SDValue(FalseVal.getNode(), 2423 FalseVal.getResNo() + i)); 2424 2425 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2426 DAG.getVTList(&ValueVTs[0], NumValues), 2427 &Values[0], NumValues)); 2428} 2429 2430void SelectionDAGBuilder::visitTrunc(const User &I) { 2431 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2432 SDValue N = getValue(I.getOperand(0)); 2433 EVT DestVT = TLI.getValueType(I.getType()); 2434 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2435} 2436 2437void SelectionDAGBuilder::visitZExt(const User &I) { 2438 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2439 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2440 SDValue N = getValue(I.getOperand(0)); 2441 EVT DestVT = TLI.getValueType(I.getType()); 2442 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2443} 2444 2445void SelectionDAGBuilder::visitSExt(const User &I) { 2446 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2447 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2448 SDValue N = getValue(I.getOperand(0)); 2449 EVT DestVT = TLI.getValueType(I.getType()); 2450 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2451} 2452 2453void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2454 // FPTrunc is never a no-op cast, no need to check 2455 SDValue N = getValue(I.getOperand(0)); 2456 EVT DestVT = TLI.getValueType(I.getType()); 2457 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2458 DestVT, N, DAG.getIntPtrConstant(0))); 2459} 2460 2461void SelectionDAGBuilder::visitFPExt(const User &I){ 2462 // FPTrunc is never a no-op cast, no need to check 2463 SDValue N = getValue(I.getOperand(0)); 2464 EVT DestVT = TLI.getValueType(I.getType()); 2465 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2466} 2467 2468void SelectionDAGBuilder::visitFPToUI(const User &I) { 2469 // FPToUI is never a no-op cast, no need to check 2470 SDValue N = getValue(I.getOperand(0)); 2471 EVT DestVT = TLI.getValueType(I.getType()); 2472 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2473} 2474 2475void SelectionDAGBuilder::visitFPToSI(const User &I) { 2476 // FPToSI is never a no-op cast, no need to check 2477 SDValue N = getValue(I.getOperand(0)); 2478 EVT DestVT = TLI.getValueType(I.getType()); 2479 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2480} 2481 2482void SelectionDAGBuilder::visitUIToFP(const User &I) { 2483 // UIToFP is never a no-op cast, no need to check 2484 SDValue N = getValue(I.getOperand(0)); 2485 EVT DestVT = TLI.getValueType(I.getType()); 2486 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2487} 2488 2489void SelectionDAGBuilder::visitSIToFP(const User &I){ 2490 // SIToFP is never a no-op cast, no need to check 2491 SDValue N = getValue(I.getOperand(0)); 2492 EVT DestVT = TLI.getValueType(I.getType()); 2493 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2494} 2495 2496void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2497 // What to do depends on the size of the integer and the size of the pointer. 2498 // We can either truncate, zero extend, or no-op, accordingly. 2499 SDValue N = getValue(I.getOperand(0)); 2500 EVT DestVT = TLI.getValueType(I.getType()); 2501 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2502} 2503 2504void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2505 // What to do depends on the size of the integer and the size of the pointer. 2506 // We can either truncate, zero extend, or no-op, accordingly. 2507 SDValue N = getValue(I.getOperand(0)); 2508 EVT DestVT = TLI.getValueType(I.getType()); 2509 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2510} 2511 2512void SelectionDAGBuilder::visitBitCast(const User &I) { 2513 SDValue N = getValue(I.getOperand(0)); 2514 EVT DestVT = TLI.getValueType(I.getType()); 2515 2516 // BitCast assures us that source and destination are the same size so this is 2517 // either a BIT_CONVERT or a no-op. 2518 if (DestVT != N.getValueType()) 2519 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2520 DestVT, N)); // convert types. 2521 else 2522 setValue(&I, N); // noop cast. 2523} 2524 2525void SelectionDAGBuilder::visitInsertElement(const User &I) { 2526 SDValue InVec = getValue(I.getOperand(0)); 2527 SDValue InVal = getValue(I.getOperand(1)); 2528 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2529 TLI.getPointerTy(), 2530 getValue(I.getOperand(2))); 2531 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2532 TLI.getValueType(I.getType()), 2533 InVec, InVal, InIdx)); 2534} 2535 2536void SelectionDAGBuilder::visitExtractElement(const User &I) { 2537 SDValue InVec = getValue(I.getOperand(0)); 2538 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2539 TLI.getPointerTy(), 2540 getValue(I.getOperand(1))); 2541 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2542 TLI.getValueType(I.getType()), InVec, InIdx)); 2543} 2544 2545// Utility for visitShuffleVector - Returns true if the mask is mask starting 2546// from SIndx and increasing to the element length (undefs are allowed). 2547static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2548 unsigned MaskNumElts = Mask.size(); 2549 for (unsigned i = 0; i != MaskNumElts; ++i) 2550 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2551 return false; 2552 return true; 2553} 2554 2555void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2556 SmallVector<int, 8> Mask; 2557 SDValue Src1 = getValue(I.getOperand(0)); 2558 SDValue Src2 = getValue(I.getOperand(1)); 2559 2560 // Convert the ConstantVector mask operand into an array of ints, with -1 2561 // representing undef values. 2562 SmallVector<Constant*, 8> MaskElts; 2563 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2564 unsigned MaskNumElts = MaskElts.size(); 2565 for (unsigned i = 0; i != MaskNumElts; ++i) { 2566 if (isa<UndefValue>(MaskElts[i])) 2567 Mask.push_back(-1); 2568 else 2569 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2570 } 2571 2572 EVT VT = TLI.getValueType(I.getType()); 2573 EVT SrcVT = Src1.getValueType(); 2574 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2575 2576 if (SrcNumElts == MaskNumElts) { 2577 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2578 &Mask[0])); 2579 return; 2580 } 2581 2582 // Normalize the shuffle vector since mask and vector length don't match. 2583 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2584 // Mask is longer than the source vectors and is a multiple of the source 2585 // vectors. We can use concatenate vector to make the mask and vectors 2586 // lengths match. 2587 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2588 // The shuffle is concatenating two vectors together. 2589 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2590 VT, Src1, Src2)); 2591 return; 2592 } 2593 2594 // Pad both vectors with undefs to make them the same length as the mask. 2595 unsigned NumConcat = MaskNumElts / SrcNumElts; 2596 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2597 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2598 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2599 2600 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2601 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2602 MOps1[0] = Src1; 2603 MOps2[0] = Src2; 2604 2605 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2606 getCurDebugLoc(), VT, 2607 &MOps1[0], NumConcat); 2608 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2609 getCurDebugLoc(), VT, 2610 &MOps2[0], NumConcat); 2611 2612 // Readjust mask for new input vector length. 2613 SmallVector<int, 8> MappedOps; 2614 for (unsigned i = 0; i != MaskNumElts; ++i) { 2615 int Idx = Mask[i]; 2616 if (Idx < (int)SrcNumElts) 2617 MappedOps.push_back(Idx); 2618 else 2619 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2620 } 2621 2622 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2623 &MappedOps[0])); 2624 return; 2625 } 2626 2627 if (SrcNumElts > MaskNumElts) { 2628 // Analyze the access pattern of the vector to see if we can extract 2629 // two subvectors and do the shuffle. The analysis is done by calculating 2630 // the range of elements the mask access on both vectors. 2631 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2632 int MaxRange[2] = {-1, -1}; 2633 2634 for (unsigned i = 0; i != MaskNumElts; ++i) { 2635 int Idx = Mask[i]; 2636 int Input = 0; 2637 if (Idx < 0) 2638 continue; 2639 2640 if (Idx >= (int)SrcNumElts) { 2641 Input = 1; 2642 Idx -= SrcNumElts; 2643 } 2644 if (Idx > MaxRange[Input]) 2645 MaxRange[Input] = Idx; 2646 if (Idx < MinRange[Input]) 2647 MinRange[Input] = Idx; 2648 } 2649 2650 // Check if the access is smaller than the vector size and can we find 2651 // a reasonable extract index. 2652 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2653 // Extract. 2654 int StartIdx[2]; // StartIdx to extract from 2655 for (int Input=0; Input < 2; ++Input) { 2656 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2657 RangeUse[Input] = 0; // Unused 2658 StartIdx[Input] = 0; 2659 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2660 // Fits within range but we should see if we can find a good 2661 // start index that is a multiple of the mask length. 2662 if (MaxRange[Input] < (int)MaskNumElts) { 2663 RangeUse[Input] = 1; // Extract from beginning of the vector 2664 StartIdx[Input] = 0; 2665 } else { 2666 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2667 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2668 StartIdx[Input] + MaskNumElts < SrcNumElts) 2669 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2670 } 2671 } 2672 } 2673 2674 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2675 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2676 return; 2677 } 2678 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2679 // Extract appropriate subvector and generate a vector shuffle 2680 for (int Input=0; Input < 2; ++Input) { 2681 SDValue &Src = Input == 0 ? Src1 : Src2; 2682 if (RangeUse[Input] == 0) 2683 Src = DAG.getUNDEF(VT); 2684 else 2685 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2686 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2687 } 2688 2689 // Calculate new mask. 2690 SmallVector<int, 8> MappedOps; 2691 for (unsigned i = 0; i != MaskNumElts; ++i) { 2692 int Idx = Mask[i]; 2693 if (Idx < 0) 2694 MappedOps.push_back(Idx); 2695 else if (Idx < (int)SrcNumElts) 2696 MappedOps.push_back(Idx - StartIdx[0]); 2697 else 2698 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2699 } 2700 2701 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2702 &MappedOps[0])); 2703 return; 2704 } 2705 } 2706 2707 // We can't use either concat vectors or extract subvectors so fall back to 2708 // replacing the shuffle with extract and build vector. 2709 // to insert and build vector. 2710 EVT EltVT = VT.getVectorElementType(); 2711 EVT PtrVT = TLI.getPointerTy(); 2712 SmallVector<SDValue,8> Ops; 2713 for (unsigned i = 0; i != MaskNumElts; ++i) { 2714 if (Mask[i] < 0) { 2715 Ops.push_back(DAG.getUNDEF(EltVT)); 2716 } else { 2717 int Idx = Mask[i]; 2718 SDValue Res; 2719 2720 if (Idx < (int)SrcNumElts) 2721 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2722 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2723 else 2724 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2725 EltVT, Src2, 2726 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2727 2728 Ops.push_back(Res); 2729 } 2730 } 2731 2732 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2733 VT, &Ops[0], Ops.size())); 2734} 2735 2736void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2737 const Value *Op0 = I.getOperand(0); 2738 const Value *Op1 = I.getOperand(1); 2739 const Type *AggTy = I.getType(); 2740 const Type *ValTy = Op1->getType(); 2741 bool IntoUndef = isa<UndefValue>(Op0); 2742 bool FromUndef = isa<UndefValue>(Op1); 2743 2744 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2745 2746 SmallVector<EVT, 4> AggValueVTs; 2747 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2748 SmallVector<EVT, 4> ValValueVTs; 2749 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2750 2751 unsigned NumAggValues = AggValueVTs.size(); 2752 unsigned NumValValues = ValValueVTs.size(); 2753 SmallVector<SDValue, 4> Values(NumAggValues); 2754 2755 SDValue Agg = getValue(Op0); 2756 SDValue Val = getValue(Op1); 2757 unsigned i = 0; 2758 // Copy the beginning value(s) from the original aggregate. 2759 for (; i != LinearIndex; ++i) 2760 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2761 SDValue(Agg.getNode(), Agg.getResNo() + i); 2762 // Copy values from the inserted value(s). 2763 for (; i != LinearIndex + NumValValues; ++i) 2764 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2765 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2766 // Copy remaining value(s) from the original aggregate. 2767 for (; i != NumAggValues; ++i) 2768 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2769 SDValue(Agg.getNode(), Agg.getResNo() + i); 2770 2771 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2772 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2773 &Values[0], NumAggValues)); 2774} 2775 2776void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2777 const Value *Op0 = I.getOperand(0); 2778 const Type *AggTy = Op0->getType(); 2779 const Type *ValTy = I.getType(); 2780 bool OutOfUndef = isa<UndefValue>(Op0); 2781 2782 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2783 2784 SmallVector<EVT, 4> ValValueVTs; 2785 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2786 2787 unsigned NumValValues = ValValueVTs.size(); 2788 SmallVector<SDValue, 4> Values(NumValValues); 2789 2790 SDValue Agg = getValue(Op0); 2791 // Copy out the selected value(s). 2792 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2793 Values[i - LinearIndex] = 2794 OutOfUndef ? 2795 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2796 SDValue(Agg.getNode(), Agg.getResNo() + i); 2797 2798 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2799 DAG.getVTList(&ValValueVTs[0], NumValValues), 2800 &Values[0], NumValValues)); 2801} 2802 2803void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2804 SDValue N = getValue(I.getOperand(0)); 2805 const Type *Ty = I.getOperand(0)->getType(); 2806 2807 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2808 OI != E; ++OI) { 2809 const Value *Idx = *OI; 2810 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2811 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2812 if (Field) { 2813 // N = N + Offset 2814 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2815 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2816 DAG.getIntPtrConstant(Offset)); 2817 } 2818 2819 Ty = StTy->getElementType(Field); 2820 } else { 2821 Ty = cast<SequentialType>(Ty)->getElementType(); 2822 2823 // If this is a constant subscript, handle it quickly. 2824 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2825 if (CI->isZero()) continue; 2826 uint64_t Offs = 2827 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2828 SDValue OffsVal; 2829 EVT PTy = TLI.getPointerTy(); 2830 unsigned PtrBits = PTy.getSizeInBits(); 2831 if (PtrBits < 64) 2832 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2833 TLI.getPointerTy(), 2834 DAG.getConstant(Offs, MVT::i64)); 2835 else 2836 OffsVal = DAG.getIntPtrConstant(Offs); 2837 2838 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2839 OffsVal); 2840 continue; 2841 } 2842 2843 // N = N + Idx * ElementSize; 2844 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2845 TD->getTypeAllocSize(Ty)); 2846 SDValue IdxN = getValue(Idx); 2847 2848 // If the index is smaller or larger than intptr_t, truncate or extend 2849 // it. 2850 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2851 2852 // If this is a multiply by a power of two, turn it into a shl 2853 // immediately. This is a very common case. 2854 if (ElementSize != 1) { 2855 if (ElementSize.isPowerOf2()) { 2856 unsigned Amt = ElementSize.logBase2(); 2857 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2858 N.getValueType(), IdxN, 2859 DAG.getConstant(Amt, TLI.getPointerTy())); 2860 } else { 2861 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2862 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2863 N.getValueType(), IdxN, Scale); 2864 } 2865 } 2866 2867 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2868 N.getValueType(), N, IdxN); 2869 } 2870 } 2871 2872 setValue(&I, N); 2873} 2874 2875void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2876 // If this is a fixed sized alloca in the entry block of the function, 2877 // allocate it statically on the stack. 2878 if (FuncInfo.StaticAllocaMap.count(&I)) 2879 return; // getValue will auto-populate this. 2880 2881 const Type *Ty = I.getAllocatedType(); 2882 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2883 unsigned Align = 2884 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2885 I.getAlignment()); 2886 2887 SDValue AllocSize = getValue(I.getArraySize()); 2888 2889 EVT IntPtr = TLI.getPointerTy(); 2890 if (AllocSize.getValueType() != IntPtr) 2891 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2892 2893 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2894 AllocSize, 2895 DAG.getConstant(TySize, IntPtr)); 2896 2897 // Handle alignment. If the requested alignment is less than or equal to 2898 // the stack alignment, ignore it. If the size is greater than or equal to 2899 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2900 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2901 if (Align <= StackAlign) 2902 Align = 0; 2903 2904 // Round the size of the allocation up to the stack alignment size 2905 // by add SA-1 to the size. 2906 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2907 AllocSize.getValueType(), AllocSize, 2908 DAG.getIntPtrConstant(StackAlign-1)); 2909 2910 // Mask out the low bits for alignment purposes. 2911 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2912 AllocSize.getValueType(), AllocSize, 2913 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2914 2915 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2916 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2917 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2918 VTs, Ops, 3); 2919 setValue(&I, DSA); 2920 DAG.setRoot(DSA.getValue(1)); 2921 2922 // Inform the Frame Information that we have just allocated a variable-sized 2923 // object. 2924 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2925} 2926 2927void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2928 const Value *SV = I.getOperand(0); 2929 SDValue Ptr = getValue(SV); 2930 2931 const Type *Ty = I.getType(); 2932 2933 bool isVolatile = I.isVolatile(); 2934 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2935 unsigned Alignment = I.getAlignment(); 2936 2937 SmallVector<EVT, 4> ValueVTs; 2938 SmallVector<uint64_t, 4> Offsets; 2939 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2940 unsigned NumValues = ValueVTs.size(); 2941 if (NumValues == 0) 2942 return; 2943 2944 SDValue Root; 2945 bool ConstantMemory = false; 2946 if (I.isVolatile()) 2947 // Serialize volatile loads with other side effects. 2948 Root = getRoot(); 2949 else if (AA->pointsToConstantMemory(SV)) { 2950 // Do not serialize (non-volatile) loads of constant memory with anything. 2951 Root = DAG.getEntryNode(); 2952 ConstantMemory = true; 2953 } else { 2954 // Do not serialize non-volatile loads against each other. 2955 Root = DAG.getRoot(); 2956 } 2957 2958 SmallVector<SDValue, 4> Values(NumValues); 2959 SmallVector<SDValue, 4> Chains(NumValues); 2960 EVT PtrVT = Ptr.getValueType(); 2961 for (unsigned i = 0; i != NumValues; ++i) { 2962 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2963 PtrVT, Ptr, 2964 DAG.getConstant(Offsets[i], PtrVT)); 2965 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2966 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 2967 isNonTemporal, Alignment); 2968 2969 Values[i] = L; 2970 Chains[i] = L.getValue(1); 2971 } 2972 2973 if (!ConstantMemory) { 2974 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2975 MVT::Other, &Chains[0], NumValues); 2976 if (isVolatile) 2977 DAG.setRoot(Chain); 2978 else 2979 PendingLoads.push_back(Chain); 2980 } 2981 2982 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2983 DAG.getVTList(&ValueVTs[0], NumValues), 2984 &Values[0], NumValues)); 2985} 2986 2987void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2988 const Value *SrcV = I.getOperand(0); 2989 const Value *PtrV = I.getOperand(1); 2990 2991 SmallVector<EVT, 4> ValueVTs; 2992 SmallVector<uint64_t, 4> Offsets; 2993 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2994 unsigned NumValues = ValueVTs.size(); 2995 if (NumValues == 0) 2996 return; 2997 2998 // Get the lowered operands. Note that we do this after 2999 // checking if NumResults is zero, because with zero results 3000 // the operands won't have values in the map. 3001 SDValue Src = getValue(SrcV); 3002 SDValue Ptr = getValue(PtrV); 3003 3004 SDValue Root = getRoot(); 3005 SmallVector<SDValue, 4> Chains(NumValues); 3006 EVT PtrVT = Ptr.getValueType(); 3007 bool isVolatile = I.isVolatile(); 3008 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3009 unsigned Alignment = I.getAlignment(); 3010 3011 for (unsigned i = 0; i != NumValues; ++i) { 3012 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3013 DAG.getConstant(Offsets[i], PtrVT)); 3014 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 3015 SDValue(Src.getNode(), Src.getResNo() + i), 3016 Add, MachinePointerInfo(PtrV, Offsets[i]), 3017 isVolatile, isNonTemporal, Alignment); 3018 } 3019 3020 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3021 MVT::Other, &Chains[0], NumValues)); 3022} 3023 3024/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3025/// node. 3026void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3027 unsigned Intrinsic) { 3028 bool HasChain = !I.doesNotAccessMemory(); 3029 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3030 3031 // Build the operand list. 3032 SmallVector<SDValue, 8> Ops; 3033 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3034 if (OnlyLoad) { 3035 // We don't need to serialize loads against other loads. 3036 Ops.push_back(DAG.getRoot()); 3037 } else { 3038 Ops.push_back(getRoot()); 3039 } 3040 } 3041 3042 // Info is set by getTgtMemInstrinsic 3043 TargetLowering::IntrinsicInfo Info; 3044 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3045 3046 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3047 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3048 Info.opc == ISD::INTRINSIC_W_CHAIN) 3049 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3050 3051 // Add all operands of the call to the operand list. 3052 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3053 SDValue Op = getValue(I.getArgOperand(i)); 3054 assert(TLI.isTypeLegal(Op.getValueType()) && 3055 "Intrinsic uses a non-legal type?"); 3056 Ops.push_back(Op); 3057 } 3058 3059 SmallVector<EVT, 4> ValueVTs; 3060 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3061#ifndef NDEBUG 3062 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3063 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3064 "Intrinsic uses a non-legal type?"); 3065 } 3066#endif // NDEBUG 3067 3068 if (HasChain) 3069 ValueVTs.push_back(MVT::Other); 3070 3071 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3072 3073 // Create the node. 3074 SDValue Result; 3075 if (IsTgtIntrinsic) { 3076 // This is target intrinsic that touches memory 3077 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3078 VTs, &Ops[0], Ops.size(), 3079 Info.memVT, 3080 MachinePointerInfo(Info.ptrVal, Info.offset), 3081 Info.align, Info.vol, 3082 Info.readMem, Info.writeMem); 3083 } else if (!HasChain) { 3084 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3085 VTs, &Ops[0], Ops.size()); 3086 } else if (!I.getType()->isVoidTy()) { 3087 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3088 VTs, &Ops[0], Ops.size()); 3089 } else { 3090 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3091 VTs, &Ops[0], Ops.size()); 3092 } 3093 3094 if (HasChain) { 3095 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3096 if (OnlyLoad) 3097 PendingLoads.push_back(Chain); 3098 else 3099 DAG.setRoot(Chain); 3100 } 3101 3102 if (!I.getType()->isVoidTy()) { 3103 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3104 EVT VT = TLI.getValueType(PTy); 3105 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3106 } 3107 3108 setValue(&I, Result); 3109 } 3110} 3111 3112/// GetSignificand - Get the significand and build it into a floating-point 3113/// number with exponent of 1: 3114/// 3115/// Op = (Op & 0x007fffff) | 0x3f800000; 3116/// 3117/// where Op is the hexidecimal representation of floating point value. 3118static SDValue 3119GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3120 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3121 DAG.getConstant(0x007fffff, MVT::i32)); 3122 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3123 DAG.getConstant(0x3f800000, MVT::i32)); 3124 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3125} 3126 3127/// GetExponent - Get the exponent: 3128/// 3129/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3130/// 3131/// where Op is the hexidecimal representation of floating point value. 3132static SDValue 3133GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3134 DebugLoc dl) { 3135 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3136 DAG.getConstant(0x7f800000, MVT::i32)); 3137 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3138 DAG.getConstant(23, TLI.getPointerTy())); 3139 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3140 DAG.getConstant(127, MVT::i32)); 3141 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3142} 3143 3144/// getF32Constant - Get 32-bit floating point constant. 3145static SDValue 3146getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3147 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3148} 3149 3150/// Inlined utility function to implement binary input atomic intrinsics for 3151/// visitIntrinsicCall: I is a call instruction 3152/// Op is the associated NodeType for I 3153const char * 3154SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3155 ISD::NodeType Op) { 3156 SDValue Root = getRoot(); 3157 SDValue L = 3158 DAG.getAtomic(Op, getCurDebugLoc(), 3159 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3160 Root, 3161 getValue(I.getArgOperand(0)), 3162 getValue(I.getArgOperand(1)), 3163 I.getArgOperand(0)); 3164 setValue(&I, L); 3165 DAG.setRoot(L.getValue(1)); 3166 return 0; 3167} 3168 3169// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3170const char * 3171SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3172 SDValue Op1 = getValue(I.getArgOperand(0)); 3173 SDValue Op2 = getValue(I.getArgOperand(1)); 3174 3175 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3176 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3177 return 0; 3178} 3179 3180/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3181/// limited-precision mode. 3182void 3183SelectionDAGBuilder::visitExp(const CallInst &I) { 3184 SDValue result; 3185 DebugLoc dl = getCurDebugLoc(); 3186 3187 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3188 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3189 SDValue Op = getValue(I.getArgOperand(0)); 3190 3191 // Put the exponent in the right bit position for later addition to the 3192 // final result: 3193 // 3194 // #define LOG2OFe 1.4426950f 3195 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3196 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3197 getF32Constant(DAG, 0x3fb8aa3b)); 3198 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3199 3200 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3201 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3202 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3203 3204 // IntegerPartOfX <<= 23; 3205 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3206 DAG.getConstant(23, TLI.getPointerTy())); 3207 3208 if (LimitFloatPrecision <= 6) { 3209 // For floating-point precision of 6: 3210 // 3211 // TwoToFractionalPartOfX = 3212 // 0.997535578f + 3213 // (0.735607626f + 0.252464424f * x) * x; 3214 // 3215 // error 0.0144103317, which is 6 bits 3216 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3217 getF32Constant(DAG, 0x3e814304)); 3218 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3219 getF32Constant(DAG, 0x3f3c50c8)); 3220 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3221 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3222 getF32Constant(DAG, 0x3f7f5e7e)); 3223 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3224 3225 // Add the exponent into the result in integer domain. 3226 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3227 TwoToFracPartOfX, IntegerPartOfX); 3228 3229 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3230 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3231 // For floating-point precision of 12: 3232 // 3233 // TwoToFractionalPartOfX = 3234 // 0.999892986f + 3235 // (0.696457318f + 3236 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3237 // 3238 // 0.000107046256 error, which is 13 to 14 bits 3239 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3240 getF32Constant(DAG, 0x3da235e3)); 3241 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3242 getF32Constant(DAG, 0x3e65b8f3)); 3243 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3244 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3245 getF32Constant(DAG, 0x3f324b07)); 3246 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3247 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3248 getF32Constant(DAG, 0x3f7ff8fd)); 3249 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3250 3251 // Add the exponent into the result in integer domain. 3252 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3253 TwoToFracPartOfX, IntegerPartOfX); 3254 3255 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3256 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3257 // For floating-point precision of 18: 3258 // 3259 // TwoToFractionalPartOfX = 3260 // 0.999999982f + 3261 // (0.693148872f + 3262 // (0.240227044f + 3263 // (0.554906021e-1f + 3264 // (0.961591928e-2f + 3265 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3266 // 3267 // error 2.47208000*10^(-7), which is better than 18 bits 3268 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3269 getF32Constant(DAG, 0x3924b03e)); 3270 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3271 getF32Constant(DAG, 0x3ab24b87)); 3272 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3273 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3274 getF32Constant(DAG, 0x3c1d8c17)); 3275 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3276 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3277 getF32Constant(DAG, 0x3d634a1d)); 3278 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3279 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3280 getF32Constant(DAG, 0x3e75fe14)); 3281 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3282 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3283 getF32Constant(DAG, 0x3f317234)); 3284 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3285 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3286 getF32Constant(DAG, 0x3f800000)); 3287 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3288 MVT::i32, t13); 3289 3290 // Add the exponent into the result in integer domain. 3291 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3292 TwoToFracPartOfX, IntegerPartOfX); 3293 3294 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3295 } 3296 } else { 3297 // No special expansion. 3298 result = DAG.getNode(ISD::FEXP, dl, 3299 getValue(I.getArgOperand(0)).getValueType(), 3300 getValue(I.getArgOperand(0))); 3301 } 3302 3303 setValue(&I, result); 3304} 3305 3306/// visitLog - Lower a log intrinsic. Handles the special sequences for 3307/// limited-precision mode. 3308void 3309SelectionDAGBuilder::visitLog(const CallInst &I) { 3310 SDValue result; 3311 DebugLoc dl = getCurDebugLoc(); 3312 3313 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3314 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3315 SDValue Op = getValue(I.getArgOperand(0)); 3316 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3317 3318 // Scale the exponent by log(2) [0.69314718f]. 3319 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3320 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3321 getF32Constant(DAG, 0x3f317218)); 3322 3323 // Get the significand and build it into a floating-point number with 3324 // exponent of 1. 3325 SDValue X = GetSignificand(DAG, Op1, dl); 3326 3327 if (LimitFloatPrecision <= 6) { 3328 // For floating-point precision of 6: 3329 // 3330 // LogofMantissa = 3331 // -1.1609546f + 3332 // (1.4034025f - 0.23903021f * x) * x; 3333 // 3334 // error 0.0034276066, which is better than 8 bits 3335 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3336 getF32Constant(DAG, 0xbe74c456)); 3337 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3338 getF32Constant(DAG, 0x3fb3a2b1)); 3339 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3340 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3341 getF32Constant(DAG, 0x3f949a29)); 3342 3343 result = DAG.getNode(ISD::FADD, dl, 3344 MVT::f32, LogOfExponent, LogOfMantissa); 3345 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3346 // For floating-point precision of 12: 3347 // 3348 // LogOfMantissa = 3349 // -1.7417939f + 3350 // (2.8212026f + 3351 // (-1.4699568f + 3352 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3353 // 3354 // error 0.000061011436, which is 14 bits 3355 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3356 getF32Constant(DAG, 0xbd67b6d6)); 3357 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3358 getF32Constant(DAG, 0x3ee4f4b8)); 3359 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3360 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3361 getF32Constant(DAG, 0x3fbc278b)); 3362 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3363 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3364 getF32Constant(DAG, 0x40348e95)); 3365 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3366 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3367 getF32Constant(DAG, 0x3fdef31a)); 3368 3369 result = DAG.getNode(ISD::FADD, dl, 3370 MVT::f32, LogOfExponent, LogOfMantissa); 3371 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3372 // For floating-point precision of 18: 3373 // 3374 // LogOfMantissa = 3375 // -2.1072184f + 3376 // (4.2372794f + 3377 // (-3.7029485f + 3378 // (2.2781945f + 3379 // (-0.87823314f + 3380 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3381 // 3382 // error 0.0000023660568, which is better than 18 bits 3383 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3384 getF32Constant(DAG, 0xbc91e5ac)); 3385 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3386 getF32Constant(DAG, 0x3e4350aa)); 3387 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3388 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3389 getF32Constant(DAG, 0x3f60d3e3)); 3390 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3391 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3392 getF32Constant(DAG, 0x4011cdf0)); 3393 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3394 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3395 getF32Constant(DAG, 0x406cfd1c)); 3396 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3397 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3398 getF32Constant(DAG, 0x408797cb)); 3399 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3400 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3401 getF32Constant(DAG, 0x4006dcab)); 3402 3403 result = DAG.getNode(ISD::FADD, dl, 3404 MVT::f32, LogOfExponent, LogOfMantissa); 3405 } 3406 } else { 3407 // No special expansion. 3408 result = DAG.getNode(ISD::FLOG, dl, 3409 getValue(I.getArgOperand(0)).getValueType(), 3410 getValue(I.getArgOperand(0))); 3411 } 3412 3413 setValue(&I, result); 3414} 3415 3416/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3417/// limited-precision mode. 3418void 3419SelectionDAGBuilder::visitLog2(const CallInst &I) { 3420 SDValue result; 3421 DebugLoc dl = getCurDebugLoc(); 3422 3423 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3424 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3425 SDValue Op = getValue(I.getArgOperand(0)); 3426 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3427 3428 // Get the exponent. 3429 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3430 3431 // Get the significand and build it into a floating-point number with 3432 // exponent of 1. 3433 SDValue X = GetSignificand(DAG, Op1, dl); 3434 3435 // Different possible minimax approximations of significand in 3436 // floating-point for various degrees of accuracy over [1,2]. 3437 if (LimitFloatPrecision <= 6) { 3438 // For floating-point precision of 6: 3439 // 3440 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3441 // 3442 // error 0.0049451742, which is more than 7 bits 3443 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3444 getF32Constant(DAG, 0xbeb08fe0)); 3445 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3446 getF32Constant(DAG, 0x40019463)); 3447 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3448 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3449 getF32Constant(DAG, 0x3fd6633d)); 3450 3451 result = DAG.getNode(ISD::FADD, dl, 3452 MVT::f32, LogOfExponent, Log2ofMantissa); 3453 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3454 // For floating-point precision of 12: 3455 // 3456 // Log2ofMantissa = 3457 // -2.51285454f + 3458 // (4.07009056f + 3459 // (-2.12067489f + 3460 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3461 // 3462 // error 0.0000876136000, which is better than 13 bits 3463 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3464 getF32Constant(DAG, 0xbda7262e)); 3465 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3466 getF32Constant(DAG, 0x3f25280b)); 3467 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3468 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3469 getF32Constant(DAG, 0x4007b923)); 3470 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3471 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3472 getF32Constant(DAG, 0x40823e2f)); 3473 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3474 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3475 getF32Constant(DAG, 0x4020d29c)); 3476 3477 result = DAG.getNode(ISD::FADD, dl, 3478 MVT::f32, LogOfExponent, Log2ofMantissa); 3479 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3480 // For floating-point precision of 18: 3481 // 3482 // Log2ofMantissa = 3483 // -3.0400495f + 3484 // (6.1129976f + 3485 // (-5.3420409f + 3486 // (3.2865683f + 3487 // (-1.2669343f + 3488 // (0.27515199f - 3489 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3490 // 3491 // error 0.0000018516, which is better than 18 bits 3492 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3493 getF32Constant(DAG, 0xbcd2769e)); 3494 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3495 getF32Constant(DAG, 0x3e8ce0b9)); 3496 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3497 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3498 getF32Constant(DAG, 0x3fa22ae7)); 3499 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3500 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3501 getF32Constant(DAG, 0x40525723)); 3502 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3503 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3504 getF32Constant(DAG, 0x40aaf200)); 3505 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3506 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3507 getF32Constant(DAG, 0x40c39dad)); 3508 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3509 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3510 getF32Constant(DAG, 0x4042902c)); 3511 3512 result = DAG.getNode(ISD::FADD, dl, 3513 MVT::f32, LogOfExponent, Log2ofMantissa); 3514 } 3515 } else { 3516 // No special expansion. 3517 result = DAG.getNode(ISD::FLOG2, dl, 3518 getValue(I.getArgOperand(0)).getValueType(), 3519 getValue(I.getArgOperand(0))); 3520 } 3521 3522 setValue(&I, result); 3523} 3524 3525/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3526/// limited-precision mode. 3527void 3528SelectionDAGBuilder::visitLog10(const CallInst &I) { 3529 SDValue result; 3530 DebugLoc dl = getCurDebugLoc(); 3531 3532 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3533 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3534 SDValue Op = getValue(I.getArgOperand(0)); 3535 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3536 3537 // Scale the exponent by log10(2) [0.30102999f]. 3538 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3539 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3540 getF32Constant(DAG, 0x3e9a209a)); 3541 3542 // Get the significand and build it into a floating-point number with 3543 // exponent of 1. 3544 SDValue X = GetSignificand(DAG, Op1, dl); 3545 3546 if (LimitFloatPrecision <= 6) { 3547 // For floating-point precision of 6: 3548 // 3549 // Log10ofMantissa = 3550 // -0.50419619f + 3551 // (0.60948995f - 0.10380950f * x) * x; 3552 // 3553 // error 0.0014886165, which is 6 bits 3554 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3555 getF32Constant(DAG, 0xbdd49a13)); 3556 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3557 getF32Constant(DAG, 0x3f1c0789)); 3558 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3559 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3560 getF32Constant(DAG, 0x3f011300)); 3561 3562 result = DAG.getNode(ISD::FADD, dl, 3563 MVT::f32, LogOfExponent, Log10ofMantissa); 3564 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3565 // For floating-point precision of 12: 3566 // 3567 // Log10ofMantissa = 3568 // -0.64831180f + 3569 // (0.91751397f + 3570 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3571 // 3572 // error 0.00019228036, which is better than 12 bits 3573 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3574 getF32Constant(DAG, 0x3d431f31)); 3575 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3576 getF32Constant(DAG, 0x3ea21fb2)); 3577 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3578 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3579 getF32Constant(DAG, 0x3f6ae232)); 3580 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3581 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3582 getF32Constant(DAG, 0x3f25f7c3)); 3583 3584 result = DAG.getNode(ISD::FADD, dl, 3585 MVT::f32, LogOfExponent, Log10ofMantissa); 3586 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3587 // For floating-point precision of 18: 3588 // 3589 // Log10ofMantissa = 3590 // -0.84299375f + 3591 // (1.5327582f + 3592 // (-1.0688956f + 3593 // (0.49102474f + 3594 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3595 // 3596 // error 0.0000037995730, which is better than 18 bits 3597 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3598 getF32Constant(DAG, 0x3c5d51ce)); 3599 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3600 getF32Constant(DAG, 0x3e00685a)); 3601 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3602 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3603 getF32Constant(DAG, 0x3efb6798)); 3604 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3605 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3606 getF32Constant(DAG, 0x3f88d192)); 3607 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3608 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3609 getF32Constant(DAG, 0x3fc4316c)); 3610 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3611 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3612 getF32Constant(DAG, 0x3f57ce70)); 3613 3614 result = DAG.getNode(ISD::FADD, dl, 3615 MVT::f32, LogOfExponent, Log10ofMantissa); 3616 } 3617 } else { 3618 // No special expansion. 3619 result = DAG.getNode(ISD::FLOG10, dl, 3620 getValue(I.getArgOperand(0)).getValueType(), 3621 getValue(I.getArgOperand(0))); 3622 } 3623 3624 setValue(&I, result); 3625} 3626 3627/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3628/// limited-precision mode. 3629void 3630SelectionDAGBuilder::visitExp2(const CallInst &I) { 3631 SDValue result; 3632 DebugLoc dl = getCurDebugLoc(); 3633 3634 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3635 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3636 SDValue Op = getValue(I.getArgOperand(0)); 3637 3638 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3639 3640 // FractionalPartOfX = x - (float)IntegerPartOfX; 3641 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3642 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3643 3644 // IntegerPartOfX <<= 23; 3645 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3646 DAG.getConstant(23, TLI.getPointerTy())); 3647 3648 if (LimitFloatPrecision <= 6) { 3649 // For floating-point precision of 6: 3650 // 3651 // TwoToFractionalPartOfX = 3652 // 0.997535578f + 3653 // (0.735607626f + 0.252464424f * x) * x; 3654 // 3655 // error 0.0144103317, which is 6 bits 3656 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3657 getF32Constant(DAG, 0x3e814304)); 3658 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3659 getF32Constant(DAG, 0x3f3c50c8)); 3660 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3661 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3662 getF32Constant(DAG, 0x3f7f5e7e)); 3663 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3664 SDValue TwoToFractionalPartOfX = 3665 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3666 3667 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3668 MVT::f32, TwoToFractionalPartOfX); 3669 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3670 // For floating-point precision of 12: 3671 // 3672 // TwoToFractionalPartOfX = 3673 // 0.999892986f + 3674 // (0.696457318f + 3675 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3676 // 3677 // error 0.000107046256, which is 13 to 14 bits 3678 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3679 getF32Constant(DAG, 0x3da235e3)); 3680 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3681 getF32Constant(DAG, 0x3e65b8f3)); 3682 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3683 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3684 getF32Constant(DAG, 0x3f324b07)); 3685 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3686 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3687 getF32Constant(DAG, 0x3f7ff8fd)); 3688 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3689 SDValue TwoToFractionalPartOfX = 3690 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3691 3692 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3693 MVT::f32, TwoToFractionalPartOfX); 3694 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3695 // For floating-point precision of 18: 3696 // 3697 // TwoToFractionalPartOfX = 3698 // 0.999999982f + 3699 // (0.693148872f + 3700 // (0.240227044f + 3701 // (0.554906021e-1f + 3702 // (0.961591928e-2f + 3703 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3704 // error 2.47208000*10^(-7), which is better than 18 bits 3705 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3706 getF32Constant(DAG, 0x3924b03e)); 3707 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3708 getF32Constant(DAG, 0x3ab24b87)); 3709 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3710 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3711 getF32Constant(DAG, 0x3c1d8c17)); 3712 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3713 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3714 getF32Constant(DAG, 0x3d634a1d)); 3715 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3716 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3717 getF32Constant(DAG, 0x3e75fe14)); 3718 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3719 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3720 getF32Constant(DAG, 0x3f317234)); 3721 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3722 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3723 getF32Constant(DAG, 0x3f800000)); 3724 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3725 SDValue TwoToFractionalPartOfX = 3726 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3727 3728 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3729 MVT::f32, TwoToFractionalPartOfX); 3730 } 3731 } else { 3732 // No special expansion. 3733 result = DAG.getNode(ISD::FEXP2, dl, 3734 getValue(I.getArgOperand(0)).getValueType(), 3735 getValue(I.getArgOperand(0))); 3736 } 3737 3738 setValue(&I, result); 3739} 3740 3741/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3742/// limited-precision mode with x == 10.0f. 3743void 3744SelectionDAGBuilder::visitPow(const CallInst &I) { 3745 SDValue result; 3746 const Value *Val = I.getArgOperand(0); 3747 DebugLoc dl = getCurDebugLoc(); 3748 bool IsExp10 = false; 3749 3750 if (getValue(Val).getValueType() == MVT::f32 && 3751 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3752 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3753 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3754 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3755 APFloat Ten(10.0f); 3756 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3757 } 3758 } 3759 } 3760 3761 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3762 SDValue Op = getValue(I.getArgOperand(1)); 3763 3764 // Put the exponent in the right bit position for later addition to the 3765 // final result: 3766 // 3767 // #define LOG2OF10 3.3219281f 3768 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3769 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3770 getF32Constant(DAG, 0x40549a78)); 3771 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3772 3773 // FractionalPartOfX = x - (float)IntegerPartOfX; 3774 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3775 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3776 3777 // IntegerPartOfX <<= 23; 3778 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3779 DAG.getConstant(23, TLI.getPointerTy())); 3780 3781 if (LimitFloatPrecision <= 6) { 3782 // For floating-point precision of 6: 3783 // 3784 // twoToFractionalPartOfX = 3785 // 0.997535578f + 3786 // (0.735607626f + 0.252464424f * x) * x; 3787 // 3788 // error 0.0144103317, which is 6 bits 3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3790 getF32Constant(DAG, 0x3e814304)); 3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3792 getF32Constant(DAG, 0x3f3c50c8)); 3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3795 getF32Constant(DAG, 0x3f7f5e7e)); 3796 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3797 SDValue TwoToFractionalPartOfX = 3798 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3799 3800 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3801 MVT::f32, TwoToFractionalPartOfX); 3802 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3803 // For floating-point precision of 12: 3804 // 3805 // TwoToFractionalPartOfX = 3806 // 0.999892986f + 3807 // (0.696457318f + 3808 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3809 // 3810 // error 0.000107046256, which is 13 to 14 bits 3811 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3812 getF32Constant(DAG, 0x3da235e3)); 3813 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3814 getF32Constant(DAG, 0x3e65b8f3)); 3815 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3816 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3817 getF32Constant(DAG, 0x3f324b07)); 3818 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3819 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3820 getF32Constant(DAG, 0x3f7ff8fd)); 3821 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3822 SDValue TwoToFractionalPartOfX = 3823 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3824 3825 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3826 MVT::f32, TwoToFractionalPartOfX); 3827 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3828 // For floating-point precision of 18: 3829 // 3830 // TwoToFractionalPartOfX = 3831 // 0.999999982f + 3832 // (0.693148872f + 3833 // (0.240227044f + 3834 // (0.554906021e-1f + 3835 // (0.961591928e-2f + 3836 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3837 // error 2.47208000*10^(-7), which is better than 18 bits 3838 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3839 getF32Constant(DAG, 0x3924b03e)); 3840 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3841 getF32Constant(DAG, 0x3ab24b87)); 3842 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3843 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3844 getF32Constant(DAG, 0x3c1d8c17)); 3845 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3846 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3847 getF32Constant(DAG, 0x3d634a1d)); 3848 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3849 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3850 getF32Constant(DAG, 0x3e75fe14)); 3851 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3852 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3853 getF32Constant(DAG, 0x3f317234)); 3854 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3855 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3856 getF32Constant(DAG, 0x3f800000)); 3857 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3858 SDValue TwoToFractionalPartOfX = 3859 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3860 3861 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3862 MVT::f32, TwoToFractionalPartOfX); 3863 } 3864 } else { 3865 // No special expansion. 3866 result = DAG.getNode(ISD::FPOW, dl, 3867 getValue(I.getArgOperand(0)).getValueType(), 3868 getValue(I.getArgOperand(0)), 3869 getValue(I.getArgOperand(1))); 3870 } 3871 3872 setValue(&I, result); 3873} 3874 3875 3876/// ExpandPowI - Expand a llvm.powi intrinsic. 3877static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3878 SelectionDAG &DAG) { 3879 // If RHS is a constant, we can expand this out to a multiplication tree, 3880 // otherwise we end up lowering to a call to __powidf2 (for example). When 3881 // optimizing for size, we only want to do this if the expansion would produce 3882 // a small number of multiplies, otherwise we do the full expansion. 3883 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3884 // Get the exponent as a positive value. 3885 unsigned Val = RHSC->getSExtValue(); 3886 if ((int)Val < 0) Val = -Val; 3887 3888 // powi(x, 0) -> 1.0 3889 if (Val == 0) 3890 return DAG.getConstantFP(1.0, LHS.getValueType()); 3891 3892 const Function *F = DAG.getMachineFunction().getFunction(); 3893 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3894 // If optimizing for size, don't insert too many multiplies. This 3895 // inserts up to 5 multiplies. 3896 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3897 // We use the simple binary decomposition method to generate the multiply 3898 // sequence. There are more optimal ways to do this (for example, 3899 // powi(x,15) generates one more multiply than it should), but this has 3900 // the benefit of being both really simple and much better than a libcall. 3901 SDValue Res; // Logically starts equal to 1.0 3902 SDValue CurSquare = LHS; 3903 while (Val) { 3904 if (Val & 1) { 3905 if (Res.getNode()) 3906 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3907 else 3908 Res = CurSquare; // 1.0*CurSquare. 3909 } 3910 3911 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3912 CurSquare, CurSquare); 3913 Val >>= 1; 3914 } 3915 3916 // If the original was negative, invert the result, producing 1/(x*x*x). 3917 if (RHSC->getSExtValue() < 0) 3918 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3919 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3920 return Res; 3921 } 3922 } 3923 3924 // Otherwise, expand to a libcall. 3925 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3926} 3927 3928/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3929/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3930/// At the end of instruction selection, they will be inserted to the entry BB. 3931bool 3932SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 3933 int64_t Offset, 3934 const SDValue &N) { 3935 const Argument *Arg = dyn_cast<Argument>(V); 3936 if (!Arg) 3937 return false; 3938 3939 MachineFunction &MF = DAG.getMachineFunction(); 3940 // Ignore inlined function arguments here. 3941 DIVariable DV(Variable); 3942 if (DV.isInlinedFnArgument(MF.getFunction())) 3943 return false; 3944 3945 MachineBasicBlock *MBB = FuncInfo.MBB; 3946 if (MBB != &MF.front()) 3947 return false; 3948 3949 unsigned Reg = 0; 3950 if (Arg->hasByValAttr()) { 3951 // Byval arguments' frame index is recorded during argument lowering. 3952 // Use this info directly. 3953 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3954 Reg = TRI->getFrameRegister(MF); 3955 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 3956 // If byval argument ofset is not recorded then ignore this. 3957 if (!Offset) 3958 Reg = 0; 3959 } 3960 3961 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 3962 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3963 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3964 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3965 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3966 if (PR) 3967 Reg = PR; 3968 } 3969 } 3970 3971 if (!Reg) { 3972 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3973 if (VMI == FuncInfo.ValueMap.end()) 3974 return false; 3975 Reg = VMI->second; 3976 } 3977 3978 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3979 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3980 TII->get(TargetOpcode::DBG_VALUE)) 3981 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 3982 FuncInfo.ArgDbgValues.push_back(&*MIB); 3983 return true; 3984} 3985 3986// VisualStudio defines setjmp as _setjmp 3987#if defined(_MSC_VER) && defined(setjmp) && \ 3988 !defined(setjmp_undefined_for_msvc) 3989# pragma push_macro("setjmp") 3990# undef setjmp 3991# define setjmp_undefined_for_msvc 3992#endif 3993 3994/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3995/// we want to emit this as a call to a named external function, return the name 3996/// otherwise lower it and return null. 3997const char * 3998SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3999 DebugLoc dl = getCurDebugLoc(); 4000 SDValue Res; 4001 4002 switch (Intrinsic) { 4003 default: 4004 // By default, turn this into a target intrinsic node. 4005 visitTargetIntrinsic(I, Intrinsic); 4006 return 0; 4007 case Intrinsic::vastart: visitVAStart(I); return 0; 4008 case Intrinsic::vaend: visitVAEnd(I); return 0; 4009 case Intrinsic::vacopy: visitVACopy(I); return 0; 4010 case Intrinsic::returnaddress: 4011 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4012 getValue(I.getArgOperand(0)))); 4013 return 0; 4014 case Intrinsic::frameaddress: 4015 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4016 getValue(I.getArgOperand(0)))); 4017 return 0; 4018 case Intrinsic::setjmp: 4019 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4020 case Intrinsic::longjmp: 4021 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4022 case Intrinsic::memcpy: { 4023 // Assert for address < 256 since we support only user defined address 4024 // spaces. 4025 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4026 < 256 && 4027 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4028 < 256 && 4029 "Unknown address space"); 4030 SDValue Op1 = getValue(I.getArgOperand(0)); 4031 SDValue Op2 = getValue(I.getArgOperand(1)); 4032 SDValue Op3 = getValue(I.getArgOperand(2)); 4033 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4034 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4035 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4036 MachinePointerInfo(I.getArgOperand(0)), 4037 MachinePointerInfo(I.getArgOperand(1)))); 4038 return 0; 4039 } 4040 case Intrinsic::memset: { 4041 // Assert for address < 256 since we support only user defined address 4042 // spaces. 4043 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4044 < 256 && 4045 "Unknown address space"); 4046 SDValue Op1 = getValue(I.getArgOperand(0)); 4047 SDValue Op2 = getValue(I.getArgOperand(1)); 4048 SDValue Op3 = getValue(I.getArgOperand(2)); 4049 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4050 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4051 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4052 MachinePointerInfo(I.getArgOperand(0)))); 4053 return 0; 4054 } 4055 case Intrinsic::memmove: { 4056 // Assert for address < 256 since we support only user defined address 4057 // spaces. 4058 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4059 < 256 && 4060 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4061 < 256 && 4062 "Unknown address space"); 4063 SDValue Op1 = getValue(I.getArgOperand(0)); 4064 SDValue Op2 = getValue(I.getArgOperand(1)); 4065 SDValue Op3 = getValue(I.getArgOperand(2)); 4066 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4067 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4068 4069 // If the source and destination are known to not be aliases, we can 4070 // lower memmove as memcpy. 4071 uint64_t Size = -1ULL; 4072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4073 Size = C->getZExtValue(); 4074 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == 4075 AliasAnalysis::NoAlias) { 4076 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4077 false, MachinePointerInfo(I.getArgOperand(0)), 4078 MachinePointerInfo(I.getArgOperand(1)))); 4079 return 0; 4080 } 4081 4082 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4083 MachinePointerInfo(I.getArgOperand(0)), 4084 MachinePointerInfo(I.getArgOperand(1)))); 4085 return 0; 4086 } 4087 case Intrinsic::dbg_declare: { 4088 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4089 MDNode *Variable = DI.getVariable(); 4090 const Value *Address = DI.getAddress(); 4091 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4092 return 0; 4093 4094 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4095 // but do not always have a corresponding SDNode built. The SDNodeOrder 4096 // absolute, but not relative, values are different depending on whether 4097 // debug info exists. 4098 ++SDNodeOrder; 4099 4100 // Check if address has undef value. 4101 if (isa<UndefValue>(Address) || 4102 (Address->use_empty() && !isa<Argument>(Address))) { 4103 SDDbgValue*SDV = 4104 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4105 0, dl, SDNodeOrder); 4106 DAG.AddDbgValue(SDV, 0, false); 4107 return 0; 4108 } 4109 4110 SDValue &N = NodeMap[Address]; 4111 if (!N.getNode() && isa<Argument>(Address)) 4112 // Check unused arguments map. 4113 N = UnusedArgNodeMap[Address]; 4114 SDDbgValue *SDV; 4115 if (N.getNode()) { 4116 // Parameters are handled specially. 4117 bool isParameter = 4118 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4119 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4120 Address = BCI->getOperand(0); 4121 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4122 4123 if (isParameter && !AI) { 4124 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4125 if (FINode) 4126 // Byval parameter. We have a frame index at this point. 4127 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4128 0, dl, SDNodeOrder); 4129 else 4130 // Can't do anything with other non-AI cases yet. This might be a 4131 // parameter of a callee function that got inlined, for example. 4132 return 0; 4133 } else if (AI) 4134 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4135 0, dl, SDNodeOrder); 4136 else 4137 // Can't do anything with other non-AI cases yet. 4138 return 0; 4139 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4140 } else { 4141 // If Address is an argument then try to emit its dbg value using 4142 // virtual register info from the FuncInfo.ValueMap. 4143 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4144 // If variable is pinned by a alloca in dominating bb then 4145 // use StaticAllocaMap. 4146 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4147 if (AI->getParent() != DI.getParent()) { 4148 DenseMap<const AllocaInst*, int>::iterator SI = 4149 FuncInfo.StaticAllocaMap.find(AI); 4150 if (SI != FuncInfo.StaticAllocaMap.end()) { 4151 SDV = DAG.getDbgValue(Variable, SI->second, 4152 0, dl, SDNodeOrder); 4153 DAG.AddDbgValue(SDV, 0, false); 4154 return 0; 4155 } 4156 } 4157 } 4158 // Otherwise add undef to help track missing debug info. 4159 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4160 0, dl, SDNodeOrder); 4161 DAG.AddDbgValue(SDV, 0, false); 4162 } 4163 } 4164 return 0; 4165 } 4166 case Intrinsic::dbg_value: { 4167 const DbgValueInst &DI = cast<DbgValueInst>(I); 4168 if (!DIVariable(DI.getVariable()).Verify()) 4169 return 0; 4170 4171 MDNode *Variable = DI.getVariable(); 4172 uint64_t Offset = DI.getOffset(); 4173 const Value *V = DI.getValue(); 4174 if (!V) 4175 return 0; 4176 4177 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4178 // but do not always have a corresponding SDNode built. The SDNodeOrder 4179 // absolute, but not relative, values are different depending on whether 4180 // debug info exists. 4181 ++SDNodeOrder; 4182 SDDbgValue *SDV; 4183 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4184 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4185 DAG.AddDbgValue(SDV, 0, false); 4186 } else { 4187 // Do not use getValue() in here; we don't want to generate code at 4188 // this point if it hasn't been done yet. 4189 SDValue N = NodeMap[V]; 4190 if (!N.getNode() && isa<Argument>(V)) 4191 // Check unused arguments map. 4192 N = UnusedArgNodeMap[V]; 4193 if (N.getNode()) { 4194 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4195 SDV = DAG.getDbgValue(Variable, N.getNode(), 4196 N.getResNo(), Offset, dl, SDNodeOrder); 4197 DAG.AddDbgValue(SDV, N.getNode(), false); 4198 } 4199 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4200 // Do not call getValue(V) yet, as we don't want to generate code. 4201 // Remember it for later. 4202 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4203 DanglingDebugInfoMap[V] = DDI; 4204 } else { 4205 // We may expand this to cover more cases. One case where we have no 4206 // data available is an unreferenced parameter; we need this fallback. 4207 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4208 Offset, dl, SDNodeOrder); 4209 DAG.AddDbgValue(SDV, 0, false); 4210 } 4211 } 4212 4213 // Build a debug info table entry. 4214 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4215 V = BCI->getOperand(0); 4216 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4217 // Don't handle byval struct arguments or VLAs, for example. 4218 if (!AI) 4219 return 0; 4220 DenseMap<const AllocaInst*, int>::iterator SI = 4221 FuncInfo.StaticAllocaMap.find(AI); 4222 if (SI == FuncInfo.StaticAllocaMap.end()) 4223 return 0; // VLAs. 4224 int FI = SI->second; 4225 4226 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4227 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4228 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4229 return 0; 4230 } 4231 case Intrinsic::eh_exception: { 4232 // Insert the EXCEPTIONADDR instruction. 4233 assert(FuncInfo.MBB->isLandingPad() && 4234 "Call to eh.exception not in landing pad!"); 4235 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4236 SDValue Ops[1]; 4237 Ops[0] = DAG.getRoot(); 4238 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4239 setValue(&I, Op); 4240 DAG.setRoot(Op.getValue(1)); 4241 return 0; 4242 } 4243 4244 case Intrinsic::eh_selector: { 4245 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4246 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4247 if (CallMBB->isLandingPad()) 4248 AddCatchInfo(I, &MMI, CallMBB); 4249 else { 4250#ifndef NDEBUG 4251 FuncInfo.CatchInfoLost.insert(&I); 4252#endif 4253 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4254 unsigned Reg = TLI.getExceptionSelectorRegister(); 4255 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4256 } 4257 4258 // Insert the EHSELECTION instruction. 4259 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4260 SDValue Ops[2]; 4261 Ops[0] = getValue(I.getArgOperand(0)); 4262 Ops[1] = getRoot(); 4263 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4264 DAG.setRoot(Op.getValue(1)); 4265 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4266 return 0; 4267 } 4268 4269 case Intrinsic::eh_typeid_for: { 4270 // Find the type id for the given typeinfo. 4271 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4272 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4273 Res = DAG.getConstant(TypeID, MVT::i32); 4274 setValue(&I, Res); 4275 return 0; 4276 } 4277 4278 case Intrinsic::eh_return_i32: 4279 case Intrinsic::eh_return_i64: 4280 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4281 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4282 MVT::Other, 4283 getControlRoot(), 4284 getValue(I.getArgOperand(0)), 4285 getValue(I.getArgOperand(1)))); 4286 return 0; 4287 case Intrinsic::eh_unwind_init: 4288 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4289 return 0; 4290 case Intrinsic::eh_dwarf_cfa: { 4291 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4292 TLI.getPointerTy()); 4293 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4294 TLI.getPointerTy(), 4295 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4296 TLI.getPointerTy()), 4297 CfaArg); 4298 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4299 TLI.getPointerTy(), 4300 DAG.getConstant(0, TLI.getPointerTy())); 4301 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4302 FA, Offset)); 4303 return 0; 4304 } 4305 case Intrinsic::eh_sjlj_callsite: { 4306 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4307 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4308 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4309 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4310 4311 MMI.setCurrentCallSite(CI->getZExtValue()); 4312 return 0; 4313 } 4314 case Intrinsic::eh_sjlj_setjmp: { 4315 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4316 getValue(I.getArgOperand(0)))); 4317 return 0; 4318 } 4319 case Intrinsic::eh_sjlj_longjmp: { 4320 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4321 getRoot(), 4322 getValue(I.getArgOperand(0)))); 4323 return 0; 4324 } 4325 4326 case Intrinsic::x86_mmx_pslli_w: 4327 case Intrinsic::x86_mmx_pslli_d: 4328 case Intrinsic::x86_mmx_pslli_q: 4329 case Intrinsic::x86_mmx_psrli_w: 4330 case Intrinsic::x86_mmx_psrli_d: 4331 case Intrinsic::x86_mmx_psrli_q: 4332 case Intrinsic::x86_mmx_psrai_w: 4333 case Intrinsic::x86_mmx_psrai_d: { 4334 SDValue ShAmt = getValue(I.getArgOperand(1)); 4335 if (isa<ConstantSDNode>(ShAmt)) { 4336 visitTargetIntrinsic(I, Intrinsic); 4337 return 0; 4338 } 4339 unsigned NewIntrinsic = 0; 4340 EVT ShAmtVT = MVT::v2i32; 4341 switch (Intrinsic) { 4342 case Intrinsic::x86_mmx_pslli_w: 4343 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4344 break; 4345 case Intrinsic::x86_mmx_pslli_d: 4346 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4347 break; 4348 case Intrinsic::x86_mmx_pslli_q: 4349 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4350 break; 4351 case Intrinsic::x86_mmx_psrli_w: 4352 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4353 break; 4354 case Intrinsic::x86_mmx_psrli_d: 4355 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4356 break; 4357 case Intrinsic::x86_mmx_psrli_q: 4358 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4359 break; 4360 case Intrinsic::x86_mmx_psrai_w: 4361 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4362 break; 4363 case Intrinsic::x86_mmx_psrai_d: 4364 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4365 break; 4366 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4367 } 4368 4369 // The vector shift intrinsics with scalars uses 32b shift amounts but 4370 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4371 // to be zero. 4372 // We must do this early because v2i32 is not a legal type. 4373 DebugLoc dl = getCurDebugLoc(); 4374 SDValue ShOps[2]; 4375 ShOps[0] = ShAmt; 4376 ShOps[1] = DAG.getConstant(0, MVT::i32); 4377 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4378 EVT DestVT = TLI.getValueType(I.getType()); 4379 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt); 4380 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4381 DAG.getConstant(NewIntrinsic, MVT::i32), 4382 getValue(I.getArgOperand(0)), ShAmt); 4383 setValue(&I, Res); 4384 return 0; 4385 } 4386 case Intrinsic::convertff: 4387 case Intrinsic::convertfsi: 4388 case Intrinsic::convertfui: 4389 case Intrinsic::convertsif: 4390 case Intrinsic::convertuif: 4391 case Intrinsic::convertss: 4392 case Intrinsic::convertsu: 4393 case Intrinsic::convertus: 4394 case Intrinsic::convertuu: { 4395 ISD::CvtCode Code = ISD::CVT_INVALID; 4396 switch (Intrinsic) { 4397 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4398 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4399 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4400 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4401 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4402 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4403 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4404 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4405 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4406 } 4407 EVT DestVT = TLI.getValueType(I.getType()); 4408 const Value *Op1 = I.getArgOperand(0); 4409 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4410 DAG.getValueType(DestVT), 4411 DAG.getValueType(getValue(Op1).getValueType()), 4412 getValue(I.getArgOperand(1)), 4413 getValue(I.getArgOperand(2)), 4414 Code); 4415 setValue(&I, Res); 4416 return 0; 4417 } 4418 case Intrinsic::sqrt: 4419 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4420 getValue(I.getArgOperand(0)).getValueType(), 4421 getValue(I.getArgOperand(0)))); 4422 return 0; 4423 case Intrinsic::powi: 4424 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4425 getValue(I.getArgOperand(1)), DAG)); 4426 return 0; 4427 case Intrinsic::sin: 4428 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4429 getValue(I.getArgOperand(0)).getValueType(), 4430 getValue(I.getArgOperand(0)))); 4431 return 0; 4432 case Intrinsic::cos: 4433 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4434 getValue(I.getArgOperand(0)).getValueType(), 4435 getValue(I.getArgOperand(0)))); 4436 return 0; 4437 case Intrinsic::log: 4438 visitLog(I); 4439 return 0; 4440 case Intrinsic::log2: 4441 visitLog2(I); 4442 return 0; 4443 case Intrinsic::log10: 4444 visitLog10(I); 4445 return 0; 4446 case Intrinsic::exp: 4447 visitExp(I); 4448 return 0; 4449 case Intrinsic::exp2: 4450 visitExp2(I); 4451 return 0; 4452 case Intrinsic::pow: 4453 visitPow(I); 4454 return 0; 4455 case Intrinsic::convert_to_fp16: 4456 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4457 MVT::i16, getValue(I.getArgOperand(0)))); 4458 return 0; 4459 case Intrinsic::convert_from_fp16: 4460 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4461 MVT::f32, getValue(I.getArgOperand(0)))); 4462 return 0; 4463 case Intrinsic::pcmarker: { 4464 SDValue Tmp = getValue(I.getArgOperand(0)); 4465 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4466 return 0; 4467 } 4468 case Intrinsic::readcyclecounter: { 4469 SDValue Op = getRoot(); 4470 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4471 DAG.getVTList(MVT::i64, MVT::Other), 4472 &Op, 1); 4473 setValue(&I, Res); 4474 DAG.setRoot(Res.getValue(1)); 4475 return 0; 4476 } 4477 case Intrinsic::bswap: 4478 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4479 getValue(I.getArgOperand(0)).getValueType(), 4480 getValue(I.getArgOperand(0)))); 4481 return 0; 4482 case Intrinsic::cttz: { 4483 SDValue Arg = getValue(I.getArgOperand(0)); 4484 EVT Ty = Arg.getValueType(); 4485 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4486 return 0; 4487 } 4488 case Intrinsic::ctlz: { 4489 SDValue Arg = getValue(I.getArgOperand(0)); 4490 EVT Ty = Arg.getValueType(); 4491 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4492 return 0; 4493 } 4494 case Intrinsic::ctpop: { 4495 SDValue Arg = getValue(I.getArgOperand(0)); 4496 EVT Ty = Arg.getValueType(); 4497 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4498 return 0; 4499 } 4500 case Intrinsic::stacksave: { 4501 SDValue Op = getRoot(); 4502 Res = DAG.getNode(ISD::STACKSAVE, dl, 4503 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4504 setValue(&I, Res); 4505 DAG.setRoot(Res.getValue(1)); 4506 return 0; 4507 } 4508 case Intrinsic::stackrestore: { 4509 Res = getValue(I.getArgOperand(0)); 4510 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4511 return 0; 4512 } 4513 case Intrinsic::stackprotector: { 4514 // Emit code into the DAG to store the stack guard onto the stack. 4515 MachineFunction &MF = DAG.getMachineFunction(); 4516 MachineFrameInfo *MFI = MF.getFrameInfo(); 4517 EVT PtrTy = TLI.getPointerTy(); 4518 4519 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4520 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4521 4522 int FI = FuncInfo.StaticAllocaMap[Slot]; 4523 MFI->setStackProtectorIndex(FI); 4524 4525 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4526 4527 // Store the stack protector onto the stack. 4528 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4529 MachinePointerInfo::getFixedStack(FI), 4530 true, false, 0); 4531 setValue(&I, Res); 4532 DAG.setRoot(Res); 4533 return 0; 4534 } 4535 case Intrinsic::objectsize: { 4536 // If we don't know by now, we're never going to know. 4537 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4538 4539 assert(CI && "Non-constant type in __builtin_object_size?"); 4540 4541 SDValue Arg = getValue(I.getCalledValue()); 4542 EVT Ty = Arg.getValueType(); 4543 4544 if (CI->isZero()) 4545 Res = DAG.getConstant(-1ULL, Ty); 4546 else 4547 Res = DAG.getConstant(0, Ty); 4548 4549 setValue(&I, Res); 4550 return 0; 4551 } 4552 case Intrinsic::var_annotation: 4553 // Discard annotate attributes 4554 return 0; 4555 4556 case Intrinsic::init_trampoline: { 4557 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4558 4559 SDValue Ops[6]; 4560 Ops[0] = getRoot(); 4561 Ops[1] = getValue(I.getArgOperand(0)); 4562 Ops[2] = getValue(I.getArgOperand(1)); 4563 Ops[3] = getValue(I.getArgOperand(2)); 4564 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4565 Ops[5] = DAG.getSrcValue(F); 4566 4567 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4568 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4569 Ops, 6); 4570 4571 setValue(&I, Res); 4572 DAG.setRoot(Res.getValue(1)); 4573 return 0; 4574 } 4575 case Intrinsic::gcroot: 4576 if (GFI) { 4577 const Value *Alloca = I.getArgOperand(0); 4578 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4579 4580 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4581 GFI->addStackRoot(FI->getIndex(), TypeMap); 4582 } 4583 return 0; 4584 case Intrinsic::gcread: 4585 case Intrinsic::gcwrite: 4586 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4587 return 0; 4588 case Intrinsic::flt_rounds: 4589 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4590 return 0; 4591 case Intrinsic::trap: 4592 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4593 return 0; 4594 case Intrinsic::uadd_with_overflow: 4595 return implVisitAluOverflow(I, ISD::UADDO); 4596 case Intrinsic::sadd_with_overflow: 4597 return implVisitAluOverflow(I, ISD::SADDO); 4598 case Intrinsic::usub_with_overflow: 4599 return implVisitAluOverflow(I, ISD::USUBO); 4600 case Intrinsic::ssub_with_overflow: 4601 return implVisitAluOverflow(I, ISD::SSUBO); 4602 case Intrinsic::umul_with_overflow: 4603 return implVisitAluOverflow(I, ISD::UMULO); 4604 case Intrinsic::smul_with_overflow: 4605 return implVisitAluOverflow(I, ISD::SMULO); 4606 4607 case Intrinsic::prefetch: { 4608 SDValue Ops[4]; 4609 Ops[0] = getRoot(); 4610 Ops[1] = getValue(I.getArgOperand(0)); 4611 Ops[2] = getValue(I.getArgOperand(1)); 4612 Ops[3] = getValue(I.getArgOperand(2)); 4613 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4614 return 0; 4615 } 4616 4617 case Intrinsic::memory_barrier: { 4618 SDValue Ops[6]; 4619 Ops[0] = getRoot(); 4620 for (int x = 1; x < 6; ++x) 4621 Ops[x] = getValue(I.getArgOperand(x - 1)); 4622 4623 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4624 return 0; 4625 } 4626 case Intrinsic::atomic_cmp_swap: { 4627 SDValue Root = getRoot(); 4628 SDValue L = 4629 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4630 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4631 Root, 4632 getValue(I.getArgOperand(0)), 4633 getValue(I.getArgOperand(1)), 4634 getValue(I.getArgOperand(2)), 4635 MachinePointerInfo(I.getArgOperand(0))); 4636 setValue(&I, L); 4637 DAG.setRoot(L.getValue(1)); 4638 return 0; 4639 } 4640 case Intrinsic::atomic_load_add: 4641 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4642 case Intrinsic::atomic_load_sub: 4643 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4644 case Intrinsic::atomic_load_or: 4645 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4646 case Intrinsic::atomic_load_xor: 4647 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4648 case Intrinsic::atomic_load_and: 4649 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4650 case Intrinsic::atomic_load_nand: 4651 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4652 case Intrinsic::atomic_load_max: 4653 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4654 case Intrinsic::atomic_load_min: 4655 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4656 case Intrinsic::atomic_load_umin: 4657 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4658 case Intrinsic::atomic_load_umax: 4659 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4660 case Intrinsic::atomic_swap: 4661 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4662 4663 case Intrinsic::invariant_start: 4664 case Intrinsic::lifetime_start: 4665 // Discard region information. 4666 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4667 return 0; 4668 case Intrinsic::invariant_end: 4669 case Intrinsic::lifetime_end: 4670 // Discard region information. 4671 return 0; 4672 } 4673} 4674 4675void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4676 bool isTailCall, 4677 MachineBasicBlock *LandingPad) { 4678 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4679 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4680 const Type *RetTy = FTy->getReturnType(); 4681 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4682 MCSymbol *BeginLabel = 0; 4683 4684 TargetLowering::ArgListTy Args; 4685 TargetLowering::ArgListEntry Entry; 4686 Args.reserve(CS.arg_size()); 4687 4688 // Check whether the function can return without sret-demotion. 4689 SmallVector<ISD::OutputArg, 4> Outs; 4690 SmallVector<uint64_t, 4> Offsets; 4691 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4692 Outs, TLI, &Offsets); 4693 4694 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4695 FTy->isVarArg(), Outs, FTy->getContext()); 4696 4697 SDValue DemoteStackSlot; 4698 int DemoteStackIdx = -100; 4699 4700 if (!CanLowerReturn) { 4701 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4702 FTy->getReturnType()); 4703 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4704 FTy->getReturnType()); 4705 MachineFunction &MF = DAG.getMachineFunction(); 4706 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4707 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4708 4709 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4710 Entry.Node = DemoteStackSlot; 4711 Entry.Ty = StackSlotPtrType; 4712 Entry.isSExt = false; 4713 Entry.isZExt = false; 4714 Entry.isInReg = false; 4715 Entry.isSRet = true; 4716 Entry.isNest = false; 4717 Entry.isByVal = false; 4718 Entry.Alignment = Align; 4719 Args.push_back(Entry); 4720 RetTy = Type::getVoidTy(FTy->getContext()); 4721 } 4722 4723 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4724 i != e; ++i) { 4725 SDValue ArgNode = getValue(*i); 4726 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4727 4728 unsigned attrInd = i - CS.arg_begin() + 1; 4729 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4730 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4731 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4732 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4733 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4734 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4735 Entry.Alignment = CS.getParamAlignment(attrInd); 4736 Args.push_back(Entry); 4737 } 4738 4739 if (LandingPad) { 4740 // Insert a label before the invoke call to mark the try range. This can be 4741 // used to detect deletion of the invoke via the MachineModuleInfo. 4742 BeginLabel = MMI.getContext().CreateTempSymbol(); 4743 4744 // For SjLj, keep track of which landing pads go with which invokes 4745 // so as to maintain the ordering of pads in the LSDA. 4746 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4747 if (CallSiteIndex) { 4748 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4749 // Now that the call site is handled, stop tracking it. 4750 MMI.setCurrentCallSite(0); 4751 } 4752 4753 // Both PendingLoads and PendingExports must be flushed here; 4754 // this call might not return. 4755 (void)getRoot(); 4756 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4757 } 4758 4759 // Check if target-independent constraints permit a tail call here. 4760 // Target-dependent constraints are checked within TLI.LowerCallTo. 4761 if (isTailCall && 4762 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4763 isTailCall = false; 4764 4765 // If there's a possibility that fast-isel has already selected some amount 4766 // of the current basic block, don't emit a tail call. 4767 if (isTailCall && EnableFastISel) 4768 isTailCall = false; 4769 4770 std::pair<SDValue,SDValue> Result = 4771 TLI.LowerCallTo(getRoot(), RetTy, 4772 CS.paramHasAttr(0, Attribute::SExt), 4773 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4774 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4775 CS.getCallingConv(), 4776 isTailCall, 4777 !CS.getInstruction()->use_empty(), 4778 Callee, Args, DAG, getCurDebugLoc()); 4779 assert((isTailCall || Result.second.getNode()) && 4780 "Non-null chain expected with non-tail call!"); 4781 assert((Result.second.getNode() || !Result.first.getNode()) && 4782 "Null value expected with tail call!"); 4783 if (Result.first.getNode()) { 4784 setValue(CS.getInstruction(), Result.first); 4785 } else if (!CanLowerReturn && Result.second.getNode()) { 4786 // The instruction result is the result of loading from the 4787 // hidden sret parameter. 4788 SmallVector<EVT, 1> PVTs; 4789 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4790 4791 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4792 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4793 EVT PtrVT = PVTs[0]; 4794 unsigned NumValues = Outs.size(); 4795 SmallVector<SDValue, 4> Values(NumValues); 4796 SmallVector<SDValue, 4> Chains(NumValues); 4797 4798 for (unsigned i = 0; i < NumValues; ++i) { 4799 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4800 DemoteStackSlot, 4801 DAG.getConstant(Offsets[i], PtrVT)); 4802 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4803 Add, 4804 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4805 false, false, 1); 4806 Values[i] = L; 4807 Chains[i] = L.getValue(1); 4808 } 4809 4810 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4811 MVT::Other, &Chains[0], NumValues); 4812 PendingLoads.push_back(Chain); 4813 4814 // Collect the legal value parts into potentially illegal values 4815 // that correspond to the original function's return values. 4816 SmallVector<EVT, 4> RetTys; 4817 RetTy = FTy->getReturnType(); 4818 ComputeValueVTs(TLI, RetTy, RetTys); 4819 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4820 SmallVector<SDValue, 4> ReturnValues; 4821 unsigned CurReg = 0; 4822 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4823 EVT VT = RetTys[I]; 4824 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4825 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4826 4827 SDValue ReturnValue = 4828 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4829 RegisterVT, VT, AssertOp); 4830 ReturnValues.push_back(ReturnValue); 4831 CurReg += NumRegs; 4832 } 4833 4834 setValue(CS.getInstruction(), 4835 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4836 DAG.getVTList(&RetTys[0], RetTys.size()), 4837 &ReturnValues[0], ReturnValues.size())); 4838 4839 } 4840 4841 // As a special case, a null chain means that a tail call has been emitted and 4842 // the DAG root is already updated. 4843 if (Result.second.getNode()) 4844 DAG.setRoot(Result.second); 4845 else 4846 HasTailCall = true; 4847 4848 if (LandingPad) { 4849 // Insert a label at the end of the invoke call to mark the try range. This 4850 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4851 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4852 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4853 4854 // Inform MachineModuleInfo of range. 4855 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4856 } 4857} 4858 4859/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4860/// value is equal or not-equal to zero. 4861static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4862 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4863 UI != E; ++UI) { 4864 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4865 if (IC->isEquality()) 4866 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4867 if (C->isNullValue()) 4868 continue; 4869 // Unknown instruction. 4870 return false; 4871 } 4872 return true; 4873} 4874 4875static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4876 const Type *LoadTy, 4877 SelectionDAGBuilder &Builder) { 4878 4879 // Check to see if this load can be trivially constant folded, e.g. if the 4880 // input is from a string literal. 4881 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4882 // Cast pointer to the type we really want to load. 4883 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4884 PointerType::getUnqual(LoadTy)); 4885 4886 if (const Constant *LoadCst = 4887 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4888 Builder.TD)) 4889 return Builder.getValue(LoadCst); 4890 } 4891 4892 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4893 // still constant memory, the input chain can be the entry node. 4894 SDValue Root; 4895 bool ConstantMemory = false; 4896 4897 // Do not serialize (non-volatile) loads of constant memory with anything. 4898 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4899 Root = Builder.DAG.getEntryNode(); 4900 ConstantMemory = true; 4901 } else { 4902 // Do not serialize non-volatile loads against each other. 4903 Root = Builder.DAG.getRoot(); 4904 } 4905 4906 SDValue Ptr = Builder.getValue(PtrVal); 4907 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4908 Ptr, MachinePointerInfo(PtrVal), 4909 false /*volatile*/, 4910 false /*nontemporal*/, 1 /* align=1 */); 4911 4912 if (!ConstantMemory) 4913 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4914 return LoadVal; 4915} 4916 4917 4918/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4919/// If so, return true and lower it, otherwise return false and it will be 4920/// lowered like a normal call. 4921bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4922 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4923 if (I.getNumArgOperands() != 3) 4924 return false; 4925 4926 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 4927 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4928 !I.getArgOperand(2)->getType()->isIntegerTy() || 4929 !I.getType()->isIntegerTy()) 4930 return false; 4931 4932 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 4933 4934 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4935 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4936 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4937 bool ActuallyDoIt = true; 4938 MVT LoadVT; 4939 const Type *LoadTy; 4940 switch (Size->getZExtValue()) { 4941 default: 4942 LoadVT = MVT::Other; 4943 LoadTy = 0; 4944 ActuallyDoIt = false; 4945 break; 4946 case 2: 4947 LoadVT = MVT::i16; 4948 LoadTy = Type::getInt16Ty(Size->getContext()); 4949 break; 4950 case 4: 4951 LoadVT = MVT::i32; 4952 LoadTy = Type::getInt32Ty(Size->getContext()); 4953 break; 4954 case 8: 4955 LoadVT = MVT::i64; 4956 LoadTy = Type::getInt64Ty(Size->getContext()); 4957 break; 4958 /* 4959 case 16: 4960 LoadVT = MVT::v4i32; 4961 LoadTy = Type::getInt32Ty(Size->getContext()); 4962 LoadTy = VectorType::get(LoadTy, 4); 4963 break; 4964 */ 4965 } 4966 4967 // This turns into unaligned loads. We only do this if the target natively 4968 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4969 // we'll only produce a small number of byte loads. 4970 4971 // Require that we can find a legal MVT, and only do this if the target 4972 // supports unaligned loads of that type. Expanding into byte loads would 4973 // bloat the code. 4974 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4975 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4976 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4977 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4978 ActuallyDoIt = false; 4979 } 4980 4981 if (ActuallyDoIt) { 4982 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4983 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4984 4985 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4986 ISD::SETNE); 4987 EVT CallVT = TLI.getValueType(I.getType(), true); 4988 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4989 return true; 4990 } 4991 } 4992 4993 4994 return false; 4995} 4996 4997 4998void SelectionDAGBuilder::visitCall(const CallInst &I) { 4999 // Handle inline assembly differently. 5000 if (isa<InlineAsm>(I.getCalledValue())) { 5001 visitInlineAsm(&I); 5002 return; 5003 } 5004 5005 const char *RenameFn = 0; 5006 if (Function *F = I.getCalledFunction()) { 5007 if (F->isDeclaration()) { 5008 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5009 if (unsigned IID = II->getIntrinsicID(F)) { 5010 RenameFn = visitIntrinsicCall(I, IID); 5011 if (!RenameFn) 5012 return; 5013 } 5014 } 5015 if (unsigned IID = F->getIntrinsicID()) { 5016 RenameFn = visitIntrinsicCall(I, IID); 5017 if (!RenameFn) 5018 return; 5019 } 5020 } 5021 5022 // Check for well-known libc/libm calls. If the function is internal, it 5023 // can't be a library call. 5024 if (!F->hasLocalLinkage() && F->hasName()) { 5025 StringRef Name = F->getName(); 5026 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5027 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5028 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5029 I.getType() == I.getArgOperand(0)->getType() && 5030 I.getType() == I.getArgOperand(1)->getType()) { 5031 SDValue LHS = getValue(I.getArgOperand(0)); 5032 SDValue RHS = getValue(I.getArgOperand(1)); 5033 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5034 LHS.getValueType(), LHS, RHS)); 5035 return; 5036 } 5037 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5038 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5039 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5040 I.getType() == I.getArgOperand(0)->getType()) { 5041 SDValue Tmp = getValue(I.getArgOperand(0)); 5042 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5043 Tmp.getValueType(), Tmp)); 5044 return; 5045 } 5046 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5047 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5048 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5049 I.getType() == I.getArgOperand(0)->getType() && 5050 I.onlyReadsMemory()) { 5051 SDValue Tmp = getValue(I.getArgOperand(0)); 5052 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5053 Tmp.getValueType(), Tmp)); 5054 return; 5055 } 5056 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5057 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5058 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5059 I.getType() == I.getArgOperand(0)->getType() && 5060 I.onlyReadsMemory()) { 5061 SDValue Tmp = getValue(I.getArgOperand(0)); 5062 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5063 Tmp.getValueType(), Tmp)); 5064 return; 5065 } 5066 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5067 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5068 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5069 I.getType() == I.getArgOperand(0)->getType() && 5070 I.onlyReadsMemory()) { 5071 SDValue Tmp = getValue(I.getArgOperand(0)); 5072 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5073 Tmp.getValueType(), Tmp)); 5074 return; 5075 } 5076 } else if (Name == "memcmp") { 5077 if (visitMemCmpCall(I)) 5078 return; 5079 } 5080 } 5081 } 5082 5083 SDValue Callee; 5084 if (!RenameFn) 5085 Callee = getValue(I.getCalledValue()); 5086 else 5087 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5088 5089 // Check if we can potentially perform a tail call. More detailed checking is 5090 // be done within LowerCallTo, after more information about the call is known. 5091 LowerCallTo(&I, Callee, I.isTailCall()); 5092} 5093 5094namespace llvm { 5095 5096/// AsmOperandInfo - This contains information for each constraint that we are 5097/// lowering. 5098class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5099 public TargetLowering::AsmOperandInfo { 5100public: 5101 /// CallOperand - If this is the result output operand or a clobber 5102 /// this is null, otherwise it is the incoming operand to the CallInst. 5103 /// This gets modified as the asm is processed. 5104 SDValue CallOperand; 5105 5106 /// AssignedRegs - If this is a register or register class operand, this 5107 /// contains the set of register corresponding to the operand. 5108 RegsForValue AssignedRegs; 5109 5110 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5111 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5112 } 5113 5114 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5115 /// busy in OutputRegs/InputRegs. 5116 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5117 std::set<unsigned> &OutputRegs, 5118 std::set<unsigned> &InputRegs, 5119 const TargetRegisterInfo &TRI) const { 5120 if (isOutReg) { 5121 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5122 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5123 } 5124 if (isInReg) { 5125 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5126 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5127 } 5128 } 5129 5130 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5131 /// corresponds to. If there is no Value* for this operand, it returns 5132 /// MVT::Other. 5133 EVT getCallOperandValEVT(LLVMContext &Context, 5134 const TargetLowering &TLI, 5135 const TargetData *TD) const { 5136 if (CallOperandVal == 0) return MVT::Other; 5137 5138 if (isa<BasicBlock>(CallOperandVal)) 5139 return TLI.getPointerTy(); 5140 5141 const llvm::Type *OpTy = CallOperandVal->getType(); 5142 5143 // If this is an indirect operand, the operand is a pointer to the 5144 // accessed type. 5145 if (isIndirect) { 5146 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5147 if (!PtrTy) 5148 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5149 OpTy = PtrTy->getElementType(); 5150 } 5151 5152 // If OpTy is not a single value, it may be a struct/union that we 5153 // can tile with integers. 5154 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5155 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5156 switch (BitSize) { 5157 default: break; 5158 case 1: 5159 case 8: 5160 case 16: 5161 case 32: 5162 case 64: 5163 case 128: 5164 OpTy = IntegerType::get(Context, BitSize); 5165 break; 5166 } 5167 } 5168 5169 return TLI.getValueType(OpTy, true); 5170 } 5171 5172private: 5173 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5174 /// specified set. 5175 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5176 const TargetRegisterInfo &TRI) { 5177 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5178 Regs.insert(Reg); 5179 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5180 for (; *Aliases; ++Aliases) 5181 Regs.insert(*Aliases); 5182 } 5183}; 5184 5185} // end llvm namespace. 5186 5187/// isAllocatableRegister - If the specified register is safe to allocate, 5188/// i.e. it isn't a stack pointer or some other special register, return the 5189/// register class for the register. Otherwise, return null. 5190static const TargetRegisterClass * 5191isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5192 const TargetLowering &TLI, 5193 const TargetRegisterInfo *TRI) { 5194 EVT FoundVT = MVT::Other; 5195 const TargetRegisterClass *FoundRC = 0; 5196 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5197 E = TRI->regclass_end(); RCI != E; ++RCI) { 5198 EVT ThisVT = MVT::Other; 5199 5200 const TargetRegisterClass *RC = *RCI; 5201 // If none of the value types for this register class are valid, we 5202 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5203 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5204 I != E; ++I) { 5205 if (TLI.isTypeLegal(*I)) { 5206 // If we have already found this register in a different register class, 5207 // choose the one with the largest VT specified. For example, on 5208 // PowerPC, we favor f64 register classes over f32. 5209 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5210 ThisVT = *I; 5211 break; 5212 } 5213 } 5214 } 5215 5216 if (ThisVT == MVT::Other) continue; 5217 5218 // NOTE: This isn't ideal. In particular, this might allocate the 5219 // frame pointer in functions that need it (due to them not being taken 5220 // out of allocation, because a variable sized allocation hasn't been seen 5221 // yet). This is a slight code pessimization, but should still work. 5222 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5223 E = RC->allocation_order_end(MF); I != E; ++I) 5224 if (*I == Reg) { 5225 // We found a matching register class. Keep looking at others in case 5226 // we find one with larger registers that this physreg is also in. 5227 FoundRC = RC; 5228 FoundVT = ThisVT; 5229 break; 5230 } 5231 } 5232 return FoundRC; 5233} 5234 5235/// GetRegistersForValue - Assign registers (virtual or physical) for the 5236/// specified operand. We prefer to assign virtual registers, to allow the 5237/// register allocator to handle the assignment process. However, if the asm 5238/// uses features that we can't model on machineinstrs, we have SDISel do the 5239/// allocation. This produces generally horrible, but correct, code. 5240/// 5241/// OpInfo describes the operand. 5242/// Input and OutputRegs are the set of already allocated physical registers. 5243/// 5244void SelectionDAGBuilder:: 5245GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5246 std::set<unsigned> &OutputRegs, 5247 std::set<unsigned> &InputRegs) { 5248 LLVMContext &Context = FuncInfo.Fn->getContext(); 5249 5250 // Compute whether this value requires an input register, an output register, 5251 // or both. 5252 bool isOutReg = false; 5253 bool isInReg = false; 5254 switch (OpInfo.Type) { 5255 case InlineAsm::isOutput: 5256 isOutReg = true; 5257 5258 // If there is an input constraint that matches this, we need to reserve 5259 // the input register so no other inputs allocate to it. 5260 isInReg = OpInfo.hasMatchingInput(); 5261 break; 5262 case InlineAsm::isInput: 5263 isInReg = true; 5264 isOutReg = false; 5265 break; 5266 case InlineAsm::isClobber: 5267 isOutReg = true; 5268 isInReg = true; 5269 break; 5270 } 5271 5272 5273 MachineFunction &MF = DAG.getMachineFunction(); 5274 SmallVector<unsigned, 4> Regs; 5275 5276 // If this is a constraint for a single physreg, or a constraint for a 5277 // register class, find it. 5278 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5279 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5280 OpInfo.ConstraintVT); 5281 5282 unsigned NumRegs = 1; 5283 if (OpInfo.ConstraintVT != MVT::Other) { 5284 // If this is a FP input in an integer register (or visa versa) insert a bit 5285 // cast of the input value. More generally, handle any case where the input 5286 // value disagrees with the register class we plan to stick this in. 5287 if (OpInfo.Type == InlineAsm::isInput && 5288 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5289 // Try to convert to the first EVT that the reg class contains. If the 5290 // types are identical size, use a bitcast to convert (e.g. two differing 5291 // vector types). 5292 EVT RegVT = *PhysReg.second->vt_begin(); 5293 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5294 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5295 RegVT, OpInfo.CallOperand); 5296 OpInfo.ConstraintVT = RegVT; 5297 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5298 // If the input is a FP value and we want it in FP registers, do a 5299 // bitcast to the corresponding integer type. This turns an f64 value 5300 // into i64, which can be passed with two i32 values on a 32-bit 5301 // machine. 5302 RegVT = EVT::getIntegerVT(Context, 5303 OpInfo.ConstraintVT.getSizeInBits()); 5304 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5305 RegVT, OpInfo.CallOperand); 5306 OpInfo.ConstraintVT = RegVT; 5307 } 5308 } 5309 5310 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5311 } 5312 5313 EVT RegVT; 5314 EVT ValueVT = OpInfo.ConstraintVT; 5315 5316 // If this is a constraint for a specific physical register, like {r17}, 5317 // assign it now. 5318 if (unsigned AssignedReg = PhysReg.first) { 5319 const TargetRegisterClass *RC = PhysReg.second; 5320 if (OpInfo.ConstraintVT == MVT::Other) 5321 ValueVT = *RC->vt_begin(); 5322 5323 // Get the actual register value type. This is important, because the user 5324 // may have asked for (e.g.) the AX register in i32 type. We need to 5325 // remember that AX is actually i16 to get the right extension. 5326 RegVT = *RC->vt_begin(); 5327 5328 // This is a explicit reference to a physical register. 5329 Regs.push_back(AssignedReg); 5330 5331 // If this is an expanded reference, add the rest of the regs to Regs. 5332 if (NumRegs != 1) { 5333 TargetRegisterClass::iterator I = RC->begin(); 5334 for (; *I != AssignedReg; ++I) 5335 assert(I != RC->end() && "Didn't find reg!"); 5336 5337 // Already added the first reg. 5338 --NumRegs; ++I; 5339 for (; NumRegs; --NumRegs, ++I) { 5340 assert(I != RC->end() && "Ran out of registers to allocate!"); 5341 Regs.push_back(*I); 5342 } 5343 } 5344 5345 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5346 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5347 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5348 return; 5349 } 5350 5351 // Otherwise, if this was a reference to an LLVM register class, create vregs 5352 // for this reference. 5353 if (const TargetRegisterClass *RC = PhysReg.second) { 5354 RegVT = *RC->vt_begin(); 5355 if (OpInfo.ConstraintVT == MVT::Other) 5356 ValueVT = RegVT; 5357 5358 // Create the appropriate number of virtual registers. 5359 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5360 for (; NumRegs; --NumRegs) 5361 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5362 5363 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5364 return; 5365 } 5366 5367 // This is a reference to a register class that doesn't directly correspond 5368 // to an LLVM register class. Allocate NumRegs consecutive, available, 5369 // registers from the class. 5370 std::vector<unsigned> RegClassRegs 5371 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5372 OpInfo.ConstraintVT); 5373 5374 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5375 unsigned NumAllocated = 0; 5376 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5377 unsigned Reg = RegClassRegs[i]; 5378 // See if this register is available. 5379 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5380 (isInReg && InputRegs.count(Reg))) { // Already used. 5381 // Make sure we find consecutive registers. 5382 NumAllocated = 0; 5383 continue; 5384 } 5385 5386 // Check to see if this register is allocatable (i.e. don't give out the 5387 // stack pointer). 5388 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5389 if (!RC) { // Couldn't allocate this register. 5390 // Reset NumAllocated to make sure we return consecutive registers. 5391 NumAllocated = 0; 5392 continue; 5393 } 5394 5395 // Okay, this register is good, we can use it. 5396 ++NumAllocated; 5397 5398 // If we allocated enough consecutive registers, succeed. 5399 if (NumAllocated == NumRegs) { 5400 unsigned RegStart = (i-NumAllocated)+1; 5401 unsigned RegEnd = i+1; 5402 // Mark all of the allocated registers used. 5403 for (unsigned i = RegStart; i != RegEnd; ++i) 5404 Regs.push_back(RegClassRegs[i]); 5405 5406 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5407 OpInfo.ConstraintVT); 5408 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5409 return; 5410 } 5411 } 5412 5413 // Otherwise, we couldn't allocate enough registers for this. 5414} 5415 5416/// visitInlineAsm - Handle a call to an InlineAsm object. 5417/// 5418void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5419 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5420 5421 /// ConstraintOperands - Information about all of the constraints. 5422 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5423 5424 std::set<unsigned> OutputRegs, InputRegs; 5425 5426 std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(CS); 5427 bool hasMemory = false; 5428 5429 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5430 unsigned ResNo = 0; // ResNo - The result number of the next output. 5431 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5432 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5433 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5434 5435 EVT OpVT = MVT::Other; 5436 5437 // Compute the value type for each operand. 5438 switch (OpInfo.Type) { 5439 case InlineAsm::isOutput: 5440 // Indirect outputs just consume an argument. 5441 if (OpInfo.isIndirect) { 5442 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5443 break; 5444 } 5445 5446 // The return value of the call is this value. As such, there is no 5447 // corresponding argument. 5448 assert(!CS.getType()->isVoidTy() && 5449 "Bad inline asm!"); 5450 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5451 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5452 } else { 5453 assert(ResNo == 0 && "Asm only has one result!"); 5454 OpVT = TLI.getValueType(CS.getType()); 5455 } 5456 ++ResNo; 5457 break; 5458 case InlineAsm::isInput: 5459 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5460 break; 5461 case InlineAsm::isClobber: 5462 // Nothing to do. 5463 break; 5464 } 5465 5466 // If this is an input or an indirect output, process the call argument. 5467 // BasicBlocks are labels, currently appearing only in asm's. 5468 if (OpInfo.CallOperandVal) { 5469 // Strip bitcasts, if any. This mostly comes up for functions. 5470 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5471 5472 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5473 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5474 } else { 5475 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5476 } 5477 5478 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5479 } 5480 5481 OpInfo.ConstraintVT = OpVT; 5482 5483 // Indirect operand accesses access memory. 5484 if (OpInfo.isIndirect) 5485 hasMemory = true; 5486 else { 5487 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5488 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5489 if (CType == TargetLowering::C_Memory) { 5490 hasMemory = true; 5491 break; 5492 } 5493 } 5494 } 5495 } 5496 5497 SDValue Chain, Flag; 5498 5499 // We won't need to flush pending loads if this asm doesn't touch 5500 // memory and is nonvolatile. 5501 if (hasMemory || IA->hasSideEffects()) 5502 Chain = getRoot(); 5503 else 5504 Chain = DAG.getRoot(); 5505 5506 // Second pass over the constraints: compute which constraint option to use 5507 // and assign registers to constraints that want a specific physreg. 5508 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5509 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5510 5511 // If this is an output operand with a matching input operand, look up the 5512 // matching input. If their types mismatch, e.g. one is an integer, the 5513 // other is floating point, or their sizes are different, flag it as an 5514 // error. 5515 if (OpInfo.hasMatchingInput()) { 5516 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5517 5518 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5519 if ((OpInfo.ConstraintVT.isInteger() != 5520 Input.ConstraintVT.isInteger()) || 5521 (OpInfo.ConstraintVT.getSizeInBits() != 5522 Input.ConstraintVT.getSizeInBits())) { 5523 report_fatal_error("Unsupported asm: input constraint" 5524 " with a matching output constraint of" 5525 " incompatible type!"); 5526 } 5527 Input.ConstraintVT = OpInfo.ConstraintVT; 5528 } 5529 } 5530 5531 // Compute the constraint code and ConstraintType to use. 5532 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5533 5534 // If this is a memory input, and if the operand is not indirect, do what we 5535 // need to to provide an address for the memory input. 5536 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5537 !OpInfo.isIndirect) { 5538 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5539 "Can only indirectify direct input operands!"); 5540 5541 // Memory operands really want the address of the value. If we don't have 5542 // an indirect input, put it in the constpool if we can, otherwise spill 5543 // it to a stack slot. 5544 5545 // If the operand is a float, integer, or vector constant, spill to a 5546 // constant pool entry to get its address. 5547 const Value *OpVal = OpInfo.CallOperandVal; 5548 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5549 isa<ConstantVector>(OpVal)) { 5550 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5551 TLI.getPointerTy()); 5552 } else { 5553 // Otherwise, create a stack slot and emit a store to it before the 5554 // asm. 5555 const Type *Ty = OpVal->getType(); 5556 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5557 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5558 MachineFunction &MF = DAG.getMachineFunction(); 5559 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5560 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5561 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5562 OpInfo.CallOperand, StackSlot, 5563 MachinePointerInfo::getFixedStack(SSFI), 5564 false, false, 0); 5565 OpInfo.CallOperand = StackSlot; 5566 } 5567 5568 // There is no longer a Value* corresponding to this operand. 5569 OpInfo.CallOperandVal = 0; 5570 5571 // It is now an indirect operand. 5572 OpInfo.isIndirect = true; 5573 } 5574 5575 // If this constraint is for a specific register, allocate it before 5576 // anything else. 5577 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5578 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5579 } 5580 5581 // Second pass - Loop over all of the operands, assigning virtual or physregs 5582 // to register class operands. 5583 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5584 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5585 5586 // C_Register operands have already been allocated, Other/Memory don't need 5587 // to be. 5588 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5589 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5590 } 5591 5592 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5593 std::vector<SDValue> AsmNodeOperands; 5594 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5595 AsmNodeOperands.push_back( 5596 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5597 TLI.getPointerTy())); 5598 5599 // If we have a !srcloc metadata node associated with it, we want to attach 5600 // this to the ultimately generated inline asm machineinstr. To do this, we 5601 // pass in the third operand as this (potentially null) inline asm MDNode. 5602 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5603 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5604 5605 // Remember the AlignStack bit as operand 3. 5606 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5607 MVT::i1)); 5608 5609 // Loop over all of the inputs, copying the operand values into the 5610 // appropriate registers and processing the output regs. 5611 RegsForValue RetValRegs; 5612 5613 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5614 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5615 5616 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5617 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5618 5619 switch (OpInfo.Type) { 5620 case InlineAsm::isOutput: { 5621 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5622 OpInfo.ConstraintType != TargetLowering::C_Register) { 5623 // Memory output, or 'other' output (e.g. 'X' constraint). 5624 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5625 5626 // Add information to the INLINEASM node to know about this output. 5627 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5628 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5629 TLI.getPointerTy())); 5630 AsmNodeOperands.push_back(OpInfo.CallOperand); 5631 break; 5632 } 5633 5634 // Otherwise, this is a register or register class output. 5635 5636 // Copy the output from the appropriate register. Find a register that 5637 // we can use. 5638 if (OpInfo.AssignedRegs.Regs.empty()) 5639 report_fatal_error("Couldn't allocate output reg for constraint '" + 5640 Twine(OpInfo.ConstraintCode) + "'!"); 5641 5642 // If this is an indirect operand, store through the pointer after the 5643 // asm. 5644 if (OpInfo.isIndirect) { 5645 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5646 OpInfo.CallOperandVal)); 5647 } else { 5648 // This is the result value of the call. 5649 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5650 // Concatenate this output onto the outputs list. 5651 RetValRegs.append(OpInfo.AssignedRegs); 5652 } 5653 5654 // Add information to the INLINEASM node to know that this register is 5655 // set. 5656 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5657 InlineAsm::Kind_RegDefEarlyClobber : 5658 InlineAsm::Kind_RegDef, 5659 false, 5660 0, 5661 DAG, 5662 AsmNodeOperands); 5663 break; 5664 } 5665 case InlineAsm::isInput: { 5666 SDValue InOperandVal = OpInfo.CallOperand; 5667 5668 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5669 // If this is required to match an output register we have already set, 5670 // just use its register. 5671 unsigned OperandNo = OpInfo.getMatchedOperand(); 5672 5673 // Scan until we find the definition we already emitted of this operand. 5674 // When we find it, create a RegsForValue operand. 5675 unsigned CurOp = InlineAsm::Op_FirstOperand; 5676 for (; OperandNo; --OperandNo) { 5677 // Advance to the next operand. 5678 unsigned OpFlag = 5679 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5680 assert((InlineAsm::isRegDefKind(OpFlag) || 5681 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5682 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5683 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5684 } 5685 5686 unsigned OpFlag = 5687 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5688 if (InlineAsm::isRegDefKind(OpFlag) || 5689 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5690 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5691 if (OpInfo.isIndirect) { 5692 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5693 LLVMContext &Ctx = *DAG.getContext(); 5694 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5695 " don't know how to handle tied " 5696 "indirect register inputs"); 5697 } 5698 5699 RegsForValue MatchedRegs; 5700 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5701 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5702 MatchedRegs.RegVTs.push_back(RegVT); 5703 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5704 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5705 i != e; ++i) 5706 MatchedRegs.Regs.push_back 5707 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5708 5709 // Use the produced MatchedRegs object to 5710 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5711 Chain, &Flag); 5712 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5713 true, OpInfo.getMatchedOperand(), 5714 DAG, AsmNodeOperands); 5715 break; 5716 } 5717 5718 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5719 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5720 "Unexpected number of operands"); 5721 // Add information to the INLINEASM node to know about this input. 5722 // See InlineAsm.h isUseOperandTiedToDef. 5723 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5724 OpInfo.getMatchedOperand()); 5725 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5726 TLI.getPointerTy())); 5727 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5728 break; 5729 } 5730 5731 // Treat indirect 'X' constraint as memory. 5732 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5733 OpInfo.isIndirect) 5734 OpInfo.ConstraintType = TargetLowering::C_Memory; 5735 5736 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5737 std::vector<SDValue> Ops; 5738 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5739 Ops, DAG); 5740 if (Ops.empty()) 5741 report_fatal_error("Invalid operand for inline asm constraint '" + 5742 Twine(OpInfo.ConstraintCode) + "'!"); 5743 5744 // Add information to the INLINEASM node to know about this input. 5745 unsigned ResOpType = 5746 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5747 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5748 TLI.getPointerTy())); 5749 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5750 break; 5751 } 5752 5753 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5754 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5755 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5756 "Memory operands expect pointer values"); 5757 5758 // Add information to the INLINEASM node to know about this input. 5759 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5760 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5761 TLI.getPointerTy())); 5762 AsmNodeOperands.push_back(InOperandVal); 5763 break; 5764 } 5765 5766 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5767 OpInfo.ConstraintType == TargetLowering::C_Register) && 5768 "Unknown constraint type!"); 5769 assert(!OpInfo.isIndirect && 5770 "Don't know how to handle indirect register inputs yet!"); 5771 5772 // Copy the input into the appropriate registers. 5773 if (OpInfo.AssignedRegs.Regs.empty() || 5774 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5775 report_fatal_error("Couldn't allocate input reg for constraint '" + 5776 Twine(OpInfo.ConstraintCode) + "'!"); 5777 5778 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5779 Chain, &Flag); 5780 5781 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5782 DAG, AsmNodeOperands); 5783 break; 5784 } 5785 case InlineAsm::isClobber: { 5786 // Add the clobbered value to the operand list, so that the register 5787 // allocator is aware that the physreg got clobbered. 5788 if (!OpInfo.AssignedRegs.Regs.empty()) 5789 OpInfo.AssignedRegs.AddInlineAsmOperands( 5790 InlineAsm::Kind_RegDefEarlyClobber, 5791 false, 0, DAG, 5792 AsmNodeOperands); 5793 break; 5794 } 5795 } 5796 } 5797 5798 // Finish up input operands. Set the input chain and add the flag last. 5799 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5800 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5801 5802 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5803 DAG.getVTList(MVT::Other, MVT::Flag), 5804 &AsmNodeOperands[0], AsmNodeOperands.size()); 5805 Flag = Chain.getValue(1); 5806 5807 // If this asm returns a register value, copy the result from that register 5808 // and set it as the value of the call. 5809 if (!RetValRegs.Regs.empty()) { 5810 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5811 Chain, &Flag); 5812 5813 // FIXME: Why don't we do this for inline asms with MRVs? 5814 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5815 EVT ResultType = TLI.getValueType(CS.getType()); 5816 5817 // If any of the results of the inline asm is a vector, it may have the 5818 // wrong width/num elts. This can happen for register classes that can 5819 // contain multiple different value types. The preg or vreg allocated may 5820 // not have the same VT as was expected. Convert it to the right type 5821 // with bit_convert. 5822 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5823 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5824 ResultType, Val); 5825 5826 } else if (ResultType != Val.getValueType() && 5827 ResultType.isInteger() && Val.getValueType().isInteger()) { 5828 // If a result value was tied to an input value, the computed result may 5829 // have a wider width than the expected result. Extract the relevant 5830 // portion. 5831 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5832 } 5833 5834 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5835 } 5836 5837 setValue(CS.getInstruction(), Val); 5838 // Don't need to use this as a chain in this case. 5839 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5840 return; 5841 } 5842 5843 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5844 5845 // Process indirect outputs, first output all of the flagged copies out of 5846 // physregs. 5847 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5848 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5849 const Value *Ptr = IndirectStoresToEmit[i].second; 5850 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5851 Chain, &Flag); 5852 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5853 } 5854 5855 // Emit the non-flagged stores from the physregs. 5856 SmallVector<SDValue, 8> OutChains; 5857 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5858 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5859 StoresToEmit[i].first, 5860 getValue(StoresToEmit[i].second), 5861 MachinePointerInfo(StoresToEmit[i].second), 5862 false, false, 0); 5863 OutChains.push_back(Val); 5864 } 5865 5866 if (!OutChains.empty()) 5867 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5868 &OutChains[0], OutChains.size()); 5869 5870 DAG.setRoot(Chain); 5871} 5872 5873void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5874 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5875 MVT::Other, getRoot(), 5876 getValue(I.getArgOperand(0)), 5877 DAG.getSrcValue(I.getArgOperand(0)))); 5878} 5879 5880void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5881 const TargetData &TD = *TLI.getTargetData(); 5882 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5883 getRoot(), getValue(I.getOperand(0)), 5884 DAG.getSrcValue(I.getOperand(0)), 5885 TD.getABITypeAlignment(I.getType())); 5886 setValue(&I, V); 5887 DAG.setRoot(V.getValue(1)); 5888} 5889 5890void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5891 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5892 MVT::Other, getRoot(), 5893 getValue(I.getArgOperand(0)), 5894 DAG.getSrcValue(I.getArgOperand(0)))); 5895} 5896 5897void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5898 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5899 MVT::Other, getRoot(), 5900 getValue(I.getArgOperand(0)), 5901 getValue(I.getArgOperand(1)), 5902 DAG.getSrcValue(I.getArgOperand(0)), 5903 DAG.getSrcValue(I.getArgOperand(1)))); 5904} 5905 5906/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5907/// implementation, which just calls LowerCall. 5908/// FIXME: When all targets are 5909/// migrated to using LowerCall, this hook should be integrated into SDISel. 5910std::pair<SDValue, SDValue> 5911TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5912 bool RetSExt, bool RetZExt, bool isVarArg, 5913 bool isInreg, unsigned NumFixedArgs, 5914 CallingConv::ID CallConv, bool isTailCall, 5915 bool isReturnValueUsed, 5916 SDValue Callee, 5917 ArgListTy &Args, SelectionDAG &DAG, 5918 DebugLoc dl) const { 5919 // Handle all of the outgoing arguments. 5920 SmallVector<ISD::OutputArg, 32> Outs; 5921 SmallVector<SDValue, 32> OutVals; 5922 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5923 SmallVector<EVT, 4> ValueVTs; 5924 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5925 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5926 Value != NumValues; ++Value) { 5927 EVT VT = ValueVTs[Value]; 5928 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5929 SDValue Op = SDValue(Args[i].Node.getNode(), 5930 Args[i].Node.getResNo() + Value); 5931 ISD::ArgFlagsTy Flags; 5932 unsigned OriginalAlignment = 5933 getTargetData()->getABITypeAlignment(ArgTy); 5934 5935 if (Args[i].isZExt) 5936 Flags.setZExt(); 5937 if (Args[i].isSExt) 5938 Flags.setSExt(); 5939 if (Args[i].isInReg) 5940 Flags.setInReg(); 5941 if (Args[i].isSRet) 5942 Flags.setSRet(); 5943 if (Args[i].isByVal) { 5944 Flags.setByVal(); 5945 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5946 const Type *ElementTy = Ty->getElementType(); 5947 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5948 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5949 // For ByVal, alignment should come from FE. BE will guess if this 5950 // info is not there but there are cases it cannot get right. 5951 if (Args[i].Alignment) 5952 FrameAlign = Args[i].Alignment; 5953 Flags.setByValAlign(FrameAlign); 5954 Flags.setByValSize(FrameSize); 5955 } 5956 if (Args[i].isNest) 5957 Flags.setNest(); 5958 Flags.setOrigAlign(OriginalAlignment); 5959 5960 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5961 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5962 SmallVector<SDValue, 4> Parts(NumParts); 5963 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5964 5965 if (Args[i].isSExt) 5966 ExtendKind = ISD::SIGN_EXTEND; 5967 else if (Args[i].isZExt) 5968 ExtendKind = ISD::ZERO_EXTEND; 5969 5970 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5971 PartVT, ExtendKind); 5972 5973 for (unsigned j = 0; j != NumParts; ++j) { 5974 // if it isn't first piece, alignment must be 1 5975 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 5976 i < NumFixedArgs); 5977 if (NumParts > 1 && j == 0) 5978 MyFlags.Flags.setSplit(); 5979 else if (j != 0) 5980 MyFlags.Flags.setOrigAlign(1); 5981 5982 Outs.push_back(MyFlags); 5983 OutVals.push_back(Parts[j]); 5984 } 5985 } 5986 } 5987 5988 // Handle the incoming return values from the call. 5989 SmallVector<ISD::InputArg, 32> Ins; 5990 SmallVector<EVT, 4> RetTys; 5991 ComputeValueVTs(*this, RetTy, RetTys); 5992 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5993 EVT VT = RetTys[I]; 5994 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5995 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5996 for (unsigned i = 0; i != NumRegs; ++i) { 5997 ISD::InputArg MyFlags; 5998 MyFlags.VT = RegisterVT; 5999 MyFlags.Used = isReturnValueUsed; 6000 if (RetSExt) 6001 MyFlags.Flags.setSExt(); 6002 if (RetZExt) 6003 MyFlags.Flags.setZExt(); 6004 if (isInreg) 6005 MyFlags.Flags.setInReg(); 6006 Ins.push_back(MyFlags); 6007 } 6008 } 6009 6010 SmallVector<SDValue, 4> InVals; 6011 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6012 Outs, OutVals, Ins, dl, DAG, InVals); 6013 6014 // Verify that the target's LowerCall behaved as expected. 6015 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6016 "LowerCall didn't return a valid chain!"); 6017 assert((!isTailCall || InVals.empty()) && 6018 "LowerCall emitted a return value for a tail call!"); 6019 assert((isTailCall || InVals.size() == Ins.size()) && 6020 "LowerCall didn't emit the correct number of values!"); 6021 6022 // For a tail call, the return value is merely live-out and there aren't 6023 // any nodes in the DAG representing it. Return a special value to 6024 // indicate that a tail call has been emitted and no more Instructions 6025 // should be processed in the current block. 6026 if (isTailCall) { 6027 DAG.setRoot(Chain); 6028 return std::make_pair(SDValue(), SDValue()); 6029 } 6030 6031 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6032 assert(InVals[i].getNode() && 6033 "LowerCall emitted a null value!"); 6034 assert(Ins[i].VT == InVals[i].getValueType() && 6035 "LowerCall emitted a value with the wrong type!"); 6036 }); 6037 6038 // Collect the legal value parts into potentially illegal values 6039 // that correspond to the original function's return values. 6040 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6041 if (RetSExt) 6042 AssertOp = ISD::AssertSext; 6043 else if (RetZExt) 6044 AssertOp = ISD::AssertZext; 6045 SmallVector<SDValue, 4> ReturnValues; 6046 unsigned CurReg = 0; 6047 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6048 EVT VT = RetTys[I]; 6049 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6050 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6051 6052 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6053 NumRegs, RegisterVT, VT, 6054 AssertOp)); 6055 CurReg += NumRegs; 6056 } 6057 6058 // For a function returning void, there is no return value. We can't create 6059 // such a node, so we just return a null return value in that case. In 6060 // that case, nothing will actualy look at the value. 6061 if (ReturnValues.empty()) 6062 return std::make_pair(SDValue(), Chain); 6063 6064 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6065 DAG.getVTList(&RetTys[0], RetTys.size()), 6066 &ReturnValues[0], ReturnValues.size()); 6067 return std::make_pair(Res, Chain); 6068} 6069 6070void TargetLowering::LowerOperationWrapper(SDNode *N, 6071 SmallVectorImpl<SDValue> &Results, 6072 SelectionDAG &DAG) const { 6073 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6074 if (Res.getNode()) 6075 Results.push_back(Res); 6076} 6077 6078SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6079 llvm_unreachable("LowerOperation not implemented for this target!"); 6080 return SDValue(); 6081} 6082 6083void 6084SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6085 SDValue Op = getNonRegisterValue(V); 6086 assert((Op.getOpcode() != ISD::CopyFromReg || 6087 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6088 "Copy from a reg to the same reg!"); 6089 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6090 6091 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6092 SDValue Chain = DAG.getEntryNode(); 6093 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6094 PendingExports.push_back(Chain); 6095} 6096 6097#include "llvm/CodeGen/SelectionDAGISel.h" 6098 6099void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6100 // If this is the entry block, emit arguments. 6101 const Function &F = *LLVMBB->getParent(); 6102 SelectionDAG &DAG = SDB->DAG; 6103 DebugLoc dl = SDB->getCurDebugLoc(); 6104 const TargetData *TD = TLI.getTargetData(); 6105 SmallVector<ISD::InputArg, 16> Ins; 6106 6107 // Check whether the function can return without sret-demotion. 6108 SmallVector<ISD::OutputArg, 4> Outs; 6109 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6110 Outs, TLI); 6111 6112 if (!FuncInfo->CanLowerReturn) { 6113 // Put in an sret pointer parameter before all the other parameters. 6114 SmallVector<EVT, 1> ValueVTs; 6115 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6116 6117 // NOTE: Assuming that a pointer will never break down to more than one VT 6118 // or one register. 6119 ISD::ArgFlagsTy Flags; 6120 Flags.setSRet(); 6121 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6122 ISD::InputArg RetArg(Flags, RegisterVT, true); 6123 Ins.push_back(RetArg); 6124 } 6125 6126 // Set up the incoming argument description vector. 6127 unsigned Idx = 1; 6128 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6129 I != E; ++I, ++Idx) { 6130 SmallVector<EVT, 4> ValueVTs; 6131 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6132 bool isArgValueUsed = !I->use_empty(); 6133 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6134 Value != NumValues; ++Value) { 6135 EVT VT = ValueVTs[Value]; 6136 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6137 ISD::ArgFlagsTy Flags; 6138 unsigned OriginalAlignment = 6139 TD->getABITypeAlignment(ArgTy); 6140 6141 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6142 Flags.setZExt(); 6143 if (F.paramHasAttr(Idx, Attribute::SExt)) 6144 Flags.setSExt(); 6145 if (F.paramHasAttr(Idx, Attribute::InReg)) 6146 Flags.setInReg(); 6147 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6148 Flags.setSRet(); 6149 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6150 Flags.setByVal(); 6151 const PointerType *Ty = cast<PointerType>(I->getType()); 6152 const Type *ElementTy = Ty->getElementType(); 6153 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6154 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6155 // For ByVal, alignment should be passed from FE. BE will guess if 6156 // this info is not there but there are cases it cannot get right. 6157 if (F.getParamAlignment(Idx)) 6158 FrameAlign = F.getParamAlignment(Idx); 6159 Flags.setByValAlign(FrameAlign); 6160 Flags.setByValSize(FrameSize); 6161 } 6162 if (F.paramHasAttr(Idx, Attribute::Nest)) 6163 Flags.setNest(); 6164 Flags.setOrigAlign(OriginalAlignment); 6165 6166 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6167 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6168 for (unsigned i = 0; i != NumRegs; ++i) { 6169 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6170 if (NumRegs > 1 && i == 0) 6171 MyFlags.Flags.setSplit(); 6172 // if it isn't first piece, alignment must be 1 6173 else if (i > 0) 6174 MyFlags.Flags.setOrigAlign(1); 6175 Ins.push_back(MyFlags); 6176 } 6177 } 6178 } 6179 6180 // Call the target to set up the argument values. 6181 SmallVector<SDValue, 8> InVals; 6182 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6183 F.isVarArg(), Ins, 6184 dl, DAG, InVals); 6185 6186 // Verify that the target's LowerFormalArguments behaved as expected. 6187 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6188 "LowerFormalArguments didn't return a valid chain!"); 6189 assert(InVals.size() == Ins.size() && 6190 "LowerFormalArguments didn't emit the correct number of values!"); 6191 DEBUG({ 6192 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6193 assert(InVals[i].getNode() && 6194 "LowerFormalArguments emitted a null value!"); 6195 assert(Ins[i].VT == InVals[i].getValueType() && 6196 "LowerFormalArguments emitted a value with the wrong type!"); 6197 } 6198 }); 6199 6200 // Update the DAG with the new chain value resulting from argument lowering. 6201 DAG.setRoot(NewRoot); 6202 6203 // Set up the argument values. 6204 unsigned i = 0; 6205 Idx = 1; 6206 if (!FuncInfo->CanLowerReturn) { 6207 // Create a virtual register for the sret pointer, and put in a copy 6208 // from the sret argument into it. 6209 SmallVector<EVT, 1> ValueVTs; 6210 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6211 EVT VT = ValueVTs[0]; 6212 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6213 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6214 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6215 RegVT, VT, AssertOp); 6216 6217 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6218 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6219 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6220 FuncInfo->DemoteRegister = SRetReg; 6221 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6222 SRetReg, ArgValue); 6223 DAG.setRoot(NewRoot); 6224 6225 // i indexes lowered arguments. Bump it past the hidden sret argument. 6226 // Idx indexes LLVM arguments. Don't touch it. 6227 ++i; 6228 } 6229 6230 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6231 ++I, ++Idx) { 6232 SmallVector<SDValue, 4> ArgValues; 6233 SmallVector<EVT, 4> ValueVTs; 6234 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6235 unsigned NumValues = ValueVTs.size(); 6236 6237 // If this argument is unused then remember its value. It is used to generate 6238 // debugging information. 6239 if (I->use_empty() && NumValues) 6240 SDB->setUnusedArgValue(I, InVals[i]); 6241 6242 for (unsigned Value = 0; Value != NumValues; ++Value) { 6243 EVT VT = ValueVTs[Value]; 6244 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6245 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6246 6247 if (!I->use_empty()) { 6248 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6249 if (F.paramHasAttr(Idx, Attribute::SExt)) 6250 AssertOp = ISD::AssertSext; 6251 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6252 AssertOp = ISD::AssertZext; 6253 6254 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6255 NumParts, PartVT, VT, 6256 AssertOp)); 6257 } 6258 6259 i += NumParts; 6260 } 6261 6262 // Note down frame index for byval arguments. 6263 if (I->hasByValAttr() && !ArgValues.empty()) 6264 if (FrameIndexSDNode *FI = 6265 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6266 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6267 6268 if (!I->use_empty()) { 6269 SDValue Res; 6270 if (!ArgValues.empty()) 6271 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6272 SDB->getCurDebugLoc()); 6273 SDB->setValue(I, Res); 6274 6275 // If this argument is live outside of the entry block, insert a copy from 6276 // whereever we got it to the vreg that other BB's will reference it as. 6277 SDB->CopyToExportRegsIfNeeded(I); 6278 } 6279 } 6280 6281 assert(i == InVals.size() && "Argument register count mismatch!"); 6282 6283 // Finally, if the target has anything special to do, allow it to do so. 6284 // FIXME: this should insert code into the DAG! 6285 EmitFunctionEntryCode(); 6286} 6287 6288/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6289/// ensure constants are generated when needed. Remember the virtual registers 6290/// that need to be added to the Machine PHI nodes as input. We cannot just 6291/// directly add them, because expansion might result in multiple MBB's for one 6292/// BB. As such, the start of the BB might correspond to a different MBB than 6293/// the end. 6294/// 6295void 6296SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6297 const TerminatorInst *TI = LLVMBB->getTerminator(); 6298 6299 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6300 6301 // Check successor nodes' PHI nodes that expect a constant to be available 6302 // from this block. 6303 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6304 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6305 if (!isa<PHINode>(SuccBB->begin())) continue; 6306 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6307 6308 // If this terminator has multiple identical successors (common for 6309 // switches), only handle each succ once. 6310 if (!SuccsHandled.insert(SuccMBB)) continue; 6311 6312 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6313 6314 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6315 // nodes and Machine PHI nodes, but the incoming operands have not been 6316 // emitted yet. 6317 for (BasicBlock::const_iterator I = SuccBB->begin(); 6318 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6319 // Ignore dead phi's. 6320 if (PN->use_empty()) continue; 6321 6322 unsigned Reg; 6323 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6324 6325 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6326 unsigned &RegOut = ConstantsOut[C]; 6327 if (RegOut == 0) { 6328 RegOut = FuncInfo.CreateRegs(C->getType()); 6329 CopyValueToVirtualRegister(C, RegOut); 6330 } 6331 Reg = RegOut; 6332 } else { 6333 DenseMap<const Value *, unsigned>::iterator I = 6334 FuncInfo.ValueMap.find(PHIOp); 6335 if (I != FuncInfo.ValueMap.end()) 6336 Reg = I->second; 6337 else { 6338 assert(isa<AllocaInst>(PHIOp) && 6339 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6340 "Didn't codegen value into a register!??"); 6341 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6342 CopyValueToVirtualRegister(PHIOp, Reg); 6343 } 6344 } 6345 6346 // Remember that this register needs to added to the machine PHI node as 6347 // the input for this MBB. 6348 SmallVector<EVT, 4> ValueVTs; 6349 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6350 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6351 EVT VT = ValueVTs[vti]; 6352 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6353 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6354 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6355 Reg += NumRegisters; 6356 } 6357 } 6358 } 6359 ConstantsOut.clear(); 6360} 6361