SelectionDAGBuilder.cpp revision 1ee0ecf84a07693c3a517ba030fac8ac1f9f3fbc
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getTargetConstant(1, TLI.getPointerTy())); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209} 210 211/// getCopyFromParts - Create a value that contains the specified legal parts 212/// combined into the value they represent. If the parts combine to a type 213/// larger then ValueVT then AssertOp can be used to specify whether the extra 214/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 215/// (ISD::AssertSext). 216static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 217 const SDValue *Parts, unsigned NumParts, 218 EVT PartVT, EVT ValueVT) { 219 assert(ValueVT.isVector() && "Not a vector value"); 220 assert(NumParts > 0 && "No parts to assemble!"); 221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 222 SDValue Val = Parts[0]; 223 224 // Handle a multi-element vector. 225 if (NumParts > 1) { 226 EVT IntermediateVT, RegisterVT; 227 unsigned NumIntermediates; 228 unsigned NumRegs = 229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 230 NumIntermediates, RegisterVT); 231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 232 NumParts = NumRegs; // Silence a compiler warning. 233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 234 assert(RegisterVT == Parts[0].getValueType() && 235 "Part type doesn't match part!"); 236 237 // Assemble the parts into intermediate operands. 238 SmallVector<SDValue, 8> Ops(NumIntermediates); 239 if (NumIntermediates == NumParts) { 240 // If the register was not expanded, truncate or copy the value, 241 // as appropriate. 242 for (unsigned i = 0; i != NumParts; ++i) 243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 244 PartVT, IntermediateVT); 245 } else if (NumParts > 0) { 246 // If the intermediate type was expanded, build the intermediate 247 // operands from the parts. 248 assert(NumParts % NumIntermediates == 0 && 249 "Must expand into a divisible number of parts!"); 250 unsigned Factor = NumParts / NumIntermediates; 251 for (unsigned i = 0; i != NumIntermediates; ++i) 252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 253 PartVT, IntermediateVT); 254 } 255 256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 257 // intermediate operands. 258 Val = DAG.getNode(IntermediateVT.isVector() ? 259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 260 ValueVT, &Ops[0], NumIntermediates); 261 } 262 263 // There is now one part, held in Val. Correct it to match ValueVT. 264 PartVT = Val.getValueType(); 265 266 if (PartVT == ValueVT) 267 return Val; 268 269 if (PartVT.isVector()) { 270 // If the element type of the source/dest vectors are the same, but the 271 // parts vector has more elements than the value vector, then we have a 272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 273 // elements we want. 274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 276 "Cannot narrow, it would be a lossy transformation"); 277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 278 DAG.getIntPtrConstant(0)); 279 } 280 281 // Vector/Vector bitcast. 282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 284 285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 286 "Cannot handle this kind of promotion"); 287 // Promoted vector extract 288 bool Smaller = ValueVT.bitsLE(PartVT); 289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 290 DL, ValueVT, Val); 291 292 } 293 294 // Trivial bitcast if the types are the same size and the destination 295 // vector type is legal. 296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 297 TLI.isTypeLegal(ValueVT)) 298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 299 300 // Handle cases such as i8 -> <1 x i1> 301 assert(ValueVT.getVectorNumElements() == 1 && 302 "Only trivial scalar-to-vector conversions should get here!"); 303 304 if (ValueVT.getVectorNumElements() == 1 && 305 ValueVT.getVectorElementType() != PartVT) { 306 bool Smaller = ValueVT.bitsLE(PartVT); 307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 308 DL, ValueVT.getScalarType(), Val); 309 } 310 311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 312} 313 314 315 316 317static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 318 SDValue Val, SDValue *Parts, unsigned NumParts, 319 EVT PartVT); 320 321/// getCopyToParts - Create a series of nodes that contain the specified value 322/// split into legal parts. If the parts contain more bits than Val, then, for 323/// integers, ExtendKind can be used to specify how to generate the extra bits. 324static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 325 SDValue Val, SDValue *Parts, unsigned NumParts, 326 EVT PartVT, 327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 328 EVT ValueVT = Val.getValueType(); 329 330 // Handle the vector case separately. 331 if (ValueVT.isVector()) 332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 333 334 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 335 unsigned PartBits = PartVT.getSizeInBits(); 336 unsigned OrigNumParts = NumParts; 337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 338 339 if (NumParts == 0) 340 return; 341 342 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 343 if (PartVT == ValueVT) { 344 assert(NumParts == 1 && "No-op copy with multiple parts!"); 345 Parts[0] = Val; 346 return; 347 } 348 349 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 350 // If the parts cover more bits than the value has, promote the value. 351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 352 assert(NumParts == 1 && "Do not know what to promote to!"); 353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 354 } else { 355 assert(PartVT.isInteger() && ValueVT.isInteger() && 356 "Unknown mismatch!"); 357 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 358 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 359 } 360 } else if (PartBits == ValueVT.getSizeInBits()) { 361 // Different types of the same size. 362 assert(NumParts == 1 && PartVT != ValueVT); 363 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 364 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 365 // If the parts cover less bits than value has, truncate the value. 366 assert(PartVT.isInteger() && ValueVT.isInteger() && 367 "Unknown mismatch!"); 368 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 369 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 370 } 371 372 // The value may have changed - recompute ValueVT. 373 ValueVT = Val.getValueType(); 374 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 375 "Failed to tile the value with PartVT!"); 376 377 if (NumParts == 1) { 378 assert(PartVT == ValueVT && "Type conversion failed!"); 379 Parts[0] = Val; 380 return; 381 } 382 383 // Expand the value into multiple parts. 384 if (NumParts & (NumParts - 1)) { 385 // The number of parts is not a power of 2. Split off and copy the tail. 386 assert(PartVT.isInteger() && ValueVT.isInteger() && 387 "Do not know what to expand to!"); 388 unsigned RoundParts = 1 << Log2_32(NumParts); 389 unsigned RoundBits = RoundParts * PartBits; 390 unsigned OddParts = NumParts - RoundParts; 391 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 392 DAG.getIntPtrConstant(RoundBits)); 393 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 394 395 if (TLI.isBigEndian()) 396 // The odd parts were reversed by getCopyToParts - unreverse them. 397 std::reverse(Parts + RoundParts, Parts + NumParts); 398 399 NumParts = RoundParts; 400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 402 } 403 404 // The number of parts is a power of 2. Repeatedly bisect the value using 405 // EXTRACT_ELEMENT. 406 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 407 EVT::getIntegerVT(*DAG.getContext(), 408 ValueVT.getSizeInBits()), 409 Val); 410 411 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 412 for (unsigned i = 0; i < NumParts; i += StepSize) { 413 unsigned ThisBits = StepSize * PartBits / 2; 414 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 415 SDValue &Part0 = Parts[i]; 416 SDValue &Part1 = Parts[i+StepSize/2]; 417 418 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 419 ThisVT, Part0, DAG.getIntPtrConstant(1)); 420 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 421 ThisVT, Part0, DAG.getIntPtrConstant(0)); 422 423 if (ThisBits == PartBits && ThisVT != PartVT) { 424 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 425 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 426 } 427 } 428 } 429 430 if (TLI.isBigEndian()) 431 std::reverse(Parts, Parts + OrigNumParts); 432} 433 434 435/// getCopyToPartsVector - Create a series of nodes that contain the specified 436/// value split into legal parts. 437static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 438 SDValue Val, SDValue *Parts, unsigned NumParts, 439 EVT PartVT) { 440 EVT ValueVT = Val.getValueType(); 441 assert(ValueVT.isVector() && "Not a vector"); 442 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 443 444 if (NumParts == 1) { 445 if (PartVT == ValueVT) { 446 // Nothing to do. 447 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 448 // Bitconvert vector->vector case. 449 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 450 } else if (PartVT.isVector() && 451 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 452 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 453 EVT ElementVT = PartVT.getVectorElementType(); 454 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 455 // undef elements. 456 SmallVector<SDValue, 16> Ops; 457 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 458 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 459 ElementVT, Val, DAG.getIntPtrConstant(i))); 460 461 for (unsigned i = ValueVT.getVectorNumElements(), 462 e = PartVT.getVectorNumElements(); i != e; ++i) 463 Ops.push_back(DAG.getUNDEF(ElementVT)); 464 465 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 466 467 // FIXME: Use CONCAT for 2x -> 4x. 468 469 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 470 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 471 } else if (PartVT.isVector() && 472 PartVT.getVectorElementType().bitsGE( 473 ValueVT.getVectorElementType()) && 474 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 475 476 // Promoted vector extract 477 bool Smaller = PartVT.bitsLE(ValueVT); 478 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 479 DL, PartVT, Val); 480 } else{ 481 // Vector -> scalar conversion. 482 assert(ValueVT.getVectorNumElements() == 1 && 483 "Only trivial vector-to-scalar conversions should get here!"); 484 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 485 PartVT, Val, DAG.getIntPtrConstant(0)); 486 487 bool Smaller = ValueVT.bitsLE(PartVT); 488 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 489 DL, PartVT, Val); 490 } 491 492 Parts[0] = Val; 493 return; 494 } 495 496 // Handle a multi-element vector. 497 EVT IntermediateVT, RegisterVT; 498 unsigned NumIntermediates; 499 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 500 IntermediateVT, 501 NumIntermediates, RegisterVT); 502 unsigned NumElements = ValueVT.getVectorNumElements(); 503 504 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 505 NumParts = NumRegs; // Silence a compiler warning. 506 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 507 508 // Split the vector into intermediate operands. 509 SmallVector<SDValue, 8> Ops(NumIntermediates); 510 for (unsigned i = 0; i != NumIntermediates; ++i) { 511 if (IntermediateVT.isVector()) 512 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 513 IntermediateVT, Val, 514 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 515 else 516 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 517 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 518 } 519 520 // Split the intermediate operands into legal parts. 521 if (NumParts == NumIntermediates) { 522 // If the register was not expanded, promote or copy the value, 523 // as appropriate. 524 for (unsigned i = 0; i != NumParts; ++i) 525 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 526 } else if (NumParts > 0) { 527 // If the intermediate type was expanded, split each the value into 528 // legal parts. 529 assert(NumParts % NumIntermediates == 0 && 530 "Must expand into a divisible number of parts!"); 531 unsigned Factor = NumParts / NumIntermediates; 532 for (unsigned i = 0; i != NumIntermediates; ++i) 533 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 534 } 535} 536 537 538 539 540namespace { 541 /// RegsForValue - This struct represents the registers (physical or virtual) 542 /// that a particular set of values is assigned, and the type information 543 /// about the value. The most common situation is to represent one value at a 544 /// time, but struct or array values are handled element-wise as multiple 545 /// values. The splitting of aggregates is performed recursively, so that we 546 /// never have aggregate-typed registers. The values at this point do not 547 /// necessarily have legal types, so each value may require one or more 548 /// registers of some legal type. 549 /// 550 struct RegsForValue { 551 /// ValueVTs - The value types of the values, which may not be legal, and 552 /// may need be promoted or synthesized from one or more registers. 553 /// 554 SmallVector<EVT, 4> ValueVTs; 555 556 /// RegVTs - The value types of the registers. This is the same size as 557 /// ValueVTs and it records, for each value, what the type of the assigned 558 /// register or registers are. (Individual values are never synthesized 559 /// from more than one type of register.) 560 /// 561 /// With virtual registers, the contents of RegVTs is redundant with TLI's 562 /// getRegisterType member function, however when with physical registers 563 /// it is necessary to have a separate record of the types. 564 /// 565 SmallVector<EVT, 4> RegVTs; 566 567 /// Regs - This list holds the registers assigned to the values. 568 /// Each legal or promoted value requires one register, and each 569 /// expanded value requires multiple registers. 570 /// 571 SmallVector<unsigned, 4> Regs; 572 573 RegsForValue() {} 574 575 RegsForValue(const SmallVector<unsigned, 4> ®s, 576 EVT regvt, EVT valuevt) 577 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 578 579 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 580 unsigned Reg, Type *Ty) { 581 ComputeValueVTs(tli, Ty, ValueVTs); 582 583 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 584 EVT ValueVT = ValueVTs[Value]; 585 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 586 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 587 for (unsigned i = 0; i != NumRegs; ++i) 588 Regs.push_back(Reg + i); 589 RegVTs.push_back(RegisterVT); 590 Reg += NumRegs; 591 } 592 } 593 594 /// areValueTypesLegal - Return true if types of all the values are legal. 595 bool areValueTypesLegal(const TargetLowering &TLI) { 596 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 597 EVT RegisterVT = RegVTs[Value]; 598 if (!TLI.isTypeLegal(RegisterVT)) 599 return false; 600 } 601 return true; 602 } 603 604 /// append - Add the specified values to this one. 605 void append(const RegsForValue &RHS) { 606 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 607 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 608 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 609 } 610 611 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 612 /// this value and returns the result as a ValueVTs value. This uses 613 /// Chain/Flag as the input and updates them for the output Chain/Flag. 614 /// If the Flag pointer is NULL, no flag is used. 615 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 616 DebugLoc dl, 617 SDValue &Chain, SDValue *Flag) const; 618 619 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 620 /// specified value into the registers specified by this object. This uses 621 /// Chain/Flag as the input and updates them for the output Chain/Flag. 622 /// If the Flag pointer is NULL, no flag is used. 623 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 624 SDValue &Chain, SDValue *Flag) const; 625 626 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 627 /// operand list. This adds the code marker, matching input operand index 628 /// (if applicable), and includes the number of values added into it. 629 void AddInlineAsmOperands(unsigned Kind, 630 bool HasMatching, unsigned MatchingIdx, 631 SelectionDAG &DAG, 632 std::vector<SDValue> &Ops) const; 633 }; 634} 635 636/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 637/// this value and returns the result as a ValueVT value. This uses 638/// Chain/Flag as the input and updates them for the output Chain/Flag. 639/// If the Flag pointer is NULL, no flag is used. 640SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 641 FunctionLoweringInfo &FuncInfo, 642 DebugLoc dl, 643 SDValue &Chain, SDValue *Flag) const { 644 // A Value with type {} or [0 x %t] needs no registers. 645 if (ValueVTs.empty()) 646 return SDValue(); 647 648 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 649 650 // Assemble the legal parts into the final values. 651 SmallVector<SDValue, 4> Values(ValueVTs.size()); 652 SmallVector<SDValue, 8> Parts; 653 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 654 // Copy the legal parts from the registers. 655 EVT ValueVT = ValueVTs[Value]; 656 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 657 EVT RegisterVT = RegVTs[Value]; 658 659 Parts.resize(NumRegs); 660 for (unsigned i = 0; i != NumRegs; ++i) { 661 SDValue P; 662 if (Flag == 0) { 663 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 664 } else { 665 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 666 *Flag = P.getValue(2); 667 } 668 669 Chain = P.getValue(1); 670 Parts[i] = P; 671 672 // If the source register was virtual and if we know something about it, 673 // add an assert node. 674 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 675 !RegisterVT.isInteger() || RegisterVT.isVector()) 676 continue; 677 678 const FunctionLoweringInfo::LiveOutInfo *LOI = 679 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 680 if (!LOI) 681 continue; 682 683 unsigned RegSize = RegisterVT.getSizeInBits(); 684 unsigned NumSignBits = LOI->NumSignBits; 685 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 686 687 // FIXME: We capture more information than the dag can represent. For 688 // now, just use the tightest assertzext/assertsext possible. 689 bool isSExt = true; 690 EVT FromVT(MVT::Other); 691 if (NumSignBits == RegSize) 692 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 693 else if (NumZeroBits >= RegSize-1) 694 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 695 else if (NumSignBits > RegSize-8) 696 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 697 else if (NumZeroBits >= RegSize-8) 698 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 699 else if (NumSignBits > RegSize-16) 700 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 701 else if (NumZeroBits >= RegSize-16) 702 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 703 else if (NumSignBits > RegSize-32) 704 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 705 else if (NumZeroBits >= RegSize-32) 706 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 707 else 708 continue; 709 710 // Add an assertion node. 711 assert(FromVT != MVT::Other); 712 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 713 RegisterVT, P, DAG.getValueType(FromVT)); 714 } 715 716 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 717 NumRegs, RegisterVT, ValueVT); 718 Part += NumRegs; 719 Parts.clear(); 720 } 721 722 return DAG.getNode(ISD::MERGE_VALUES, dl, 723 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 724 &Values[0], ValueVTs.size()); 725} 726 727/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 728/// specified value into the registers specified by this object. This uses 729/// Chain/Flag as the input and updates them for the output Chain/Flag. 730/// If the Flag pointer is NULL, no flag is used. 731void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 732 SDValue &Chain, SDValue *Flag) const { 733 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 734 735 // Get the list of the values's legal parts. 736 unsigned NumRegs = Regs.size(); 737 SmallVector<SDValue, 8> Parts(NumRegs); 738 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 739 EVT ValueVT = ValueVTs[Value]; 740 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 741 EVT RegisterVT = RegVTs[Value]; 742 743 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 744 &Parts[Part], NumParts, RegisterVT); 745 Part += NumParts; 746 } 747 748 // Copy the parts into the registers. 749 SmallVector<SDValue, 8> Chains(NumRegs); 750 for (unsigned i = 0; i != NumRegs; ++i) { 751 SDValue Part; 752 if (Flag == 0) { 753 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 754 } else { 755 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 756 *Flag = Part.getValue(1); 757 } 758 759 Chains[i] = Part.getValue(0); 760 } 761 762 if (NumRegs == 1 || Flag) 763 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 764 // flagged to it. That is the CopyToReg nodes and the user are considered 765 // a single scheduling unit. If we create a TokenFactor and return it as 766 // chain, then the TokenFactor is both a predecessor (operand) of the 767 // user as well as a successor (the TF operands are flagged to the user). 768 // c1, f1 = CopyToReg 769 // c2, f2 = CopyToReg 770 // c3 = TokenFactor c1, c2 771 // ... 772 // = op c3, ..., f2 773 Chain = Chains[NumRegs-1]; 774 else 775 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 776} 777 778/// AddInlineAsmOperands - Add this value to the specified inlineasm node 779/// operand list. This adds the code marker and includes the number of 780/// values added into it. 781void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 782 unsigned MatchingIdx, 783 SelectionDAG &DAG, 784 std::vector<SDValue> &Ops) const { 785 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 786 787 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 788 if (HasMatching) 789 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 790 else if (!Regs.empty() && 791 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 792 // Put the register class of the virtual registers in the flag word. That 793 // way, later passes can recompute register class constraints for inline 794 // assembly as well as normal instructions. 795 // Don't do this for tied operands that can use the regclass information 796 // from the def. 797 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 798 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 799 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 800 } 801 802 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 803 Ops.push_back(Res); 804 805 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 806 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 807 EVT RegisterVT = RegVTs[Value]; 808 for (unsigned i = 0; i != NumRegs; ++i) { 809 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 810 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 811 } 812 } 813} 814 815void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 816 const TargetLibraryInfo *li) { 817 AA = &aa; 818 GFI = gfi; 819 LibInfo = li; 820 TD = DAG.getTarget().getTargetData(); 821 LPadToCallSiteMap.clear(); 822} 823 824/// clear - Clear out the current SelectionDAG and the associated 825/// state and prepare this SelectionDAGBuilder object to be used 826/// for a new block. This doesn't clear out information about 827/// additional blocks that are needed to complete switch lowering 828/// or PHI node updating; that information is cleared out as it is 829/// consumed. 830void SelectionDAGBuilder::clear() { 831 NodeMap.clear(); 832 UnusedArgNodeMap.clear(); 833 PendingLoads.clear(); 834 PendingExports.clear(); 835 CurDebugLoc = DebugLoc(); 836 HasTailCall = false; 837} 838 839/// clearDanglingDebugInfo - Clear the dangling debug information 840/// map. This function is seperated from the clear so that debug 841/// information that is dangling in a basic block can be properly 842/// resolved in a different basic block. This allows the 843/// SelectionDAG to resolve dangling debug information attached 844/// to PHI nodes. 845void SelectionDAGBuilder::clearDanglingDebugInfo() { 846 DanglingDebugInfoMap.clear(); 847} 848 849/// getRoot - Return the current virtual root of the Selection DAG, 850/// flushing any PendingLoad items. This must be done before emitting 851/// a store or any other node that may need to be ordered after any 852/// prior load instructions. 853/// 854SDValue SelectionDAGBuilder::getRoot() { 855 if (PendingLoads.empty()) 856 return DAG.getRoot(); 857 858 if (PendingLoads.size() == 1) { 859 SDValue Root = PendingLoads[0]; 860 DAG.setRoot(Root); 861 PendingLoads.clear(); 862 return Root; 863 } 864 865 // Otherwise, we have to make a token factor node. 866 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 867 &PendingLoads[0], PendingLoads.size()); 868 PendingLoads.clear(); 869 DAG.setRoot(Root); 870 return Root; 871} 872 873/// getControlRoot - Similar to getRoot, but instead of flushing all the 874/// PendingLoad items, flush all the PendingExports items. It is necessary 875/// to do this before emitting a terminator instruction. 876/// 877SDValue SelectionDAGBuilder::getControlRoot() { 878 SDValue Root = DAG.getRoot(); 879 880 if (PendingExports.empty()) 881 return Root; 882 883 // Turn all of the CopyToReg chains into one factored node. 884 if (Root.getOpcode() != ISD::EntryToken) { 885 unsigned i = 0, e = PendingExports.size(); 886 for (; i != e; ++i) { 887 assert(PendingExports[i].getNode()->getNumOperands() > 1); 888 if (PendingExports[i].getNode()->getOperand(0) == Root) 889 break; // Don't add the root if we already indirectly depend on it. 890 } 891 892 if (i == e) 893 PendingExports.push_back(Root); 894 } 895 896 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 897 &PendingExports[0], 898 PendingExports.size()); 899 PendingExports.clear(); 900 DAG.setRoot(Root); 901 return Root; 902} 903 904void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 905 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 906 DAG.AssignOrdering(Node, SDNodeOrder); 907 908 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 909 AssignOrderingToNode(Node->getOperand(I).getNode()); 910} 911 912void SelectionDAGBuilder::visit(const Instruction &I) { 913 // Set up outgoing PHI node register values before emitting the terminator. 914 if (isa<TerminatorInst>(&I)) 915 HandlePHINodesInSuccessorBlocks(I.getParent()); 916 917 CurDebugLoc = I.getDebugLoc(); 918 919 visit(I.getOpcode(), I); 920 921 if (!isa<TerminatorInst>(&I) && !HasTailCall) 922 CopyToExportRegsIfNeeded(&I); 923 924 CurDebugLoc = DebugLoc(); 925} 926 927void SelectionDAGBuilder::visitPHI(const PHINode &) { 928 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 929} 930 931void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 932 // Note: this doesn't use InstVisitor, because it has to work with 933 // ConstantExpr's in addition to instructions. 934 switch (Opcode) { 935 default: llvm_unreachable("Unknown instruction type encountered!"); 936 // Build the switch statement using the Instruction.def file. 937#define HANDLE_INST(NUM, OPCODE, CLASS) \ 938 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 939#include "llvm/Instruction.def" 940 } 941 942 // Assign the ordering to the freshly created DAG nodes. 943 if (NodeMap.count(&I)) { 944 ++SDNodeOrder; 945 AssignOrderingToNode(getValue(&I).getNode()); 946 } 947} 948 949// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 950// generate the debug data structures now that we've seen its definition. 951void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 952 SDValue Val) { 953 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 954 if (DDI.getDI()) { 955 const DbgValueInst *DI = DDI.getDI(); 956 DebugLoc dl = DDI.getdl(); 957 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 958 MDNode *Variable = DI->getVariable(); 959 uint64_t Offset = DI->getOffset(); 960 SDDbgValue *SDV; 961 if (Val.getNode()) { 962 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 963 SDV = DAG.getDbgValue(Variable, Val.getNode(), 964 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 965 DAG.AddDbgValue(SDV, Val.getNode(), false); 966 } 967 } else 968 DEBUG(dbgs() << "Dropping debug info for " << DI); 969 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 970 } 971} 972 973/// getValue - Return an SDValue for the given Value. 974SDValue SelectionDAGBuilder::getValue(const Value *V) { 975 // If we already have an SDValue for this value, use it. It's important 976 // to do this first, so that we don't create a CopyFromReg if we already 977 // have a regular SDValue. 978 SDValue &N = NodeMap[V]; 979 if (N.getNode()) return N; 980 981 // If there's a virtual register allocated and initialized for this 982 // value, use it. 983 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 984 if (It != FuncInfo.ValueMap.end()) { 985 unsigned InReg = It->second; 986 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 987 SDValue Chain = DAG.getEntryNode(); 988 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 989 resolveDanglingDebugInfo(V, N); 990 return N; 991 } 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getNonRegisterValue - Return an SDValue for the given Value, but 1001/// don't look in FuncInfo.ValueMap for a virtual register. 1002SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1003 // If we already have an SDValue for this value, use it. 1004 SDValue &N = NodeMap[V]; 1005 if (N.getNode()) return N; 1006 1007 // Otherwise create a new SDValue and remember it. 1008 SDValue Val = getValueImpl(V); 1009 NodeMap[V] = Val; 1010 resolveDanglingDebugInfo(V, Val); 1011 return Val; 1012} 1013 1014/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1015/// Create an SDValue for the given value. 1016SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1017 if (const Constant *C = dyn_cast<Constant>(V)) { 1018 EVT VT = TLI.getValueType(V->getType(), true); 1019 1020 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1021 return DAG.getConstant(*CI, VT); 1022 1023 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1024 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1025 1026 if (isa<ConstantPointerNull>(C)) 1027 return DAG.getConstant(0, TLI.getPointerTy()); 1028 1029 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1030 return DAG.getConstantFP(*CFP, VT); 1031 1032 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1033 return DAG.getUNDEF(VT); 1034 1035 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1036 visit(CE->getOpcode(), *CE); 1037 SDValue N1 = NodeMap[V]; 1038 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1039 return N1; 1040 } 1041 1042 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1043 SmallVector<SDValue, 4> Constants; 1044 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1045 OI != OE; ++OI) { 1046 SDNode *Val = getValue(*OI).getNode(); 1047 // If the operand is an empty aggregate, there are no values. 1048 if (!Val) continue; 1049 // Add each leaf value from the operand to the Constants list 1050 // to form a flattened list of all the values. 1051 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1052 Constants.push_back(SDValue(Val, i)); 1053 } 1054 1055 return DAG.getMergeValues(&Constants[0], Constants.size(), 1056 getCurDebugLoc()); 1057 } 1058 1059 if (const ConstantDataSequential *CDS = 1060 dyn_cast<ConstantDataSequential>(C)) { 1061 SmallVector<SDValue, 4> Ops; 1062 for (unsigned i = 0, e = CDS->getType()->getNumElements(); i != e; ++i) { 1063 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1064 // Add each leaf value from the operand to the Constants list 1065 // to form a flattened list of all the values. 1066 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1067 Ops.push_back(SDValue(Val, i)); 1068 } 1069 1070 if (isa<ArrayType>(CDS->getType())) 1071 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1072 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1073 VT, &Ops[0], Ops.size()); 1074 } 1075 1076 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1077 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1078 "Unknown struct or array constant!"); 1079 1080 SmallVector<EVT, 4> ValueVTs; 1081 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1082 unsigned NumElts = ValueVTs.size(); 1083 if (NumElts == 0) 1084 return SDValue(); // empty struct 1085 SmallVector<SDValue, 4> Constants(NumElts); 1086 for (unsigned i = 0; i != NumElts; ++i) { 1087 EVT EltVT = ValueVTs[i]; 1088 if (isa<UndefValue>(C)) 1089 Constants[i] = DAG.getUNDEF(EltVT); 1090 else if (EltVT.isFloatingPoint()) 1091 Constants[i] = DAG.getConstantFP(0, EltVT); 1092 else 1093 Constants[i] = DAG.getConstant(0, EltVT); 1094 } 1095 1096 return DAG.getMergeValues(&Constants[0], NumElts, 1097 getCurDebugLoc()); 1098 } 1099 1100 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1101 return DAG.getBlockAddress(BA, VT); 1102 1103 VectorType *VecTy = cast<VectorType>(V->getType()); 1104 unsigned NumElements = VecTy->getNumElements(); 1105 1106 // Now that we know the number and type of the elements, get that number of 1107 // elements into the Ops array based on what kind of constant it is. 1108 SmallVector<SDValue, 16> Ops; 1109 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1110 for (unsigned i = 0; i != NumElements; ++i) 1111 Ops.push_back(getValue(CV->getOperand(i))); 1112 } else { 1113 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1114 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1115 1116 SDValue Op; 1117 if (EltVT.isFloatingPoint()) 1118 Op = DAG.getConstantFP(0, EltVT); 1119 else 1120 Op = DAG.getConstant(0, EltVT); 1121 Ops.assign(NumElements, Op); 1122 } 1123 1124 // Create a BUILD_VECTOR node. 1125 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1126 VT, &Ops[0], Ops.size()); 1127 } 1128 1129 // If this is a static alloca, generate it as the frameindex instead of 1130 // computation. 1131 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1132 DenseMap<const AllocaInst*, int>::iterator SI = 1133 FuncInfo.StaticAllocaMap.find(AI); 1134 if (SI != FuncInfo.StaticAllocaMap.end()) 1135 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1136 } 1137 1138 // If this is an instruction which fast-isel has deferred, select it now. 1139 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1140 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1141 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1142 SDValue Chain = DAG.getEntryNode(); 1143 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1144 } 1145 1146 llvm_unreachable("Can't get register for value!"); 1147} 1148 1149void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1150 SDValue Chain = getControlRoot(); 1151 SmallVector<ISD::OutputArg, 8> Outs; 1152 SmallVector<SDValue, 8> OutVals; 1153 1154 if (!FuncInfo.CanLowerReturn) { 1155 unsigned DemoteReg = FuncInfo.DemoteRegister; 1156 const Function *F = I.getParent()->getParent(); 1157 1158 // Emit a store of the return value through the virtual register. 1159 // Leave Outs empty so that LowerReturn won't try to load return 1160 // registers the usual way. 1161 SmallVector<EVT, 1> PtrValueVTs; 1162 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1163 PtrValueVTs); 1164 1165 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1166 SDValue RetOp = getValue(I.getOperand(0)); 1167 1168 SmallVector<EVT, 4> ValueVTs; 1169 SmallVector<uint64_t, 4> Offsets; 1170 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1171 unsigned NumValues = ValueVTs.size(); 1172 1173 SmallVector<SDValue, 4> Chains(NumValues); 1174 for (unsigned i = 0; i != NumValues; ++i) { 1175 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1176 RetPtr.getValueType(), RetPtr, 1177 DAG.getIntPtrConstant(Offsets[i])); 1178 Chains[i] = 1179 DAG.getStore(Chain, getCurDebugLoc(), 1180 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1181 // FIXME: better loc info would be nice. 1182 Add, MachinePointerInfo(), false, false, 0); 1183 } 1184 1185 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1186 MVT::Other, &Chains[0], NumValues); 1187 } else if (I.getNumOperands() != 0) { 1188 SmallVector<EVT, 4> ValueVTs; 1189 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1190 unsigned NumValues = ValueVTs.size(); 1191 if (NumValues) { 1192 SDValue RetOp = getValue(I.getOperand(0)); 1193 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1194 EVT VT = ValueVTs[j]; 1195 1196 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1197 1198 const Function *F = I.getParent()->getParent(); 1199 if (F->paramHasAttr(0, Attribute::SExt)) 1200 ExtendKind = ISD::SIGN_EXTEND; 1201 else if (F->paramHasAttr(0, Attribute::ZExt)) 1202 ExtendKind = ISD::ZERO_EXTEND; 1203 1204 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1205 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1206 1207 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1208 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1209 SmallVector<SDValue, 4> Parts(NumParts); 1210 getCopyToParts(DAG, getCurDebugLoc(), 1211 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1212 &Parts[0], NumParts, PartVT, ExtendKind); 1213 1214 // 'inreg' on function refers to return value 1215 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1216 if (F->paramHasAttr(0, Attribute::InReg)) 1217 Flags.setInReg(); 1218 1219 // Propagate extension type if any 1220 if (ExtendKind == ISD::SIGN_EXTEND) 1221 Flags.setSExt(); 1222 else if (ExtendKind == ISD::ZERO_EXTEND) 1223 Flags.setZExt(); 1224 1225 for (unsigned i = 0; i < NumParts; ++i) { 1226 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1227 /*isfixed=*/true)); 1228 OutVals.push_back(Parts[i]); 1229 } 1230 } 1231 } 1232 } 1233 1234 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1235 CallingConv::ID CallConv = 1236 DAG.getMachineFunction().getFunction()->getCallingConv(); 1237 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1238 Outs, OutVals, getCurDebugLoc(), DAG); 1239 1240 // Verify that the target's LowerReturn behaved as expected. 1241 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1242 "LowerReturn didn't return a valid chain!"); 1243 1244 // Update the DAG with the new chain value resulting from return lowering. 1245 DAG.setRoot(Chain); 1246} 1247 1248/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1249/// created for it, emit nodes to copy the value into the virtual 1250/// registers. 1251void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1252 // Skip empty types 1253 if (V->getType()->isEmptyTy()) 1254 return; 1255 1256 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1257 if (VMI != FuncInfo.ValueMap.end()) { 1258 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1259 CopyValueToVirtualRegister(V, VMI->second); 1260 } 1261} 1262 1263/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1264/// the current basic block, add it to ValueMap now so that we'll get a 1265/// CopyTo/FromReg. 1266void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1267 // No need to export constants. 1268 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1269 1270 // Already exported? 1271 if (FuncInfo.isExportedInst(V)) return; 1272 1273 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1274 CopyValueToVirtualRegister(V, Reg); 1275} 1276 1277bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1278 const BasicBlock *FromBB) { 1279 // The operands of the setcc have to be in this block. We don't know 1280 // how to export them from some other block. 1281 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1282 // Can export from current BB. 1283 if (VI->getParent() == FromBB) 1284 return true; 1285 1286 // Is already exported, noop. 1287 return FuncInfo.isExportedInst(V); 1288 } 1289 1290 // If this is an argument, we can export it if the BB is the entry block or 1291 // if it is already exported. 1292 if (isa<Argument>(V)) { 1293 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1294 return true; 1295 1296 // Otherwise, can only export this if it is already exported. 1297 return FuncInfo.isExportedInst(V); 1298 } 1299 1300 // Otherwise, constants can always be exported. 1301 return true; 1302} 1303 1304/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1305uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1306 const MachineBasicBlock *Dst) const { 1307 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1308 if (!BPI) 1309 return 0; 1310 const BasicBlock *SrcBB = Src->getBasicBlock(); 1311 const BasicBlock *DstBB = Dst->getBasicBlock(); 1312 return BPI->getEdgeWeight(SrcBB, DstBB); 1313} 1314 1315void SelectionDAGBuilder:: 1316addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1317 uint32_t Weight /* = 0 */) { 1318 if (!Weight) 1319 Weight = getEdgeWeight(Src, Dst); 1320 Src->addSuccessor(Dst, Weight); 1321} 1322 1323 1324static bool InBlock(const Value *V, const BasicBlock *BB) { 1325 if (const Instruction *I = dyn_cast<Instruction>(V)) 1326 return I->getParent() == BB; 1327 return true; 1328} 1329 1330/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1331/// This function emits a branch and is used at the leaves of an OR or an 1332/// AND operator tree. 1333/// 1334void 1335SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1336 MachineBasicBlock *TBB, 1337 MachineBasicBlock *FBB, 1338 MachineBasicBlock *CurBB, 1339 MachineBasicBlock *SwitchBB) { 1340 const BasicBlock *BB = CurBB->getBasicBlock(); 1341 1342 // If the leaf of the tree is a comparison, merge the condition into 1343 // the caseblock. 1344 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1345 // The operands of the cmp have to be in this block. We don't know 1346 // how to export them from some other block. If this is the first block 1347 // of the sequence, no exporting is needed. 1348 if (CurBB == SwitchBB || 1349 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1350 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1351 ISD::CondCode Condition; 1352 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1353 Condition = getICmpCondCode(IC->getPredicate()); 1354 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1355 Condition = getFCmpCondCode(FC->getPredicate()); 1356 if (TM.Options.NoNaNsFPMath) 1357 Condition = getFCmpCodeWithoutNaN(Condition); 1358 } else { 1359 Condition = ISD::SETEQ; // silence warning. 1360 llvm_unreachable("Unknown compare instruction"); 1361 } 1362 1363 CaseBlock CB(Condition, BOp->getOperand(0), 1364 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1365 SwitchCases.push_back(CB); 1366 return; 1367 } 1368 } 1369 1370 // Create a CaseBlock record representing this branch. 1371 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1372 NULL, TBB, FBB, CurBB); 1373 SwitchCases.push_back(CB); 1374} 1375 1376/// FindMergedConditions - If Cond is an expression like 1377void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1378 MachineBasicBlock *TBB, 1379 MachineBasicBlock *FBB, 1380 MachineBasicBlock *CurBB, 1381 MachineBasicBlock *SwitchBB, 1382 unsigned Opc) { 1383 // If this node is not part of the or/and tree, emit it as a branch. 1384 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1385 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1386 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1387 BOp->getParent() != CurBB->getBasicBlock() || 1388 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1389 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1390 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1391 return; 1392 } 1393 1394 // Create TmpBB after CurBB. 1395 MachineFunction::iterator BBI = CurBB; 1396 MachineFunction &MF = DAG.getMachineFunction(); 1397 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1398 CurBB->getParent()->insert(++BBI, TmpBB); 1399 1400 if (Opc == Instruction::Or) { 1401 // Codegen X | Y as: 1402 // jmp_if_X TBB 1403 // jmp TmpBB 1404 // TmpBB: 1405 // jmp_if_Y TBB 1406 // jmp FBB 1407 // 1408 1409 // Emit the LHS condition. 1410 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1411 1412 // Emit the RHS condition into TmpBB. 1413 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1414 } else { 1415 assert(Opc == Instruction::And && "Unknown merge op!"); 1416 // Codegen X & Y as: 1417 // jmp_if_X TmpBB 1418 // jmp FBB 1419 // TmpBB: 1420 // jmp_if_Y TBB 1421 // jmp FBB 1422 // 1423 // This requires creation of TmpBB after CurBB. 1424 1425 // Emit the LHS condition. 1426 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1427 1428 // Emit the RHS condition into TmpBB. 1429 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1430 } 1431} 1432 1433/// If the set of cases should be emitted as a series of branches, return true. 1434/// If we should emit this as a bunch of and/or'd together conditions, return 1435/// false. 1436bool 1437SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1438 if (Cases.size() != 2) return true; 1439 1440 // If this is two comparisons of the same values or'd or and'd together, they 1441 // will get folded into a single comparison, so don't emit two blocks. 1442 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1443 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1444 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1445 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1446 return false; 1447 } 1448 1449 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1450 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1451 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1452 Cases[0].CC == Cases[1].CC && 1453 isa<Constant>(Cases[0].CmpRHS) && 1454 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1455 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1456 return false; 1457 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1458 return false; 1459 } 1460 1461 return true; 1462} 1463 1464void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1465 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1466 1467 // Update machine-CFG edges. 1468 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1469 1470 // Figure out which block is immediately after the current one. 1471 MachineBasicBlock *NextBlock = 0; 1472 MachineFunction::iterator BBI = BrMBB; 1473 if (++BBI != FuncInfo.MF->end()) 1474 NextBlock = BBI; 1475 1476 if (I.isUnconditional()) { 1477 // Update machine-CFG edges. 1478 BrMBB->addSuccessor(Succ0MBB); 1479 1480 // If this is not a fall-through branch, emit the branch. 1481 if (Succ0MBB != NextBlock) 1482 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1483 MVT::Other, getControlRoot(), 1484 DAG.getBasicBlock(Succ0MBB))); 1485 1486 return; 1487 } 1488 1489 // If this condition is one of the special cases we handle, do special stuff 1490 // now. 1491 const Value *CondVal = I.getCondition(); 1492 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1493 1494 // If this is a series of conditions that are or'd or and'd together, emit 1495 // this as a sequence of branches instead of setcc's with and/or operations. 1496 // As long as jumps are not expensive, this should improve performance. 1497 // For example, instead of something like: 1498 // cmp A, B 1499 // C = seteq 1500 // cmp D, E 1501 // F = setle 1502 // or C, F 1503 // jnz foo 1504 // Emit: 1505 // cmp A, B 1506 // je foo 1507 // cmp D, E 1508 // jle foo 1509 // 1510 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1511 if (!TLI.isJumpExpensive() && 1512 BOp->hasOneUse() && 1513 (BOp->getOpcode() == Instruction::And || 1514 BOp->getOpcode() == Instruction::Or)) { 1515 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1516 BOp->getOpcode()); 1517 // If the compares in later blocks need to use values not currently 1518 // exported from this block, export them now. This block should always 1519 // be the first entry. 1520 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1521 1522 // Allow some cases to be rejected. 1523 if (ShouldEmitAsBranches(SwitchCases)) { 1524 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1525 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1526 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1527 } 1528 1529 // Emit the branch for this block. 1530 visitSwitchCase(SwitchCases[0], BrMBB); 1531 SwitchCases.erase(SwitchCases.begin()); 1532 return; 1533 } 1534 1535 // Okay, we decided not to do this, remove any inserted MBB's and clear 1536 // SwitchCases. 1537 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1538 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1539 1540 SwitchCases.clear(); 1541 } 1542 } 1543 1544 // Create a CaseBlock record representing this branch. 1545 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1546 NULL, Succ0MBB, Succ1MBB, BrMBB); 1547 1548 // Use visitSwitchCase to actually insert the fast branch sequence for this 1549 // cond branch. 1550 visitSwitchCase(CB, BrMBB); 1551} 1552 1553/// visitSwitchCase - Emits the necessary code to represent a single node in 1554/// the binary search tree resulting from lowering a switch instruction. 1555void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1556 MachineBasicBlock *SwitchBB) { 1557 SDValue Cond; 1558 SDValue CondLHS = getValue(CB.CmpLHS); 1559 DebugLoc dl = getCurDebugLoc(); 1560 1561 // Build the setcc now. 1562 if (CB.CmpMHS == NULL) { 1563 // Fold "(X == true)" to X and "(X == false)" to !X to 1564 // handle common cases produced by branch lowering. 1565 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1566 CB.CC == ISD::SETEQ) 1567 Cond = CondLHS; 1568 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1569 CB.CC == ISD::SETEQ) { 1570 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1571 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1572 } else 1573 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1574 } else { 1575 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1576 1577 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1578 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1579 1580 SDValue CmpOp = getValue(CB.CmpMHS); 1581 EVT VT = CmpOp.getValueType(); 1582 1583 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1584 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1585 ISD::SETLE); 1586 } else { 1587 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1588 VT, CmpOp, DAG.getConstant(Low, VT)); 1589 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1590 DAG.getConstant(High-Low, VT), ISD::SETULE); 1591 } 1592 } 1593 1594 // Update successor info 1595 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1596 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1597 1598 // Set NextBlock to be the MBB immediately after the current one, if any. 1599 // This is used to avoid emitting unnecessary branches to the next block. 1600 MachineBasicBlock *NextBlock = 0; 1601 MachineFunction::iterator BBI = SwitchBB; 1602 if (++BBI != FuncInfo.MF->end()) 1603 NextBlock = BBI; 1604 1605 // If the lhs block is the next block, invert the condition so that we can 1606 // fall through to the lhs instead of the rhs block. 1607 if (CB.TrueBB == NextBlock) { 1608 std::swap(CB.TrueBB, CB.FalseBB); 1609 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1610 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1611 } 1612 1613 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1614 MVT::Other, getControlRoot(), Cond, 1615 DAG.getBasicBlock(CB.TrueBB)); 1616 1617 // Insert the false branch. Do this even if it's a fall through branch, 1618 // this makes it easier to do DAG optimizations which require inverting 1619 // the branch condition. 1620 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1621 DAG.getBasicBlock(CB.FalseBB)); 1622 1623 DAG.setRoot(BrCond); 1624} 1625 1626/// visitJumpTable - Emit JumpTable node in the current MBB 1627void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1628 // Emit the code for the jump table 1629 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1630 EVT PTy = TLI.getPointerTy(); 1631 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1632 JT.Reg, PTy); 1633 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1634 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1635 MVT::Other, Index.getValue(1), 1636 Table, Index); 1637 DAG.setRoot(BrJumpTable); 1638} 1639 1640/// visitJumpTableHeader - This function emits necessary code to produce index 1641/// in the JumpTable from switch case. 1642void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1643 JumpTableHeader &JTH, 1644 MachineBasicBlock *SwitchBB) { 1645 // Subtract the lowest switch case value from the value being switched on and 1646 // conditional branch to default mbb if the result is greater than the 1647 // difference between smallest and largest cases. 1648 SDValue SwitchOp = getValue(JTH.SValue); 1649 EVT VT = SwitchOp.getValueType(); 1650 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1651 DAG.getConstant(JTH.First, VT)); 1652 1653 // The SDNode we just created, which holds the value being switched on minus 1654 // the smallest case value, needs to be copied to a virtual register so it 1655 // can be used as an index into the jump table in a subsequent basic block. 1656 // This value may be smaller or larger than the target's pointer type, and 1657 // therefore require extension or truncating. 1658 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1659 1660 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1661 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1662 JumpTableReg, SwitchOp); 1663 JT.Reg = JumpTableReg; 1664 1665 // Emit the range check for the jump table, and branch to the default block 1666 // for the switch statement if the value being switched on exceeds the largest 1667 // case in the switch. 1668 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1669 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1670 DAG.getConstant(JTH.Last-JTH.First,VT), 1671 ISD::SETUGT); 1672 1673 // Set NextBlock to be the MBB immediately after the current one, if any. 1674 // This is used to avoid emitting unnecessary branches to the next block. 1675 MachineBasicBlock *NextBlock = 0; 1676 MachineFunction::iterator BBI = SwitchBB; 1677 1678 if (++BBI != FuncInfo.MF->end()) 1679 NextBlock = BBI; 1680 1681 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1682 MVT::Other, CopyTo, CMP, 1683 DAG.getBasicBlock(JT.Default)); 1684 1685 if (JT.MBB != NextBlock) 1686 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1687 DAG.getBasicBlock(JT.MBB)); 1688 1689 DAG.setRoot(BrCond); 1690} 1691 1692/// visitBitTestHeader - This function emits necessary code to produce value 1693/// suitable for "bit tests" 1694void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1695 MachineBasicBlock *SwitchBB) { 1696 // Subtract the minimum value 1697 SDValue SwitchOp = getValue(B.SValue); 1698 EVT VT = SwitchOp.getValueType(); 1699 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1700 DAG.getConstant(B.First, VT)); 1701 1702 // Check range 1703 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1704 TLI.getSetCCResultType(Sub.getValueType()), 1705 Sub, DAG.getConstant(B.Range, VT), 1706 ISD::SETUGT); 1707 1708 // Determine the type of the test operands. 1709 bool UsePtrType = false; 1710 if (!TLI.isTypeLegal(VT)) 1711 UsePtrType = true; 1712 else { 1713 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1714 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1715 // Switch table case range are encoded into series of masks. 1716 // Just use pointer type, it's guaranteed to fit. 1717 UsePtrType = true; 1718 break; 1719 } 1720 } 1721 if (UsePtrType) { 1722 VT = TLI.getPointerTy(); 1723 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1724 } 1725 1726 B.RegVT = VT; 1727 B.Reg = FuncInfo.CreateReg(VT); 1728 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1729 B.Reg, Sub); 1730 1731 // Set NextBlock to be the MBB immediately after the current one, if any. 1732 // This is used to avoid emitting unnecessary branches to the next block. 1733 MachineBasicBlock *NextBlock = 0; 1734 MachineFunction::iterator BBI = SwitchBB; 1735 if (++BBI != FuncInfo.MF->end()) 1736 NextBlock = BBI; 1737 1738 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1739 1740 addSuccessorWithWeight(SwitchBB, B.Default); 1741 addSuccessorWithWeight(SwitchBB, MBB); 1742 1743 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1744 MVT::Other, CopyTo, RangeCmp, 1745 DAG.getBasicBlock(B.Default)); 1746 1747 if (MBB != NextBlock) 1748 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1749 DAG.getBasicBlock(MBB)); 1750 1751 DAG.setRoot(BrRange); 1752} 1753 1754/// visitBitTestCase - this function produces one "bit test" 1755void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1756 MachineBasicBlock* NextMBB, 1757 unsigned Reg, 1758 BitTestCase &B, 1759 MachineBasicBlock *SwitchBB) { 1760 EVT VT = BB.RegVT; 1761 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1762 Reg, VT); 1763 SDValue Cmp; 1764 unsigned PopCount = CountPopulation_64(B.Mask); 1765 if (PopCount == 1) { 1766 // Testing for a single bit; just compare the shift count with what it 1767 // would need to be to shift a 1 bit in that position. 1768 Cmp = DAG.getSetCC(getCurDebugLoc(), 1769 TLI.getSetCCResultType(VT), 1770 ShiftOp, 1771 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1772 ISD::SETEQ); 1773 } else if (PopCount == BB.Range) { 1774 // There is only one zero bit in the range, test for it directly. 1775 Cmp = DAG.getSetCC(getCurDebugLoc(), 1776 TLI.getSetCCResultType(VT), 1777 ShiftOp, 1778 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1779 ISD::SETNE); 1780 } else { 1781 // Make desired shift 1782 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1783 DAG.getConstant(1, VT), ShiftOp); 1784 1785 // Emit bit tests and jumps 1786 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1787 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1788 Cmp = DAG.getSetCC(getCurDebugLoc(), 1789 TLI.getSetCCResultType(VT), 1790 AndOp, DAG.getConstant(0, VT), 1791 ISD::SETNE); 1792 } 1793 1794 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1795 addSuccessorWithWeight(SwitchBB, NextMBB); 1796 1797 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1798 MVT::Other, getControlRoot(), 1799 Cmp, DAG.getBasicBlock(B.TargetBB)); 1800 1801 // Set NextBlock to be the MBB immediately after the current one, if any. 1802 // This is used to avoid emitting unnecessary branches to the next block. 1803 MachineBasicBlock *NextBlock = 0; 1804 MachineFunction::iterator BBI = SwitchBB; 1805 if (++BBI != FuncInfo.MF->end()) 1806 NextBlock = BBI; 1807 1808 if (NextMBB != NextBlock) 1809 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1810 DAG.getBasicBlock(NextMBB)); 1811 1812 DAG.setRoot(BrAnd); 1813} 1814 1815void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1816 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1817 1818 // Retrieve successors. 1819 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1820 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1821 1822 const Value *Callee(I.getCalledValue()); 1823 if (isa<InlineAsm>(Callee)) 1824 visitInlineAsm(&I); 1825 else 1826 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1827 1828 // If the value of the invoke is used outside of its defining block, make it 1829 // available as a virtual register. 1830 CopyToExportRegsIfNeeded(&I); 1831 1832 // Update successor info 1833 addSuccessorWithWeight(InvokeMBB, Return); 1834 addSuccessorWithWeight(InvokeMBB, LandingPad); 1835 1836 // Drop into normal successor. 1837 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1838 MVT::Other, getControlRoot(), 1839 DAG.getBasicBlock(Return))); 1840} 1841 1842void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1843} 1844 1845void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1846 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1847} 1848 1849void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1850 assert(FuncInfo.MBB->isLandingPad() && 1851 "Call to landingpad not in landing pad!"); 1852 1853 MachineBasicBlock *MBB = FuncInfo.MBB; 1854 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1855 AddLandingPadInfo(LP, MMI, MBB); 1856 1857 SmallVector<EVT, 2> ValueVTs; 1858 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1859 1860 // Insert the EXCEPTIONADDR instruction. 1861 assert(FuncInfo.MBB->isLandingPad() && 1862 "Call to eh.exception not in landing pad!"); 1863 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1864 SDValue Ops[2]; 1865 Ops[0] = DAG.getRoot(); 1866 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1867 SDValue Chain = Op1.getValue(1); 1868 1869 // Insert the EHSELECTION instruction. 1870 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1871 Ops[0] = Op1; 1872 Ops[1] = Chain; 1873 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1874 Chain = Op2.getValue(1); 1875 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1876 1877 Ops[0] = Op1; 1878 Ops[1] = Op2; 1879 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1880 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1881 &Ops[0], 2); 1882 1883 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1884 setValue(&LP, RetPair.first); 1885 DAG.setRoot(RetPair.second); 1886} 1887 1888/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1889/// small case ranges). 1890bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1891 CaseRecVector& WorkList, 1892 const Value* SV, 1893 MachineBasicBlock *Default, 1894 MachineBasicBlock *SwitchBB) { 1895 Case& BackCase = *(CR.Range.second-1); 1896 1897 // Size is the number of Cases represented by this range. 1898 size_t Size = CR.Range.second - CR.Range.first; 1899 if (Size > 3) 1900 return false; 1901 1902 // Get the MachineFunction which holds the current MBB. This is used when 1903 // inserting any additional MBBs necessary to represent the switch. 1904 MachineFunction *CurMF = FuncInfo.MF; 1905 1906 // Figure out which block is immediately after the current one. 1907 MachineBasicBlock *NextBlock = 0; 1908 MachineFunction::iterator BBI = CR.CaseBB; 1909 1910 if (++BBI != FuncInfo.MF->end()) 1911 NextBlock = BBI; 1912 1913 // If any two of the cases has the same destination, and if one value 1914 // is the same as the other, but has one bit unset that the other has set, 1915 // use bit manipulation to do two compares at once. For example: 1916 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1917 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1918 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1919 if (Size == 2 && CR.CaseBB == SwitchBB) { 1920 Case &Small = *CR.Range.first; 1921 Case &Big = *(CR.Range.second-1); 1922 1923 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1924 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1925 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1926 1927 // Check that there is only one bit different. 1928 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1929 (SmallValue | BigValue) == BigValue) { 1930 // Isolate the common bit. 1931 APInt CommonBit = BigValue & ~SmallValue; 1932 assert((SmallValue | CommonBit) == BigValue && 1933 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1934 1935 SDValue CondLHS = getValue(SV); 1936 EVT VT = CondLHS.getValueType(); 1937 DebugLoc DL = getCurDebugLoc(); 1938 1939 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1940 DAG.getConstant(CommonBit, VT)); 1941 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1942 Or, DAG.getConstant(BigValue, VT), 1943 ISD::SETEQ); 1944 1945 // Update successor info. 1946 addSuccessorWithWeight(SwitchBB, Small.BB); 1947 addSuccessorWithWeight(SwitchBB, Default); 1948 1949 // Insert the true branch. 1950 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1951 getControlRoot(), Cond, 1952 DAG.getBasicBlock(Small.BB)); 1953 1954 // Insert the false branch. 1955 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1956 DAG.getBasicBlock(Default)); 1957 1958 DAG.setRoot(BrCond); 1959 return true; 1960 } 1961 } 1962 } 1963 1964 // Rearrange the case blocks so that the last one falls through if possible. 1965 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1966 // The last case block won't fall through into 'NextBlock' if we emit the 1967 // branches in this order. See if rearranging a case value would help. 1968 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1969 if (I->BB == NextBlock) { 1970 std::swap(*I, BackCase); 1971 break; 1972 } 1973 } 1974 } 1975 1976 // Create a CaseBlock record representing a conditional branch to 1977 // the Case's target mbb if the value being switched on SV is equal 1978 // to C. 1979 MachineBasicBlock *CurBlock = CR.CaseBB; 1980 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1981 MachineBasicBlock *FallThrough; 1982 if (I != E-1) { 1983 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1984 CurMF->insert(BBI, FallThrough); 1985 1986 // Put SV in a virtual register to make it available from the new blocks. 1987 ExportFromCurrentBlock(SV); 1988 } else { 1989 // If the last case doesn't match, go to the default block. 1990 FallThrough = Default; 1991 } 1992 1993 const Value *RHS, *LHS, *MHS; 1994 ISD::CondCode CC; 1995 if (I->High == I->Low) { 1996 // This is just small small case range :) containing exactly 1 case 1997 CC = ISD::SETEQ; 1998 LHS = SV; RHS = I->High; MHS = NULL; 1999 } else { 2000 CC = ISD::SETLE; 2001 LHS = I->Low; MHS = SV; RHS = I->High; 2002 } 2003 2004 uint32_t ExtraWeight = I->ExtraWeight; 2005 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2006 /* me */ CurBlock, 2007 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2008 2009 // If emitting the first comparison, just call visitSwitchCase to emit the 2010 // code into the current block. Otherwise, push the CaseBlock onto the 2011 // vector to be later processed by SDISel, and insert the node's MBB 2012 // before the next MBB. 2013 if (CurBlock == SwitchBB) 2014 visitSwitchCase(CB, SwitchBB); 2015 else 2016 SwitchCases.push_back(CB); 2017 2018 CurBlock = FallThrough; 2019 } 2020 2021 return true; 2022} 2023 2024static inline bool areJTsAllowed(const TargetLowering &TLI) { 2025 return !TLI.getTargetMachine().Options.DisableJumpTables && 2026 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2027 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2028} 2029 2030static APInt ComputeRange(const APInt &First, const APInt &Last) { 2031 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2032 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2033 return (LastExt - FirstExt + 1ULL); 2034} 2035 2036/// handleJTSwitchCase - Emit jumptable for current switch case range 2037bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2038 CaseRecVector &WorkList, 2039 const Value *SV, 2040 MachineBasicBlock *Default, 2041 MachineBasicBlock *SwitchBB) { 2042 Case& FrontCase = *CR.Range.first; 2043 Case& BackCase = *(CR.Range.second-1); 2044 2045 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2046 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2047 2048 APInt TSize(First.getBitWidth(), 0); 2049 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2050 TSize += I->size(); 2051 2052 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2053 return false; 2054 2055 APInt Range = ComputeRange(First, Last); 2056 // The density is TSize / Range. Require at least 40%. 2057 // It should not be possible for IntTSize to saturate for sane code, but make 2058 // sure we handle Range saturation correctly. 2059 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2060 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2061 if (IntTSize * 10 < IntRange * 4) 2062 return false; 2063 2064 DEBUG(dbgs() << "Lowering jump table\n" 2065 << "First entry: " << First << ". Last entry: " << Last << '\n' 2066 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2067 2068 // Get the MachineFunction which holds the current MBB. This is used when 2069 // inserting any additional MBBs necessary to represent the switch. 2070 MachineFunction *CurMF = FuncInfo.MF; 2071 2072 // Figure out which block is immediately after the current one. 2073 MachineFunction::iterator BBI = CR.CaseBB; 2074 ++BBI; 2075 2076 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2077 2078 // Create a new basic block to hold the code for loading the address 2079 // of the jump table, and jumping to it. Update successor information; 2080 // we will either branch to the default case for the switch, or the jump 2081 // table. 2082 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2083 CurMF->insert(BBI, JumpTableBB); 2084 2085 addSuccessorWithWeight(CR.CaseBB, Default); 2086 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2087 2088 // Build a vector of destination BBs, corresponding to each target 2089 // of the jump table. If the value of the jump table slot corresponds to 2090 // a case statement, push the case's BB onto the vector, otherwise, push 2091 // the default BB. 2092 std::vector<MachineBasicBlock*> DestBBs; 2093 APInt TEI = First; 2094 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2095 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2096 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2097 2098 if (Low.sle(TEI) && TEI.sle(High)) { 2099 DestBBs.push_back(I->BB); 2100 if (TEI==High) 2101 ++I; 2102 } else { 2103 DestBBs.push_back(Default); 2104 } 2105 } 2106 2107 // Update successor info. Add one edge to each unique successor. 2108 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2109 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2110 E = DestBBs.end(); I != E; ++I) { 2111 if (!SuccsHandled[(*I)->getNumber()]) { 2112 SuccsHandled[(*I)->getNumber()] = true; 2113 addSuccessorWithWeight(JumpTableBB, *I); 2114 } 2115 } 2116 2117 // Create a jump table index for this jump table. 2118 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2119 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2120 ->createJumpTableIndex(DestBBs); 2121 2122 // Set the jump table information so that we can codegen it as a second 2123 // MachineBasicBlock 2124 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2125 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2126 if (CR.CaseBB == SwitchBB) 2127 visitJumpTableHeader(JT, JTH, SwitchBB); 2128 2129 JTCases.push_back(JumpTableBlock(JTH, JT)); 2130 return true; 2131} 2132 2133/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2134/// 2 subtrees. 2135bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2136 CaseRecVector& WorkList, 2137 const Value* SV, 2138 MachineBasicBlock *Default, 2139 MachineBasicBlock *SwitchBB) { 2140 // Get the MachineFunction which holds the current MBB. This is used when 2141 // inserting any additional MBBs necessary to represent the switch. 2142 MachineFunction *CurMF = FuncInfo.MF; 2143 2144 // Figure out which block is immediately after the current one. 2145 MachineFunction::iterator BBI = CR.CaseBB; 2146 ++BBI; 2147 2148 Case& FrontCase = *CR.Range.first; 2149 Case& BackCase = *(CR.Range.second-1); 2150 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2151 2152 // Size is the number of Cases represented by this range. 2153 unsigned Size = CR.Range.second - CR.Range.first; 2154 2155 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2156 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2157 double FMetric = 0; 2158 CaseItr Pivot = CR.Range.first + Size/2; 2159 2160 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2161 // (heuristically) allow us to emit JumpTable's later. 2162 APInt TSize(First.getBitWidth(), 0); 2163 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2164 I!=E; ++I) 2165 TSize += I->size(); 2166 2167 APInt LSize = FrontCase.size(); 2168 APInt RSize = TSize-LSize; 2169 DEBUG(dbgs() << "Selecting best pivot: \n" 2170 << "First: " << First << ", Last: " << Last <<'\n' 2171 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2172 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2173 J!=E; ++I, ++J) { 2174 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2175 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2176 APInt Range = ComputeRange(LEnd, RBegin); 2177 assert((Range - 2ULL).isNonNegative() && 2178 "Invalid case distance"); 2179 // Use volatile double here to avoid excess precision issues on some hosts, 2180 // e.g. that use 80-bit X87 registers. 2181 volatile double LDensity = 2182 (double)LSize.roundToDouble() / 2183 (LEnd - First + 1ULL).roundToDouble(); 2184 volatile double RDensity = 2185 (double)RSize.roundToDouble() / 2186 (Last - RBegin + 1ULL).roundToDouble(); 2187 double Metric = Range.logBase2()*(LDensity+RDensity); 2188 // Should always split in some non-trivial place 2189 DEBUG(dbgs() <<"=>Step\n" 2190 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2191 << "LDensity: " << LDensity 2192 << ", RDensity: " << RDensity << '\n' 2193 << "Metric: " << Metric << '\n'); 2194 if (FMetric < Metric) { 2195 Pivot = J; 2196 FMetric = Metric; 2197 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2198 } 2199 2200 LSize += J->size(); 2201 RSize -= J->size(); 2202 } 2203 if (areJTsAllowed(TLI)) { 2204 // If our case is dense we *really* should handle it earlier! 2205 assert((FMetric > 0) && "Should handle dense range earlier!"); 2206 } else { 2207 Pivot = CR.Range.first + Size/2; 2208 } 2209 2210 CaseRange LHSR(CR.Range.first, Pivot); 2211 CaseRange RHSR(Pivot, CR.Range.second); 2212 Constant *C = Pivot->Low; 2213 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2214 2215 // We know that we branch to the LHS if the Value being switched on is 2216 // less than the Pivot value, C. We use this to optimize our binary 2217 // tree a bit, by recognizing that if SV is greater than or equal to the 2218 // LHS's Case Value, and that Case Value is exactly one less than the 2219 // Pivot's Value, then we can branch directly to the LHS's Target, 2220 // rather than creating a leaf node for it. 2221 if ((LHSR.second - LHSR.first) == 1 && 2222 LHSR.first->High == CR.GE && 2223 cast<ConstantInt>(C)->getValue() == 2224 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2225 TrueBB = LHSR.first->BB; 2226 } else { 2227 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2228 CurMF->insert(BBI, TrueBB); 2229 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2230 2231 // Put SV in a virtual register to make it available from the new blocks. 2232 ExportFromCurrentBlock(SV); 2233 } 2234 2235 // Similar to the optimization above, if the Value being switched on is 2236 // known to be less than the Constant CR.LT, and the current Case Value 2237 // is CR.LT - 1, then we can branch directly to the target block for 2238 // the current Case Value, rather than emitting a RHS leaf node for it. 2239 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2240 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2241 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2242 FalseBB = RHSR.first->BB; 2243 } else { 2244 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2245 CurMF->insert(BBI, FalseBB); 2246 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2247 2248 // Put SV in a virtual register to make it available from the new blocks. 2249 ExportFromCurrentBlock(SV); 2250 } 2251 2252 // Create a CaseBlock record representing a conditional branch to 2253 // the LHS node if the value being switched on SV is less than C. 2254 // Otherwise, branch to LHS. 2255 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2256 2257 if (CR.CaseBB == SwitchBB) 2258 visitSwitchCase(CB, SwitchBB); 2259 else 2260 SwitchCases.push_back(CB); 2261 2262 return true; 2263} 2264 2265/// handleBitTestsSwitchCase - if current case range has few destination and 2266/// range span less, than machine word bitwidth, encode case range into series 2267/// of masks and emit bit tests with these masks. 2268bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2269 CaseRecVector& WorkList, 2270 const Value* SV, 2271 MachineBasicBlock* Default, 2272 MachineBasicBlock *SwitchBB){ 2273 EVT PTy = TLI.getPointerTy(); 2274 unsigned IntPtrBits = PTy.getSizeInBits(); 2275 2276 Case& FrontCase = *CR.Range.first; 2277 Case& BackCase = *(CR.Range.second-1); 2278 2279 // Get the MachineFunction which holds the current MBB. This is used when 2280 // inserting any additional MBBs necessary to represent the switch. 2281 MachineFunction *CurMF = FuncInfo.MF; 2282 2283 // If target does not have legal shift left, do not emit bit tests at all. 2284 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2285 return false; 2286 2287 size_t numCmps = 0; 2288 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2289 I!=E; ++I) { 2290 // Single case counts one, case range - two. 2291 numCmps += (I->Low == I->High ? 1 : 2); 2292 } 2293 2294 // Count unique destinations 2295 SmallSet<MachineBasicBlock*, 4> Dests; 2296 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2297 Dests.insert(I->BB); 2298 if (Dests.size() > 3) 2299 // Don't bother the code below, if there are too much unique destinations 2300 return false; 2301 } 2302 DEBUG(dbgs() << "Total number of unique destinations: " 2303 << Dests.size() << '\n' 2304 << "Total number of comparisons: " << numCmps << '\n'); 2305 2306 // Compute span of values. 2307 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2308 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2309 APInt cmpRange = maxValue - minValue; 2310 2311 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2312 << "Low bound: " << minValue << '\n' 2313 << "High bound: " << maxValue << '\n'); 2314 2315 if (cmpRange.uge(IntPtrBits) || 2316 (!(Dests.size() == 1 && numCmps >= 3) && 2317 !(Dests.size() == 2 && numCmps >= 5) && 2318 !(Dests.size() >= 3 && numCmps >= 6))) 2319 return false; 2320 2321 DEBUG(dbgs() << "Emitting bit tests\n"); 2322 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2323 2324 // Optimize the case where all the case values fit in a 2325 // word without having to subtract minValue. In this case, 2326 // we can optimize away the subtraction. 2327 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2328 cmpRange = maxValue; 2329 } else { 2330 lowBound = minValue; 2331 } 2332 2333 CaseBitsVector CasesBits; 2334 unsigned i, count = 0; 2335 2336 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2337 MachineBasicBlock* Dest = I->BB; 2338 for (i = 0; i < count; ++i) 2339 if (Dest == CasesBits[i].BB) 2340 break; 2341 2342 if (i == count) { 2343 assert((count < 3) && "Too much destinations to test!"); 2344 CasesBits.push_back(CaseBits(0, Dest, 0)); 2345 count++; 2346 } 2347 2348 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2349 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2350 2351 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2352 uint64_t hi = (highValue - lowBound).getZExtValue(); 2353 2354 for (uint64_t j = lo; j <= hi; j++) { 2355 CasesBits[i].Mask |= 1ULL << j; 2356 CasesBits[i].Bits++; 2357 } 2358 2359 } 2360 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2361 2362 BitTestInfo BTC; 2363 2364 // Figure out which block is immediately after the current one. 2365 MachineFunction::iterator BBI = CR.CaseBB; 2366 ++BBI; 2367 2368 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2369 2370 DEBUG(dbgs() << "Cases:\n"); 2371 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2372 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2373 << ", Bits: " << CasesBits[i].Bits 2374 << ", BB: " << CasesBits[i].BB << '\n'); 2375 2376 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2377 CurMF->insert(BBI, CaseBB); 2378 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2379 CaseBB, 2380 CasesBits[i].BB)); 2381 2382 // Put SV in a virtual register to make it available from the new blocks. 2383 ExportFromCurrentBlock(SV); 2384 } 2385 2386 BitTestBlock BTB(lowBound, cmpRange, SV, 2387 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2388 CR.CaseBB, Default, BTC); 2389 2390 if (CR.CaseBB == SwitchBB) 2391 visitBitTestHeader(BTB, SwitchBB); 2392 2393 BitTestCases.push_back(BTB); 2394 2395 return true; 2396} 2397 2398/// Clusterify - Transform simple list of Cases into list of CaseRange's 2399size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2400 const SwitchInst& SI) { 2401 size_t numCmps = 0; 2402 2403 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2404 // Start with "simple" cases 2405 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2406 BasicBlock *SuccBB = SI.getSuccessor(i); 2407 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2408 2409 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2410 2411 Cases.push_back(Case(SI.getSuccessorValue(i), 2412 SI.getSuccessorValue(i), 2413 SMBB, ExtraWeight)); 2414 } 2415 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2416 2417 // Merge case into clusters 2418 if (Cases.size() >= 2) 2419 // Must recompute end() each iteration because it may be 2420 // invalidated by erase if we hold on to it 2421 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2422 J != Cases.end(); ) { 2423 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2424 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2425 MachineBasicBlock* nextBB = J->BB; 2426 MachineBasicBlock* currentBB = I->BB; 2427 2428 // If the two neighboring cases go to the same destination, merge them 2429 // into a single case. 2430 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2431 I->High = J->High; 2432 J = Cases.erase(J); 2433 2434 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2435 uint32_t CurWeight = currentBB->getBasicBlock() ? 2436 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2437 uint32_t NextWeight = nextBB->getBasicBlock() ? 2438 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2439 2440 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2441 CurWeight + NextWeight); 2442 } 2443 } else { 2444 I = J++; 2445 } 2446 } 2447 2448 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2449 if (I->Low != I->High) 2450 // A range counts double, since it requires two compares. 2451 ++numCmps; 2452 } 2453 2454 return numCmps; 2455} 2456 2457void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2458 MachineBasicBlock *Last) { 2459 // Update JTCases. 2460 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2461 if (JTCases[i].first.HeaderBB == First) 2462 JTCases[i].first.HeaderBB = Last; 2463 2464 // Update BitTestCases. 2465 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2466 if (BitTestCases[i].Parent == First) 2467 BitTestCases[i].Parent = Last; 2468} 2469 2470void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2471 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2472 2473 // Figure out which block is immediately after the current one. 2474 MachineBasicBlock *NextBlock = 0; 2475 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2476 2477 // If there is only the default destination, branch to it if it is not the 2478 // next basic block. Otherwise, just fall through. 2479 if (SI.getNumCases() == 1) { 2480 // Update machine-CFG edges. 2481 2482 // If this is not a fall-through branch, emit the branch. 2483 SwitchMBB->addSuccessor(Default); 2484 if (Default != NextBlock) 2485 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2486 MVT::Other, getControlRoot(), 2487 DAG.getBasicBlock(Default))); 2488 2489 return; 2490 } 2491 2492 // If there are any non-default case statements, create a vector of Cases 2493 // representing each one, and sort the vector so that we can efficiently 2494 // create a binary search tree from them. 2495 CaseVector Cases; 2496 size_t numCmps = Clusterify(Cases, SI); 2497 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2498 << ". Total compares: " << numCmps << '\n'); 2499 (void)numCmps; 2500 2501 // Get the Value to be switched on and default basic blocks, which will be 2502 // inserted into CaseBlock records, representing basic blocks in the binary 2503 // search tree. 2504 const Value *SV = SI.getCondition(); 2505 2506 // Push the initial CaseRec onto the worklist 2507 CaseRecVector WorkList; 2508 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2509 CaseRange(Cases.begin(),Cases.end()))); 2510 2511 while (!WorkList.empty()) { 2512 // Grab a record representing a case range to process off the worklist 2513 CaseRec CR = WorkList.back(); 2514 WorkList.pop_back(); 2515 2516 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2517 continue; 2518 2519 // If the range has few cases (two or less) emit a series of specific 2520 // tests. 2521 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2522 continue; 2523 2524 // If the switch has more than 5 blocks, and at least 40% dense, and the 2525 // target supports indirect branches, then emit a jump table rather than 2526 // lowering the switch to a binary tree of conditional branches. 2527 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2528 continue; 2529 2530 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2531 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2532 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2533 } 2534} 2535 2536void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2537 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2538 2539 // Update machine-CFG edges with unique successors. 2540 SmallVector<BasicBlock*, 32> succs; 2541 succs.reserve(I.getNumSuccessors()); 2542 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2543 succs.push_back(I.getSuccessor(i)); 2544 array_pod_sort(succs.begin(), succs.end()); 2545 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2546 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2547 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2548 addSuccessorWithWeight(IndirectBrMBB, Succ); 2549 } 2550 2551 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2552 MVT::Other, getControlRoot(), 2553 getValue(I.getAddress()))); 2554} 2555 2556void SelectionDAGBuilder::visitFSub(const User &I) { 2557 // -0.0 - X --> fneg 2558 Type *Ty = I.getType(); 2559 if (isa<Constant>(I.getOperand(0)) && 2560 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2561 SDValue Op2 = getValue(I.getOperand(1)); 2562 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2563 Op2.getValueType(), Op2)); 2564 return; 2565 } 2566 2567 visitBinary(I, ISD::FSUB); 2568} 2569 2570void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2571 SDValue Op1 = getValue(I.getOperand(0)); 2572 SDValue Op2 = getValue(I.getOperand(1)); 2573 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2574 Op1.getValueType(), Op1, Op2)); 2575} 2576 2577void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2578 SDValue Op1 = getValue(I.getOperand(0)); 2579 SDValue Op2 = getValue(I.getOperand(1)); 2580 2581 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2582 2583 // Coerce the shift amount to the right type if we can. 2584 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2585 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2586 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2587 DebugLoc DL = getCurDebugLoc(); 2588 2589 // If the operand is smaller than the shift count type, promote it. 2590 if (ShiftSize > Op2Size) 2591 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2592 2593 // If the operand is larger than the shift count type but the shift 2594 // count type has enough bits to represent any shift value, truncate 2595 // it now. This is a common case and it exposes the truncate to 2596 // optimization early. 2597 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2598 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2599 // Otherwise we'll need to temporarily settle for some other convenient 2600 // type. Type legalization will make adjustments once the shiftee is split. 2601 else 2602 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2603 } 2604 2605 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2606 Op1.getValueType(), Op1, Op2)); 2607} 2608 2609void SelectionDAGBuilder::visitSDiv(const User &I) { 2610 SDValue Op1 = getValue(I.getOperand(0)); 2611 SDValue Op2 = getValue(I.getOperand(1)); 2612 2613 // Turn exact SDivs into multiplications. 2614 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2615 // exact bit. 2616 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2617 !isa<ConstantSDNode>(Op1) && 2618 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2619 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2620 else 2621 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2622 Op1, Op2)); 2623} 2624 2625void SelectionDAGBuilder::visitICmp(const User &I) { 2626 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2627 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2628 predicate = IC->getPredicate(); 2629 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2630 predicate = ICmpInst::Predicate(IC->getPredicate()); 2631 SDValue Op1 = getValue(I.getOperand(0)); 2632 SDValue Op2 = getValue(I.getOperand(1)); 2633 ISD::CondCode Opcode = getICmpCondCode(predicate); 2634 2635 EVT DestVT = TLI.getValueType(I.getType()); 2636 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2637} 2638 2639void SelectionDAGBuilder::visitFCmp(const User &I) { 2640 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2641 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2642 predicate = FC->getPredicate(); 2643 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2644 predicate = FCmpInst::Predicate(FC->getPredicate()); 2645 SDValue Op1 = getValue(I.getOperand(0)); 2646 SDValue Op2 = getValue(I.getOperand(1)); 2647 ISD::CondCode Condition = getFCmpCondCode(predicate); 2648 if (TM.Options.NoNaNsFPMath) 2649 Condition = getFCmpCodeWithoutNaN(Condition); 2650 EVT DestVT = TLI.getValueType(I.getType()); 2651 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2652} 2653 2654void SelectionDAGBuilder::visitSelect(const User &I) { 2655 SmallVector<EVT, 4> ValueVTs; 2656 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2657 unsigned NumValues = ValueVTs.size(); 2658 if (NumValues == 0) return; 2659 2660 SmallVector<SDValue, 4> Values(NumValues); 2661 SDValue Cond = getValue(I.getOperand(0)); 2662 SDValue TrueVal = getValue(I.getOperand(1)); 2663 SDValue FalseVal = getValue(I.getOperand(2)); 2664 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2665 ISD::VSELECT : ISD::SELECT; 2666 2667 for (unsigned i = 0; i != NumValues; ++i) 2668 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2669 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2670 Cond, 2671 SDValue(TrueVal.getNode(), 2672 TrueVal.getResNo() + i), 2673 SDValue(FalseVal.getNode(), 2674 FalseVal.getResNo() + i)); 2675 2676 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2677 DAG.getVTList(&ValueVTs[0], NumValues), 2678 &Values[0], NumValues)); 2679} 2680 2681void SelectionDAGBuilder::visitTrunc(const User &I) { 2682 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2683 SDValue N = getValue(I.getOperand(0)); 2684 EVT DestVT = TLI.getValueType(I.getType()); 2685 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2686} 2687 2688void SelectionDAGBuilder::visitZExt(const User &I) { 2689 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2690 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2691 SDValue N = getValue(I.getOperand(0)); 2692 EVT DestVT = TLI.getValueType(I.getType()); 2693 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2694} 2695 2696void SelectionDAGBuilder::visitSExt(const User &I) { 2697 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2698 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2699 SDValue N = getValue(I.getOperand(0)); 2700 EVT DestVT = TLI.getValueType(I.getType()); 2701 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2702} 2703 2704void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2705 // FPTrunc is never a no-op cast, no need to check 2706 SDValue N = getValue(I.getOperand(0)); 2707 EVT DestVT = TLI.getValueType(I.getType()); 2708 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2709 DestVT, N, 2710 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2711} 2712 2713void SelectionDAGBuilder::visitFPExt(const User &I){ 2714 // FPExt is never a no-op cast, no need to check 2715 SDValue N = getValue(I.getOperand(0)); 2716 EVT DestVT = TLI.getValueType(I.getType()); 2717 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2718} 2719 2720void SelectionDAGBuilder::visitFPToUI(const User &I) { 2721 // FPToUI is never a no-op cast, no need to check 2722 SDValue N = getValue(I.getOperand(0)); 2723 EVT DestVT = TLI.getValueType(I.getType()); 2724 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2725} 2726 2727void SelectionDAGBuilder::visitFPToSI(const User &I) { 2728 // FPToSI is never a no-op cast, no need to check 2729 SDValue N = getValue(I.getOperand(0)); 2730 EVT DestVT = TLI.getValueType(I.getType()); 2731 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2732} 2733 2734void SelectionDAGBuilder::visitUIToFP(const User &I) { 2735 // UIToFP is never a no-op cast, no need to check 2736 SDValue N = getValue(I.getOperand(0)); 2737 EVT DestVT = TLI.getValueType(I.getType()); 2738 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2739} 2740 2741void SelectionDAGBuilder::visitSIToFP(const User &I){ 2742 // SIToFP is never a no-op cast, no need to check 2743 SDValue N = getValue(I.getOperand(0)); 2744 EVT DestVT = TLI.getValueType(I.getType()); 2745 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2746} 2747 2748void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2749 // What to do depends on the size of the integer and the size of the pointer. 2750 // We can either truncate, zero extend, or no-op, accordingly. 2751 SDValue N = getValue(I.getOperand(0)); 2752 EVT DestVT = TLI.getValueType(I.getType()); 2753 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2754} 2755 2756void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2757 // What to do depends on the size of the integer and the size of the pointer. 2758 // We can either truncate, zero extend, or no-op, accordingly. 2759 SDValue N = getValue(I.getOperand(0)); 2760 EVT DestVT = TLI.getValueType(I.getType()); 2761 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2762} 2763 2764void SelectionDAGBuilder::visitBitCast(const User &I) { 2765 SDValue N = getValue(I.getOperand(0)); 2766 EVT DestVT = TLI.getValueType(I.getType()); 2767 2768 // BitCast assures us that source and destination are the same size so this is 2769 // either a BITCAST or a no-op. 2770 if (DestVT != N.getValueType()) 2771 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2772 DestVT, N)); // convert types. 2773 else 2774 setValue(&I, N); // noop cast. 2775} 2776 2777void SelectionDAGBuilder::visitInsertElement(const User &I) { 2778 SDValue InVec = getValue(I.getOperand(0)); 2779 SDValue InVal = getValue(I.getOperand(1)); 2780 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2781 TLI.getPointerTy(), 2782 getValue(I.getOperand(2))); 2783 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2784 TLI.getValueType(I.getType()), 2785 InVec, InVal, InIdx)); 2786} 2787 2788void SelectionDAGBuilder::visitExtractElement(const User &I) { 2789 SDValue InVec = getValue(I.getOperand(0)); 2790 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2791 TLI.getPointerTy(), 2792 getValue(I.getOperand(1))); 2793 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2794 TLI.getValueType(I.getType()), InVec, InIdx)); 2795} 2796 2797// Utility for visitShuffleVector - Return true if every element in Mask, 2798// begining // from position Pos and ending in Pos+Size, falls within the 2799// specified sequential range [L, L+Pos). or is undef. 2800static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2801 int Pos, int Size, int Low) { 2802 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2803 if (Mask[i] >= 0 && Mask[i] != Low) 2804 return false; 2805 return true; 2806} 2807 2808void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2809 SmallVector<int, 8> Mask; 2810 SDValue Src1 = getValue(I.getOperand(0)); 2811 SDValue Src2 = getValue(I.getOperand(1)); 2812 2813 // Convert the ConstantVector mask operand into an array of ints, with -1 2814 // representing undef values. 2815 SmallVector<Constant*, 8> MaskElts; 2816 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2817 unsigned MaskNumElts = MaskElts.size(); 2818 for (unsigned i = 0; i != MaskNumElts; ++i) { 2819 if (isa<UndefValue>(MaskElts[i])) 2820 Mask.push_back(-1); 2821 else 2822 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2823 } 2824 2825 EVT VT = TLI.getValueType(I.getType()); 2826 EVT SrcVT = Src1.getValueType(); 2827 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2828 2829 if (SrcNumElts == MaskNumElts) { 2830 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2831 &Mask[0])); 2832 return; 2833 } 2834 2835 // Normalize the shuffle vector since mask and vector length don't match. 2836 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2837 // Mask is longer than the source vectors and is a multiple of the source 2838 // vectors. We can use concatenate vector to make the mask and vectors 2839 // lengths match. 2840 if (SrcNumElts*2 == MaskNumElts) { 2841 // First check for Src1 in low and Src2 in high 2842 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2843 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2844 // The shuffle is concatenating two vectors together. 2845 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2846 VT, Src1, Src2)); 2847 return; 2848 } 2849 // Then check for Src2 in low and Src1 in high 2850 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2851 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2852 // The shuffle is concatenating two vectors together. 2853 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2854 VT, Src2, Src1)); 2855 return; 2856 } 2857 } 2858 2859 // Pad both vectors with undefs to make them the same length as the mask. 2860 unsigned NumConcat = MaskNumElts / SrcNumElts; 2861 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2862 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2863 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2864 2865 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2866 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2867 MOps1[0] = Src1; 2868 MOps2[0] = Src2; 2869 2870 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2871 getCurDebugLoc(), VT, 2872 &MOps1[0], NumConcat); 2873 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2874 getCurDebugLoc(), VT, 2875 &MOps2[0], NumConcat); 2876 2877 // Readjust mask for new input vector length. 2878 SmallVector<int, 8> MappedOps; 2879 for (unsigned i = 0; i != MaskNumElts; ++i) { 2880 int Idx = Mask[i]; 2881 if (Idx < (int)SrcNumElts) 2882 MappedOps.push_back(Idx); 2883 else 2884 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2885 } 2886 2887 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2888 &MappedOps[0])); 2889 return; 2890 } 2891 2892 if (SrcNumElts > MaskNumElts) { 2893 // Analyze the access pattern of the vector to see if we can extract 2894 // two subvectors and do the shuffle. The analysis is done by calculating 2895 // the range of elements the mask access on both vectors. 2896 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2897 static_cast<int>(SrcNumElts+1)}; 2898 int MaxRange[2] = {-1, -1}; 2899 2900 for (unsigned i = 0; i != MaskNumElts; ++i) { 2901 int Idx = Mask[i]; 2902 int Input = 0; 2903 if (Idx < 0) 2904 continue; 2905 2906 if (Idx >= (int)SrcNumElts) { 2907 Input = 1; 2908 Idx -= SrcNumElts; 2909 } 2910 if (Idx > MaxRange[Input]) 2911 MaxRange[Input] = Idx; 2912 if (Idx < MinRange[Input]) 2913 MinRange[Input] = Idx; 2914 } 2915 2916 // Check if the access is smaller than the vector size and can we find 2917 // a reasonable extract index. 2918 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2919 // Extract. 2920 int StartIdx[2]; // StartIdx to extract from 2921 for (int Input=0; Input < 2; ++Input) { 2922 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2923 RangeUse[Input] = 0; // Unused 2924 StartIdx[Input] = 0; 2925 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2926 // Fits within range but we should see if we can find a good 2927 // start index that is a multiple of the mask length. 2928 if (MaxRange[Input] < (int)MaskNumElts) { 2929 RangeUse[Input] = 1; // Extract from beginning of the vector 2930 StartIdx[Input] = 0; 2931 } else { 2932 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2933 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2934 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2935 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2936 } 2937 } 2938 } 2939 2940 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2941 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2942 return; 2943 } 2944 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2945 // Extract appropriate subvector and generate a vector shuffle 2946 for (int Input=0; Input < 2; ++Input) { 2947 SDValue &Src = Input == 0 ? Src1 : Src2; 2948 if (RangeUse[Input] == 0) 2949 Src = DAG.getUNDEF(VT); 2950 else 2951 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2952 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2953 } 2954 2955 // Calculate new mask. 2956 SmallVector<int, 8> MappedOps; 2957 for (unsigned i = 0; i != MaskNumElts; ++i) { 2958 int Idx = Mask[i]; 2959 if (Idx < 0) 2960 MappedOps.push_back(Idx); 2961 else if (Idx < (int)SrcNumElts) 2962 MappedOps.push_back(Idx - StartIdx[0]); 2963 else 2964 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2965 } 2966 2967 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2968 &MappedOps[0])); 2969 return; 2970 } 2971 } 2972 2973 // We can't use either concat vectors or extract subvectors so fall back to 2974 // replacing the shuffle with extract and build vector. 2975 // to insert and build vector. 2976 EVT EltVT = VT.getVectorElementType(); 2977 EVT PtrVT = TLI.getPointerTy(); 2978 SmallVector<SDValue,8> Ops; 2979 for (unsigned i = 0; i != MaskNumElts; ++i) { 2980 if (Mask[i] < 0) { 2981 Ops.push_back(DAG.getUNDEF(EltVT)); 2982 } else { 2983 int Idx = Mask[i]; 2984 SDValue Res; 2985 2986 if (Idx < (int)SrcNumElts) 2987 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2988 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2989 else 2990 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2991 EltVT, Src2, 2992 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2993 2994 Ops.push_back(Res); 2995 } 2996 } 2997 2998 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2999 VT, &Ops[0], Ops.size())); 3000} 3001 3002void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3003 const Value *Op0 = I.getOperand(0); 3004 const Value *Op1 = I.getOperand(1); 3005 Type *AggTy = I.getType(); 3006 Type *ValTy = Op1->getType(); 3007 bool IntoUndef = isa<UndefValue>(Op0); 3008 bool FromUndef = isa<UndefValue>(Op1); 3009 3010 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3011 3012 SmallVector<EVT, 4> AggValueVTs; 3013 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3014 SmallVector<EVT, 4> ValValueVTs; 3015 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3016 3017 unsigned NumAggValues = AggValueVTs.size(); 3018 unsigned NumValValues = ValValueVTs.size(); 3019 SmallVector<SDValue, 4> Values(NumAggValues); 3020 3021 SDValue Agg = getValue(Op0); 3022 unsigned i = 0; 3023 // Copy the beginning value(s) from the original aggregate. 3024 for (; i != LinearIndex; ++i) 3025 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3026 SDValue(Agg.getNode(), Agg.getResNo() + i); 3027 // Copy values from the inserted value(s). 3028 if (NumValValues) { 3029 SDValue Val = getValue(Op1); 3030 for (; i != LinearIndex + NumValValues; ++i) 3031 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3032 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3033 } 3034 // Copy remaining value(s) from the original aggregate. 3035 for (; i != NumAggValues; ++i) 3036 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3037 SDValue(Agg.getNode(), Agg.getResNo() + i); 3038 3039 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3040 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3041 &Values[0], NumAggValues)); 3042} 3043 3044void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3045 const Value *Op0 = I.getOperand(0); 3046 Type *AggTy = Op0->getType(); 3047 Type *ValTy = I.getType(); 3048 bool OutOfUndef = isa<UndefValue>(Op0); 3049 3050 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3051 3052 SmallVector<EVT, 4> ValValueVTs; 3053 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3054 3055 unsigned NumValValues = ValValueVTs.size(); 3056 3057 // Ignore a extractvalue that produces an empty object 3058 if (!NumValValues) { 3059 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3060 return; 3061 } 3062 3063 SmallVector<SDValue, 4> Values(NumValValues); 3064 3065 SDValue Agg = getValue(Op0); 3066 // Copy out the selected value(s). 3067 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3068 Values[i - LinearIndex] = 3069 OutOfUndef ? 3070 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3071 SDValue(Agg.getNode(), Agg.getResNo() + i); 3072 3073 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3074 DAG.getVTList(&ValValueVTs[0], NumValValues), 3075 &Values[0], NumValValues)); 3076} 3077 3078void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3079 SDValue N = getValue(I.getOperand(0)); 3080 Type *Ty = I.getOperand(0)->getType(); 3081 3082 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3083 OI != E; ++OI) { 3084 const Value *Idx = *OI; 3085 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3086 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3087 if (Field) { 3088 // N = N + Offset 3089 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3090 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3091 DAG.getIntPtrConstant(Offset)); 3092 } 3093 3094 Ty = StTy->getElementType(Field); 3095 } else { 3096 Ty = cast<SequentialType>(Ty)->getElementType(); 3097 3098 // If this is a constant subscript, handle it quickly. 3099 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3100 if (CI->isZero()) continue; 3101 uint64_t Offs = 3102 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3103 SDValue OffsVal; 3104 EVT PTy = TLI.getPointerTy(); 3105 unsigned PtrBits = PTy.getSizeInBits(); 3106 if (PtrBits < 64) 3107 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3108 TLI.getPointerTy(), 3109 DAG.getConstant(Offs, MVT::i64)); 3110 else 3111 OffsVal = DAG.getIntPtrConstant(Offs); 3112 3113 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3114 OffsVal); 3115 continue; 3116 } 3117 3118 // N = N + Idx * ElementSize; 3119 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3120 TD->getTypeAllocSize(Ty)); 3121 SDValue IdxN = getValue(Idx); 3122 3123 // If the index is smaller or larger than intptr_t, truncate or extend 3124 // it. 3125 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3126 3127 // If this is a multiply by a power of two, turn it into a shl 3128 // immediately. This is a very common case. 3129 if (ElementSize != 1) { 3130 if (ElementSize.isPowerOf2()) { 3131 unsigned Amt = ElementSize.logBase2(); 3132 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3133 N.getValueType(), IdxN, 3134 DAG.getConstant(Amt, IdxN.getValueType())); 3135 } else { 3136 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3137 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3138 N.getValueType(), IdxN, Scale); 3139 } 3140 } 3141 3142 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3143 N.getValueType(), N, IdxN); 3144 } 3145 } 3146 3147 setValue(&I, N); 3148} 3149 3150void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3151 // If this is a fixed sized alloca in the entry block of the function, 3152 // allocate it statically on the stack. 3153 if (FuncInfo.StaticAllocaMap.count(&I)) 3154 return; // getValue will auto-populate this. 3155 3156 Type *Ty = I.getAllocatedType(); 3157 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3158 unsigned Align = 3159 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3160 I.getAlignment()); 3161 3162 SDValue AllocSize = getValue(I.getArraySize()); 3163 3164 EVT IntPtr = TLI.getPointerTy(); 3165 if (AllocSize.getValueType() != IntPtr) 3166 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3167 3168 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3169 AllocSize, 3170 DAG.getConstant(TySize, IntPtr)); 3171 3172 // Handle alignment. If the requested alignment is less than or equal to 3173 // the stack alignment, ignore it. If the size is greater than or equal to 3174 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3175 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3176 if (Align <= StackAlign) 3177 Align = 0; 3178 3179 // Round the size of the allocation up to the stack alignment size 3180 // by add SA-1 to the size. 3181 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3182 AllocSize.getValueType(), AllocSize, 3183 DAG.getIntPtrConstant(StackAlign-1)); 3184 3185 // Mask out the low bits for alignment purposes. 3186 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3187 AllocSize.getValueType(), AllocSize, 3188 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3189 3190 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3191 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3192 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3193 VTs, Ops, 3); 3194 setValue(&I, DSA); 3195 DAG.setRoot(DSA.getValue(1)); 3196 3197 // Inform the Frame Information that we have just allocated a variable-sized 3198 // object. 3199 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3200} 3201 3202void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3203 if (I.isAtomic()) 3204 return visitAtomicLoad(I); 3205 3206 const Value *SV = I.getOperand(0); 3207 SDValue Ptr = getValue(SV); 3208 3209 Type *Ty = I.getType(); 3210 3211 bool isVolatile = I.isVolatile(); 3212 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3213 bool isInvariant = I.getMetadata("invariant.load") != 0; 3214 unsigned Alignment = I.getAlignment(); 3215 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3216 3217 SmallVector<EVT, 4> ValueVTs; 3218 SmallVector<uint64_t, 4> Offsets; 3219 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3220 unsigned NumValues = ValueVTs.size(); 3221 if (NumValues == 0) 3222 return; 3223 3224 SDValue Root; 3225 bool ConstantMemory = false; 3226 if (I.isVolatile() || NumValues > MaxParallelChains) 3227 // Serialize volatile loads with other side effects. 3228 Root = getRoot(); 3229 else if (AA->pointsToConstantMemory( 3230 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3231 // Do not serialize (non-volatile) loads of constant memory with anything. 3232 Root = DAG.getEntryNode(); 3233 ConstantMemory = true; 3234 } else { 3235 // Do not serialize non-volatile loads against each other. 3236 Root = DAG.getRoot(); 3237 } 3238 3239 SmallVector<SDValue, 4> Values(NumValues); 3240 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3241 NumValues)); 3242 EVT PtrVT = Ptr.getValueType(); 3243 unsigned ChainI = 0; 3244 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3245 // Serializing loads here may result in excessive register pressure, and 3246 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3247 // could recover a bit by hoisting nodes upward in the chain by recognizing 3248 // they are side-effect free or do not alias. The optimizer should really 3249 // avoid this case by converting large object/array copies to llvm.memcpy 3250 // (MaxParallelChains should always remain as failsafe). 3251 if (ChainI == MaxParallelChains) { 3252 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3253 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3254 MVT::Other, &Chains[0], ChainI); 3255 Root = Chain; 3256 ChainI = 0; 3257 } 3258 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3259 PtrVT, Ptr, 3260 DAG.getConstant(Offsets[i], PtrVT)); 3261 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3262 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3263 isNonTemporal, isInvariant, Alignment, TBAAInfo); 3264 3265 Values[i] = L; 3266 Chains[ChainI] = L.getValue(1); 3267 } 3268 3269 if (!ConstantMemory) { 3270 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3271 MVT::Other, &Chains[0], ChainI); 3272 if (isVolatile) 3273 DAG.setRoot(Chain); 3274 else 3275 PendingLoads.push_back(Chain); 3276 } 3277 3278 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3279 DAG.getVTList(&ValueVTs[0], NumValues), 3280 &Values[0], NumValues)); 3281} 3282 3283void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3284 if (I.isAtomic()) 3285 return visitAtomicStore(I); 3286 3287 const Value *SrcV = I.getOperand(0); 3288 const Value *PtrV = I.getOperand(1); 3289 3290 SmallVector<EVT, 4> ValueVTs; 3291 SmallVector<uint64_t, 4> Offsets; 3292 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3293 unsigned NumValues = ValueVTs.size(); 3294 if (NumValues == 0) 3295 return; 3296 3297 // Get the lowered operands. Note that we do this after 3298 // checking if NumResults is zero, because with zero results 3299 // the operands won't have values in the map. 3300 SDValue Src = getValue(SrcV); 3301 SDValue Ptr = getValue(PtrV); 3302 3303 SDValue Root = getRoot(); 3304 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3305 NumValues)); 3306 EVT PtrVT = Ptr.getValueType(); 3307 bool isVolatile = I.isVolatile(); 3308 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3309 unsigned Alignment = I.getAlignment(); 3310 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3311 3312 unsigned ChainI = 0; 3313 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3314 // See visitLoad comments. 3315 if (ChainI == MaxParallelChains) { 3316 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3317 MVT::Other, &Chains[0], ChainI); 3318 Root = Chain; 3319 ChainI = 0; 3320 } 3321 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3322 DAG.getConstant(Offsets[i], PtrVT)); 3323 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3324 SDValue(Src.getNode(), Src.getResNo() + i), 3325 Add, MachinePointerInfo(PtrV, Offsets[i]), 3326 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3327 Chains[ChainI] = St; 3328 } 3329 3330 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3331 MVT::Other, &Chains[0], ChainI); 3332 ++SDNodeOrder; 3333 AssignOrderingToNode(StoreNode.getNode()); 3334 DAG.setRoot(StoreNode); 3335} 3336 3337static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3338 SynchronizationScope Scope, 3339 bool Before, DebugLoc dl, 3340 SelectionDAG &DAG, 3341 const TargetLowering &TLI) { 3342 // Fence, if necessary 3343 if (Before) { 3344 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3345 Order = Release; 3346 else if (Order == Acquire || Order == Monotonic) 3347 return Chain; 3348 } else { 3349 if (Order == AcquireRelease) 3350 Order = Acquire; 3351 else if (Order == Release || Order == Monotonic) 3352 return Chain; 3353 } 3354 SDValue Ops[3]; 3355 Ops[0] = Chain; 3356 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3357 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3358 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3359} 3360 3361void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3362 DebugLoc dl = getCurDebugLoc(); 3363 AtomicOrdering Order = I.getOrdering(); 3364 SynchronizationScope Scope = I.getSynchScope(); 3365 3366 SDValue InChain = getRoot(); 3367 3368 if (TLI.getInsertFencesForAtomic()) 3369 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3370 DAG, TLI); 3371 3372 SDValue L = 3373 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3374 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3375 InChain, 3376 getValue(I.getPointerOperand()), 3377 getValue(I.getCompareOperand()), 3378 getValue(I.getNewValOperand()), 3379 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3380 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3381 Scope); 3382 3383 SDValue OutChain = L.getValue(1); 3384 3385 if (TLI.getInsertFencesForAtomic()) 3386 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3387 DAG, TLI); 3388 3389 setValue(&I, L); 3390 DAG.setRoot(OutChain); 3391} 3392 3393void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3394 DebugLoc dl = getCurDebugLoc(); 3395 ISD::NodeType NT; 3396 switch (I.getOperation()) { 3397 default: llvm_unreachable("Unknown atomicrmw operation"); 3398 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3399 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3400 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3401 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3402 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3403 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3404 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3405 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3406 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3407 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3408 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3409 } 3410 AtomicOrdering Order = I.getOrdering(); 3411 SynchronizationScope Scope = I.getSynchScope(); 3412 3413 SDValue InChain = getRoot(); 3414 3415 if (TLI.getInsertFencesForAtomic()) 3416 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3417 DAG, TLI); 3418 3419 SDValue L = 3420 DAG.getAtomic(NT, dl, 3421 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3422 InChain, 3423 getValue(I.getPointerOperand()), 3424 getValue(I.getValOperand()), 3425 I.getPointerOperand(), 0 /* Alignment */, 3426 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3427 Scope); 3428 3429 SDValue OutChain = L.getValue(1); 3430 3431 if (TLI.getInsertFencesForAtomic()) 3432 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3433 DAG, TLI); 3434 3435 setValue(&I, L); 3436 DAG.setRoot(OutChain); 3437} 3438 3439void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3440 DebugLoc dl = getCurDebugLoc(); 3441 SDValue Ops[3]; 3442 Ops[0] = getRoot(); 3443 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3444 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3445 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3446} 3447 3448void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3449 DebugLoc dl = getCurDebugLoc(); 3450 AtomicOrdering Order = I.getOrdering(); 3451 SynchronizationScope Scope = I.getSynchScope(); 3452 3453 SDValue InChain = getRoot(); 3454 3455 EVT VT = EVT::getEVT(I.getType()); 3456 3457 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3458 report_fatal_error("Cannot generate unaligned atomic load"); 3459 3460 SDValue L = 3461 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3462 getValue(I.getPointerOperand()), 3463 I.getPointerOperand(), I.getAlignment(), 3464 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3465 Scope); 3466 3467 SDValue OutChain = L.getValue(1); 3468 3469 if (TLI.getInsertFencesForAtomic()) 3470 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3471 DAG, TLI); 3472 3473 setValue(&I, L); 3474 DAG.setRoot(OutChain); 3475} 3476 3477void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3478 DebugLoc dl = getCurDebugLoc(); 3479 3480 AtomicOrdering Order = I.getOrdering(); 3481 SynchronizationScope Scope = I.getSynchScope(); 3482 3483 SDValue InChain = getRoot(); 3484 3485 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3486 3487 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3488 report_fatal_error("Cannot generate unaligned atomic store"); 3489 3490 if (TLI.getInsertFencesForAtomic()) 3491 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3492 DAG, TLI); 3493 3494 SDValue OutChain = 3495 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3496 InChain, 3497 getValue(I.getPointerOperand()), 3498 getValue(I.getValueOperand()), 3499 I.getPointerOperand(), I.getAlignment(), 3500 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3501 Scope); 3502 3503 if (TLI.getInsertFencesForAtomic()) 3504 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3505 DAG, TLI); 3506 3507 DAG.setRoot(OutChain); 3508} 3509 3510/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3511/// node. 3512void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3513 unsigned Intrinsic) { 3514 bool HasChain = !I.doesNotAccessMemory(); 3515 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3516 3517 // Build the operand list. 3518 SmallVector<SDValue, 8> Ops; 3519 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3520 if (OnlyLoad) { 3521 // We don't need to serialize loads against other loads. 3522 Ops.push_back(DAG.getRoot()); 3523 } else { 3524 Ops.push_back(getRoot()); 3525 } 3526 } 3527 3528 // Info is set by getTgtMemInstrinsic 3529 TargetLowering::IntrinsicInfo Info; 3530 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3531 3532 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3533 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3534 Info.opc == ISD::INTRINSIC_W_CHAIN) 3535 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3536 3537 // Add all operands of the call to the operand list. 3538 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3539 SDValue Op = getValue(I.getArgOperand(i)); 3540 Ops.push_back(Op); 3541 } 3542 3543 SmallVector<EVT, 4> ValueVTs; 3544 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3545 3546 if (HasChain) 3547 ValueVTs.push_back(MVT::Other); 3548 3549 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3550 3551 // Create the node. 3552 SDValue Result; 3553 if (IsTgtIntrinsic) { 3554 // This is target intrinsic that touches memory 3555 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3556 VTs, &Ops[0], Ops.size(), 3557 Info.memVT, 3558 MachinePointerInfo(Info.ptrVal, Info.offset), 3559 Info.align, Info.vol, 3560 Info.readMem, Info.writeMem); 3561 } else if (!HasChain) { 3562 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3563 VTs, &Ops[0], Ops.size()); 3564 } else if (!I.getType()->isVoidTy()) { 3565 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3566 VTs, &Ops[0], Ops.size()); 3567 } else { 3568 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3569 VTs, &Ops[0], Ops.size()); 3570 } 3571 3572 if (HasChain) { 3573 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3574 if (OnlyLoad) 3575 PendingLoads.push_back(Chain); 3576 else 3577 DAG.setRoot(Chain); 3578 } 3579 3580 if (!I.getType()->isVoidTy()) { 3581 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3582 EVT VT = TLI.getValueType(PTy); 3583 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3584 } 3585 3586 setValue(&I, Result); 3587 } 3588} 3589 3590/// GetSignificand - Get the significand and build it into a floating-point 3591/// number with exponent of 1: 3592/// 3593/// Op = (Op & 0x007fffff) | 0x3f800000; 3594/// 3595/// where Op is the hexidecimal representation of floating point value. 3596static SDValue 3597GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3598 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3599 DAG.getConstant(0x007fffff, MVT::i32)); 3600 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3601 DAG.getConstant(0x3f800000, MVT::i32)); 3602 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3603} 3604 3605/// GetExponent - Get the exponent: 3606/// 3607/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3608/// 3609/// where Op is the hexidecimal representation of floating point value. 3610static SDValue 3611GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3612 DebugLoc dl) { 3613 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3614 DAG.getConstant(0x7f800000, MVT::i32)); 3615 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3616 DAG.getConstant(23, TLI.getPointerTy())); 3617 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3618 DAG.getConstant(127, MVT::i32)); 3619 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3620} 3621 3622/// getF32Constant - Get 32-bit floating point constant. 3623static SDValue 3624getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3625 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3626} 3627 3628// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3629const char * 3630SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3631 SDValue Op1 = getValue(I.getArgOperand(0)); 3632 SDValue Op2 = getValue(I.getArgOperand(1)); 3633 3634 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3635 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3636 return 0; 3637} 3638 3639/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3640/// limited-precision mode. 3641void 3642SelectionDAGBuilder::visitExp(const CallInst &I) { 3643 SDValue result; 3644 DebugLoc dl = getCurDebugLoc(); 3645 3646 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3647 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3648 SDValue Op = getValue(I.getArgOperand(0)); 3649 3650 // Put the exponent in the right bit position for later addition to the 3651 // final result: 3652 // 3653 // #define LOG2OFe 1.4426950f 3654 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3655 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3656 getF32Constant(DAG, 0x3fb8aa3b)); 3657 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3658 3659 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3660 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3661 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3662 3663 // IntegerPartOfX <<= 23; 3664 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3665 DAG.getConstant(23, TLI.getPointerTy())); 3666 3667 if (LimitFloatPrecision <= 6) { 3668 // For floating-point precision of 6: 3669 // 3670 // TwoToFractionalPartOfX = 3671 // 0.997535578f + 3672 // (0.735607626f + 0.252464424f * x) * x; 3673 // 3674 // error 0.0144103317, which is 6 bits 3675 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3676 getF32Constant(DAG, 0x3e814304)); 3677 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3678 getF32Constant(DAG, 0x3f3c50c8)); 3679 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3680 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3681 getF32Constant(DAG, 0x3f7f5e7e)); 3682 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3683 3684 // Add the exponent into the result in integer domain. 3685 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3686 TwoToFracPartOfX, IntegerPartOfX); 3687 3688 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3689 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3690 // For floating-point precision of 12: 3691 // 3692 // TwoToFractionalPartOfX = 3693 // 0.999892986f + 3694 // (0.696457318f + 3695 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3696 // 3697 // 0.000107046256 error, which is 13 to 14 bits 3698 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3699 getF32Constant(DAG, 0x3da235e3)); 3700 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3701 getF32Constant(DAG, 0x3e65b8f3)); 3702 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3703 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3704 getF32Constant(DAG, 0x3f324b07)); 3705 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3706 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3707 getF32Constant(DAG, 0x3f7ff8fd)); 3708 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3709 3710 // Add the exponent into the result in integer domain. 3711 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3712 TwoToFracPartOfX, IntegerPartOfX); 3713 3714 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3715 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3716 // For floating-point precision of 18: 3717 // 3718 // TwoToFractionalPartOfX = 3719 // 0.999999982f + 3720 // (0.693148872f + 3721 // (0.240227044f + 3722 // (0.554906021e-1f + 3723 // (0.961591928e-2f + 3724 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3725 // 3726 // error 2.47208000*10^(-7), which is better than 18 bits 3727 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3728 getF32Constant(DAG, 0x3924b03e)); 3729 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3730 getF32Constant(DAG, 0x3ab24b87)); 3731 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3732 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3733 getF32Constant(DAG, 0x3c1d8c17)); 3734 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3735 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3736 getF32Constant(DAG, 0x3d634a1d)); 3737 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3738 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3739 getF32Constant(DAG, 0x3e75fe14)); 3740 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3741 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3742 getF32Constant(DAG, 0x3f317234)); 3743 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3744 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3745 getF32Constant(DAG, 0x3f800000)); 3746 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3747 MVT::i32, t13); 3748 3749 // Add the exponent into the result in integer domain. 3750 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3751 TwoToFracPartOfX, IntegerPartOfX); 3752 3753 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3754 } 3755 } else { 3756 // No special expansion. 3757 result = DAG.getNode(ISD::FEXP, dl, 3758 getValue(I.getArgOperand(0)).getValueType(), 3759 getValue(I.getArgOperand(0))); 3760 } 3761 3762 setValue(&I, result); 3763} 3764 3765/// visitLog - Lower a log intrinsic. Handles the special sequences for 3766/// limited-precision mode. 3767void 3768SelectionDAGBuilder::visitLog(const CallInst &I) { 3769 SDValue result; 3770 DebugLoc dl = getCurDebugLoc(); 3771 3772 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3773 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3774 SDValue Op = getValue(I.getArgOperand(0)); 3775 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3776 3777 // Scale the exponent by log(2) [0.69314718f]. 3778 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3779 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3780 getF32Constant(DAG, 0x3f317218)); 3781 3782 // Get the significand and build it into a floating-point number with 3783 // exponent of 1. 3784 SDValue X = GetSignificand(DAG, Op1, dl); 3785 3786 if (LimitFloatPrecision <= 6) { 3787 // For floating-point precision of 6: 3788 // 3789 // LogofMantissa = 3790 // -1.1609546f + 3791 // (1.4034025f - 0.23903021f * x) * x; 3792 // 3793 // error 0.0034276066, which is better than 8 bits 3794 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3795 getF32Constant(DAG, 0xbe74c456)); 3796 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3797 getF32Constant(DAG, 0x3fb3a2b1)); 3798 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3799 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3800 getF32Constant(DAG, 0x3f949a29)); 3801 3802 result = DAG.getNode(ISD::FADD, dl, 3803 MVT::f32, LogOfExponent, LogOfMantissa); 3804 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3805 // For floating-point precision of 12: 3806 // 3807 // LogOfMantissa = 3808 // -1.7417939f + 3809 // (2.8212026f + 3810 // (-1.4699568f + 3811 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3812 // 3813 // error 0.000061011436, which is 14 bits 3814 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3815 getF32Constant(DAG, 0xbd67b6d6)); 3816 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3817 getF32Constant(DAG, 0x3ee4f4b8)); 3818 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3819 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3820 getF32Constant(DAG, 0x3fbc278b)); 3821 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3822 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3823 getF32Constant(DAG, 0x40348e95)); 3824 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3825 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3826 getF32Constant(DAG, 0x3fdef31a)); 3827 3828 result = DAG.getNode(ISD::FADD, dl, 3829 MVT::f32, LogOfExponent, LogOfMantissa); 3830 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3831 // For floating-point precision of 18: 3832 // 3833 // LogOfMantissa = 3834 // -2.1072184f + 3835 // (4.2372794f + 3836 // (-3.7029485f + 3837 // (2.2781945f + 3838 // (-0.87823314f + 3839 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3840 // 3841 // error 0.0000023660568, which is better than 18 bits 3842 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3843 getF32Constant(DAG, 0xbc91e5ac)); 3844 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3845 getF32Constant(DAG, 0x3e4350aa)); 3846 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3847 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3848 getF32Constant(DAG, 0x3f60d3e3)); 3849 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3850 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3851 getF32Constant(DAG, 0x4011cdf0)); 3852 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3853 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3854 getF32Constant(DAG, 0x406cfd1c)); 3855 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3856 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3857 getF32Constant(DAG, 0x408797cb)); 3858 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3859 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3860 getF32Constant(DAG, 0x4006dcab)); 3861 3862 result = DAG.getNode(ISD::FADD, dl, 3863 MVT::f32, LogOfExponent, LogOfMantissa); 3864 } 3865 } else { 3866 // No special expansion. 3867 result = DAG.getNode(ISD::FLOG, dl, 3868 getValue(I.getArgOperand(0)).getValueType(), 3869 getValue(I.getArgOperand(0))); 3870 } 3871 3872 setValue(&I, result); 3873} 3874 3875/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3876/// limited-precision mode. 3877void 3878SelectionDAGBuilder::visitLog2(const CallInst &I) { 3879 SDValue result; 3880 DebugLoc dl = getCurDebugLoc(); 3881 3882 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3883 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3884 SDValue Op = getValue(I.getArgOperand(0)); 3885 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3886 3887 // Get the exponent. 3888 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3889 3890 // Get the significand and build it into a floating-point number with 3891 // exponent of 1. 3892 SDValue X = GetSignificand(DAG, Op1, dl); 3893 3894 // Different possible minimax approximations of significand in 3895 // floating-point for various degrees of accuracy over [1,2]. 3896 if (LimitFloatPrecision <= 6) { 3897 // For floating-point precision of 6: 3898 // 3899 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3900 // 3901 // error 0.0049451742, which is more than 7 bits 3902 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3903 getF32Constant(DAG, 0xbeb08fe0)); 3904 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3905 getF32Constant(DAG, 0x40019463)); 3906 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3907 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3908 getF32Constant(DAG, 0x3fd6633d)); 3909 3910 result = DAG.getNode(ISD::FADD, dl, 3911 MVT::f32, LogOfExponent, Log2ofMantissa); 3912 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3913 // For floating-point precision of 12: 3914 // 3915 // Log2ofMantissa = 3916 // -2.51285454f + 3917 // (4.07009056f + 3918 // (-2.12067489f + 3919 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3920 // 3921 // error 0.0000876136000, which is better than 13 bits 3922 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3923 getF32Constant(DAG, 0xbda7262e)); 3924 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3925 getF32Constant(DAG, 0x3f25280b)); 3926 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3927 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3928 getF32Constant(DAG, 0x4007b923)); 3929 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3930 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3931 getF32Constant(DAG, 0x40823e2f)); 3932 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3933 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3934 getF32Constant(DAG, 0x4020d29c)); 3935 3936 result = DAG.getNode(ISD::FADD, dl, 3937 MVT::f32, LogOfExponent, Log2ofMantissa); 3938 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3939 // For floating-point precision of 18: 3940 // 3941 // Log2ofMantissa = 3942 // -3.0400495f + 3943 // (6.1129976f + 3944 // (-5.3420409f + 3945 // (3.2865683f + 3946 // (-1.2669343f + 3947 // (0.27515199f - 3948 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3949 // 3950 // error 0.0000018516, which is better than 18 bits 3951 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3952 getF32Constant(DAG, 0xbcd2769e)); 3953 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3954 getF32Constant(DAG, 0x3e8ce0b9)); 3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3956 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3957 getF32Constant(DAG, 0x3fa22ae7)); 3958 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3959 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3960 getF32Constant(DAG, 0x40525723)); 3961 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3962 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3963 getF32Constant(DAG, 0x40aaf200)); 3964 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3965 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3966 getF32Constant(DAG, 0x40c39dad)); 3967 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3968 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3969 getF32Constant(DAG, 0x4042902c)); 3970 3971 result = DAG.getNode(ISD::FADD, dl, 3972 MVT::f32, LogOfExponent, Log2ofMantissa); 3973 } 3974 } else { 3975 // No special expansion. 3976 result = DAG.getNode(ISD::FLOG2, dl, 3977 getValue(I.getArgOperand(0)).getValueType(), 3978 getValue(I.getArgOperand(0))); 3979 } 3980 3981 setValue(&I, result); 3982} 3983 3984/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3985/// limited-precision mode. 3986void 3987SelectionDAGBuilder::visitLog10(const CallInst &I) { 3988 SDValue result; 3989 DebugLoc dl = getCurDebugLoc(); 3990 3991 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3992 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3993 SDValue Op = getValue(I.getArgOperand(0)); 3994 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3995 3996 // Scale the exponent by log10(2) [0.30102999f]. 3997 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3998 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3999 getF32Constant(DAG, 0x3e9a209a)); 4000 4001 // Get the significand and build it into a floating-point number with 4002 // exponent of 1. 4003 SDValue X = GetSignificand(DAG, Op1, dl); 4004 4005 if (LimitFloatPrecision <= 6) { 4006 // For floating-point precision of 6: 4007 // 4008 // Log10ofMantissa = 4009 // -0.50419619f + 4010 // (0.60948995f - 0.10380950f * x) * x; 4011 // 4012 // error 0.0014886165, which is 6 bits 4013 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4014 getF32Constant(DAG, 0xbdd49a13)); 4015 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4016 getF32Constant(DAG, 0x3f1c0789)); 4017 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4018 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4019 getF32Constant(DAG, 0x3f011300)); 4020 4021 result = DAG.getNode(ISD::FADD, dl, 4022 MVT::f32, LogOfExponent, Log10ofMantissa); 4023 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4024 // For floating-point precision of 12: 4025 // 4026 // Log10ofMantissa = 4027 // -0.64831180f + 4028 // (0.91751397f + 4029 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4030 // 4031 // error 0.00019228036, which is better than 12 bits 4032 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4033 getF32Constant(DAG, 0x3d431f31)); 4034 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4035 getF32Constant(DAG, 0x3ea21fb2)); 4036 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4037 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4038 getF32Constant(DAG, 0x3f6ae232)); 4039 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4040 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4041 getF32Constant(DAG, 0x3f25f7c3)); 4042 4043 result = DAG.getNode(ISD::FADD, dl, 4044 MVT::f32, LogOfExponent, Log10ofMantissa); 4045 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4046 // For floating-point precision of 18: 4047 // 4048 // Log10ofMantissa = 4049 // -0.84299375f + 4050 // (1.5327582f + 4051 // (-1.0688956f + 4052 // (0.49102474f + 4053 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4054 // 4055 // error 0.0000037995730, which is better than 18 bits 4056 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4057 getF32Constant(DAG, 0x3c5d51ce)); 4058 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4059 getF32Constant(DAG, 0x3e00685a)); 4060 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4061 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4062 getF32Constant(DAG, 0x3efb6798)); 4063 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4064 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4065 getF32Constant(DAG, 0x3f88d192)); 4066 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4067 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4068 getF32Constant(DAG, 0x3fc4316c)); 4069 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4070 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4071 getF32Constant(DAG, 0x3f57ce70)); 4072 4073 result = DAG.getNode(ISD::FADD, dl, 4074 MVT::f32, LogOfExponent, Log10ofMantissa); 4075 } 4076 } else { 4077 // No special expansion. 4078 result = DAG.getNode(ISD::FLOG10, dl, 4079 getValue(I.getArgOperand(0)).getValueType(), 4080 getValue(I.getArgOperand(0))); 4081 } 4082 4083 setValue(&I, result); 4084} 4085 4086/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4087/// limited-precision mode. 4088void 4089SelectionDAGBuilder::visitExp2(const CallInst &I) { 4090 SDValue result; 4091 DebugLoc dl = getCurDebugLoc(); 4092 4093 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4094 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4095 SDValue Op = getValue(I.getArgOperand(0)); 4096 4097 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4098 4099 // FractionalPartOfX = x - (float)IntegerPartOfX; 4100 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4101 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4102 4103 // IntegerPartOfX <<= 23; 4104 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4105 DAG.getConstant(23, TLI.getPointerTy())); 4106 4107 if (LimitFloatPrecision <= 6) { 4108 // For floating-point precision of 6: 4109 // 4110 // TwoToFractionalPartOfX = 4111 // 0.997535578f + 4112 // (0.735607626f + 0.252464424f * x) * x; 4113 // 4114 // error 0.0144103317, which is 6 bits 4115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4116 getF32Constant(DAG, 0x3e814304)); 4117 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4118 getF32Constant(DAG, 0x3f3c50c8)); 4119 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4120 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4121 getF32Constant(DAG, 0x3f7f5e7e)); 4122 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4123 SDValue TwoToFractionalPartOfX = 4124 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4125 4126 result = DAG.getNode(ISD::BITCAST, dl, 4127 MVT::f32, TwoToFractionalPartOfX); 4128 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4129 // For floating-point precision of 12: 4130 // 4131 // TwoToFractionalPartOfX = 4132 // 0.999892986f + 4133 // (0.696457318f + 4134 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4135 // 4136 // error 0.000107046256, which is 13 to 14 bits 4137 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4138 getF32Constant(DAG, 0x3da235e3)); 4139 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4140 getF32Constant(DAG, 0x3e65b8f3)); 4141 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4142 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4143 getF32Constant(DAG, 0x3f324b07)); 4144 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4145 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4146 getF32Constant(DAG, 0x3f7ff8fd)); 4147 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4148 SDValue TwoToFractionalPartOfX = 4149 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4150 4151 result = DAG.getNode(ISD::BITCAST, dl, 4152 MVT::f32, TwoToFractionalPartOfX); 4153 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4154 // For floating-point precision of 18: 4155 // 4156 // TwoToFractionalPartOfX = 4157 // 0.999999982f + 4158 // (0.693148872f + 4159 // (0.240227044f + 4160 // (0.554906021e-1f + 4161 // (0.961591928e-2f + 4162 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4163 // error 2.47208000*10^(-7), which is better than 18 bits 4164 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4165 getF32Constant(DAG, 0x3924b03e)); 4166 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4167 getF32Constant(DAG, 0x3ab24b87)); 4168 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4169 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4170 getF32Constant(DAG, 0x3c1d8c17)); 4171 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4172 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4173 getF32Constant(DAG, 0x3d634a1d)); 4174 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4175 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4176 getF32Constant(DAG, 0x3e75fe14)); 4177 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4178 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4179 getF32Constant(DAG, 0x3f317234)); 4180 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4181 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4182 getF32Constant(DAG, 0x3f800000)); 4183 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4184 SDValue TwoToFractionalPartOfX = 4185 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4186 4187 result = DAG.getNode(ISD::BITCAST, dl, 4188 MVT::f32, TwoToFractionalPartOfX); 4189 } 4190 } else { 4191 // No special expansion. 4192 result = DAG.getNode(ISD::FEXP2, dl, 4193 getValue(I.getArgOperand(0)).getValueType(), 4194 getValue(I.getArgOperand(0))); 4195 } 4196 4197 setValue(&I, result); 4198} 4199 4200/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4201/// limited-precision mode with x == 10.0f. 4202void 4203SelectionDAGBuilder::visitPow(const CallInst &I) { 4204 SDValue result; 4205 const Value *Val = I.getArgOperand(0); 4206 DebugLoc dl = getCurDebugLoc(); 4207 bool IsExp10 = false; 4208 4209 if (getValue(Val).getValueType() == MVT::f32 && 4210 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4211 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4212 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4213 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4214 APFloat Ten(10.0f); 4215 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4216 } 4217 } 4218 } 4219 4220 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4221 SDValue Op = getValue(I.getArgOperand(1)); 4222 4223 // Put the exponent in the right bit position for later addition to the 4224 // final result: 4225 // 4226 // #define LOG2OF10 3.3219281f 4227 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4228 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4229 getF32Constant(DAG, 0x40549a78)); 4230 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4231 4232 // FractionalPartOfX = x - (float)IntegerPartOfX; 4233 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4234 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4235 4236 // IntegerPartOfX <<= 23; 4237 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4238 DAG.getConstant(23, TLI.getPointerTy())); 4239 4240 if (LimitFloatPrecision <= 6) { 4241 // For floating-point precision of 6: 4242 // 4243 // twoToFractionalPartOfX = 4244 // 0.997535578f + 4245 // (0.735607626f + 0.252464424f * x) * x; 4246 // 4247 // error 0.0144103317, which is 6 bits 4248 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4249 getF32Constant(DAG, 0x3e814304)); 4250 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4251 getF32Constant(DAG, 0x3f3c50c8)); 4252 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4253 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4254 getF32Constant(DAG, 0x3f7f5e7e)); 4255 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4256 SDValue TwoToFractionalPartOfX = 4257 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4258 4259 result = DAG.getNode(ISD::BITCAST, dl, 4260 MVT::f32, TwoToFractionalPartOfX); 4261 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4262 // For floating-point precision of 12: 4263 // 4264 // TwoToFractionalPartOfX = 4265 // 0.999892986f + 4266 // (0.696457318f + 4267 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4268 // 4269 // error 0.000107046256, which is 13 to 14 bits 4270 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4271 getF32Constant(DAG, 0x3da235e3)); 4272 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4273 getF32Constant(DAG, 0x3e65b8f3)); 4274 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4275 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4276 getF32Constant(DAG, 0x3f324b07)); 4277 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4278 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4279 getF32Constant(DAG, 0x3f7ff8fd)); 4280 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4281 SDValue TwoToFractionalPartOfX = 4282 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4283 4284 result = DAG.getNode(ISD::BITCAST, dl, 4285 MVT::f32, TwoToFractionalPartOfX); 4286 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4287 // For floating-point precision of 18: 4288 // 4289 // TwoToFractionalPartOfX = 4290 // 0.999999982f + 4291 // (0.693148872f + 4292 // (0.240227044f + 4293 // (0.554906021e-1f + 4294 // (0.961591928e-2f + 4295 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4296 // error 2.47208000*10^(-7), which is better than 18 bits 4297 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4298 getF32Constant(DAG, 0x3924b03e)); 4299 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4300 getF32Constant(DAG, 0x3ab24b87)); 4301 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4302 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4303 getF32Constant(DAG, 0x3c1d8c17)); 4304 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4305 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4306 getF32Constant(DAG, 0x3d634a1d)); 4307 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4308 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4309 getF32Constant(DAG, 0x3e75fe14)); 4310 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4311 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4312 getF32Constant(DAG, 0x3f317234)); 4313 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4314 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4315 getF32Constant(DAG, 0x3f800000)); 4316 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4317 SDValue TwoToFractionalPartOfX = 4318 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4319 4320 result = DAG.getNode(ISD::BITCAST, dl, 4321 MVT::f32, TwoToFractionalPartOfX); 4322 } 4323 } else { 4324 // No special expansion. 4325 result = DAG.getNode(ISD::FPOW, dl, 4326 getValue(I.getArgOperand(0)).getValueType(), 4327 getValue(I.getArgOperand(0)), 4328 getValue(I.getArgOperand(1))); 4329 } 4330 4331 setValue(&I, result); 4332} 4333 4334 4335/// ExpandPowI - Expand a llvm.powi intrinsic. 4336static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4337 SelectionDAG &DAG) { 4338 // If RHS is a constant, we can expand this out to a multiplication tree, 4339 // otherwise we end up lowering to a call to __powidf2 (for example). When 4340 // optimizing for size, we only want to do this if the expansion would produce 4341 // a small number of multiplies, otherwise we do the full expansion. 4342 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4343 // Get the exponent as a positive value. 4344 unsigned Val = RHSC->getSExtValue(); 4345 if ((int)Val < 0) Val = -Val; 4346 4347 // powi(x, 0) -> 1.0 4348 if (Val == 0) 4349 return DAG.getConstantFP(1.0, LHS.getValueType()); 4350 4351 const Function *F = DAG.getMachineFunction().getFunction(); 4352 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4353 // If optimizing for size, don't insert too many multiplies. This 4354 // inserts up to 5 multiplies. 4355 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4356 // We use the simple binary decomposition method to generate the multiply 4357 // sequence. There are more optimal ways to do this (for example, 4358 // powi(x,15) generates one more multiply than it should), but this has 4359 // the benefit of being both really simple and much better than a libcall. 4360 SDValue Res; // Logically starts equal to 1.0 4361 SDValue CurSquare = LHS; 4362 while (Val) { 4363 if (Val & 1) { 4364 if (Res.getNode()) 4365 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4366 else 4367 Res = CurSquare; // 1.0*CurSquare. 4368 } 4369 4370 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4371 CurSquare, CurSquare); 4372 Val >>= 1; 4373 } 4374 4375 // If the original was negative, invert the result, producing 1/(x*x*x). 4376 if (RHSC->getSExtValue() < 0) 4377 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4378 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4379 return Res; 4380 } 4381 } 4382 4383 // Otherwise, expand to a libcall. 4384 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4385} 4386 4387// getTruncatedArgReg - Find underlying register used for an truncated 4388// argument. 4389static unsigned getTruncatedArgReg(const SDValue &N) { 4390 if (N.getOpcode() != ISD::TRUNCATE) 4391 return 0; 4392 4393 const SDValue &Ext = N.getOperand(0); 4394 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4395 const SDValue &CFR = Ext.getOperand(0); 4396 if (CFR.getOpcode() == ISD::CopyFromReg) 4397 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4398 else 4399 if (CFR.getOpcode() == ISD::TRUNCATE) 4400 return getTruncatedArgReg(CFR); 4401 } 4402 return 0; 4403} 4404 4405/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4406/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4407/// At the end of instruction selection, they will be inserted to the entry BB. 4408bool 4409SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4410 int64_t Offset, 4411 const SDValue &N) { 4412 const Argument *Arg = dyn_cast<Argument>(V); 4413 if (!Arg) 4414 return false; 4415 4416 MachineFunction &MF = DAG.getMachineFunction(); 4417 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4418 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4419 4420 // Ignore inlined function arguments here. 4421 DIVariable DV(Variable); 4422 if (DV.isInlinedFnArgument(MF.getFunction())) 4423 return false; 4424 4425 unsigned Reg = 0; 4426 // Some arguments' frame index is recorded during argument lowering. 4427 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4428 if (Offset) 4429 Reg = TRI->getFrameRegister(MF); 4430 4431 if (!Reg && N.getNode()) { 4432 if (N.getOpcode() == ISD::CopyFromReg) 4433 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4434 else 4435 Reg = getTruncatedArgReg(N); 4436 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4437 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4438 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4439 if (PR) 4440 Reg = PR; 4441 } 4442 } 4443 4444 if (!Reg) { 4445 // Check if ValueMap has reg number. 4446 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4447 if (VMI != FuncInfo.ValueMap.end()) 4448 Reg = VMI->second; 4449 } 4450 4451 if (!Reg && N.getNode()) { 4452 // Check if frame index is available. 4453 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4454 if (FrameIndexSDNode *FINode = 4455 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4456 Reg = TRI->getFrameRegister(MF); 4457 Offset = FINode->getIndex(); 4458 } 4459 } 4460 4461 if (!Reg) 4462 return false; 4463 4464 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4465 TII->get(TargetOpcode::DBG_VALUE)) 4466 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4467 FuncInfo.ArgDbgValues.push_back(&*MIB); 4468 return true; 4469} 4470 4471// VisualStudio defines setjmp as _setjmp 4472#if defined(_MSC_VER) && defined(setjmp) && \ 4473 !defined(setjmp_undefined_for_msvc) 4474# pragma push_macro("setjmp") 4475# undef setjmp 4476# define setjmp_undefined_for_msvc 4477#endif 4478 4479/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4480/// we want to emit this as a call to a named external function, return the name 4481/// otherwise lower it and return null. 4482const char * 4483SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4484 DebugLoc dl = getCurDebugLoc(); 4485 SDValue Res; 4486 4487 switch (Intrinsic) { 4488 default: 4489 // By default, turn this into a target intrinsic node. 4490 visitTargetIntrinsic(I, Intrinsic); 4491 return 0; 4492 case Intrinsic::vastart: visitVAStart(I); return 0; 4493 case Intrinsic::vaend: visitVAEnd(I); return 0; 4494 case Intrinsic::vacopy: visitVACopy(I); return 0; 4495 case Intrinsic::returnaddress: 4496 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4497 getValue(I.getArgOperand(0)))); 4498 return 0; 4499 case Intrinsic::frameaddress: 4500 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4501 getValue(I.getArgOperand(0)))); 4502 return 0; 4503 case Intrinsic::setjmp: 4504 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4505 case Intrinsic::longjmp: 4506 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4507 case Intrinsic::memcpy: { 4508 // Assert for address < 256 since we support only user defined address 4509 // spaces. 4510 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4511 < 256 && 4512 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4513 < 256 && 4514 "Unknown address space"); 4515 SDValue Op1 = getValue(I.getArgOperand(0)); 4516 SDValue Op2 = getValue(I.getArgOperand(1)); 4517 SDValue Op3 = getValue(I.getArgOperand(2)); 4518 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4519 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4520 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4521 MachinePointerInfo(I.getArgOperand(0)), 4522 MachinePointerInfo(I.getArgOperand(1)))); 4523 return 0; 4524 } 4525 case Intrinsic::memset: { 4526 // Assert for address < 256 since we support only user defined address 4527 // spaces. 4528 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4529 < 256 && 4530 "Unknown address space"); 4531 SDValue Op1 = getValue(I.getArgOperand(0)); 4532 SDValue Op2 = getValue(I.getArgOperand(1)); 4533 SDValue Op3 = getValue(I.getArgOperand(2)); 4534 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4535 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4536 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4537 MachinePointerInfo(I.getArgOperand(0)))); 4538 return 0; 4539 } 4540 case Intrinsic::memmove: { 4541 // Assert for address < 256 since we support only user defined address 4542 // spaces. 4543 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4544 < 256 && 4545 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4546 < 256 && 4547 "Unknown address space"); 4548 SDValue Op1 = getValue(I.getArgOperand(0)); 4549 SDValue Op2 = getValue(I.getArgOperand(1)); 4550 SDValue Op3 = getValue(I.getArgOperand(2)); 4551 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4552 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4553 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4554 MachinePointerInfo(I.getArgOperand(0)), 4555 MachinePointerInfo(I.getArgOperand(1)))); 4556 return 0; 4557 } 4558 case Intrinsic::dbg_declare: { 4559 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4560 MDNode *Variable = DI.getVariable(); 4561 const Value *Address = DI.getAddress(); 4562 if (!Address || !DIVariable(Variable).Verify()) 4563 return 0; 4564 4565 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4566 // but do not always have a corresponding SDNode built. The SDNodeOrder 4567 // absolute, but not relative, values are different depending on whether 4568 // debug info exists. 4569 ++SDNodeOrder; 4570 4571 // Check if address has undef value. 4572 if (isa<UndefValue>(Address) || 4573 (Address->use_empty() && !isa<Argument>(Address))) { 4574 DEBUG(dbgs() << "Dropping debug info for " << DI); 4575 return 0; 4576 } 4577 4578 SDValue &N = NodeMap[Address]; 4579 if (!N.getNode() && isa<Argument>(Address)) 4580 // Check unused arguments map. 4581 N = UnusedArgNodeMap[Address]; 4582 SDDbgValue *SDV; 4583 if (N.getNode()) { 4584 // Parameters are handled specially. 4585 bool isParameter = 4586 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4587 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4588 Address = BCI->getOperand(0); 4589 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4590 4591 if (isParameter && !AI) { 4592 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4593 if (FINode) 4594 // Byval parameter. We have a frame index at this point. 4595 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4596 0, dl, SDNodeOrder); 4597 else { 4598 // Address is an argument, so try to emit its dbg value using 4599 // virtual register info from the FuncInfo.ValueMap. 4600 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4601 return 0; 4602 } 4603 } else if (AI) 4604 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4605 0, dl, SDNodeOrder); 4606 else { 4607 // Can't do anything with other non-AI cases yet. 4608 DEBUG(dbgs() << "Dropping debug info for " << DI); 4609 return 0; 4610 } 4611 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4612 } else { 4613 // If Address is an argument then try to emit its dbg value using 4614 // virtual register info from the FuncInfo.ValueMap. 4615 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4616 // If variable is pinned by a alloca in dominating bb then 4617 // use StaticAllocaMap. 4618 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4619 if (AI->getParent() != DI.getParent()) { 4620 DenseMap<const AllocaInst*, int>::iterator SI = 4621 FuncInfo.StaticAllocaMap.find(AI); 4622 if (SI != FuncInfo.StaticAllocaMap.end()) { 4623 SDV = DAG.getDbgValue(Variable, SI->second, 4624 0, dl, SDNodeOrder); 4625 DAG.AddDbgValue(SDV, 0, false); 4626 return 0; 4627 } 4628 } 4629 } 4630 DEBUG(dbgs() << "Dropping debug info for " << DI); 4631 } 4632 } 4633 return 0; 4634 } 4635 case Intrinsic::dbg_value: { 4636 const DbgValueInst &DI = cast<DbgValueInst>(I); 4637 if (!DIVariable(DI.getVariable()).Verify()) 4638 return 0; 4639 4640 MDNode *Variable = DI.getVariable(); 4641 uint64_t Offset = DI.getOffset(); 4642 const Value *V = DI.getValue(); 4643 if (!V) 4644 return 0; 4645 4646 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4647 // but do not always have a corresponding SDNode built. The SDNodeOrder 4648 // absolute, but not relative, values are different depending on whether 4649 // debug info exists. 4650 ++SDNodeOrder; 4651 SDDbgValue *SDV; 4652 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4653 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4654 DAG.AddDbgValue(SDV, 0, false); 4655 } else { 4656 // Do not use getValue() in here; we don't want to generate code at 4657 // this point if it hasn't been done yet. 4658 SDValue N = NodeMap[V]; 4659 if (!N.getNode() && isa<Argument>(V)) 4660 // Check unused arguments map. 4661 N = UnusedArgNodeMap[V]; 4662 if (N.getNode()) { 4663 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4664 SDV = DAG.getDbgValue(Variable, N.getNode(), 4665 N.getResNo(), Offset, dl, SDNodeOrder); 4666 DAG.AddDbgValue(SDV, N.getNode(), false); 4667 } 4668 } else if (!V->use_empty() ) { 4669 // Do not call getValue(V) yet, as we don't want to generate code. 4670 // Remember it for later. 4671 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4672 DanglingDebugInfoMap[V] = DDI; 4673 } else { 4674 // We may expand this to cover more cases. One case where we have no 4675 // data available is an unreferenced parameter. 4676 DEBUG(dbgs() << "Dropping debug info for " << DI); 4677 } 4678 } 4679 4680 // Build a debug info table entry. 4681 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4682 V = BCI->getOperand(0); 4683 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4684 // Don't handle byval struct arguments or VLAs, for example. 4685 if (!AI) 4686 return 0; 4687 DenseMap<const AllocaInst*, int>::iterator SI = 4688 FuncInfo.StaticAllocaMap.find(AI); 4689 if (SI == FuncInfo.StaticAllocaMap.end()) 4690 return 0; // VLAs. 4691 int FI = SI->second; 4692 4693 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4694 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4695 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4696 return 0; 4697 } 4698 case Intrinsic::eh_exception: { 4699 // Insert the EXCEPTIONADDR instruction. 4700 assert(FuncInfo.MBB->isLandingPad() && 4701 "Call to eh.exception not in landing pad!"); 4702 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4703 SDValue Ops[1]; 4704 Ops[0] = DAG.getRoot(); 4705 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4706 setValue(&I, Op); 4707 DAG.setRoot(Op.getValue(1)); 4708 return 0; 4709 } 4710 4711 case Intrinsic::eh_selector: { 4712 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4713 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4714 if (CallMBB->isLandingPad()) 4715 AddCatchInfo(I, &MMI, CallMBB); 4716 else { 4717#ifndef NDEBUG 4718 FuncInfo.CatchInfoLost.insert(&I); 4719#endif 4720 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4721 unsigned Reg = TLI.getExceptionSelectorRegister(); 4722 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4723 } 4724 4725 // Insert the EHSELECTION instruction. 4726 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4727 SDValue Ops[2]; 4728 Ops[0] = getValue(I.getArgOperand(0)); 4729 Ops[1] = getRoot(); 4730 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4731 DAG.setRoot(Op.getValue(1)); 4732 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4733 return 0; 4734 } 4735 4736 case Intrinsic::eh_typeid_for: { 4737 // Find the type id for the given typeinfo. 4738 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4739 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4740 Res = DAG.getConstant(TypeID, MVT::i32); 4741 setValue(&I, Res); 4742 return 0; 4743 } 4744 4745 case Intrinsic::eh_return_i32: 4746 case Intrinsic::eh_return_i64: 4747 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4748 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4749 MVT::Other, 4750 getControlRoot(), 4751 getValue(I.getArgOperand(0)), 4752 getValue(I.getArgOperand(1)))); 4753 return 0; 4754 case Intrinsic::eh_unwind_init: 4755 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4756 return 0; 4757 case Intrinsic::eh_dwarf_cfa: { 4758 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4759 TLI.getPointerTy()); 4760 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4761 TLI.getPointerTy(), 4762 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4763 TLI.getPointerTy()), 4764 CfaArg); 4765 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4766 TLI.getPointerTy(), 4767 DAG.getConstant(0, TLI.getPointerTy())); 4768 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4769 FA, Offset)); 4770 return 0; 4771 } 4772 case Intrinsic::eh_sjlj_callsite: { 4773 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4774 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4775 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4776 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4777 4778 MMI.setCurrentCallSite(CI->getZExtValue()); 4779 return 0; 4780 } 4781 case Intrinsic::eh_sjlj_functioncontext: { 4782 // Get and store the index of the function context. 4783 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4784 AllocaInst *FnCtx = 4785 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4786 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4787 MFI->setFunctionContextIndex(FI); 4788 return 0; 4789 } 4790 case Intrinsic::eh_sjlj_setjmp: { 4791 SDValue Ops[2]; 4792 Ops[0] = getRoot(); 4793 Ops[1] = getValue(I.getArgOperand(0)); 4794 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4795 DAG.getVTList(MVT::i32, MVT::Other), 4796 Ops, 2); 4797 setValue(&I, Op.getValue(0)); 4798 DAG.setRoot(Op.getValue(1)); 4799 return 0; 4800 } 4801 case Intrinsic::eh_sjlj_longjmp: { 4802 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4803 getRoot(), getValue(I.getArgOperand(0)))); 4804 return 0; 4805 } 4806 4807 case Intrinsic::x86_mmx_pslli_w: 4808 case Intrinsic::x86_mmx_pslli_d: 4809 case Intrinsic::x86_mmx_pslli_q: 4810 case Intrinsic::x86_mmx_psrli_w: 4811 case Intrinsic::x86_mmx_psrli_d: 4812 case Intrinsic::x86_mmx_psrli_q: 4813 case Intrinsic::x86_mmx_psrai_w: 4814 case Intrinsic::x86_mmx_psrai_d: { 4815 SDValue ShAmt = getValue(I.getArgOperand(1)); 4816 if (isa<ConstantSDNode>(ShAmt)) { 4817 visitTargetIntrinsic(I, Intrinsic); 4818 return 0; 4819 } 4820 unsigned NewIntrinsic = 0; 4821 EVT ShAmtVT = MVT::v2i32; 4822 switch (Intrinsic) { 4823 case Intrinsic::x86_mmx_pslli_w: 4824 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4825 break; 4826 case Intrinsic::x86_mmx_pslli_d: 4827 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4828 break; 4829 case Intrinsic::x86_mmx_pslli_q: 4830 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4831 break; 4832 case Intrinsic::x86_mmx_psrli_w: 4833 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4834 break; 4835 case Intrinsic::x86_mmx_psrli_d: 4836 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4837 break; 4838 case Intrinsic::x86_mmx_psrli_q: 4839 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4840 break; 4841 case Intrinsic::x86_mmx_psrai_w: 4842 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4843 break; 4844 case Intrinsic::x86_mmx_psrai_d: 4845 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4846 break; 4847 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4848 } 4849 4850 // The vector shift intrinsics with scalars uses 32b shift amounts but 4851 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4852 // to be zero. 4853 // We must do this early because v2i32 is not a legal type. 4854 DebugLoc dl = getCurDebugLoc(); 4855 SDValue ShOps[2]; 4856 ShOps[0] = ShAmt; 4857 ShOps[1] = DAG.getConstant(0, MVT::i32); 4858 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4859 EVT DestVT = TLI.getValueType(I.getType()); 4860 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4861 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4862 DAG.getConstant(NewIntrinsic, MVT::i32), 4863 getValue(I.getArgOperand(0)), ShAmt); 4864 setValue(&I, Res); 4865 return 0; 4866 } 4867 case Intrinsic::convertff: 4868 case Intrinsic::convertfsi: 4869 case Intrinsic::convertfui: 4870 case Intrinsic::convertsif: 4871 case Intrinsic::convertuif: 4872 case Intrinsic::convertss: 4873 case Intrinsic::convertsu: 4874 case Intrinsic::convertus: 4875 case Intrinsic::convertuu: { 4876 ISD::CvtCode Code = ISD::CVT_INVALID; 4877 switch (Intrinsic) { 4878 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4879 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4880 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4881 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4882 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4883 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4884 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4885 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4886 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4887 } 4888 EVT DestVT = TLI.getValueType(I.getType()); 4889 const Value *Op1 = I.getArgOperand(0); 4890 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4891 DAG.getValueType(DestVT), 4892 DAG.getValueType(getValue(Op1).getValueType()), 4893 getValue(I.getArgOperand(1)), 4894 getValue(I.getArgOperand(2)), 4895 Code); 4896 setValue(&I, Res); 4897 return 0; 4898 } 4899 case Intrinsic::sqrt: 4900 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4901 getValue(I.getArgOperand(0)).getValueType(), 4902 getValue(I.getArgOperand(0)))); 4903 return 0; 4904 case Intrinsic::powi: 4905 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4906 getValue(I.getArgOperand(1)), DAG)); 4907 return 0; 4908 case Intrinsic::sin: 4909 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4910 getValue(I.getArgOperand(0)).getValueType(), 4911 getValue(I.getArgOperand(0)))); 4912 return 0; 4913 case Intrinsic::cos: 4914 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4915 getValue(I.getArgOperand(0)).getValueType(), 4916 getValue(I.getArgOperand(0)))); 4917 return 0; 4918 case Intrinsic::log: 4919 visitLog(I); 4920 return 0; 4921 case Intrinsic::log2: 4922 visitLog2(I); 4923 return 0; 4924 case Intrinsic::log10: 4925 visitLog10(I); 4926 return 0; 4927 case Intrinsic::exp: 4928 visitExp(I); 4929 return 0; 4930 case Intrinsic::exp2: 4931 visitExp2(I); 4932 return 0; 4933 case Intrinsic::pow: 4934 visitPow(I); 4935 return 0; 4936 case Intrinsic::fma: 4937 setValue(&I, DAG.getNode(ISD::FMA, dl, 4938 getValue(I.getArgOperand(0)).getValueType(), 4939 getValue(I.getArgOperand(0)), 4940 getValue(I.getArgOperand(1)), 4941 getValue(I.getArgOperand(2)))); 4942 return 0; 4943 case Intrinsic::convert_to_fp16: 4944 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4945 MVT::i16, getValue(I.getArgOperand(0)))); 4946 return 0; 4947 case Intrinsic::convert_from_fp16: 4948 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4949 MVT::f32, getValue(I.getArgOperand(0)))); 4950 return 0; 4951 case Intrinsic::pcmarker: { 4952 SDValue Tmp = getValue(I.getArgOperand(0)); 4953 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4954 return 0; 4955 } 4956 case Intrinsic::readcyclecounter: { 4957 SDValue Op = getRoot(); 4958 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4959 DAG.getVTList(MVT::i64, MVT::Other), 4960 &Op, 1); 4961 setValue(&I, Res); 4962 DAG.setRoot(Res.getValue(1)); 4963 return 0; 4964 } 4965 case Intrinsic::bswap: 4966 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4967 getValue(I.getArgOperand(0)).getValueType(), 4968 getValue(I.getArgOperand(0)))); 4969 return 0; 4970 case Intrinsic::cttz: { 4971 SDValue Arg = getValue(I.getArgOperand(0)); 4972 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4973 EVT Ty = Arg.getValueType(); 4974 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4975 dl, Ty, Arg)); 4976 return 0; 4977 } 4978 case Intrinsic::ctlz: { 4979 SDValue Arg = getValue(I.getArgOperand(0)); 4980 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4981 EVT Ty = Arg.getValueType(); 4982 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4983 dl, Ty, Arg)); 4984 return 0; 4985 } 4986 case Intrinsic::ctpop: { 4987 SDValue Arg = getValue(I.getArgOperand(0)); 4988 EVT Ty = Arg.getValueType(); 4989 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4990 return 0; 4991 } 4992 case Intrinsic::stacksave: { 4993 SDValue Op = getRoot(); 4994 Res = DAG.getNode(ISD::STACKSAVE, dl, 4995 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4996 setValue(&I, Res); 4997 DAG.setRoot(Res.getValue(1)); 4998 return 0; 4999 } 5000 case Intrinsic::stackrestore: { 5001 Res = getValue(I.getArgOperand(0)); 5002 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 5003 return 0; 5004 } 5005 case Intrinsic::stackprotector: { 5006 // Emit code into the DAG to store the stack guard onto the stack. 5007 MachineFunction &MF = DAG.getMachineFunction(); 5008 MachineFrameInfo *MFI = MF.getFrameInfo(); 5009 EVT PtrTy = TLI.getPointerTy(); 5010 5011 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5012 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5013 5014 int FI = FuncInfo.StaticAllocaMap[Slot]; 5015 MFI->setStackProtectorIndex(FI); 5016 5017 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5018 5019 // Store the stack protector onto the stack. 5020 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5021 MachinePointerInfo::getFixedStack(FI), 5022 true, false, 0); 5023 setValue(&I, Res); 5024 DAG.setRoot(Res); 5025 return 0; 5026 } 5027 case Intrinsic::objectsize: { 5028 // If we don't know by now, we're never going to know. 5029 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5030 5031 assert(CI && "Non-constant type in __builtin_object_size?"); 5032 5033 SDValue Arg = getValue(I.getCalledValue()); 5034 EVT Ty = Arg.getValueType(); 5035 5036 if (CI->isZero()) 5037 Res = DAG.getConstant(-1ULL, Ty); 5038 else 5039 Res = DAG.getConstant(0, Ty); 5040 5041 setValue(&I, Res); 5042 return 0; 5043 } 5044 case Intrinsic::var_annotation: 5045 // Discard annotate attributes 5046 return 0; 5047 5048 case Intrinsic::init_trampoline: { 5049 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5050 5051 SDValue Ops[6]; 5052 Ops[0] = getRoot(); 5053 Ops[1] = getValue(I.getArgOperand(0)); 5054 Ops[2] = getValue(I.getArgOperand(1)); 5055 Ops[3] = getValue(I.getArgOperand(2)); 5056 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5057 Ops[5] = DAG.getSrcValue(F); 5058 5059 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5060 5061 DAG.setRoot(Res); 5062 return 0; 5063 } 5064 case Intrinsic::adjust_trampoline: { 5065 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5066 TLI.getPointerTy(), 5067 getValue(I.getArgOperand(0)))); 5068 return 0; 5069 } 5070 case Intrinsic::gcroot: 5071 if (GFI) { 5072 const Value *Alloca = I.getArgOperand(0); 5073 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5074 5075 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5076 GFI->addStackRoot(FI->getIndex(), TypeMap); 5077 } 5078 return 0; 5079 case Intrinsic::gcread: 5080 case Intrinsic::gcwrite: 5081 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5082 case Intrinsic::flt_rounds: 5083 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5084 return 0; 5085 5086 case Intrinsic::expect: { 5087 // Just replace __builtin_expect(exp, c) with EXP. 5088 setValue(&I, getValue(I.getArgOperand(0))); 5089 return 0; 5090 } 5091 5092 case Intrinsic::trap: { 5093 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5094 if (TrapFuncName.empty()) { 5095 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5096 return 0; 5097 } 5098 TargetLowering::ArgListTy Args; 5099 std::pair<SDValue, SDValue> Result = 5100 TLI.LowerCallTo(getRoot(), I.getType(), 5101 false, false, false, false, 0, CallingConv::C, 5102 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 5103 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5104 Args, DAG, getCurDebugLoc()); 5105 DAG.setRoot(Result.second); 5106 return 0; 5107 } 5108 case Intrinsic::uadd_with_overflow: 5109 return implVisitAluOverflow(I, ISD::UADDO); 5110 case Intrinsic::sadd_with_overflow: 5111 return implVisitAluOverflow(I, ISD::SADDO); 5112 case Intrinsic::usub_with_overflow: 5113 return implVisitAluOverflow(I, ISD::USUBO); 5114 case Intrinsic::ssub_with_overflow: 5115 return implVisitAluOverflow(I, ISD::SSUBO); 5116 case Intrinsic::umul_with_overflow: 5117 return implVisitAluOverflow(I, ISD::UMULO); 5118 case Intrinsic::smul_with_overflow: 5119 return implVisitAluOverflow(I, ISD::SMULO); 5120 5121 case Intrinsic::prefetch: { 5122 SDValue Ops[5]; 5123 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5124 Ops[0] = getRoot(); 5125 Ops[1] = getValue(I.getArgOperand(0)); 5126 Ops[2] = getValue(I.getArgOperand(1)); 5127 Ops[3] = getValue(I.getArgOperand(2)); 5128 Ops[4] = getValue(I.getArgOperand(3)); 5129 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5130 DAG.getVTList(MVT::Other), 5131 &Ops[0], 5, 5132 EVT::getIntegerVT(*Context, 8), 5133 MachinePointerInfo(I.getArgOperand(0)), 5134 0, /* align */ 5135 false, /* volatile */ 5136 rw==0, /* read */ 5137 rw==1)); /* write */ 5138 return 0; 5139 } 5140 5141 case Intrinsic::invariant_start: 5142 case Intrinsic::lifetime_start: 5143 // Discard region information. 5144 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5145 return 0; 5146 case Intrinsic::invariant_end: 5147 case Intrinsic::lifetime_end: 5148 // Discard region information. 5149 return 0; 5150 } 5151} 5152 5153void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5154 bool isTailCall, 5155 MachineBasicBlock *LandingPad) { 5156 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5157 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5158 Type *RetTy = FTy->getReturnType(); 5159 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5160 MCSymbol *BeginLabel = 0; 5161 5162 TargetLowering::ArgListTy Args; 5163 TargetLowering::ArgListEntry Entry; 5164 Args.reserve(CS.arg_size()); 5165 5166 // Check whether the function can return without sret-demotion. 5167 SmallVector<ISD::OutputArg, 4> Outs; 5168 SmallVector<uint64_t, 4> Offsets; 5169 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5170 Outs, TLI, &Offsets); 5171 5172 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5173 DAG.getMachineFunction(), 5174 FTy->isVarArg(), Outs, 5175 FTy->getContext()); 5176 5177 SDValue DemoteStackSlot; 5178 int DemoteStackIdx = -100; 5179 5180 if (!CanLowerReturn) { 5181 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5182 FTy->getReturnType()); 5183 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5184 FTy->getReturnType()); 5185 MachineFunction &MF = DAG.getMachineFunction(); 5186 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5187 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5188 5189 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5190 Entry.Node = DemoteStackSlot; 5191 Entry.Ty = StackSlotPtrType; 5192 Entry.isSExt = false; 5193 Entry.isZExt = false; 5194 Entry.isInReg = false; 5195 Entry.isSRet = true; 5196 Entry.isNest = false; 5197 Entry.isByVal = false; 5198 Entry.Alignment = Align; 5199 Args.push_back(Entry); 5200 RetTy = Type::getVoidTy(FTy->getContext()); 5201 } 5202 5203 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5204 i != e; ++i) { 5205 const Value *V = *i; 5206 5207 // Skip empty types 5208 if (V->getType()->isEmptyTy()) 5209 continue; 5210 5211 SDValue ArgNode = getValue(V); 5212 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5213 5214 unsigned attrInd = i - CS.arg_begin() + 1; 5215 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5216 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5217 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5218 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5219 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5220 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5221 Entry.Alignment = CS.getParamAlignment(attrInd); 5222 Args.push_back(Entry); 5223 } 5224 5225 if (LandingPad) { 5226 // Insert a label before the invoke call to mark the try range. This can be 5227 // used to detect deletion of the invoke via the MachineModuleInfo. 5228 BeginLabel = MMI.getContext().CreateTempSymbol(); 5229 5230 // For SjLj, keep track of which landing pads go with which invokes 5231 // so as to maintain the ordering of pads in the LSDA. 5232 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5233 if (CallSiteIndex) { 5234 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5235 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5236 5237 // Now that the call site is handled, stop tracking it. 5238 MMI.setCurrentCallSite(0); 5239 } 5240 5241 // Both PendingLoads and PendingExports must be flushed here; 5242 // this call might not return. 5243 (void)getRoot(); 5244 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5245 } 5246 5247 // Check if target-independent constraints permit a tail call here. 5248 // Target-dependent constraints are checked within TLI.LowerCallTo. 5249 if (isTailCall && 5250 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5251 isTailCall = false; 5252 5253 // If there's a possibility that fast-isel has already selected some amount 5254 // of the current basic block, don't emit a tail call. 5255 if (isTailCall && TM.Options.EnableFastISel) 5256 isTailCall = false; 5257 5258 std::pair<SDValue,SDValue> Result = 5259 TLI.LowerCallTo(getRoot(), RetTy, 5260 CS.paramHasAttr(0, Attribute::SExt), 5261 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5262 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5263 CS.getCallingConv(), 5264 isTailCall, 5265 !CS.getInstruction()->use_empty(), 5266 Callee, Args, DAG, getCurDebugLoc()); 5267 assert((isTailCall || Result.second.getNode()) && 5268 "Non-null chain expected with non-tail call!"); 5269 assert((Result.second.getNode() || !Result.first.getNode()) && 5270 "Null value expected with tail call!"); 5271 if (Result.first.getNode()) { 5272 setValue(CS.getInstruction(), Result.first); 5273 } else if (!CanLowerReturn && Result.second.getNode()) { 5274 // The instruction result is the result of loading from the 5275 // hidden sret parameter. 5276 SmallVector<EVT, 1> PVTs; 5277 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5278 5279 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5280 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5281 EVT PtrVT = PVTs[0]; 5282 unsigned NumValues = Outs.size(); 5283 SmallVector<SDValue, 4> Values(NumValues); 5284 SmallVector<SDValue, 4> Chains(NumValues); 5285 5286 for (unsigned i = 0; i < NumValues; ++i) { 5287 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5288 DemoteStackSlot, 5289 DAG.getConstant(Offsets[i], PtrVT)); 5290 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5291 Add, 5292 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5293 false, false, false, 1); 5294 Values[i] = L; 5295 Chains[i] = L.getValue(1); 5296 } 5297 5298 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5299 MVT::Other, &Chains[0], NumValues); 5300 PendingLoads.push_back(Chain); 5301 5302 // Collect the legal value parts into potentially illegal values 5303 // that correspond to the original function's return values. 5304 SmallVector<EVT, 4> RetTys; 5305 RetTy = FTy->getReturnType(); 5306 ComputeValueVTs(TLI, RetTy, RetTys); 5307 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5308 SmallVector<SDValue, 4> ReturnValues; 5309 unsigned CurReg = 0; 5310 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5311 EVT VT = RetTys[I]; 5312 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5313 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5314 5315 SDValue ReturnValue = 5316 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5317 RegisterVT, VT, AssertOp); 5318 ReturnValues.push_back(ReturnValue); 5319 CurReg += NumRegs; 5320 } 5321 5322 setValue(CS.getInstruction(), 5323 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5324 DAG.getVTList(&RetTys[0], RetTys.size()), 5325 &ReturnValues[0], ReturnValues.size())); 5326 } 5327 5328 // Assign order to nodes here. If the call does not produce a result, it won't 5329 // be mapped to a SDNode and visit() will not assign it an order number. 5330 if (!Result.second.getNode()) { 5331 // As a special case, a null chain means that a tail call has been emitted and 5332 // the DAG root is already updated. 5333 HasTailCall = true; 5334 ++SDNodeOrder; 5335 AssignOrderingToNode(DAG.getRoot().getNode()); 5336 } else { 5337 DAG.setRoot(Result.second); 5338 ++SDNodeOrder; 5339 AssignOrderingToNode(Result.second.getNode()); 5340 } 5341 5342 if (LandingPad) { 5343 // Insert a label at the end of the invoke call to mark the try range. This 5344 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5345 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5346 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5347 5348 // Inform MachineModuleInfo of range. 5349 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5350 } 5351} 5352 5353/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5354/// value is equal or not-equal to zero. 5355static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5356 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5357 UI != E; ++UI) { 5358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5359 if (IC->isEquality()) 5360 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5361 if (C->isNullValue()) 5362 continue; 5363 // Unknown instruction. 5364 return false; 5365 } 5366 return true; 5367} 5368 5369static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5370 Type *LoadTy, 5371 SelectionDAGBuilder &Builder) { 5372 5373 // Check to see if this load can be trivially constant folded, e.g. if the 5374 // input is from a string literal. 5375 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5376 // Cast pointer to the type we really want to load. 5377 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5378 PointerType::getUnqual(LoadTy)); 5379 5380 if (const Constant *LoadCst = 5381 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5382 Builder.TD)) 5383 return Builder.getValue(LoadCst); 5384 } 5385 5386 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5387 // still constant memory, the input chain can be the entry node. 5388 SDValue Root; 5389 bool ConstantMemory = false; 5390 5391 // Do not serialize (non-volatile) loads of constant memory with anything. 5392 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5393 Root = Builder.DAG.getEntryNode(); 5394 ConstantMemory = true; 5395 } else { 5396 // Do not serialize non-volatile loads against each other. 5397 Root = Builder.DAG.getRoot(); 5398 } 5399 5400 SDValue Ptr = Builder.getValue(PtrVal); 5401 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5402 Ptr, MachinePointerInfo(PtrVal), 5403 false /*volatile*/, 5404 false /*nontemporal*/, 5405 false /*isinvariant*/, 1 /* align=1 */); 5406 5407 if (!ConstantMemory) 5408 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5409 return LoadVal; 5410} 5411 5412 5413/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5414/// If so, return true and lower it, otherwise return false and it will be 5415/// lowered like a normal call. 5416bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5417 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5418 if (I.getNumArgOperands() != 3) 5419 return false; 5420 5421 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5422 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5423 !I.getArgOperand(2)->getType()->isIntegerTy() || 5424 !I.getType()->isIntegerTy()) 5425 return false; 5426 5427 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5428 5429 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5430 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5431 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5432 bool ActuallyDoIt = true; 5433 MVT LoadVT; 5434 Type *LoadTy; 5435 switch (Size->getZExtValue()) { 5436 default: 5437 LoadVT = MVT::Other; 5438 LoadTy = 0; 5439 ActuallyDoIt = false; 5440 break; 5441 case 2: 5442 LoadVT = MVT::i16; 5443 LoadTy = Type::getInt16Ty(Size->getContext()); 5444 break; 5445 case 4: 5446 LoadVT = MVT::i32; 5447 LoadTy = Type::getInt32Ty(Size->getContext()); 5448 break; 5449 case 8: 5450 LoadVT = MVT::i64; 5451 LoadTy = Type::getInt64Ty(Size->getContext()); 5452 break; 5453 /* 5454 case 16: 5455 LoadVT = MVT::v4i32; 5456 LoadTy = Type::getInt32Ty(Size->getContext()); 5457 LoadTy = VectorType::get(LoadTy, 4); 5458 break; 5459 */ 5460 } 5461 5462 // This turns into unaligned loads. We only do this if the target natively 5463 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5464 // we'll only produce a small number of byte loads. 5465 5466 // Require that we can find a legal MVT, and only do this if the target 5467 // supports unaligned loads of that type. Expanding into byte loads would 5468 // bloat the code. 5469 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5470 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5471 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5472 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5473 ActuallyDoIt = false; 5474 } 5475 5476 if (ActuallyDoIt) { 5477 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5478 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5479 5480 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5481 ISD::SETNE); 5482 EVT CallVT = TLI.getValueType(I.getType(), true); 5483 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5484 return true; 5485 } 5486 } 5487 5488 5489 return false; 5490} 5491 5492 5493void SelectionDAGBuilder::visitCall(const CallInst &I) { 5494 // Handle inline assembly differently. 5495 if (isa<InlineAsm>(I.getCalledValue())) { 5496 visitInlineAsm(&I); 5497 return; 5498 } 5499 5500 // See if any floating point values are being passed to this function. This is 5501 // used to emit an undefined reference to fltused on Windows. 5502 FunctionType *FT = 5503 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5504 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5505 if (FT->isVarArg() && 5506 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5507 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5508 Type* T = I.getArgOperand(i)->getType(); 5509 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5510 i != e; ++i) { 5511 if (!i->isFloatingPointTy()) continue; 5512 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5513 break; 5514 } 5515 } 5516 } 5517 5518 const char *RenameFn = 0; 5519 if (Function *F = I.getCalledFunction()) { 5520 if (F->isDeclaration()) { 5521 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5522 if (unsigned IID = II->getIntrinsicID(F)) { 5523 RenameFn = visitIntrinsicCall(I, IID); 5524 if (!RenameFn) 5525 return; 5526 } 5527 } 5528 if (unsigned IID = F->getIntrinsicID()) { 5529 RenameFn = visitIntrinsicCall(I, IID); 5530 if (!RenameFn) 5531 return; 5532 } 5533 } 5534 5535 // Check for well-known libc/libm calls. If the function is internal, it 5536 // can't be a library call. 5537 if (!F->hasLocalLinkage() && F->hasName()) { 5538 StringRef Name = F->getName(); 5539 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5540 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5541 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5542 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5543 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5544 I.getType() == I.getArgOperand(0)->getType() && 5545 I.getType() == I.getArgOperand(1)->getType()) { 5546 SDValue LHS = getValue(I.getArgOperand(0)); 5547 SDValue RHS = getValue(I.getArgOperand(1)); 5548 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5549 LHS.getValueType(), LHS, RHS)); 5550 return; 5551 } 5552 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5553 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5554 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5555 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5556 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5557 I.getType() == I.getArgOperand(0)->getType()) { 5558 SDValue Tmp = getValue(I.getArgOperand(0)); 5559 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5560 Tmp.getValueType(), Tmp)); 5561 return; 5562 } 5563 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5564 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5565 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5566 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5567 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5568 I.getType() == I.getArgOperand(0)->getType() && 5569 I.onlyReadsMemory()) { 5570 SDValue Tmp = getValue(I.getArgOperand(0)); 5571 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5572 Tmp.getValueType(), Tmp)); 5573 return; 5574 } 5575 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5576 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5577 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5578 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5579 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5580 I.getType() == I.getArgOperand(0)->getType() && 5581 I.onlyReadsMemory()) { 5582 SDValue Tmp = getValue(I.getArgOperand(0)); 5583 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5584 Tmp.getValueType(), Tmp)); 5585 return; 5586 } 5587 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5588 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5589 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5590 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5591 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5592 I.getType() == I.getArgOperand(0)->getType() && 5593 I.onlyReadsMemory()) { 5594 SDValue Tmp = getValue(I.getArgOperand(0)); 5595 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5596 Tmp.getValueType(), Tmp)); 5597 return; 5598 } 5599 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5600 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5601 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5602 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5603 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5604 I.getType() == I.getArgOperand(0)->getType()) { 5605 SDValue Tmp = getValue(I.getArgOperand(0)); 5606 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5607 Tmp.getValueType(), Tmp)); 5608 return; 5609 } 5610 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5611 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5612 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5613 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5614 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5615 I.getType() == I.getArgOperand(0)->getType()) { 5616 SDValue Tmp = getValue(I.getArgOperand(0)); 5617 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5618 Tmp.getValueType(), Tmp)); 5619 return; 5620 } 5621 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5622 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5623 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5624 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5625 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5626 I.getType() == I.getArgOperand(0)->getType()) { 5627 SDValue Tmp = getValue(I.getArgOperand(0)); 5628 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5629 Tmp.getValueType(), Tmp)); 5630 return; 5631 } 5632 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5633 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5634 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5635 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5636 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5637 I.getType() == I.getArgOperand(0)->getType()) { 5638 SDValue Tmp = getValue(I.getArgOperand(0)); 5639 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5640 Tmp.getValueType(), Tmp)); 5641 return; 5642 } 5643 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5644 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5645 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5646 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5647 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5648 I.getType() == I.getArgOperand(0)->getType()) { 5649 SDValue Tmp = getValue(I.getArgOperand(0)); 5650 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5651 Tmp.getValueType(), Tmp)); 5652 return; 5653 } 5654 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5655 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5656 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5657 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5658 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5659 I.getType() == I.getArgOperand(0)->getType()) { 5660 SDValue Tmp = getValue(I.getArgOperand(0)); 5661 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5662 Tmp.getValueType(), Tmp)); 5663 return; 5664 } 5665 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5666 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5667 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5668 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5669 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5670 I.getType() == I.getArgOperand(0)->getType()) { 5671 SDValue Tmp = getValue(I.getArgOperand(0)); 5672 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5673 Tmp.getValueType(), Tmp)); 5674 return; 5675 } 5676 } else if (Name == "memcmp") { 5677 if (visitMemCmpCall(I)) 5678 return; 5679 } 5680 } 5681 } 5682 5683 SDValue Callee; 5684 if (!RenameFn) 5685 Callee = getValue(I.getCalledValue()); 5686 else 5687 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5688 5689 // Check if we can potentially perform a tail call. More detailed checking is 5690 // be done within LowerCallTo, after more information about the call is known. 5691 LowerCallTo(&I, Callee, I.isTailCall()); 5692} 5693 5694namespace { 5695 5696/// AsmOperandInfo - This contains information for each constraint that we are 5697/// lowering. 5698class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5699public: 5700 /// CallOperand - If this is the result output operand or a clobber 5701 /// this is null, otherwise it is the incoming operand to the CallInst. 5702 /// This gets modified as the asm is processed. 5703 SDValue CallOperand; 5704 5705 /// AssignedRegs - If this is a register or register class operand, this 5706 /// contains the set of register corresponding to the operand. 5707 RegsForValue AssignedRegs; 5708 5709 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5710 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5711 } 5712 5713 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5714 /// busy in OutputRegs/InputRegs. 5715 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5716 std::set<unsigned> &OutputRegs, 5717 std::set<unsigned> &InputRegs, 5718 const TargetRegisterInfo &TRI) const { 5719 if (isOutReg) { 5720 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5721 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5722 } 5723 if (isInReg) { 5724 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5725 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5726 } 5727 } 5728 5729 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5730 /// corresponds to. If there is no Value* for this operand, it returns 5731 /// MVT::Other. 5732 EVT getCallOperandValEVT(LLVMContext &Context, 5733 const TargetLowering &TLI, 5734 const TargetData *TD) const { 5735 if (CallOperandVal == 0) return MVT::Other; 5736 5737 if (isa<BasicBlock>(CallOperandVal)) 5738 return TLI.getPointerTy(); 5739 5740 llvm::Type *OpTy = CallOperandVal->getType(); 5741 5742 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5743 // If this is an indirect operand, the operand is a pointer to the 5744 // accessed type. 5745 if (isIndirect) { 5746 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5747 if (!PtrTy) 5748 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5749 OpTy = PtrTy->getElementType(); 5750 } 5751 5752 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5753 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5754 if (STy->getNumElements() == 1) 5755 OpTy = STy->getElementType(0); 5756 5757 // If OpTy is not a single value, it may be a struct/union that we 5758 // can tile with integers. 5759 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5760 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5761 switch (BitSize) { 5762 default: break; 5763 case 1: 5764 case 8: 5765 case 16: 5766 case 32: 5767 case 64: 5768 case 128: 5769 OpTy = IntegerType::get(Context, BitSize); 5770 break; 5771 } 5772 } 5773 5774 return TLI.getValueType(OpTy, true); 5775 } 5776 5777private: 5778 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5779 /// specified set. 5780 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5781 const TargetRegisterInfo &TRI) { 5782 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5783 Regs.insert(Reg); 5784 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5785 for (; *Aliases; ++Aliases) 5786 Regs.insert(*Aliases); 5787 } 5788}; 5789 5790typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5791 5792} // end anonymous namespace 5793 5794/// GetRegistersForValue - Assign registers (virtual or physical) for the 5795/// specified operand. We prefer to assign virtual registers, to allow the 5796/// register allocator to handle the assignment process. However, if the asm 5797/// uses features that we can't model on machineinstrs, we have SDISel do the 5798/// allocation. This produces generally horrible, but correct, code. 5799/// 5800/// OpInfo describes the operand. 5801/// Input and OutputRegs are the set of already allocated physical registers. 5802/// 5803static void GetRegistersForValue(SelectionDAG &DAG, 5804 const TargetLowering &TLI, 5805 DebugLoc DL, 5806 SDISelAsmOperandInfo &OpInfo, 5807 std::set<unsigned> &OutputRegs, 5808 std::set<unsigned> &InputRegs) { 5809 LLVMContext &Context = *DAG.getContext(); 5810 5811 // Compute whether this value requires an input register, an output register, 5812 // or both. 5813 bool isOutReg = false; 5814 bool isInReg = false; 5815 switch (OpInfo.Type) { 5816 case InlineAsm::isOutput: 5817 isOutReg = true; 5818 5819 // If there is an input constraint that matches this, we need to reserve 5820 // the input register so no other inputs allocate to it. 5821 isInReg = OpInfo.hasMatchingInput(); 5822 break; 5823 case InlineAsm::isInput: 5824 isInReg = true; 5825 isOutReg = false; 5826 break; 5827 case InlineAsm::isClobber: 5828 isOutReg = true; 5829 isInReg = true; 5830 break; 5831 } 5832 5833 5834 MachineFunction &MF = DAG.getMachineFunction(); 5835 SmallVector<unsigned, 4> Regs; 5836 5837 // If this is a constraint for a single physreg, or a constraint for a 5838 // register class, find it. 5839 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5840 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5841 OpInfo.ConstraintVT); 5842 5843 unsigned NumRegs = 1; 5844 if (OpInfo.ConstraintVT != MVT::Other) { 5845 // If this is a FP input in an integer register (or visa versa) insert a bit 5846 // cast of the input value. More generally, handle any case where the input 5847 // value disagrees with the register class we plan to stick this in. 5848 if (OpInfo.Type == InlineAsm::isInput && 5849 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5850 // Try to convert to the first EVT that the reg class contains. If the 5851 // types are identical size, use a bitcast to convert (e.g. two differing 5852 // vector types). 5853 EVT RegVT = *PhysReg.second->vt_begin(); 5854 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5855 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5856 RegVT, OpInfo.CallOperand); 5857 OpInfo.ConstraintVT = RegVT; 5858 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5859 // If the input is a FP value and we want it in FP registers, do a 5860 // bitcast to the corresponding integer type. This turns an f64 value 5861 // into i64, which can be passed with two i32 values on a 32-bit 5862 // machine. 5863 RegVT = EVT::getIntegerVT(Context, 5864 OpInfo.ConstraintVT.getSizeInBits()); 5865 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5866 RegVT, OpInfo.CallOperand); 5867 OpInfo.ConstraintVT = RegVT; 5868 } 5869 } 5870 5871 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5872 } 5873 5874 EVT RegVT; 5875 EVT ValueVT = OpInfo.ConstraintVT; 5876 5877 // If this is a constraint for a specific physical register, like {r17}, 5878 // assign it now. 5879 if (unsigned AssignedReg = PhysReg.first) { 5880 const TargetRegisterClass *RC = PhysReg.second; 5881 if (OpInfo.ConstraintVT == MVT::Other) 5882 ValueVT = *RC->vt_begin(); 5883 5884 // Get the actual register value type. This is important, because the user 5885 // may have asked for (e.g.) the AX register in i32 type. We need to 5886 // remember that AX is actually i16 to get the right extension. 5887 RegVT = *RC->vt_begin(); 5888 5889 // This is a explicit reference to a physical register. 5890 Regs.push_back(AssignedReg); 5891 5892 // If this is an expanded reference, add the rest of the regs to Regs. 5893 if (NumRegs != 1) { 5894 TargetRegisterClass::iterator I = RC->begin(); 5895 for (; *I != AssignedReg; ++I) 5896 assert(I != RC->end() && "Didn't find reg!"); 5897 5898 // Already added the first reg. 5899 --NumRegs; ++I; 5900 for (; NumRegs; --NumRegs, ++I) { 5901 assert(I != RC->end() && "Ran out of registers to allocate!"); 5902 Regs.push_back(*I); 5903 } 5904 } 5905 5906 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5907 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5908 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5909 return; 5910 } 5911 5912 // Otherwise, if this was a reference to an LLVM register class, create vregs 5913 // for this reference. 5914 if (const TargetRegisterClass *RC = PhysReg.second) { 5915 RegVT = *RC->vt_begin(); 5916 if (OpInfo.ConstraintVT == MVT::Other) 5917 ValueVT = RegVT; 5918 5919 // Create the appropriate number of virtual registers. 5920 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5921 for (; NumRegs; --NumRegs) 5922 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5923 5924 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5925 return; 5926 } 5927 5928 // Otherwise, we couldn't allocate enough registers for this. 5929} 5930 5931/// visitInlineAsm - Handle a call to an InlineAsm object. 5932/// 5933void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5934 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5935 5936 /// ConstraintOperands - Information about all of the constraints. 5937 SDISelAsmOperandInfoVector ConstraintOperands; 5938 5939 std::set<unsigned> OutputRegs, InputRegs; 5940 5941 TargetLowering::AsmOperandInfoVector 5942 TargetConstraints = TLI.ParseConstraints(CS); 5943 5944 bool hasMemory = false; 5945 5946 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5947 unsigned ResNo = 0; // ResNo - The result number of the next output. 5948 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5949 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5950 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5951 5952 EVT OpVT = MVT::Other; 5953 5954 // Compute the value type for each operand. 5955 switch (OpInfo.Type) { 5956 case InlineAsm::isOutput: 5957 // Indirect outputs just consume an argument. 5958 if (OpInfo.isIndirect) { 5959 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5960 break; 5961 } 5962 5963 // The return value of the call is this value. As such, there is no 5964 // corresponding argument. 5965 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5966 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5967 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5968 } else { 5969 assert(ResNo == 0 && "Asm only has one result!"); 5970 OpVT = TLI.getValueType(CS.getType()); 5971 } 5972 ++ResNo; 5973 break; 5974 case InlineAsm::isInput: 5975 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5976 break; 5977 case InlineAsm::isClobber: 5978 // Nothing to do. 5979 break; 5980 } 5981 5982 // If this is an input or an indirect output, process the call argument. 5983 // BasicBlocks are labels, currently appearing only in asm's. 5984 if (OpInfo.CallOperandVal) { 5985 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5986 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5987 } else { 5988 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5989 } 5990 5991 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5992 } 5993 5994 OpInfo.ConstraintVT = OpVT; 5995 5996 // Indirect operand accesses access memory. 5997 if (OpInfo.isIndirect) 5998 hasMemory = true; 5999 else { 6000 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 6001 TargetLowering::ConstraintType 6002 CType = TLI.getConstraintType(OpInfo.Codes[j]); 6003 if (CType == TargetLowering::C_Memory) { 6004 hasMemory = true; 6005 break; 6006 } 6007 } 6008 } 6009 } 6010 6011 SDValue Chain, Flag; 6012 6013 // We won't need to flush pending loads if this asm doesn't touch 6014 // memory and is nonvolatile. 6015 if (hasMemory || IA->hasSideEffects()) 6016 Chain = getRoot(); 6017 else 6018 Chain = DAG.getRoot(); 6019 6020 // Second pass over the constraints: compute which constraint option to use 6021 // and assign registers to constraints that want a specific physreg. 6022 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6023 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6024 6025 // If this is an output operand with a matching input operand, look up the 6026 // matching input. If their types mismatch, e.g. one is an integer, the 6027 // other is floating point, or their sizes are different, flag it as an 6028 // error. 6029 if (OpInfo.hasMatchingInput()) { 6030 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 6031 6032 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 6033 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 6034 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 6035 OpInfo.ConstraintVT); 6036 std::pair<unsigned, const TargetRegisterClass*> InputRC = 6037 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 6038 Input.ConstraintVT); 6039 if ((OpInfo.ConstraintVT.isInteger() != 6040 Input.ConstraintVT.isInteger()) || 6041 (MatchRC.second != InputRC.second)) { 6042 report_fatal_error("Unsupported asm: input constraint" 6043 " with a matching output constraint of" 6044 " incompatible type!"); 6045 } 6046 Input.ConstraintVT = OpInfo.ConstraintVT; 6047 } 6048 } 6049 6050 // Compute the constraint code and ConstraintType to use. 6051 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 6052 6053 // If this is a memory input, and if the operand is not indirect, do what we 6054 // need to to provide an address for the memory input. 6055 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6056 !OpInfo.isIndirect) { 6057 assert((OpInfo.isMultipleAlternative || 6058 (OpInfo.Type == InlineAsm::isInput)) && 6059 "Can only indirectify direct input operands!"); 6060 6061 // Memory operands really want the address of the value. If we don't have 6062 // an indirect input, put it in the constpool if we can, otherwise spill 6063 // it to a stack slot. 6064 // TODO: This isn't quite right. We need to handle these according to 6065 // the addressing mode that the constraint wants. Also, this may take 6066 // an additional register for the computation and we don't want that 6067 // either. 6068 6069 // If the operand is a float, integer, or vector constant, spill to a 6070 // constant pool entry to get its address. 6071 const Value *OpVal = OpInfo.CallOperandVal; 6072 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6073 isa<ConstantVector>(OpVal)) { 6074 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6075 TLI.getPointerTy()); 6076 } else { 6077 // Otherwise, create a stack slot and emit a store to it before the 6078 // asm. 6079 Type *Ty = OpVal->getType(); 6080 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6081 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6082 MachineFunction &MF = DAG.getMachineFunction(); 6083 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6084 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6085 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6086 OpInfo.CallOperand, StackSlot, 6087 MachinePointerInfo::getFixedStack(SSFI), 6088 false, false, 0); 6089 OpInfo.CallOperand = StackSlot; 6090 } 6091 6092 // There is no longer a Value* corresponding to this operand. 6093 OpInfo.CallOperandVal = 0; 6094 6095 // It is now an indirect operand. 6096 OpInfo.isIndirect = true; 6097 } 6098 6099 // If this constraint is for a specific register, allocate it before 6100 // anything else. 6101 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6102 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6103 InputRegs); 6104 } 6105 6106 // Second pass - Loop over all of the operands, assigning virtual or physregs 6107 // to register class operands. 6108 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6109 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6110 6111 // C_Register operands have already been allocated, Other/Memory don't need 6112 // to be. 6113 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6114 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6115 InputRegs); 6116 } 6117 6118 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6119 std::vector<SDValue> AsmNodeOperands; 6120 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6121 AsmNodeOperands.push_back( 6122 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6123 TLI.getPointerTy())); 6124 6125 // If we have a !srcloc metadata node associated with it, we want to attach 6126 // this to the ultimately generated inline asm machineinstr. To do this, we 6127 // pass in the third operand as this (potentially null) inline asm MDNode. 6128 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6129 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6130 6131 // Remember the HasSideEffect and AlignStack bits as operand 3. 6132 unsigned ExtraInfo = 0; 6133 if (IA->hasSideEffects()) 6134 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6135 if (IA->isAlignStack()) 6136 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6137 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6138 TLI.getPointerTy())); 6139 6140 // Loop over all of the inputs, copying the operand values into the 6141 // appropriate registers and processing the output regs. 6142 RegsForValue RetValRegs; 6143 6144 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6145 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6146 6147 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6148 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6149 6150 switch (OpInfo.Type) { 6151 case InlineAsm::isOutput: { 6152 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6153 OpInfo.ConstraintType != TargetLowering::C_Register) { 6154 // Memory output, or 'other' output (e.g. 'X' constraint). 6155 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6156 6157 // Add information to the INLINEASM node to know about this output. 6158 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6159 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6160 TLI.getPointerTy())); 6161 AsmNodeOperands.push_back(OpInfo.CallOperand); 6162 break; 6163 } 6164 6165 // Otherwise, this is a register or register class output. 6166 6167 // Copy the output from the appropriate register. Find a register that 6168 // we can use. 6169 if (OpInfo.AssignedRegs.Regs.empty()) { 6170 LLVMContext &Ctx = *DAG.getContext(); 6171 Ctx.emitError(CS.getInstruction(), 6172 "couldn't allocate output register for constraint '" + 6173 Twine(OpInfo.ConstraintCode) + "'"); 6174 break; 6175 } 6176 6177 // If this is an indirect operand, store through the pointer after the 6178 // asm. 6179 if (OpInfo.isIndirect) { 6180 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6181 OpInfo.CallOperandVal)); 6182 } else { 6183 // This is the result value of the call. 6184 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6185 // Concatenate this output onto the outputs list. 6186 RetValRegs.append(OpInfo.AssignedRegs); 6187 } 6188 6189 // Add information to the INLINEASM node to know that this register is 6190 // set. 6191 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6192 InlineAsm::Kind_RegDefEarlyClobber : 6193 InlineAsm::Kind_RegDef, 6194 false, 6195 0, 6196 DAG, 6197 AsmNodeOperands); 6198 break; 6199 } 6200 case InlineAsm::isInput: { 6201 SDValue InOperandVal = OpInfo.CallOperand; 6202 6203 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6204 // If this is required to match an output register we have already set, 6205 // just use its register. 6206 unsigned OperandNo = OpInfo.getMatchedOperand(); 6207 6208 // Scan until we find the definition we already emitted of this operand. 6209 // When we find it, create a RegsForValue operand. 6210 unsigned CurOp = InlineAsm::Op_FirstOperand; 6211 for (; OperandNo; --OperandNo) { 6212 // Advance to the next operand. 6213 unsigned OpFlag = 6214 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6215 assert((InlineAsm::isRegDefKind(OpFlag) || 6216 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6217 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6218 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6219 } 6220 6221 unsigned OpFlag = 6222 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6223 if (InlineAsm::isRegDefKind(OpFlag) || 6224 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6225 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6226 if (OpInfo.isIndirect) { 6227 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6228 LLVMContext &Ctx = *DAG.getContext(); 6229 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6230 " don't know how to handle tied " 6231 "indirect register inputs"); 6232 } 6233 6234 RegsForValue MatchedRegs; 6235 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6236 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6237 MatchedRegs.RegVTs.push_back(RegVT); 6238 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6239 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6240 i != e; ++i) 6241 MatchedRegs.Regs.push_back 6242 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6243 6244 // Use the produced MatchedRegs object to 6245 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6246 Chain, &Flag); 6247 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6248 true, OpInfo.getMatchedOperand(), 6249 DAG, AsmNodeOperands); 6250 break; 6251 } 6252 6253 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6254 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6255 "Unexpected number of operands"); 6256 // Add information to the INLINEASM node to know about this input. 6257 // See InlineAsm.h isUseOperandTiedToDef. 6258 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6259 OpInfo.getMatchedOperand()); 6260 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6261 TLI.getPointerTy())); 6262 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6263 break; 6264 } 6265 6266 // Treat indirect 'X' constraint as memory. 6267 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6268 OpInfo.isIndirect) 6269 OpInfo.ConstraintType = TargetLowering::C_Memory; 6270 6271 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6272 std::vector<SDValue> Ops; 6273 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6274 Ops, DAG); 6275 if (Ops.empty()) { 6276 LLVMContext &Ctx = *DAG.getContext(); 6277 Ctx.emitError(CS.getInstruction(), 6278 "invalid operand for inline asm constraint '" + 6279 Twine(OpInfo.ConstraintCode) + "'"); 6280 break; 6281 } 6282 6283 // Add information to the INLINEASM node to know about this input. 6284 unsigned ResOpType = 6285 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6286 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6287 TLI.getPointerTy())); 6288 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6289 break; 6290 } 6291 6292 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6293 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6294 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6295 "Memory operands expect pointer values"); 6296 6297 // Add information to the INLINEASM node to know about this input. 6298 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6299 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6300 TLI.getPointerTy())); 6301 AsmNodeOperands.push_back(InOperandVal); 6302 break; 6303 } 6304 6305 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6306 OpInfo.ConstraintType == TargetLowering::C_Register) && 6307 "Unknown constraint type!"); 6308 assert(!OpInfo.isIndirect && 6309 "Don't know how to handle indirect register inputs yet!"); 6310 6311 // Copy the input into the appropriate registers. 6312 if (OpInfo.AssignedRegs.Regs.empty()) { 6313 LLVMContext &Ctx = *DAG.getContext(); 6314 Ctx.emitError(CS.getInstruction(), 6315 "couldn't allocate input reg for constraint '" + 6316 Twine(OpInfo.ConstraintCode) + "'"); 6317 break; 6318 } 6319 6320 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6321 Chain, &Flag); 6322 6323 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6324 DAG, AsmNodeOperands); 6325 break; 6326 } 6327 case InlineAsm::isClobber: { 6328 // Add the clobbered value to the operand list, so that the register 6329 // allocator is aware that the physreg got clobbered. 6330 if (!OpInfo.AssignedRegs.Regs.empty()) 6331 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6332 false, 0, DAG, 6333 AsmNodeOperands); 6334 break; 6335 } 6336 } 6337 } 6338 6339 // Finish up input operands. Set the input chain and add the flag last. 6340 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6341 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6342 6343 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6344 DAG.getVTList(MVT::Other, MVT::Glue), 6345 &AsmNodeOperands[0], AsmNodeOperands.size()); 6346 Flag = Chain.getValue(1); 6347 6348 // If this asm returns a register value, copy the result from that register 6349 // and set it as the value of the call. 6350 if (!RetValRegs.Regs.empty()) { 6351 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6352 Chain, &Flag); 6353 6354 // FIXME: Why don't we do this for inline asms with MRVs? 6355 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6356 EVT ResultType = TLI.getValueType(CS.getType()); 6357 6358 // If any of the results of the inline asm is a vector, it may have the 6359 // wrong width/num elts. This can happen for register classes that can 6360 // contain multiple different value types. The preg or vreg allocated may 6361 // not have the same VT as was expected. Convert it to the right type 6362 // with bit_convert. 6363 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6364 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6365 ResultType, Val); 6366 6367 } else if (ResultType != Val.getValueType() && 6368 ResultType.isInteger() && Val.getValueType().isInteger()) { 6369 // If a result value was tied to an input value, the computed result may 6370 // have a wider width than the expected result. Extract the relevant 6371 // portion. 6372 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6373 } 6374 6375 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6376 } 6377 6378 setValue(CS.getInstruction(), Val); 6379 // Don't need to use this as a chain in this case. 6380 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6381 return; 6382 } 6383 6384 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6385 6386 // Process indirect outputs, first output all of the flagged copies out of 6387 // physregs. 6388 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6389 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6390 const Value *Ptr = IndirectStoresToEmit[i].second; 6391 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6392 Chain, &Flag); 6393 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6394 } 6395 6396 // Emit the non-flagged stores from the physregs. 6397 SmallVector<SDValue, 8> OutChains; 6398 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6399 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6400 StoresToEmit[i].first, 6401 getValue(StoresToEmit[i].second), 6402 MachinePointerInfo(StoresToEmit[i].second), 6403 false, false, 0); 6404 OutChains.push_back(Val); 6405 } 6406 6407 if (!OutChains.empty()) 6408 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6409 &OutChains[0], OutChains.size()); 6410 6411 DAG.setRoot(Chain); 6412} 6413 6414void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6415 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6416 MVT::Other, getRoot(), 6417 getValue(I.getArgOperand(0)), 6418 DAG.getSrcValue(I.getArgOperand(0)))); 6419} 6420 6421void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6422 const TargetData &TD = *TLI.getTargetData(); 6423 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6424 getRoot(), getValue(I.getOperand(0)), 6425 DAG.getSrcValue(I.getOperand(0)), 6426 TD.getABITypeAlignment(I.getType())); 6427 setValue(&I, V); 6428 DAG.setRoot(V.getValue(1)); 6429} 6430 6431void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6432 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6433 MVT::Other, getRoot(), 6434 getValue(I.getArgOperand(0)), 6435 DAG.getSrcValue(I.getArgOperand(0)))); 6436} 6437 6438void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6439 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6440 MVT::Other, getRoot(), 6441 getValue(I.getArgOperand(0)), 6442 getValue(I.getArgOperand(1)), 6443 DAG.getSrcValue(I.getArgOperand(0)), 6444 DAG.getSrcValue(I.getArgOperand(1)))); 6445} 6446 6447/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6448/// implementation, which just calls LowerCall. 6449/// FIXME: When all targets are 6450/// migrated to using LowerCall, this hook should be integrated into SDISel. 6451std::pair<SDValue, SDValue> 6452TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6453 bool RetSExt, bool RetZExt, bool isVarArg, 6454 bool isInreg, unsigned NumFixedArgs, 6455 CallingConv::ID CallConv, bool isTailCall, 6456 bool isReturnValueUsed, 6457 SDValue Callee, 6458 ArgListTy &Args, SelectionDAG &DAG, 6459 DebugLoc dl) const { 6460 // Handle all of the outgoing arguments. 6461 SmallVector<ISD::OutputArg, 32> Outs; 6462 SmallVector<SDValue, 32> OutVals; 6463 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6464 SmallVector<EVT, 4> ValueVTs; 6465 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6466 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6467 Value != NumValues; ++Value) { 6468 EVT VT = ValueVTs[Value]; 6469 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6470 SDValue Op = SDValue(Args[i].Node.getNode(), 6471 Args[i].Node.getResNo() + Value); 6472 ISD::ArgFlagsTy Flags; 6473 unsigned OriginalAlignment = 6474 getTargetData()->getABITypeAlignment(ArgTy); 6475 6476 if (Args[i].isZExt) 6477 Flags.setZExt(); 6478 if (Args[i].isSExt) 6479 Flags.setSExt(); 6480 if (Args[i].isInReg) 6481 Flags.setInReg(); 6482 if (Args[i].isSRet) 6483 Flags.setSRet(); 6484 if (Args[i].isByVal) { 6485 Flags.setByVal(); 6486 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6487 Type *ElementTy = Ty->getElementType(); 6488 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6489 // For ByVal, alignment should come from FE. BE will guess if this 6490 // info is not there but there are cases it cannot get right. 6491 unsigned FrameAlign; 6492 if (Args[i].Alignment) 6493 FrameAlign = Args[i].Alignment; 6494 else 6495 FrameAlign = getByValTypeAlignment(ElementTy); 6496 Flags.setByValAlign(FrameAlign); 6497 } 6498 if (Args[i].isNest) 6499 Flags.setNest(); 6500 Flags.setOrigAlign(OriginalAlignment); 6501 6502 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6503 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6504 SmallVector<SDValue, 4> Parts(NumParts); 6505 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6506 6507 if (Args[i].isSExt) 6508 ExtendKind = ISD::SIGN_EXTEND; 6509 else if (Args[i].isZExt) 6510 ExtendKind = ISD::ZERO_EXTEND; 6511 6512 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6513 PartVT, ExtendKind); 6514 6515 for (unsigned j = 0; j != NumParts; ++j) { 6516 // if it isn't first piece, alignment must be 1 6517 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6518 i < NumFixedArgs); 6519 if (NumParts > 1 && j == 0) 6520 MyFlags.Flags.setSplit(); 6521 else if (j != 0) 6522 MyFlags.Flags.setOrigAlign(1); 6523 6524 Outs.push_back(MyFlags); 6525 OutVals.push_back(Parts[j]); 6526 } 6527 } 6528 } 6529 6530 // Handle the incoming return values from the call. 6531 SmallVector<ISD::InputArg, 32> Ins; 6532 SmallVector<EVT, 4> RetTys; 6533 ComputeValueVTs(*this, RetTy, RetTys); 6534 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6535 EVT VT = RetTys[I]; 6536 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6537 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6538 for (unsigned i = 0; i != NumRegs; ++i) { 6539 ISD::InputArg MyFlags; 6540 MyFlags.VT = RegisterVT.getSimpleVT(); 6541 MyFlags.Used = isReturnValueUsed; 6542 if (RetSExt) 6543 MyFlags.Flags.setSExt(); 6544 if (RetZExt) 6545 MyFlags.Flags.setZExt(); 6546 if (isInreg) 6547 MyFlags.Flags.setInReg(); 6548 Ins.push_back(MyFlags); 6549 } 6550 } 6551 6552 SmallVector<SDValue, 4> InVals; 6553 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6554 Outs, OutVals, Ins, dl, DAG, InVals); 6555 6556 // Verify that the target's LowerCall behaved as expected. 6557 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6558 "LowerCall didn't return a valid chain!"); 6559 assert((!isTailCall || InVals.empty()) && 6560 "LowerCall emitted a return value for a tail call!"); 6561 assert((isTailCall || InVals.size() == Ins.size()) && 6562 "LowerCall didn't emit the correct number of values!"); 6563 6564 // For a tail call, the return value is merely live-out and there aren't 6565 // any nodes in the DAG representing it. Return a special value to 6566 // indicate that a tail call has been emitted and no more Instructions 6567 // should be processed in the current block. 6568 if (isTailCall) { 6569 DAG.setRoot(Chain); 6570 return std::make_pair(SDValue(), SDValue()); 6571 } 6572 6573 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6574 assert(InVals[i].getNode() && 6575 "LowerCall emitted a null value!"); 6576 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6577 "LowerCall emitted a value with the wrong type!"); 6578 }); 6579 6580 // Collect the legal value parts into potentially illegal values 6581 // that correspond to the original function's return values. 6582 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6583 if (RetSExt) 6584 AssertOp = ISD::AssertSext; 6585 else if (RetZExt) 6586 AssertOp = ISD::AssertZext; 6587 SmallVector<SDValue, 4> ReturnValues; 6588 unsigned CurReg = 0; 6589 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6590 EVT VT = RetTys[I]; 6591 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6592 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6593 6594 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6595 NumRegs, RegisterVT, VT, 6596 AssertOp)); 6597 CurReg += NumRegs; 6598 } 6599 6600 // For a function returning void, there is no return value. We can't create 6601 // such a node, so we just return a null return value in that case. In 6602 // that case, nothing will actually look at the value. 6603 if (ReturnValues.empty()) 6604 return std::make_pair(SDValue(), Chain); 6605 6606 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6607 DAG.getVTList(&RetTys[0], RetTys.size()), 6608 &ReturnValues[0], ReturnValues.size()); 6609 return std::make_pair(Res, Chain); 6610} 6611 6612void TargetLowering::LowerOperationWrapper(SDNode *N, 6613 SmallVectorImpl<SDValue> &Results, 6614 SelectionDAG &DAG) const { 6615 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6616 if (Res.getNode()) 6617 Results.push_back(Res); 6618} 6619 6620SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6621 llvm_unreachable("LowerOperation not implemented for this target!"); 6622} 6623 6624void 6625SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6626 SDValue Op = getNonRegisterValue(V); 6627 assert((Op.getOpcode() != ISD::CopyFromReg || 6628 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6629 "Copy from a reg to the same reg!"); 6630 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6631 6632 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6633 SDValue Chain = DAG.getEntryNode(); 6634 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6635 PendingExports.push_back(Chain); 6636} 6637 6638#include "llvm/CodeGen/SelectionDAGISel.h" 6639 6640/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6641/// entry block, return true. This includes arguments used by switches, since 6642/// the switch may expand into multiple basic blocks. 6643static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6644 // With FastISel active, we may be splitting blocks, so force creation 6645 // of virtual registers for all non-dead arguments. 6646 if (FastISel) 6647 return A->use_empty(); 6648 6649 const BasicBlock *Entry = A->getParent()->begin(); 6650 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6651 UI != E; ++UI) { 6652 const User *U = *UI; 6653 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6654 return false; // Use not in entry block. 6655 } 6656 return true; 6657} 6658 6659void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6660 // If this is the entry block, emit arguments. 6661 const Function &F = *LLVMBB->getParent(); 6662 SelectionDAG &DAG = SDB->DAG; 6663 DebugLoc dl = SDB->getCurDebugLoc(); 6664 const TargetData *TD = TLI.getTargetData(); 6665 SmallVector<ISD::InputArg, 16> Ins; 6666 6667 // Check whether the function can return without sret-demotion. 6668 SmallVector<ISD::OutputArg, 4> Outs; 6669 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6670 Outs, TLI); 6671 6672 if (!FuncInfo->CanLowerReturn) { 6673 // Put in an sret pointer parameter before all the other parameters. 6674 SmallVector<EVT, 1> ValueVTs; 6675 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6676 6677 // NOTE: Assuming that a pointer will never break down to more than one VT 6678 // or one register. 6679 ISD::ArgFlagsTy Flags; 6680 Flags.setSRet(); 6681 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6682 ISD::InputArg RetArg(Flags, RegisterVT, true); 6683 Ins.push_back(RetArg); 6684 } 6685 6686 // Set up the incoming argument description vector. 6687 unsigned Idx = 1; 6688 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6689 I != E; ++I, ++Idx) { 6690 SmallVector<EVT, 4> ValueVTs; 6691 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6692 bool isArgValueUsed = !I->use_empty(); 6693 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6694 Value != NumValues; ++Value) { 6695 EVT VT = ValueVTs[Value]; 6696 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6697 ISD::ArgFlagsTy Flags; 6698 unsigned OriginalAlignment = 6699 TD->getABITypeAlignment(ArgTy); 6700 6701 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6702 Flags.setZExt(); 6703 if (F.paramHasAttr(Idx, Attribute::SExt)) 6704 Flags.setSExt(); 6705 if (F.paramHasAttr(Idx, Attribute::InReg)) 6706 Flags.setInReg(); 6707 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6708 Flags.setSRet(); 6709 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6710 Flags.setByVal(); 6711 PointerType *Ty = cast<PointerType>(I->getType()); 6712 Type *ElementTy = Ty->getElementType(); 6713 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6714 // For ByVal, alignment should be passed from FE. BE will guess if 6715 // this info is not there but there are cases it cannot get right. 6716 unsigned FrameAlign; 6717 if (F.getParamAlignment(Idx)) 6718 FrameAlign = F.getParamAlignment(Idx); 6719 else 6720 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6721 Flags.setByValAlign(FrameAlign); 6722 } 6723 if (F.paramHasAttr(Idx, Attribute::Nest)) 6724 Flags.setNest(); 6725 Flags.setOrigAlign(OriginalAlignment); 6726 6727 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6728 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6729 for (unsigned i = 0; i != NumRegs; ++i) { 6730 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6731 if (NumRegs > 1 && i == 0) 6732 MyFlags.Flags.setSplit(); 6733 // if it isn't first piece, alignment must be 1 6734 else if (i > 0) 6735 MyFlags.Flags.setOrigAlign(1); 6736 Ins.push_back(MyFlags); 6737 } 6738 } 6739 } 6740 6741 // Call the target to set up the argument values. 6742 SmallVector<SDValue, 8> InVals; 6743 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6744 F.isVarArg(), Ins, 6745 dl, DAG, InVals); 6746 6747 // Verify that the target's LowerFormalArguments behaved as expected. 6748 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6749 "LowerFormalArguments didn't return a valid chain!"); 6750 assert(InVals.size() == Ins.size() && 6751 "LowerFormalArguments didn't emit the correct number of values!"); 6752 DEBUG({ 6753 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6754 assert(InVals[i].getNode() && 6755 "LowerFormalArguments emitted a null value!"); 6756 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6757 "LowerFormalArguments emitted a value with the wrong type!"); 6758 } 6759 }); 6760 6761 // Update the DAG with the new chain value resulting from argument lowering. 6762 DAG.setRoot(NewRoot); 6763 6764 // Set up the argument values. 6765 unsigned i = 0; 6766 Idx = 1; 6767 if (!FuncInfo->CanLowerReturn) { 6768 // Create a virtual register for the sret pointer, and put in a copy 6769 // from the sret argument into it. 6770 SmallVector<EVT, 1> ValueVTs; 6771 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6772 EVT VT = ValueVTs[0]; 6773 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6774 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6775 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6776 RegVT, VT, AssertOp); 6777 6778 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6779 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6780 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6781 FuncInfo->DemoteRegister = SRetReg; 6782 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6783 SRetReg, ArgValue); 6784 DAG.setRoot(NewRoot); 6785 6786 // i indexes lowered arguments. Bump it past the hidden sret argument. 6787 // Idx indexes LLVM arguments. Don't touch it. 6788 ++i; 6789 } 6790 6791 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6792 ++I, ++Idx) { 6793 SmallVector<SDValue, 4> ArgValues; 6794 SmallVector<EVT, 4> ValueVTs; 6795 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6796 unsigned NumValues = ValueVTs.size(); 6797 6798 // If this argument is unused then remember its value. It is used to generate 6799 // debugging information. 6800 if (I->use_empty() && NumValues) 6801 SDB->setUnusedArgValue(I, InVals[i]); 6802 6803 for (unsigned Val = 0; Val != NumValues; ++Val) { 6804 EVT VT = ValueVTs[Val]; 6805 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6806 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6807 6808 if (!I->use_empty()) { 6809 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6810 if (F.paramHasAttr(Idx, Attribute::SExt)) 6811 AssertOp = ISD::AssertSext; 6812 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6813 AssertOp = ISD::AssertZext; 6814 6815 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6816 NumParts, PartVT, VT, 6817 AssertOp)); 6818 } 6819 6820 i += NumParts; 6821 } 6822 6823 // We don't need to do anything else for unused arguments. 6824 if (ArgValues.empty()) 6825 continue; 6826 6827 // Note down frame index. 6828 if (FrameIndexSDNode *FI = 6829 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6830 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6831 6832 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6833 SDB->getCurDebugLoc()); 6834 6835 SDB->setValue(I, Res); 6836 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6837 if (LoadSDNode *LNode = 6838 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6839 if (FrameIndexSDNode *FI = 6840 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6841 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6842 } 6843 6844 // If this argument is live outside of the entry block, insert a copy from 6845 // wherever we got it to the vreg that other BB's will reference it as. 6846 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6847 // If we can, though, try to skip creating an unnecessary vreg. 6848 // FIXME: This isn't very clean... it would be nice to make this more 6849 // general. It's also subtly incompatible with the hacks FastISel 6850 // uses with vregs. 6851 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6852 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6853 FuncInfo->ValueMap[I] = Reg; 6854 continue; 6855 } 6856 } 6857 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6858 FuncInfo->InitializeRegForValue(I); 6859 SDB->CopyToExportRegsIfNeeded(I); 6860 } 6861 } 6862 6863 assert(i == InVals.size() && "Argument register count mismatch!"); 6864 6865 // Finally, if the target has anything special to do, allow it to do so. 6866 // FIXME: this should insert code into the DAG! 6867 EmitFunctionEntryCode(); 6868} 6869 6870/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6871/// ensure constants are generated when needed. Remember the virtual registers 6872/// that need to be added to the Machine PHI nodes as input. We cannot just 6873/// directly add them, because expansion might result in multiple MBB's for one 6874/// BB. As such, the start of the BB might correspond to a different MBB than 6875/// the end. 6876/// 6877void 6878SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6879 const TerminatorInst *TI = LLVMBB->getTerminator(); 6880 6881 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6882 6883 // Check successor nodes' PHI nodes that expect a constant to be available 6884 // from this block. 6885 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6886 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6887 if (!isa<PHINode>(SuccBB->begin())) continue; 6888 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6889 6890 // If this terminator has multiple identical successors (common for 6891 // switches), only handle each succ once. 6892 if (!SuccsHandled.insert(SuccMBB)) continue; 6893 6894 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6895 6896 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6897 // nodes and Machine PHI nodes, but the incoming operands have not been 6898 // emitted yet. 6899 for (BasicBlock::const_iterator I = SuccBB->begin(); 6900 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6901 // Ignore dead phi's. 6902 if (PN->use_empty()) continue; 6903 6904 // Skip empty types 6905 if (PN->getType()->isEmptyTy()) 6906 continue; 6907 6908 unsigned Reg; 6909 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6910 6911 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6912 unsigned &RegOut = ConstantsOut[C]; 6913 if (RegOut == 0) { 6914 RegOut = FuncInfo.CreateRegs(C->getType()); 6915 CopyValueToVirtualRegister(C, RegOut); 6916 } 6917 Reg = RegOut; 6918 } else { 6919 DenseMap<const Value *, unsigned>::iterator I = 6920 FuncInfo.ValueMap.find(PHIOp); 6921 if (I != FuncInfo.ValueMap.end()) 6922 Reg = I->second; 6923 else { 6924 assert(isa<AllocaInst>(PHIOp) && 6925 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6926 "Didn't codegen value into a register!??"); 6927 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6928 CopyValueToVirtualRegister(PHIOp, Reg); 6929 } 6930 } 6931 6932 // Remember that this register needs to added to the machine PHI node as 6933 // the input for this MBB. 6934 SmallVector<EVT, 4> ValueVTs; 6935 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6936 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6937 EVT VT = ValueVTs[vti]; 6938 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6939 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6940 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6941 Reg += NumRegisters; 6942 } 6943 } 6944 } 6945 ConstantsOut.clear(); 6946} 6947