SelectionDAGBuilder.cpp revision 266a99d161069071f32c7c09dded481fd573a82e
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/ConstantFolding.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/Module.h" 32#include "llvm/CodeGen/Analysis.h" 33#include "llvm/CodeGen/FastISel.h" 34#include "llvm/CodeGen/FunctionLoweringInfo.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 74 const SDValue *Parts, unsigned NumParts, 75 EVT PartVT, EVT ValueVT); 76 77/// getCopyFromParts - Create a value that contains the specified legal parts 78/// combined into the value they represent. If the parts combine to a type 79/// larger then ValueVT then AssertOp can be used to specify whether the extra 80/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 81/// (ISD::AssertSext). 82static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 83 const SDValue *Parts, 84 unsigned NumParts, EVT PartVT, EVT ValueVT, 85 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 86 if (ValueVT.isVector()) 87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 88 89 assert(NumParts > 0 && "No parts to assemble!"); 90 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 91 SDValue Val = Parts[0]; 92 93 if (NumParts > 1) { 94 // Assemble the value from multiple parts. 95 if (ValueVT.isInteger()) { 96 unsigned PartBits = PartVT.getSizeInBits(); 97 unsigned ValueBits = ValueVT.getSizeInBits(); 98 99 // Assemble the power of 2 part. 100 unsigned RoundParts = NumParts & (NumParts - 1) ? 101 1 << Log2_32(NumParts) : NumParts; 102 unsigned RoundBits = PartBits * RoundParts; 103 EVT RoundVT = RoundBits == ValueBits ? 104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 105 SDValue Lo, Hi; 106 107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 108 109 if (RoundParts > 2) { 110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 111 PartVT, HalfVT); 112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 113 RoundParts / 2, PartVT, HalfVT); 114 } else { 115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); 116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); 117 } 118 119 if (TLI.isBigEndian()) 120 std::swap(Lo, Hi); 121 122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 123 124 if (RoundParts < NumParts) { 125 // Assemble the trailing non-power-of-2 part. 126 unsigned OddParts = NumParts - RoundParts; 127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 128 Hi = getCopyFromParts(DAG, DL, 129 Parts + RoundParts, OddParts, PartVT, OddVT); 130 131 // Combine the round and odd parts. 132 Lo = Val; 133 if (TLI.isBigEndian()) 134 std::swap(Lo, Hi); 135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 138 DAG.getConstant(Lo.getValueType().getSizeInBits(), 139 TLI.getPointerTy())); 140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 142 } 143 } else if (PartVT.isFloatingPoint()) { 144 // FP split into multiple FP parts (for ppcf128) 145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 146 "Unexpected split"); 147 SDValue Lo, Hi; 148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); 149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); 150 if (TLI.isBigEndian()) 151 std::swap(Lo, Hi); 152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 153 } else { 154 // FP split into integer parts (soft fp) 155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 156 !PartVT.isVector() && "Unexpected split"); 157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 159 } 160 } 161 162 // There is now one part, held in Val. Correct it to match ValueVT. 163 PartVT = Val.getValueType(); 164 165 if (PartVT == ValueVT) 166 return Val; 167 168 if (PartVT.isInteger() && ValueVT.isInteger()) { 169 if (ValueVT.bitsLT(PartVT)) { 170 // For a truncate, see if we have any information to 171 // indicate whether the truncated bits will always be 172 // zero or sign-extension. 173 if (AssertOp != ISD::DELETED_NODE) 174 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 175 DAG.getValueType(ValueVT)); 176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 177 } 178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 179 } 180 181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 182 // FP_ROUND's are always exact here. 183 if (ValueVT.bitsLT(Val.getValueType())) 184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 185 DAG.getIntPtrConstant(1)); 186 187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 188 } 189 190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 192 193 llvm_unreachable("Unknown mismatch!"); 194 return SDValue(); 195} 196 197/// getCopyFromParts - Create a value that contains the specified legal parts 198/// combined into the value they represent. If the parts combine to a type 199/// larger then ValueVT then AssertOp can be used to specify whether the extra 200/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 201/// (ISD::AssertSext). 202static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 203 const SDValue *Parts, unsigned NumParts, 204 EVT PartVT, EVT ValueVT) { 205 assert(ValueVT.isVector() && "Not a vector value"); 206 assert(NumParts > 0 && "No parts to assemble!"); 207 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 208 SDValue Val = Parts[0]; 209 210 // Handle a multi-element vector. 211 if (NumParts > 1) { 212 EVT IntermediateVT, RegisterVT; 213 unsigned NumIntermediates; 214 unsigned NumRegs = 215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 216 NumIntermediates, RegisterVT); 217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 218 NumParts = NumRegs; // Silence a compiler warning. 219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 220 assert(RegisterVT == Parts[0].getValueType() && 221 "Part type doesn't match part!"); 222 223 // Assemble the parts into intermediate operands. 224 SmallVector<SDValue, 8> Ops(NumIntermediates); 225 if (NumIntermediates == NumParts) { 226 // If the register was not expanded, truncate or copy the value, 227 // as appropriate. 228 for (unsigned i = 0; i != NumParts; ++i) 229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 230 PartVT, IntermediateVT); 231 } else if (NumParts > 0) { 232 // If the intermediate type was expanded, build the intermediate 233 // operands from the parts. 234 assert(NumParts % NumIntermediates == 0 && 235 "Must expand into a divisible number of parts!"); 236 unsigned Factor = NumParts / NumIntermediates; 237 for (unsigned i = 0; i != NumIntermediates; ++i) 238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 239 PartVT, IntermediateVT); 240 } 241 242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 243 // intermediate operands. 244 Val = DAG.getNode(IntermediateVT.isVector() ? 245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 246 ValueVT, &Ops[0], NumIntermediates); 247 } 248 249 // There is now one part, held in Val. Correct it to match ValueVT. 250 PartVT = Val.getValueType(); 251 252 if (PartVT == ValueVT) 253 return Val; 254 255 if (PartVT.isVector()) { 256 // If the element type of the source/dest vectors are the same, but the 257 // parts vector has more elements than the value vector, then we have a 258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 259 // elements we want. 260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 262 "Cannot narrow, it would be a lossy transformation"); 263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 264 DAG.getIntPtrConstant(0)); 265 } 266 267 // Vector/Vector bitcast. 268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 269 } 270 271 assert(ValueVT.getVectorElementType() == PartVT && 272 ValueVT.getVectorNumElements() == 1 && 273 "Only trivial scalar-to-vector conversions should get here!"); 274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 275} 276 277 278 279 280static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 281 SDValue Val, SDValue *Parts, unsigned NumParts, 282 EVT PartVT); 283 284/// getCopyToParts - Create a series of nodes that contain the specified value 285/// split into legal parts. If the parts contain more bits than Val, then, for 286/// integers, ExtendKind can be used to specify how to generate the extra bits. 287static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 288 SDValue Val, SDValue *Parts, unsigned NumParts, 289 EVT PartVT, 290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 291 EVT ValueVT = Val.getValueType(); 292 293 // Handle the vector case separately. 294 if (ValueVT.isVector()) 295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 296 297 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 298 unsigned PartBits = PartVT.getSizeInBits(); 299 unsigned OrigNumParts = NumParts; 300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 301 302 if (NumParts == 0) 303 return; 304 305 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 306 if (PartVT == ValueVT) { 307 assert(NumParts == 1 && "No-op copy with multiple parts!"); 308 Parts[0] = Val; 309 return; 310 } 311 312 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 313 // If the parts cover more bits than the value has, promote the value. 314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 315 assert(NumParts == 1 && "Do not know what to promote to!"); 316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 317 } else { 318 assert(PartVT.isInteger() && ValueVT.isInteger() && 319 "Unknown mismatch!"); 320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 322 } 323 } else if (PartBits == ValueVT.getSizeInBits()) { 324 // Different types of the same size. 325 assert(NumParts == 1 && PartVT != ValueVT); 326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 328 // If the parts cover less bits than value has, truncate the value. 329 assert(PartVT.isInteger() && ValueVT.isInteger() && 330 "Unknown mismatch!"); 331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 333 } 334 335 // The value may have changed - recompute ValueVT. 336 ValueVT = Val.getValueType(); 337 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 338 "Failed to tile the value with PartVT!"); 339 340 if (NumParts == 1) { 341 assert(PartVT == ValueVT && "Type conversion failed!"); 342 Parts[0] = Val; 343 return; 344 } 345 346 // Expand the value into multiple parts. 347 if (NumParts & (NumParts - 1)) { 348 // The number of parts is not a power of 2. Split off and copy the tail. 349 assert(PartVT.isInteger() && ValueVT.isInteger() && 350 "Do not know what to expand to!"); 351 unsigned RoundParts = 1 << Log2_32(NumParts); 352 unsigned RoundBits = RoundParts * PartBits; 353 unsigned OddParts = NumParts - RoundParts; 354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 355 DAG.getIntPtrConstant(RoundBits)); 356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 357 358 if (TLI.isBigEndian()) 359 // The odd parts were reversed by getCopyToParts - unreverse them. 360 std::reverse(Parts + RoundParts, Parts + NumParts); 361 362 NumParts = RoundParts; 363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 365 } 366 367 // The number of parts is a power of 2. Repeatedly bisect the value using 368 // EXTRACT_ELEMENT. 369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, 370 EVT::getIntegerVT(*DAG.getContext(), 371 ValueVT.getSizeInBits()), 372 Val); 373 374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 375 for (unsigned i = 0; i < NumParts; i += StepSize) { 376 unsigned ThisBits = StepSize * PartBits / 2; 377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 378 SDValue &Part0 = Parts[i]; 379 SDValue &Part1 = Parts[i+StepSize/2]; 380 381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 382 ThisVT, Part0, DAG.getIntPtrConstant(1)); 383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 384 ThisVT, Part0, DAG.getIntPtrConstant(0)); 385 386 if (ThisBits == PartBits && ThisVT != PartVT) { 387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); 388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); 389 } 390 } 391 } 392 393 if (TLI.isBigEndian()) 394 std::reverse(Parts, Parts + OrigNumParts); 395} 396 397 398/// getCopyToPartsVector - Create a series of nodes that contain the specified 399/// value split into legal parts. 400static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 401 SDValue Val, SDValue *Parts, unsigned NumParts, 402 EVT PartVT) { 403 EVT ValueVT = Val.getValueType(); 404 assert(ValueVT.isVector() && "Not a vector"); 405 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 406 407 if (NumParts == 1) { 408 if (PartVT == ValueVT) { 409 // Nothing to do. 410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 411 // Bitconvert vector->vector case. 412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 413 } else if (PartVT.isVector() && 414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 416 EVT ElementVT = PartVT.getVectorElementType(); 417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 418 // undef elements. 419 SmallVector<SDValue, 16> Ops; 420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 422 ElementVT, Val, DAG.getIntPtrConstant(i))); 423 424 for (unsigned i = ValueVT.getVectorNumElements(), 425 e = PartVT.getVectorNumElements(); i != e; ++i) 426 Ops.push_back(DAG.getUNDEF(ElementVT)); 427 428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 429 430 // FIXME: Use CONCAT for 2x -> 4x. 431 432 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 434 } else { 435 // Vector -> scalar conversion. 436 assert(ValueVT.getVectorElementType() == PartVT && 437 ValueVT.getVectorNumElements() == 1 && 438 "Only trivial vector-to-scalar conversions should get here!"); 439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 PartVT, Val, DAG.getIntPtrConstant(0)); 441 } 442 443 Parts[0] = Val; 444 return; 445 } 446 447 // Handle a multi-element vector. 448 EVT IntermediateVT, RegisterVT; 449 unsigned NumIntermediates; 450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 451 IntermediateVT, 452 NumIntermediates, RegisterVT); 453 unsigned NumElements = ValueVT.getVectorNumElements(); 454 455 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 456 NumParts = NumRegs; // Silence a compiler warning. 457 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 458 459 // Split the vector into intermediate operands. 460 SmallVector<SDValue, 8> Ops(NumIntermediates); 461 for (unsigned i = 0; i != NumIntermediates; ++i) { 462 if (IntermediateVT.isVector()) 463 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 464 IntermediateVT, Val, 465 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 466 else 467 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 468 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 469 } 470 471 // Split the intermediate operands into legal parts. 472 if (NumParts == NumIntermediates) { 473 // If the register was not expanded, promote or copy the value, 474 // as appropriate. 475 for (unsigned i = 0; i != NumParts; ++i) 476 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 477 } else if (NumParts > 0) { 478 // If the intermediate type was expanded, split each the value into 479 // legal parts. 480 assert(NumParts % NumIntermediates == 0 && 481 "Must expand into a divisible number of parts!"); 482 unsigned Factor = NumParts / NumIntermediates; 483 for (unsigned i = 0; i != NumIntermediates; ++i) 484 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 485 } 486} 487 488 489 490 491namespace { 492 /// RegsForValue - This struct represents the registers (physical or virtual) 493 /// that a particular set of values is assigned, and the type information 494 /// about the value. The most common situation is to represent one value at a 495 /// time, but struct or array values are handled element-wise as multiple 496 /// values. The splitting of aggregates is performed recursively, so that we 497 /// never have aggregate-typed registers. The values at this point do not 498 /// necessarily have legal types, so each value may require one or more 499 /// registers of some legal type. 500 /// 501 struct RegsForValue { 502 /// ValueVTs - The value types of the values, which may not be legal, and 503 /// may need be promoted or synthesized from one or more registers. 504 /// 505 SmallVector<EVT, 4> ValueVTs; 506 507 /// RegVTs - The value types of the registers. This is the same size as 508 /// ValueVTs and it records, for each value, what the type of the assigned 509 /// register or registers are. (Individual values are never synthesized 510 /// from more than one type of register.) 511 /// 512 /// With virtual registers, the contents of RegVTs is redundant with TLI's 513 /// getRegisterType member function, however when with physical registers 514 /// it is necessary to have a separate record of the types. 515 /// 516 SmallVector<EVT, 4> RegVTs; 517 518 /// Regs - This list holds the registers assigned to the values. 519 /// Each legal or promoted value requires one register, and each 520 /// expanded value requires multiple registers. 521 /// 522 SmallVector<unsigned, 4> Regs; 523 524 RegsForValue() {} 525 526 RegsForValue(const SmallVector<unsigned, 4> ®s, 527 EVT regvt, EVT valuevt) 528 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 529 530 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 531 unsigned Reg, const Type *Ty) { 532 ComputeValueVTs(tli, Ty, ValueVTs); 533 534 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 535 EVT ValueVT = ValueVTs[Value]; 536 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 537 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 538 for (unsigned i = 0; i != NumRegs; ++i) 539 Regs.push_back(Reg + i); 540 RegVTs.push_back(RegisterVT); 541 Reg += NumRegs; 542 } 543 } 544 545 /// areValueTypesLegal - Return true if types of all the values are legal. 546 bool areValueTypesLegal(const TargetLowering &TLI) { 547 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 548 EVT RegisterVT = RegVTs[Value]; 549 if (!TLI.isTypeLegal(RegisterVT)) 550 return false; 551 } 552 return true; 553 } 554 555 /// append - Add the specified values to this one. 556 void append(const RegsForValue &RHS) { 557 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 558 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 559 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 560 } 561 562 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 563 /// this value and returns the result as a ValueVTs value. This uses 564 /// Chain/Flag as the input and updates them for the output Chain/Flag. 565 /// If the Flag pointer is NULL, no flag is used. 566 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 567 DebugLoc dl, 568 SDValue &Chain, SDValue *Flag) const; 569 570 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 571 /// specified value into the registers specified by this object. This uses 572 /// Chain/Flag as the input and updates them for the output Chain/Flag. 573 /// If the Flag pointer is NULL, no flag is used. 574 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 575 SDValue &Chain, SDValue *Flag) const; 576 577 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 578 /// operand list. This adds the code marker, matching input operand index 579 /// (if applicable), and includes the number of values added into it. 580 void AddInlineAsmOperands(unsigned Kind, 581 bool HasMatching, unsigned MatchingIdx, 582 SelectionDAG &DAG, 583 std::vector<SDValue> &Ops) const; 584 }; 585} 586 587/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 588/// this value and returns the result as a ValueVT value. This uses 589/// Chain/Flag as the input and updates them for the output Chain/Flag. 590/// If the Flag pointer is NULL, no flag is used. 591SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 592 FunctionLoweringInfo &FuncInfo, 593 DebugLoc dl, 594 SDValue &Chain, SDValue *Flag) const { 595 // A Value with type {} or [0 x %t] needs no registers. 596 if (ValueVTs.empty()) 597 return SDValue(); 598 599 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 600 601 // Assemble the legal parts into the final values. 602 SmallVector<SDValue, 4> Values(ValueVTs.size()); 603 SmallVector<SDValue, 8> Parts; 604 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 605 // Copy the legal parts from the registers. 606 EVT ValueVT = ValueVTs[Value]; 607 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 608 EVT RegisterVT = RegVTs[Value]; 609 610 Parts.resize(NumRegs); 611 for (unsigned i = 0; i != NumRegs; ++i) { 612 SDValue P; 613 if (Flag == 0) { 614 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 615 } else { 616 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 617 *Flag = P.getValue(2); 618 } 619 620 Chain = P.getValue(1); 621 622 // If the source register was virtual and if we know something about it, 623 // add an assert node. 624 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 625 RegisterVT.isInteger() && !RegisterVT.isVector()) { 626 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 627 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 628 const FunctionLoweringInfo::LiveOutInfo &LOI = 629 FuncInfo.LiveOutRegInfo[SlotNo]; 630 631 unsigned RegSize = RegisterVT.getSizeInBits(); 632 unsigned NumSignBits = LOI.NumSignBits; 633 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 634 635 // FIXME: We capture more information than the dag can represent. For 636 // now, just use the tightest assertzext/assertsext possible. 637 bool isSExt = true; 638 EVT FromVT(MVT::Other); 639 if (NumSignBits == RegSize) 640 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 641 else if (NumZeroBits >= RegSize-1) 642 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 643 else if (NumSignBits > RegSize-8) 644 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 645 else if (NumZeroBits >= RegSize-8) 646 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 647 else if (NumSignBits > RegSize-16) 648 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 649 else if (NumZeroBits >= RegSize-16) 650 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 651 else if (NumSignBits > RegSize-32) 652 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 653 else if (NumZeroBits >= RegSize-32) 654 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 655 656 if (FromVT != MVT::Other) 657 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 658 RegisterVT, P, DAG.getValueType(FromVT)); 659 } 660 } 661 662 Parts[i] = P; 663 } 664 665 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 666 NumRegs, RegisterVT, ValueVT); 667 Part += NumRegs; 668 Parts.clear(); 669 } 670 671 return DAG.getNode(ISD::MERGE_VALUES, dl, 672 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 673 &Values[0], ValueVTs.size()); 674} 675 676/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 677/// specified value into the registers specified by this object. This uses 678/// Chain/Flag as the input and updates them for the output Chain/Flag. 679/// If the Flag pointer is NULL, no flag is used. 680void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 681 SDValue &Chain, SDValue *Flag) const { 682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 683 684 // Get the list of the values's legal parts. 685 unsigned NumRegs = Regs.size(); 686 SmallVector<SDValue, 8> Parts(NumRegs); 687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 EVT RegisterVT = RegVTs[Value]; 691 692 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 693 &Parts[Part], NumParts, RegisterVT); 694 Part += NumParts; 695 } 696 697 // Copy the parts into the registers. 698 SmallVector<SDValue, 8> Chains(NumRegs); 699 for (unsigned i = 0; i != NumRegs; ++i) { 700 SDValue Part; 701 if (Flag == 0) { 702 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 703 } else { 704 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 705 *Flag = Part.getValue(1); 706 } 707 708 Chains[i] = Part.getValue(0); 709 } 710 711 if (NumRegs == 1 || Flag) 712 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 713 // flagged to it. That is the CopyToReg nodes and the user are considered 714 // a single scheduling unit. If we create a TokenFactor and return it as 715 // chain, then the TokenFactor is both a predecessor (operand) of the 716 // user as well as a successor (the TF operands are flagged to the user). 717 // c1, f1 = CopyToReg 718 // c2, f2 = CopyToReg 719 // c3 = TokenFactor c1, c2 720 // ... 721 // = op c3, ..., f2 722 Chain = Chains[NumRegs-1]; 723 else 724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 725} 726 727/// AddInlineAsmOperands - Add this value to the specified inlineasm node 728/// operand list. This adds the code marker and includes the number of 729/// values added into it. 730void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 731 unsigned MatchingIdx, 732 SelectionDAG &DAG, 733 std::vector<SDValue> &Ops) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 737 if (HasMatching) 738 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 739 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 740 Ops.push_back(Res); 741 742 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 743 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 744 EVT RegisterVT = RegVTs[Value]; 745 for (unsigned i = 0; i != NumRegs; ++i) { 746 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 747 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 748 } 749 } 750} 751 752void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 753 AA = &aa; 754 GFI = gfi; 755 TD = DAG.getTarget().getTargetData(); 756} 757 758/// clear - Clear out the current SelectionDAG and the associated 759/// state and prepare this SelectionDAGBuilder object to be used 760/// for a new block. This doesn't clear out information about 761/// additional blocks that are needed to complete switch lowering 762/// or PHI node updating; that information is cleared out as it is 763/// consumed. 764void SelectionDAGBuilder::clear() { 765 NodeMap.clear(); 766 UnusedArgNodeMap.clear(); 767 PendingLoads.clear(); 768 PendingExports.clear(); 769 DanglingDebugInfoMap.clear(); 770 CurDebugLoc = DebugLoc(); 771 HasTailCall = false; 772} 773 774/// getRoot - Return the current virtual root of the Selection DAG, 775/// flushing any PendingLoad items. This must be done before emitting 776/// a store or any other node that may need to be ordered after any 777/// prior load instructions. 778/// 779SDValue SelectionDAGBuilder::getRoot() { 780 if (PendingLoads.empty()) 781 return DAG.getRoot(); 782 783 if (PendingLoads.size() == 1) { 784 SDValue Root = PendingLoads[0]; 785 DAG.setRoot(Root); 786 PendingLoads.clear(); 787 return Root; 788 } 789 790 // Otherwise, we have to make a token factor node. 791 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 792 &PendingLoads[0], PendingLoads.size()); 793 PendingLoads.clear(); 794 DAG.setRoot(Root); 795 return Root; 796} 797 798/// getControlRoot - Similar to getRoot, but instead of flushing all the 799/// PendingLoad items, flush all the PendingExports items. It is necessary 800/// to do this before emitting a terminator instruction. 801/// 802SDValue SelectionDAGBuilder::getControlRoot() { 803 SDValue Root = DAG.getRoot(); 804 805 if (PendingExports.empty()) 806 return Root; 807 808 // Turn all of the CopyToReg chains into one factored node. 809 if (Root.getOpcode() != ISD::EntryToken) { 810 unsigned i = 0, e = PendingExports.size(); 811 for (; i != e; ++i) { 812 assert(PendingExports[i].getNode()->getNumOperands() > 1); 813 if (PendingExports[i].getNode()->getOperand(0) == Root) 814 break; // Don't add the root if we already indirectly depend on it. 815 } 816 817 if (i == e) 818 PendingExports.push_back(Root); 819 } 820 821 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 822 &PendingExports[0], 823 PendingExports.size()); 824 PendingExports.clear(); 825 DAG.setRoot(Root); 826 return Root; 827} 828 829void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 830 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 831 DAG.AssignOrdering(Node, SDNodeOrder); 832 833 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 834 AssignOrderingToNode(Node->getOperand(I).getNode()); 835} 836 837void SelectionDAGBuilder::visit(const Instruction &I) { 838 // Set up outgoing PHI node register values before emitting the terminator. 839 if (isa<TerminatorInst>(&I)) 840 HandlePHINodesInSuccessorBlocks(I.getParent()); 841 842 CurDebugLoc = I.getDebugLoc(); 843 844 visit(I.getOpcode(), I); 845 846 if (!isa<TerminatorInst>(&I) && !HasTailCall) 847 CopyToExportRegsIfNeeded(&I); 848 849 CurDebugLoc = DebugLoc(); 850} 851 852void SelectionDAGBuilder::visitPHI(const PHINode &) { 853 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 854} 855 856void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 857 // Note: this doesn't use InstVisitor, because it has to work with 858 // ConstantExpr's in addition to instructions. 859 switch (Opcode) { 860 default: llvm_unreachable("Unknown instruction type encountered!"); 861 // Build the switch statement using the Instruction.def file. 862#define HANDLE_INST(NUM, OPCODE, CLASS) \ 863 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 864#include "llvm/Instruction.def" 865 } 866 867 // Assign the ordering to the freshly created DAG nodes. 868 if (NodeMap.count(&I)) { 869 ++SDNodeOrder; 870 AssignOrderingToNode(getValue(&I).getNode()); 871 } 872} 873 874// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 875// generate the debug data structures now that we've seen its definition. 876void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 877 SDValue Val) { 878 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 879 if (DDI.getDI()) { 880 const DbgValueInst *DI = DDI.getDI(); 881 DebugLoc dl = DDI.getdl(); 882 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 883 MDNode *Variable = DI->getVariable(); 884 uint64_t Offset = DI->getOffset(); 885 SDDbgValue *SDV; 886 if (Val.getNode()) { 887 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 888 SDV = DAG.getDbgValue(Variable, Val.getNode(), 889 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 890 DAG.AddDbgValue(SDV, Val.getNode(), false); 891 } 892 } else { 893 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 894 Offset, dl, SDNodeOrder); 895 DAG.AddDbgValue(SDV, 0, false); 896 } 897 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 898 } 899} 900 901// getValue - Return an SDValue for the given Value. 902SDValue SelectionDAGBuilder::getValue(const Value *V) { 903 // If we already have an SDValue for this value, use it. It's important 904 // to do this first, so that we don't create a CopyFromReg if we already 905 // have a regular SDValue. 906 SDValue &N = NodeMap[V]; 907 if (N.getNode()) return N; 908 909 // If there's a virtual register allocated and initialized for this 910 // value, use it. 911 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 912 if (It != FuncInfo.ValueMap.end()) { 913 unsigned InReg = It->second; 914 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 915 SDValue Chain = DAG.getEntryNode(); 916 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 917 } 918 919 // Otherwise create a new SDValue and remember it. 920 SDValue Val = getValueImpl(V); 921 NodeMap[V] = Val; 922 resolveDanglingDebugInfo(V, Val); 923 return Val; 924} 925 926/// getNonRegisterValue - Return an SDValue for the given Value, but 927/// don't look in FuncInfo.ValueMap for a virtual register. 928SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 929 // If we already have an SDValue for this value, use it. 930 SDValue &N = NodeMap[V]; 931 if (N.getNode()) return N; 932 933 // Otherwise create a new SDValue and remember it. 934 SDValue Val = getValueImpl(V); 935 NodeMap[V] = Val; 936 resolveDanglingDebugInfo(V, Val); 937 return Val; 938} 939 940/// getValueImpl - Helper function for getValue and getNonRegisterValue. 941/// Create an SDValue for the given value. 942SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 943 if (const Constant *C = dyn_cast<Constant>(V)) { 944 EVT VT = TLI.getValueType(V->getType(), true); 945 946 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 947 return DAG.getConstant(*CI, VT); 948 949 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 950 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 951 952 if (isa<ConstantPointerNull>(C)) 953 return DAG.getConstant(0, TLI.getPointerTy()); 954 955 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 956 return DAG.getConstantFP(*CFP, VT); 957 958 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 959 return DAG.getUNDEF(VT); 960 961 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 962 visit(CE->getOpcode(), *CE); 963 SDValue N1 = NodeMap[V]; 964 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 965 return N1; 966 } 967 968 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 969 SmallVector<SDValue, 4> Constants; 970 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 971 OI != OE; ++OI) { 972 SDNode *Val = getValue(*OI).getNode(); 973 // If the operand is an empty aggregate, there are no values. 974 if (!Val) continue; 975 // Add each leaf value from the operand to the Constants list 976 // to form a flattened list of all the values. 977 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 978 Constants.push_back(SDValue(Val, i)); 979 } 980 981 return DAG.getMergeValues(&Constants[0], Constants.size(), 982 getCurDebugLoc()); 983 } 984 985 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 986 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 987 "Unknown struct or array constant!"); 988 989 SmallVector<EVT, 4> ValueVTs; 990 ComputeValueVTs(TLI, C->getType(), ValueVTs); 991 unsigned NumElts = ValueVTs.size(); 992 if (NumElts == 0) 993 return SDValue(); // empty struct 994 SmallVector<SDValue, 4> Constants(NumElts); 995 for (unsigned i = 0; i != NumElts; ++i) { 996 EVT EltVT = ValueVTs[i]; 997 if (isa<UndefValue>(C)) 998 Constants[i] = DAG.getUNDEF(EltVT); 999 else if (EltVT.isFloatingPoint()) 1000 Constants[i] = DAG.getConstantFP(0, EltVT); 1001 else 1002 Constants[i] = DAG.getConstant(0, EltVT); 1003 } 1004 1005 return DAG.getMergeValues(&Constants[0], NumElts, 1006 getCurDebugLoc()); 1007 } 1008 1009 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1010 return DAG.getBlockAddress(BA, VT); 1011 1012 const VectorType *VecTy = cast<VectorType>(V->getType()); 1013 unsigned NumElements = VecTy->getNumElements(); 1014 1015 // Now that we know the number and type of the elements, get that number of 1016 // elements into the Ops array based on what kind of constant it is. 1017 SmallVector<SDValue, 16> Ops; 1018 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1019 for (unsigned i = 0; i != NumElements; ++i) 1020 Ops.push_back(getValue(CP->getOperand(i))); 1021 } else { 1022 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1023 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1024 1025 SDValue Op; 1026 if (EltVT.isFloatingPoint()) 1027 Op = DAG.getConstantFP(0, EltVT); 1028 else 1029 Op = DAG.getConstant(0, EltVT); 1030 Ops.assign(NumElements, Op); 1031 } 1032 1033 // Create a BUILD_VECTOR node. 1034 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1035 VT, &Ops[0], Ops.size()); 1036 } 1037 1038 // If this is a static alloca, generate it as the frameindex instead of 1039 // computation. 1040 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1041 DenseMap<const AllocaInst*, int>::iterator SI = 1042 FuncInfo.StaticAllocaMap.find(AI); 1043 if (SI != FuncInfo.StaticAllocaMap.end()) 1044 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1045 } 1046 1047 // If this is an instruction which fast-isel has deferred, select it now. 1048 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1049 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1050 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1051 SDValue Chain = DAG.getEntryNode(); 1052 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1053 } 1054 1055 llvm_unreachable("Can't get register for value!"); 1056 return SDValue(); 1057} 1058 1059void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1060 SDValue Chain = getControlRoot(); 1061 SmallVector<ISD::OutputArg, 8> Outs; 1062 SmallVector<SDValue, 8> OutVals; 1063 1064 if (!FuncInfo.CanLowerReturn) { 1065 unsigned DemoteReg = FuncInfo.DemoteRegister; 1066 const Function *F = I.getParent()->getParent(); 1067 1068 // Emit a store of the return value through the virtual register. 1069 // Leave Outs empty so that LowerReturn won't try to load return 1070 // registers the usual way. 1071 SmallVector<EVT, 1> PtrValueVTs; 1072 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1073 PtrValueVTs); 1074 1075 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1076 SDValue RetOp = getValue(I.getOperand(0)); 1077 1078 SmallVector<EVT, 4> ValueVTs; 1079 SmallVector<uint64_t, 4> Offsets; 1080 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1081 unsigned NumValues = ValueVTs.size(); 1082 1083 SmallVector<SDValue, 4> Chains(NumValues); 1084 for (unsigned i = 0; i != NumValues; ++i) { 1085 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1086 RetPtr.getValueType(), RetPtr, 1087 DAG.getIntPtrConstant(Offsets[i])); 1088 Chains[i] = 1089 DAG.getStore(Chain, getCurDebugLoc(), 1090 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1091 // FIXME: better loc info would be nice. 1092 Add, MachinePointerInfo(), false, false, 0); 1093 } 1094 1095 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1096 MVT::Other, &Chains[0], NumValues); 1097 } else if (I.getNumOperands() != 0) { 1098 SmallVector<EVT, 4> ValueVTs; 1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1100 unsigned NumValues = ValueVTs.size(); 1101 if (NumValues) { 1102 SDValue RetOp = getValue(I.getOperand(0)); 1103 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1104 EVT VT = ValueVTs[j]; 1105 1106 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1107 1108 const Function *F = I.getParent()->getParent(); 1109 if (F->paramHasAttr(0, Attribute::SExt)) 1110 ExtendKind = ISD::SIGN_EXTEND; 1111 else if (F->paramHasAttr(0, Attribute::ZExt)) 1112 ExtendKind = ISD::ZERO_EXTEND; 1113 1114 // FIXME: C calling convention requires the return type to be promoted 1115 // to at least 32-bit. But this is not necessary for non-C calling 1116 // conventions. The frontend should mark functions whose return values 1117 // require promoting with signext or zeroext attributes. 1118 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1119 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1120 if (VT.bitsLT(MinVT)) 1121 VT = MinVT; 1122 } 1123 1124 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1125 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1126 SmallVector<SDValue, 4> Parts(NumParts); 1127 getCopyToParts(DAG, getCurDebugLoc(), 1128 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1129 &Parts[0], NumParts, PartVT, ExtendKind); 1130 1131 // 'inreg' on function refers to return value 1132 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1133 if (F->paramHasAttr(0, Attribute::InReg)) 1134 Flags.setInReg(); 1135 1136 // Propagate extension type if any 1137 if (F->paramHasAttr(0, Attribute::SExt)) 1138 Flags.setSExt(); 1139 else if (F->paramHasAttr(0, Attribute::ZExt)) 1140 Flags.setZExt(); 1141 1142 for (unsigned i = 0; i < NumParts; ++i) { 1143 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1144 /*isfixed=*/true)); 1145 OutVals.push_back(Parts[i]); 1146 } 1147 } 1148 } 1149 } 1150 1151 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1152 CallingConv::ID CallConv = 1153 DAG.getMachineFunction().getFunction()->getCallingConv(); 1154 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1155 Outs, OutVals, getCurDebugLoc(), DAG); 1156 1157 // Verify that the target's LowerReturn behaved as expected. 1158 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1159 "LowerReturn didn't return a valid chain!"); 1160 1161 // Update the DAG with the new chain value resulting from return lowering. 1162 DAG.setRoot(Chain); 1163} 1164 1165/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1166/// created for it, emit nodes to copy the value into the virtual 1167/// registers. 1168void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1169 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1170 if (VMI != FuncInfo.ValueMap.end()) { 1171 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1172 CopyValueToVirtualRegister(V, VMI->second); 1173 } 1174} 1175 1176/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1177/// the current basic block, add it to ValueMap now so that we'll get a 1178/// CopyTo/FromReg. 1179void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1180 // No need to export constants. 1181 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1182 1183 // Already exported? 1184 if (FuncInfo.isExportedInst(V)) return; 1185 1186 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1187 CopyValueToVirtualRegister(V, Reg); 1188} 1189 1190bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1191 const BasicBlock *FromBB) { 1192 // The operands of the setcc have to be in this block. We don't know 1193 // how to export them from some other block. 1194 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1195 // Can export from current BB. 1196 if (VI->getParent() == FromBB) 1197 return true; 1198 1199 // Is already exported, noop. 1200 return FuncInfo.isExportedInst(V); 1201 } 1202 1203 // If this is an argument, we can export it if the BB is the entry block or 1204 // if it is already exported. 1205 if (isa<Argument>(V)) { 1206 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1207 return true; 1208 1209 // Otherwise, can only export this if it is already exported. 1210 return FuncInfo.isExportedInst(V); 1211 } 1212 1213 // Otherwise, constants can always be exported. 1214 return true; 1215} 1216 1217static bool InBlock(const Value *V, const BasicBlock *BB) { 1218 if (const Instruction *I = dyn_cast<Instruction>(V)) 1219 return I->getParent() == BB; 1220 return true; 1221} 1222 1223/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1224/// This function emits a branch and is used at the leaves of an OR or an 1225/// AND operator tree. 1226/// 1227void 1228SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1229 MachineBasicBlock *TBB, 1230 MachineBasicBlock *FBB, 1231 MachineBasicBlock *CurBB, 1232 MachineBasicBlock *SwitchBB) { 1233 const BasicBlock *BB = CurBB->getBasicBlock(); 1234 1235 // If the leaf of the tree is a comparison, merge the condition into 1236 // the caseblock. 1237 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1238 // The operands of the cmp have to be in this block. We don't know 1239 // how to export them from some other block. If this is the first block 1240 // of the sequence, no exporting is needed. 1241 if (CurBB == SwitchBB || 1242 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1243 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1244 ISD::CondCode Condition; 1245 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1246 Condition = getICmpCondCode(IC->getPredicate()); 1247 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1248 Condition = getFCmpCondCode(FC->getPredicate()); 1249 } else { 1250 Condition = ISD::SETEQ; // silence warning. 1251 llvm_unreachable("Unknown compare instruction"); 1252 } 1253 1254 CaseBlock CB(Condition, BOp->getOperand(0), 1255 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1256 SwitchCases.push_back(CB); 1257 return; 1258 } 1259 } 1260 1261 // Create a CaseBlock record representing this branch. 1262 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1263 NULL, TBB, FBB, CurBB); 1264 SwitchCases.push_back(CB); 1265} 1266 1267/// FindMergedConditions - If Cond is an expression like 1268void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1269 MachineBasicBlock *TBB, 1270 MachineBasicBlock *FBB, 1271 MachineBasicBlock *CurBB, 1272 MachineBasicBlock *SwitchBB, 1273 unsigned Opc) { 1274 // If this node is not part of the or/and tree, emit it as a branch. 1275 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1276 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1277 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1278 BOp->getParent() != CurBB->getBasicBlock() || 1279 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1280 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1281 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1282 return; 1283 } 1284 1285 // Create TmpBB after CurBB. 1286 MachineFunction::iterator BBI = CurBB; 1287 MachineFunction &MF = DAG.getMachineFunction(); 1288 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1289 CurBB->getParent()->insert(++BBI, TmpBB); 1290 1291 if (Opc == Instruction::Or) { 1292 // Codegen X | Y as: 1293 // jmp_if_X TBB 1294 // jmp TmpBB 1295 // TmpBB: 1296 // jmp_if_Y TBB 1297 // jmp FBB 1298 // 1299 1300 // Emit the LHS condition. 1301 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1302 1303 // Emit the RHS condition into TmpBB. 1304 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1305 } else { 1306 assert(Opc == Instruction::And && "Unknown merge op!"); 1307 // Codegen X & Y as: 1308 // jmp_if_X TmpBB 1309 // jmp FBB 1310 // TmpBB: 1311 // jmp_if_Y TBB 1312 // jmp FBB 1313 // 1314 // This requires creation of TmpBB after CurBB. 1315 1316 // Emit the LHS condition. 1317 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1318 1319 // Emit the RHS condition into TmpBB. 1320 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1321 } 1322} 1323 1324/// If the set of cases should be emitted as a series of branches, return true. 1325/// If we should emit this as a bunch of and/or'd together conditions, return 1326/// false. 1327bool 1328SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1329 if (Cases.size() != 2) return true; 1330 1331 // If this is two comparisons of the same values or'd or and'd together, they 1332 // will get folded into a single comparison, so don't emit two blocks. 1333 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1334 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1335 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1336 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1337 return false; 1338 } 1339 1340 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1341 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1342 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1343 Cases[0].CC == Cases[1].CC && 1344 isa<Constant>(Cases[0].CmpRHS) && 1345 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1346 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1347 return false; 1348 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1349 return false; 1350 } 1351 1352 return true; 1353} 1354 1355void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1356 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1357 1358 // Update machine-CFG edges. 1359 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1360 1361 // Figure out which block is immediately after the current one. 1362 MachineBasicBlock *NextBlock = 0; 1363 MachineFunction::iterator BBI = BrMBB; 1364 if (++BBI != FuncInfo.MF->end()) 1365 NextBlock = BBI; 1366 1367 if (I.isUnconditional()) { 1368 // Update machine-CFG edges. 1369 BrMBB->addSuccessor(Succ0MBB); 1370 1371 // If this is not a fall-through branch, emit the branch. 1372 if (Succ0MBB != NextBlock) 1373 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1374 MVT::Other, getControlRoot(), 1375 DAG.getBasicBlock(Succ0MBB))); 1376 1377 return; 1378 } 1379 1380 // If this condition is one of the special cases we handle, do special stuff 1381 // now. 1382 const Value *CondVal = I.getCondition(); 1383 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1384 1385 // If this is a series of conditions that are or'd or and'd together, emit 1386 // this as a sequence of branches instead of setcc's with and/or operations. 1387 // For example, instead of something like: 1388 // cmp A, B 1389 // C = seteq 1390 // cmp D, E 1391 // F = setle 1392 // or C, F 1393 // jnz foo 1394 // Emit: 1395 // cmp A, B 1396 // je foo 1397 // cmp D, E 1398 // jle foo 1399 // 1400 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1401 if (BOp->hasOneUse() && 1402 (BOp->getOpcode() == Instruction::And || 1403 BOp->getOpcode() == Instruction::Or)) { 1404 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1405 BOp->getOpcode()); 1406 // If the compares in later blocks need to use values not currently 1407 // exported from this block, export them now. This block should always 1408 // be the first entry. 1409 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1410 1411 // Allow some cases to be rejected. 1412 if (ShouldEmitAsBranches(SwitchCases)) { 1413 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1414 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1415 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1416 } 1417 1418 // Emit the branch for this block. 1419 visitSwitchCase(SwitchCases[0], BrMBB); 1420 SwitchCases.erase(SwitchCases.begin()); 1421 return; 1422 } 1423 1424 // Okay, we decided not to do this, remove any inserted MBB's and clear 1425 // SwitchCases. 1426 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1427 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1428 1429 SwitchCases.clear(); 1430 } 1431 } 1432 1433 // Create a CaseBlock record representing this branch. 1434 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1435 NULL, Succ0MBB, Succ1MBB, BrMBB); 1436 1437 // Use visitSwitchCase to actually insert the fast branch sequence for this 1438 // cond branch. 1439 visitSwitchCase(CB, BrMBB); 1440} 1441 1442/// visitSwitchCase - Emits the necessary code to represent a single node in 1443/// the binary search tree resulting from lowering a switch instruction. 1444void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1445 MachineBasicBlock *SwitchBB) { 1446 SDValue Cond; 1447 SDValue CondLHS = getValue(CB.CmpLHS); 1448 DebugLoc dl = getCurDebugLoc(); 1449 1450 // Build the setcc now. 1451 if (CB.CmpMHS == NULL) { 1452 // Fold "(X == true)" to X and "(X == false)" to !X to 1453 // handle common cases produced by branch lowering. 1454 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1455 CB.CC == ISD::SETEQ) 1456 Cond = CondLHS; 1457 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1458 CB.CC == ISD::SETEQ) { 1459 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1460 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1461 } else 1462 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1463 } else { 1464 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1465 1466 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1467 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1468 1469 SDValue CmpOp = getValue(CB.CmpMHS); 1470 EVT VT = CmpOp.getValueType(); 1471 1472 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1473 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1474 ISD::SETLE); 1475 } else { 1476 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1477 VT, CmpOp, DAG.getConstant(Low, VT)); 1478 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1479 DAG.getConstant(High-Low, VT), ISD::SETULE); 1480 } 1481 } 1482 1483 // Update successor info 1484 SwitchBB->addSuccessor(CB.TrueBB); 1485 SwitchBB->addSuccessor(CB.FalseBB); 1486 1487 // Set NextBlock to be the MBB immediately after the current one, if any. 1488 // This is used to avoid emitting unnecessary branches to the next block. 1489 MachineBasicBlock *NextBlock = 0; 1490 MachineFunction::iterator BBI = SwitchBB; 1491 if (++BBI != FuncInfo.MF->end()) 1492 NextBlock = BBI; 1493 1494 // If the lhs block is the next block, invert the condition so that we can 1495 // fall through to the lhs instead of the rhs block. 1496 if (CB.TrueBB == NextBlock) { 1497 std::swap(CB.TrueBB, CB.FalseBB); 1498 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1499 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1500 } 1501 1502 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1503 MVT::Other, getControlRoot(), Cond, 1504 DAG.getBasicBlock(CB.TrueBB)); 1505 1506 // Insert the false branch. Do this even if it's a fall through branch, 1507 // this makes it easier to do DAG optimizations which require inverting 1508 // the branch condition. 1509 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1510 DAG.getBasicBlock(CB.FalseBB)); 1511 1512 DAG.setRoot(BrCond); 1513} 1514 1515/// visitJumpTable - Emit JumpTable node in the current MBB 1516void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1517 // Emit the code for the jump table 1518 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1519 EVT PTy = TLI.getPointerTy(); 1520 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1521 JT.Reg, PTy); 1522 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1523 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1524 MVT::Other, Index.getValue(1), 1525 Table, Index); 1526 DAG.setRoot(BrJumpTable); 1527} 1528 1529/// visitJumpTableHeader - This function emits necessary code to produce index 1530/// in the JumpTable from switch case. 1531void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1532 JumpTableHeader &JTH, 1533 MachineBasicBlock *SwitchBB) { 1534 // Subtract the lowest switch case value from the value being switched on and 1535 // conditional branch to default mbb if the result is greater than the 1536 // difference between smallest and largest cases. 1537 SDValue SwitchOp = getValue(JTH.SValue); 1538 EVT VT = SwitchOp.getValueType(); 1539 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1540 DAG.getConstant(JTH.First, VT)); 1541 1542 // The SDNode we just created, which holds the value being switched on minus 1543 // the smallest case value, needs to be copied to a virtual register so it 1544 // can be used as an index into the jump table in a subsequent basic block. 1545 // This value may be smaller or larger than the target's pointer type, and 1546 // therefore require extension or truncating. 1547 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1548 1549 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1550 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1551 JumpTableReg, SwitchOp); 1552 JT.Reg = JumpTableReg; 1553 1554 // Emit the range check for the jump table, and branch to the default block 1555 // for the switch statement if the value being switched on exceeds the largest 1556 // case in the switch. 1557 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1558 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1559 DAG.getConstant(JTH.Last-JTH.First,VT), 1560 ISD::SETUGT); 1561 1562 // Set NextBlock to be the MBB immediately after the current one, if any. 1563 // This is used to avoid emitting unnecessary branches to the next block. 1564 MachineBasicBlock *NextBlock = 0; 1565 MachineFunction::iterator BBI = SwitchBB; 1566 1567 if (++BBI != FuncInfo.MF->end()) 1568 NextBlock = BBI; 1569 1570 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1571 MVT::Other, CopyTo, CMP, 1572 DAG.getBasicBlock(JT.Default)); 1573 1574 if (JT.MBB != NextBlock) 1575 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1576 DAG.getBasicBlock(JT.MBB)); 1577 1578 DAG.setRoot(BrCond); 1579} 1580 1581/// visitBitTestHeader - This function emits necessary code to produce value 1582/// suitable for "bit tests" 1583void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1584 MachineBasicBlock *SwitchBB) { 1585 // Subtract the minimum value 1586 SDValue SwitchOp = getValue(B.SValue); 1587 EVT VT = SwitchOp.getValueType(); 1588 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1589 DAG.getConstant(B.First, VT)); 1590 1591 // Check range 1592 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1593 TLI.getSetCCResultType(Sub.getValueType()), 1594 Sub, DAG.getConstant(B.Range, VT), 1595 ISD::SETUGT); 1596 1597 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1598 TLI.getPointerTy()); 1599 1600 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1601 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1602 B.Reg, ShiftOp); 1603 1604 // Set NextBlock to be the MBB immediately after the current one, if any. 1605 // This is used to avoid emitting unnecessary branches to the next block. 1606 MachineBasicBlock *NextBlock = 0; 1607 MachineFunction::iterator BBI = SwitchBB; 1608 if (++BBI != FuncInfo.MF->end()) 1609 NextBlock = BBI; 1610 1611 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1612 1613 SwitchBB->addSuccessor(B.Default); 1614 SwitchBB->addSuccessor(MBB); 1615 1616 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1617 MVT::Other, CopyTo, RangeCmp, 1618 DAG.getBasicBlock(B.Default)); 1619 1620 if (MBB != NextBlock) 1621 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1622 DAG.getBasicBlock(MBB)); 1623 1624 DAG.setRoot(BrRange); 1625} 1626 1627/// visitBitTestCase - this function produces one "bit test" 1628void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1629 unsigned Reg, 1630 BitTestCase &B, 1631 MachineBasicBlock *SwitchBB) { 1632 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1633 TLI.getPointerTy()); 1634 SDValue Cmp; 1635 if (CountPopulation_64(B.Mask) == 1) { 1636 // Testing for a single bit; just compare the shift count with what it 1637 // would need to be to shift a 1 bit in that position. 1638 Cmp = DAG.getSetCC(getCurDebugLoc(), 1639 TLI.getSetCCResultType(ShiftOp.getValueType()), 1640 ShiftOp, 1641 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1642 TLI.getPointerTy()), 1643 ISD::SETEQ); 1644 } else { 1645 // Make desired shift 1646 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1647 TLI.getPointerTy(), 1648 DAG.getConstant(1, TLI.getPointerTy()), 1649 ShiftOp); 1650 1651 // Emit bit tests and jumps 1652 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1653 TLI.getPointerTy(), SwitchVal, 1654 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1655 Cmp = DAG.getSetCC(getCurDebugLoc(), 1656 TLI.getSetCCResultType(AndOp.getValueType()), 1657 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1658 ISD::SETNE); 1659 } 1660 1661 SwitchBB->addSuccessor(B.TargetBB); 1662 SwitchBB->addSuccessor(NextMBB); 1663 1664 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1665 MVT::Other, getControlRoot(), 1666 Cmp, DAG.getBasicBlock(B.TargetBB)); 1667 1668 // Set NextBlock to be the MBB immediately after the current one, if any. 1669 // This is used to avoid emitting unnecessary branches to the next block. 1670 MachineBasicBlock *NextBlock = 0; 1671 MachineFunction::iterator BBI = SwitchBB; 1672 if (++BBI != FuncInfo.MF->end()) 1673 NextBlock = BBI; 1674 1675 if (NextMBB != NextBlock) 1676 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1677 DAG.getBasicBlock(NextMBB)); 1678 1679 DAG.setRoot(BrAnd); 1680} 1681 1682void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1683 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1684 1685 // Retrieve successors. 1686 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1687 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1688 1689 const Value *Callee(I.getCalledValue()); 1690 if (isa<InlineAsm>(Callee)) 1691 visitInlineAsm(&I); 1692 else 1693 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1694 1695 // If the value of the invoke is used outside of its defining block, make it 1696 // available as a virtual register. 1697 CopyToExportRegsIfNeeded(&I); 1698 1699 // Update successor info 1700 InvokeMBB->addSuccessor(Return); 1701 InvokeMBB->addSuccessor(LandingPad); 1702 1703 // Drop into normal successor. 1704 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1705 MVT::Other, getControlRoot(), 1706 DAG.getBasicBlock(Return))); 1707} 1708 1709void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1710} 1711 1712/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1713/// small case ranges). 1714bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1715 CaseRecVector& WorkList, 1716 const Value* SV, 1717 MachineBasicBlock *Default, 1718 MachineBasicBlock *SwitchBB) { 1719 Case& BackCase = *(CR.Range.second-1); 1720 1721 // Size is the number of Cases represented by this range. 1722 size_t Size = CR.Range.second - CR.Range.first; 1723 if (Size > 3) 1724 return false; 1725 1726 // Get the MachineFunction which holds the current MBB. This is used when 1727 // inserting any additional MBBs necessary to represent the switch. 1728 MachineFunction *CurMF = FuncInfo.MF; 1729 1730 // Figure out which block is immediately after the current one. 1731 MachineBasicBlock *NextBlock = 0; 1732 MachineFunction::iterator BBI = CR.CaseBB; 1733 1734 if (++BBI != FuncInfo.MF->end()) 1735 NextBlock = BBI; 1736 1737 // TODO: If any two of the cases has the same destination, and if one value 1738 // is the same as the other, but has one bit unset that the other has set, 1739 // use bit manipulation to do two compares at once. For example: 1740 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1741 1742 // Rearrange the case blocks so that the last one falls through if possible. 1743 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1744 // The last case block won't fall through into 'NextBlock' if we emit the 1745 // branches in this order. See if rearranging a case value would help. 1746 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1747 if (I->BB == NextBlock) { 1748 std::swap(*I, BackCase); 1749 break; 1750 } 1751 } 1752 } 1753 1754 // Create a CaseBlock record representing a conditional branch to 1755 // the Case's target mbb if the value being switched on SV is equal 1756 // to C. 1757 MachineBasicBlock *CurBlock = CR.CaseBB; 1758 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1759 MachineBasicBlock *FallThrough; 1760 if (I != E-1) { 1761 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1762 CurMF->insert(BBI, FallThrough); 1763 1764 // Put SV in a virtual register to make it available from the new blocks. 1765 ExportFromCurrentBlock(SV); 1766 } else { 1767 // If the last case doesn't match, go to the default block. 1768 FallThrough = Default; 1769 } 1770 1771 const Value *RHS, *LHS, *MHS; 1772 ISD::CondCode CC; 1773 if (I->High == I->Low) { 1774 // This is just small small case range :) containing exactly 1 case 1775 CC = ISD::SETEQ; 1776 LHS = SV; RHS = I->High; MHS = NULL; 1777 } else { 1778 CC = ISD::SETLE; 1779 LHS = I->Low; MHS = SV; RHS = I->High; 1780 } 1781 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1782 1783 // If emitting the first comparison, just call visitSwitchCase to emit the 1784 // code into the current block. Otherwise, push the CaseBlock onto the 1785 // vector to be later processed by SDISel, and insert the node's MBB 1786 // before the next MBB. 1787 if (CurBlock == SwitchBB) 1788 visitSwitchCase(CB, SwitchBB); 1789 else 1790 SwitchCases.push_back(CB); 1791 1792 CurBlock = FallThrough; 1793 } 1794 1795 return true; 1796} 1797 1798static inline bool areJTsAllowed(const TargetLowering &TLI) { 1799 return !DisableJumpTables && 1800 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1801 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1802} 1803 1804static APInt ComputeRange(const APInt &First, const APInt &Last) { 1805 APInt LastExt(Last), FirstExt(First); 1806 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1807 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1808 return (LastExt - FirstExt + 1ULL); 1809} 1810 1811/// handleJTSwitchCase - Emit jumptable for current switch case range 1812bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1813 CaseRecVector& WorkList, 1814 const Value* SV, 1815 MachineBasicBlock* Default, 1816 MachineBasicBlock *SwitchBB) { 1817 Case& FrontCase = *CR.Range.first; 1818 Case& BackCase = *(CR.Range.second-1); 1819 1820 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1821 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1822 1823 APInt TSize(First.getBitWidth(), 0); 1824 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1825 I!=E; ++I) 1826 TSize += I->size(); 1827 1828 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1829 return false; 1830 1831 APInt Range = ComputeRange(First, Last); 1832 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1833 if (Density < 0.4) 1834 return false; 1835 1836 DEBUG(dbgs() << "Lowering jump table\n" 1837 << "First entry: " << First << ". Last entry: " << Last << '\n' 1838 << "Range: " << Range 1839 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1840 1841 // Get the MachineFunction which holds the current MBB. This is used when 1842 // inserting any additional MBBs necessary to represent the switch. 1843 MachineFunction *CurMF = FuncInfo.MF; 1844 1845 // Figure out which block is immediately after the current one. 1846 MachineFunction::iterator BBI = CR.CaseBB; 1847 ++BBI; 1848 1849 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1850 1851 // Create a new basic block to hold the code for loading the address 1852 // of the jump table, and jumping to it. Update successor information; 1853 // we will either branch to the default case for the switch, or the jump 1854 // table. 1855 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1856 CurMF->insert(BBI, JumpTableBB); 1857 CR.CaseBB->addSuccessor(Default); 1858 CR.CaseBB->addSuccessor(JumpTableBB); 1859 1860 // Build a vector of destination BBs, corresponding to each target 1861 // of the jump table. If the value of the jump table slot corresponds to 1862 // a case statement, push the case's BB onto the vector, otherwise, push 1863 // the default BB. 1864 std::vector<MachineBasicBlock*> DestBBs; 1865 APInt TEI = First; 1866 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1867 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1868 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1869 1870 if (Low.sle(TEI) && TEI.sle(High)) { 1871 DestBBs.push_back(I->BB); 1872 if (TEI==High) 1873 ++I; 1874 } else { 1875 DestBBs.push_back(Default); 1876 } 1877 } 1878 1879 // Update successor info. Add one edge to each unique successor. 1880 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1881 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1882 E = DestBBs.end(); I != E; ++I) { 1883 if (!SuccsHandled[(*I)->getNumber()]) { 1884 SuccsHandled[(*I)->getNumber()] = true; 1885 JumpTableBB->addSuccessor(*I); 1886 } 1887 } 1888 1889 // Create a jump table index for this jump table. 1890 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1891 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1892 ->createJumpTableIndex(DestBBs); 1893 1894 // Set the jump table information so that we can codegen it as a second 1895 // MachineBasicBlock 1896 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1897 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1898 if (CR.CaseBB == SwitchBB) 1899 visitJumpTableHeader(JT, JTH, SwitchBB); 1900 1901 JTCases.push_back(JumpTableBlock(JTH, JT)); 1902 1903 return true; 1904} 1905 1906/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1907/// 2 subtrees. 1908bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1909 CaseRecVector& WorkList, 1910 const Value* SV, 1911 MachineBasicBlock *Default, 1912 MachineBasicBlock *SwitchBB) { 1913 // Get the MachineFunction which holds the current MBB. This is used when 1914 // inserting any additional MBBs necessary to represent the switch. 1915 MachineFunction *CurMF = FuncInfo.MF; 1916 1917 // Figure out which block is immediately after the current one. 1918 MachineFunction::iterator BBI = CR.CaseBB; 1919 ++BBI; 1920 1921 Case& FrontCase = *CR.Range.first; 1922 Case& BackCase = *(CR.Range.second-1); 1923 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1924 1925 // Size is the number of Cases represented by this range. 1926 unsigned Size = CR.Range.second - CR.Range.first; 1927 1928 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1929 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1930 double FMetric = 0; 1931 CaseItr Pivot = CR.Range.first + Size/2; 1932 1933 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1934 // (heuristically) allow us to emit JumpTable's later. 1935 APInt TSize(First.getBitWidth(), 0); 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1937 I!=E; ++I) 1938 TSize += I->size(); 1939 1940 APInt LSize = FrontCase.size(); 1941 APInt RSize = TSize-LSize; 1942 DEBUG(dbgs() << "Selecting best pivot: \n" 1943 << "First: " << First << ", Last: " << Last <<'\n' 1944 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1945 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1946 J!=E; ++I, ++J) { 1947 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1948 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1949 APInt Range = ComputeRange(LEnd, RBegin); 1950 assert((Range - 2ULL).isNonNegative() && 1951 "Invalid case distance"); 1952 double LDensity = (double)LSize.roundToDouble() / 1953 (LEnd - First + 1ULL).roundToDouble(); 1954 double RDensity = (double)RSize.roundToDouble() / 1955 (Last - RBegin + 1ULL).roundToDouble(); 1956 double Metric = Range.logBase2()*(LDensity+RDensity); 1957 // Should always split in some non-trivial place 1958 DEBUG(dbgs() <<"=>Step\n" 1959 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1960 << "LDensity: " << LDensity 1961 << ", RDensity: " << RDensity << '\n' 1962 << "Metric: " << Metric << '\n'); 1963 if (FMetric < Metric) { 1964 Pivot = J; 1965 FMetric = Metric; 1966 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1967 } 1968 1969 LSize += J->size(); 1970 RSize -= J->size(); 1971 } 1972 if (areJTsAllowed(TLI)) { 1973 // If our case is dense we *really* should handle it earlier! 1974 assert((FMetric > 0) && "Should handle dense range earlier!"); 1975 } else { 1976 Pivot = CR.Range.first + Size/2; 1977 } 1978 1979 CaseRange LHSR(CR.Range.first, Pivot); 1980 CaseRange RHSR(Pivot, CR.Range.second); 1981 Constant *C = Pivot->Low; 1982 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1983 1984 // We know that we branch to the LHS if the Value being switched on is 1985 // less than the Pivot value, C. We use this to optimize our binary 1986 // tree a bit, by recognizing that if SV is greater than or equal to the 1987 // LHS's Case Value, and that Case Value is exactly one less than the 1988 // Pivot's Value, then we can branch directly to the LHS's Target, 1989 // rather than creating a leaf node for it. 1990 if ((LHSR.second - LHSR.first) == 1 && 1991 LHSR.first->High == CR.GE && 1992 cast<ConstantInt>(C)->getValue() == 1993 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1994 TrueBB = LHSR.first->BB; 1995 } else { 1996 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1997 CurMF->insert(BBI, TrueBB); 1998 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1999 2000 // Put SV in a virtual register to make it available from the new blocks. 2001 ExportFromCurrentBlock(SV); 2002 } 2003 2004 // Similar to the optimization above, if the Value being switched on is 2005 // known to be less than the Constant CR.LT, and the current Case Value 2006 // is CR.LT - 1, then we can branch directly to the target block for 2007 // the current Case Value, rather than emitting a RHS leaf node for it. 2008 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2009 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2010 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2011 FalseBB = RHSR.first->BB; 2012 } else { 2013 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2014 CurMF->insert(BBI, FalseBB); 2015 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2016 2017 // Put SV in a virtual register to make it available from the new blocks. 2018 ExportFromCurrentBlock(SV); 2019 } 2020 2021 // Create a CaseBlock record representing a conditional branch to 2022 // the LHS node if the value being switched on SV is less than C. 2023 // Otherwise, branch to LHS. 2024 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2025 2026 if (CR.CaseBB == SwitchBB) 2027 visitSwitchCase(CB, SwitchBB); 2028 else 2029 SwitchCases.push_back(CB); 2030 2031 return true; 2032} 2033 2034/// handleBitTestsSwitchCase - if current case range has few destination and 2035/// range span less, than machine word bitwidth, encode case range into series 2036/// of masks and emit bit tests with these masks. 2037bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2038 CaseRecVector& WorkList, 2039 const Value* SV, 2040 MachineBasicBlock* Default, 2041 MachineBasicBlock *SwitchBB){ 2042 EVT PTy = TLI.getPointerTy(); 2043 unsigned IntPtrBits = PTy.getSizeInBits(); 2044 2045 Case& FrontCase = *CR.Range.first; 2046 Case& BackCase = *(CR.Range.second-1); 2047 2048 // Get the MachineFunction which holds the current MBB. This is used when 2049 // inserting any additional MBBs necessary to represent the switch. 2050 MachineFunction *CurMF = FuncInfo.MF; 2051 2052 // If target does not have legal shift left, do not emit bit tests at all. 2053 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2054 return false; 2055 2056 size_t numCmps = 0; 2057 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2058 I!=E; ++I) { 2059 // Single case counts one, case range - two. 2060 numCmps += (I->Low == I->High ? 1 : 2); 2061 } 2062 2063 // Count unique destinations 2064 SmallSet<MachineBasicBlock*, 4> Dests; 2065 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2066 Dests.insert(I->BB); 2067 if (Dests.size() > 3) 2068 // Don't bother the code below, if there are too much unique destinations 2069 return false; 2070 } 2071 DEBUG(dbgs() << "Total number of unique destinations: " 2072 << Dests.size() << '\n' 2073 << "Total number of comparisons: " << numCmps << '\n'); 2074 2075 // Compute span of values. 2076 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2077 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2078 APInt cmpRange = maxValue - minValue; 2079 2080 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2081 << "Low bound: " << minValue << '\n' 2082 << "High bound: " << maxValue << '\n'); 2083 2084 if (cmpRange.uge(IntPtrBits) || 2085 (!(Dests.size() == 1 && numCmps >= 3) && 2086 !(Dests.size() == 2 && numCmps >= 5) && 2087 !(Dests.size() >= 3 && numCmps >= 6))) 2088 return false; 2089 2090 DEBUG(dbgs() << "Emitting bit tests\n"); 2091 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2092 2093 // Optimize the case where all the case values fit in a 2094 // word without having to subtract minValue. In this case, 2095 // we can optimize away the subtraction. 2096 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2097 cmpRange = maxValue; 2098 } else { 2099 lowBound = minValue; 2100 } 2101 2102 CaseBitsVector CasesBits; 2103 unsigned i, count = 0; 2104 2105 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2106 MachineBasicBlock* Dest = I->BB; 2107 for (i = 0; i < count; ++i) 2108 if (Dest == CasesBits[i].BB) 2109 break; 2110 2111 if (i == count) { 2112 assert((count < 3) && "Too much destinations to test!"); 2113 CasesBits.push_back(CaseBits(0, Dest, 0)); 2114 count++; 2115 } 2116 2117 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2118 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2119 2120 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2121 uint64_t hi = (highValue - lowBound).getZExtValue(); 2122 2123 for (uint64_t j = lo; j <= hi; j++) { 2124 CasesBits[i].Mask |= 1ULL << j; 2125 CasesBits[i].Bits++; 2126 } 2127 2128 } 2129 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2130 2131 BitTestInfo BTC; 2132 2133 // Figure out which block is immediately after the current one. 2134 MachineFunction::iterator BBI = CR.CaseBB; 2135 ++BBI; 2136 2137 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2138 2139 DEBUG(dbgs() << "Cases:\n"); 2140 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2141 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2142 << ", Bits: " << CasesBits[i].Bits 2143 << ", BB: " << CasesBits[i].BB << '\n'); 2144 2145 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2146 CurMF->insert(BBI, CaseBB); 2147 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2148 CaseBB, 2149 CasesBits[i].BB)); 2150 2151 // Put SV in a virtual register to make it available from the new blocks. 2152 ExportFromCurrentBlock(SV); 2153 } 2154 2155 BitTestBlock BTB(lowBound, cmpRange, SV, 2156 -1U, (CR.CaseBB == SwitchBB), 2157 CR.CaseBB, Default, BTC); 2158 2159 if (CR.CaseBB == SwitchBB) 2160 visitBitTestHeader(BTB, SwitchBB); 2161 2162 BitTestCases.push_back(BTB); 2163 2164 return true; 2165} 2166 2167/// Clusterify - Transform simple list of Cases into list of CaseRange's 2168size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2169 const SwitchInst& SI) { 2170 size_t numCmps = 0; 2171 2172 // Start with "simple" cases 2173 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2174 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2175 Cases.push_back(Case(SI.getSuccessorValue(i), 2176 SI.getSuccessorValue(i), 2177 SMBB)); 2178 } 2179 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2180 2181 // Merge case into clusters 2182 if (Cases.size() >= 2) 2183 // Must recompute end() each iteration because it may be 2184 // invalidated by erase if we hold on to it 2185 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2186 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2187 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2188 MachineBasicBlock* nextBB = J->BB; 2189 MachineBasicBlock* currentBB = I->BB; 2190 2191 // If the two neighboring cases go to the same destination, merge them 2192 // into a single case. 2193 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2194 I->High = J->High; 2195 J = Cases.erase(J); 2196 } else { 2197 I = J++; 2198 } 2199 } 2200 2201 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2202 if (I->Low != I->High) 2203 // A range counts double, since it requires two compares. 2204 ++numCmps; 2205 } 2206 2207 return numCmps; 2208} 2209 2210void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2211 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2212 2213 // Figure out which block is immediately after the current one. 2214 MachineBasicBlock *NextBlock = 0; 2215 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2216 2217 // If there is only the default destination, branch to it if it is not the 2218 // next basic block. Otherwise, just fall through. 2219 if (SI.getNumOperands() == 2) { 2220 // Update machine-CFG edges. 2221 2222 // If this is not a fall-through branch, emit the branch. 2223 SwitchMBB->addSuccessor(Default); 2224 if (Default != NextBlock) 2225 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2226 MVT::Other, getControlRoot(), 2227 DAG.getBasicBlock(Default))); 2228 2229 return; 2230 } 2231 2232 // If there are any non-default case statements, create a vector of Cases 2233 // representing each one, and sort the vector so that we can efficiently 2234 // create a binary search tree from them. 2235 CaseVector Cases; 2236 size_t numCmps = Clusterify(Cases, SI); 2237 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2238 << ". Total compares: " << numCmps << '\n'); 2239 numCmps = 0; 2240 2241 // Get the Value to be switched on and default basic blocks, which will be 2242 // inserted into CaseBlock records, representing basic blocks in the binary 2243 // search tree. 2244 const Value *SV = SI.getOperand(0); 2245 2246 // Push the initial CaseRec onto the worklist 2247 CaseRecVector WorkList; 2248 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2249 CaseRange(Cases.begin(),Cases.end()))); 2250 2251 while (!WorkList.empty()) { 2252 // Grab a record representing a case range to process off the worklist 2253 CaseRec CR = WorkList.back(); 2254 WorkList.pop_back(); 2255 2256 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2257 continue; 2258 2259 // If the range has few cases (two or less) emit a series of specific 2260 // tests. 2261 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2262 continue; 2263 2264 // If the switch has more than 5 blocks, and at least 40% dense, and the 2265 // target supports indirect branches, then emit a jump table rather than 2266 // lowering the switch to a binary tree of conditional branches. 2267 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2268 continue; 2269 2270 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2271 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2272 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2273 } 2274} 2275 2276void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2277 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2278 2279 // Update machine-CFG edges with unique successors. 2280 SmallVector<BasicBlock*, 32> succs; 2281 succs.reserve(I.getNumSuccessors()); 2282 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2283 succs.push_back(I.getSuccessor(i)); 2284 array_pod_sort(succs.begin(), succs.end()); 2285 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2286 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2287 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2288 2289 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2290 MVT::Other, getControlRoot(), 2291 getValue(I.getAddress()))); 2292} 2293 2294void SelectionDAGBuilder::visitFSub(const User &I) { 2295 // -0.0 - X --> fneg 2296 const Type *Ty = I.getType(); 2297 if (Ty->isVectorTy()) { 2298 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2299 const VectorType *DestTy = cast<VectorType>(I.getType()); 2300 const Type *ElTy = DestTy->getElementType(); 2301 unsigned VL = DestTy->getNumElements(); 2302 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2303 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2304 if (CV == CNZ) { 2305 SDValue Op2 = getValue(I.getOperand(1)); 2306 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2307 Op2.getValueType(), Op2)); 2308 return; 2309 } 2310 } 2311 } 2312 2313 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2314 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2315 SDValue Op2 = getValue(I.getOperand(1)); 2316 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2317 Op2.getValueType(), Op2)); 2318 return; 2319 } 2320 2321 visitBinary(I, ISD::FSUB); 2322} 2323 2324void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2325 SDValue Op1 = getValue(I.getOperand(0)); 2326 SDValue Op2 = getValue(I.getOperand(1)); 2327 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2328 Op1.getValueType(), Op1, Op2)); 2329} 2330 2331void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2332 SDValue Op1 = getValue(I.getOperand(0)); 2333 SDValue Op2 = getValue(I.getOperand(1)); 2334 if (!I.getType()->isVectorTy() && 2335 Op2.getValueType() != TLI.getShiftAmountTy()) { 2336 // If the operand is smaller than the shift count type, promote it. 2337 EVT PTy = TLI.getPointerTy(); 2338 EVT STy = TLI.getShiftAmountTy(); 2339 if (STy.bitsGT(Op2.getValueType())) 2340 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2341 TLI.getShiftAmountTy(), Op2); 2342 // If the operand is larger than the shift count type but the shift 2343 // count type has enough bits to represent any shift value, truncate 2344 // it now. This is a common case and it exposes the truncate to 2345 // optimization early. 2346 else if (STy.getSizeInBits() >= 2347 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2348 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2349 TLI.getShiftAmountTy(), Op2); 2350 // Otherwise we'll need to temporarily settle for some other 2351 // convenient type; type legalization will make adjustments as 2352 // needed. 2353 else if (PTy.bitsLT(Op2.getValueType())) 2354 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2355 TLI.getPointerTy(), Op2); 2356 else if (PTy.bitsGT(Op2.getValueType())) 2357 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2358 TLI.getPointerTy(), Op2); 2359 } 2360 2361 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2362 Op1.getValueType(), Op1, Op2)); 2363} 2364 2365void SelectionDAGBuilder::visitICmp(const User &I) { 2366 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2367 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2368 predicate = IC->getPredicate(); 2369 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2370 predicate = ICmpInst::Predicate(IC->getPredicate()); 2371 SDValue Op1 = getValue(I.getOperand(0)); 2372 SDValue Op2 = getValue(I.getOperand(1)); 2373 ISD::CondCode Opcode = getICmpCondCode(predicate); 2374 2375 EVT DestVT = TLI.getValueType(I.getType()); 2376 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2377} 2378 2379void SelectionDAGBuilder::visitFCmp(const User &I) { 2380 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2381 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2382 predicate = FC->getPredicate(); 2383 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2384 predicate = FCmpInst::Predicate(FC->getPredicate()); 2385 SDValue Op1 = getValue(I.getOperand(0)); 2386 SDValue Op2 = getValue(I.getOperand(1)); 2387 ISD::CondCode Condition = getFCmpCondCode(predicate); 2388 EVT DestVT = TLI.getValueType(I.getType()); 2389 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2390} 2391 2392void SelectionDAGBuilder::visitSelect(const User &I) { 2393 SmallVector<EVT, 4> ValueVTs; 2394 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2395 unsigned NumValues = ValueVTs.size(); 2396 if (NumValues == 0) return; 2397 2398 SmallVector<SDValue, 4> Values(NumValues); 2399 SDValue Cond = getValue(I.getOperand(0)); 2400 SDValue TrueVal = getValue(I.getOperand(1)); 2401 SDValue FalseVal = getValue(I.getOperand(2)); 2402 2403 for (unsigned i = 0; i != NumValues; ++i) 2404 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2405 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2406 Cond, 2407 SDValue(TrueVal.getNode(), 2408 TrueVal.getResNo() + i), 2409 SDValue(FalseVal.getNode(), 2410 FalseVal.getResNo() + i)); 2411 2412 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2413 DAG.getVTList(&ValueVTs[0], NumValues), 2414 &Values[0], NumValues)); 2415} 2416 2417void SelectionDAGBuilder::visitTrunc(const User &I) { 2418 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2419 SDValue N = getValue(I.getOperand(0)); 2420 EVT DestVT = TLI.getValueType(I.getType()); 2421 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2422} 2423 2424void SelectionDAGBuilder::visitZExt(const User &I) { 2425 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2426 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2427 SDValue N = getValue(I.getOperand(0)); 2428 EVT DestVT = TLI.getValueType(I.getType()); 2429 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2430} 2431 2432void SelectionDAGBuilder::visitSExt(const User &I) { 2433 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2434 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2435 SDValue N = getValue(I.getOperand(0)); 2436 EVT DestVT = TLI.getValueType(I.getType()); 2437 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2438} 2439 2440void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2441 // FPTrunc is never a no-op cast, no need to check 2442 SDValue N = getValue(I.getOperand(0)); 2443 EVT DestVT = TLI.getValueType(I.getType()); 2444 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2445 DestVT, N, DAG.getIntPtrConstant(0))); 2446} 2447 2448void SelectionDAGBuilder::visitFPExt(const User &I){ 2449 // FPTrunc is never a no-op cast, no need to check 2450 SDValue N = getValue(I.getOperand(0)); 2451 EVT DestVT = TLI.getValueType(I.getType()); 2452 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2453} 2454 2455void SelectionDAGBuilder::visitFPToUI(const User &I) { 2456 // FPToUI is never a no-op cast, no need to check 2457 SDValue N = getValue(I.getOperand(0)); 2458 EVT DestVT = TLI.getValueType(I.getType()); 2459 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2460} 2461 2462void SelectionDAGBuilder::visitFPToSI(const User &I) { 2463 // FPToSI is never a no-op cast, no need to check 2464 SDValue N = getValue(I.getOperand(0)); 2465 EVT DestVT = TLI.getValueType(I.getType()); 2466 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2467} 2468 2469void SelectionDAGBuilder::visitUIToFP(const User &I) { 2470 // UIToFP is never a no-op cast, no need to check 2471 SDValue N = getValue(I.getOperand(0)); 2472 EVT DestVT = TLI.getValueType(I.getType()); 2473 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2474} 2475 2476void SelectionDAGBuilder::visitSIToFP(const User &I){ 2477 // SIToFP is never a no-op cast, no need to check 2478 SDValue N = getValue(I.getOperand(0)); 2479 EVT DestVT = TLI.getValueType(I.getType()); 2480 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2481} 2482 2483void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2484 // What to do depends on the size of the integer and the size of the pointer. 2485 // We can either truncate, zero extend, or no-op, accordingly. 2486 SDValue N = getValue(I.getOperand(0)); 2487 EVT DestVT = TLI.getValueType(I.getType()); 2488 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2489} 2490 2491void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2492 // What to do depends on the size of the integer and the size of the pointer. 2493 // We can either truncate, zero extend, or no-op, accordingly. 2494 SDValue N = getValue(I.getOperand(0)); 2495 EVT DestVT = TLI.getValueType(I.getType()); 2496 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2497} 2498 2499void SelectionDAGBuilder::visitBitCast(const User &I) { 2500 SDValue N = getValue(I.getOperand(0)); 2501 EVT DestVT = TLI.getValueType(I.getType()); 2502 2503 // BitCast assures us that source and destination are the same size so this is 2504 // either a BIT_CONVERT or a no-op. 2505 if (DestVT != N.getValueType()) 2506 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2507 DestVT, N)); // convert types. 2508 else 2509 setValue(&I, N); // noop cast. 2510} 2511 2512void SelectionDAGBuilder::visitInsertElement(const User &I) { 2513 SDValue InVec = getValue(I.getOperand(0)); 2514 SDValue InVal = getValue(I.getOperand(1)); 2515 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2516 TLI.getPointerTy(), 2517 getValue(I.getOperand(2))); 2518 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2519 TLI.getValueType(I.getType()), 2520 InVec, InVal, InIdx)); 2521} 2522 2523void SelectionDAGBuilder::visitExtractElement(const User &I) { 2524 SDValue InVec = getValue(I.getOperand(0)); 2525 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2526 TLI.getPointerTy(), 2527 getValue(I.getOperand(1))); 2528 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2529 TLI.getValueType(I.getType()), InVec, InIdx)); 2530} 2531 2532// Utility for visitShuffleVector - Returns true if the mask is mask starting 2533// from SIndx and increasing to the element length (undefs are allowed). 2534static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2535 unsigned MaskNumElts = Mask.size(); 2536 for (unsigned i = 0; i != MaskNumElts; ++i) 2537 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2538 return false; 2539 return true; 2540} 2541 2542void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2543 SmallVector<int, 8> Mask; 2544 SDValue Src1 = getValue(I.getOperand(0)); 2545 SDValue Src2 = getValue(I.getOperand(1)); 2546 2547 // Convert the ConstantVector mask operand into an array of ints, with -1 2548 // representing undef values. 2549 SmallVector<Constant*, 8> MaskElts; 2550 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2551 unsigned MaskNumElts = MaskElts.size(); 2552 for (unsigned i = 0; i != MaskNumElts; ++i) { 2553 if (isa<UndefValue>(MaskElts[i])) 2554 Mask.push_back(-1); 2555 else 2556 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2557 } 2558 2559 EVT VT = TLI.getValueType(I.getType()); 2560 EVT SrcVT = Src1.getValueType(); 2561 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2562 2563 if (SrcNumElts == MaskNumElts) { 2564 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2565 &Mask[0])); 2566 return; 2567 } 2568 2569 // Normalize the shuffle vector since mask and vector length don't match. 2570 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2571 // Mask is longer than the source vectors and is a multiple of the source 2572 // vectors. We can use concatenate vector to make the mask and vectors 2573 // lengths match. 2574 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2575 // The shuffle is concatenating two vectors together. 2576 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2577 VT, Src1, Src2)); 2578 return; 2579 } 2580 2581 // Pad both vectors with undefs to make them the same length as the mask. 2582 unsigned NumConcat = MaskNumElts / SrcNumElts; 2583 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2584 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2585 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2586 2587 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2588 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2589 MOps1[0] = Src1; 2590 MOps2[0] = Src2; 2591 2592 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2593 getCurDebugLoc(), VT, 2594 &MOps1[0], NumConcat); 2595 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2596 getCurDebugLoc(), VT, 2597 &MOps2[0], NumConcat); 2598 2599 // Readjust mask for new input vector length. 2600 SmallVector<int, 8> MappedOps; 2601 for (unsigned i = 0; i != MaskNumElts; ++i) { 2602 int Idx = Mask[i]; 2603 if (Idx < (int)SrcNumElts) 2604 MappedOps.push_back(Idx); 2605 else 2606 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2607 } 2608 2609 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2610 &MappedOps[0])); 2611 return; 2612 } 2613 2614 if (SrcNumElts > MaskNumElts) { 2615 // Analyze the access pattern of the vector to see if we can extract 2616 // two subvectors and do the shuffle. The analysis is done by calculating 2617 // the range of elements the mask access on both vectors. 2618 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2619 int MaxRange[2] = {-1, -1}; 2620 2621 for (unsigned i = 0; i != MaskNumElts; ++i) { 2622 int Idx = Mask[i]; 2623 int Input = 0; 2624 if (Idx < 0) 2625 continue; 2626 2627 if (Idx >= (int)SrcNumElts) { 2628 Input = 1; 2629 Idx -= SrcNumElts; 2630 } 2631 if (Idx > MaxRange[Input]) 2632 MaxRange[Input] = Idx; 2633 if (Idx < MinRange[Input]) 2634 MinRange[Input] = Idx; 2635 } 2636 2637 // Check if the access is smaller than the vector size and can we find 2638 // a reasonable extract index. 2639 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2640 // Extract. 2641 int StartIdx[2]; // StartIdx to extract from 2642 for (int Input=0; Input < 2; ++Input) { 2643 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2644 RangeUse[Input] = 0; // Unused 2645 StartIdx[Input] = 0; 2646 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2647 // Fits within range but we should see if we can find a good 2648 // start index that is a multiple of the mask length. 2649 if (MaxRange[Input] < (int)MaskNumElts) { 2650 RangeUse[Input] = 1; // Extract from beginning of the vector 2651 StartIdx[Input] = 0; 2652 } else { 2653 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2654 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2655 StartIdx[Input] + MaskNumElts < SrcNumElts) 2656 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2657 } 2658 } 2659 } 2660 2661 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2662 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2663 return; 2664 } 2665 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2666 // Extract appropriate subvector and generate a vector shuffle 2667 for (int Input=0; Input < 2; ++Input) { 2668 SDValue &Src = Input == 0 ? Src1 : Src2; 2669 if (RangeUse[Input] == 0) 2670 Src = DAG.getUNDEF(VT); 2671 else 2672 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2673 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2674 } 2675 2676 // Calculate new mask. 2677 SmallVector<int, 8> MappedOps; 2678 for (unsigned i = 0; i != MaskNumElts; ++i) { 2679 int Idx = Mask[i]; 2680 if (Idx < 0) 2681 MappedOps.push_back(Idx); 2682 else if (Idx < (int)SrcNumElts) 2683 MappedOps.push_back(Idx - StartIdx[0]); 2684 else 2685 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2686 } 2687 2688 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2689 &MappedOps[0])); 2690 return; 2691 } 2692 } 2693 2694 // We can't use either concat vectors or extract subvectors so fall back to 2695 // replacing the shuffle with extract and build vector. 2696 // to insert and build vector. 2697 EVT EltVT = VT.getVectorElementType(); 2698 EVT PtrVT = TLI.getPointerTy(); 2699 SmallVector<SDValue,8> Ops; 2700 for (unsigned i = 0; i != MaskNumElts; ++i) { 2701 if (Mask[i] < 0) { 2702 Ops.push_back(DAG.getUNDEF(EltVT)); 2703 } else { 2704 int Idx = Mask[i]; 2705 SDValue Res; 2706 2707 if (Idx < (int)SrcNumElts) 2708 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2709 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2710 else 2711 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2712 EltVT, Src2, 2713 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2714 2715 Ops.push_back(Res); 2716 } 2717 } 2718 2719 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2720 VT, &Ops[0], Ops.size())); 2721} 2722 2723void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2724 const Value *Op0 = I.getOperand(0); 2725 const Value *Op1 = I.getOperand(1); 2726 const Type *AggTy = I.getType(); 2727 const Type *ValTy = Op1->getType(); 2728 bool IntoUndef = isa<UndefValue>(Op0); 2729 bool FromUndef = isa<UndefValue>(Op1); 2730 2731 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2732 I.idx_begin(), I.idx_end()); 2733 2734 SmallVector<EVT, 4> AggValueVTs; 2735 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2736 SmallVector<EVT, 4> ValValueVTs; 2737 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2738 2739 unsigned NumAggValues = AggValueVTs.size(); 2740 unsigned NumValValues = ValValueVTs.size(); 2741 SmallVector<SDValue, 4> Values(NumAggValues); 2742 2743 SDValue Agg = getValue(Op0); 2744 SDValue Val = getValue(Op1); 2745 unsigned i = 0; 2746 // Copy the beginning value(s) from the original aggregate. 2747 for (; i != LinearIndex; ++i) 2748 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2749 SDValue(Agg.getNode(), Agg.getResNo() + i); 2750 // Copy values from the inserted value(s). 2751 for (; i != LinearIndex + NumValValues; ++i) 2752 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2753 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2754 // Copy remaining value(s) from the original aggregate. 2755 for (; i != NumAggValues; ++i) 2756 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2757 SDValue(Agg.getNode(), Agg.getResNo() + i); 2758 2759 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2760 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2761 &Values[0], NumAggValues)); 2762} 2763 2764void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2765 const Value *Op0 = I.getOperand(0); 2766 const Type *AggTy = Op0->getType(); 2767 const Type *ValTy = I.getType(); 2768 bool OutOfUndef = isa<UndefValue>(Op0); 2769 2770 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2771 I.idx_begin(), I.idx_end()); 2772 2773 SmallVector<EVT, 4> ValValueVTs; 2774 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2775 2776 unsigned NumValValues = ValValueVTs.size(); 2777 SmallVector<SDValue, 4> Values(NumValValues); 2778 2779 SDValue Agg = getValue(Op0); 2780 // Copy out the selected value(s). 2781 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2782 Values[i - LinearIndex] = 2783 OutOfUndef ? 2784 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2785 SDValue(Agg.getNode(), Agg.getResNo() + i); 2786 2787 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2788 DAG.getVTList(&ValValueVTs[0], NumValValues), 2789 &Values[0], NumValValues)); 2790} 2791 2792void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2793 SDValue N = getValue(I.getOperand(0)); 2794 const Type *Ty = I.getOperand(0)->getType(); 2795 2796 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2797 OI != E; ++OI) { 2798 const Value *Idx = *OI; 2799 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2800 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2801 if (Field) { 2802 // N = N + Offset 2803 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2804 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2805 DAG.getIntPtrConstant(Offset)); 2806 } 2807 2808 Ty = StTy->getElementType(Field); 2809 } else { 2810 Ty = cast<SequentialType>(Ty)->getElementType(); 2811 2812 // If this is a constant subscript, handle it quickly. 2813 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2814 if (CI->isZero()) continue; 2815 uint64_t Offs = 2816 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2817 SDValue OffsVal; 2818 EVT PTy = TLI.getPointerTy(); 2819 unsigned PtrBits = PTy.getSizeInBits(); 2820 if (PtrBits < 64) 2821 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2822 TLI.getPointerTy(), 2823 DAG.getConstant(Offs, MVT::i64)); 2824 else 2825 OffsVal = DAG.getIntPtrConstant(Offs); 2826 2827 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2828 OffsVal); 2829 continue; 2830 } 2831 2832 // N = N + Idx * ElementSize; 2833 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2834 TD->getTypeAllocSize(Ty)); 2835 SDValue IdxN = getValue(Idx); 2836 2837 // If the index is smaller or larger than intptr_t, truncate or extend 2838 // it. 2839 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2840 2841 // If this is a multiply by a power of two, turn it into a shl 2842 // immediately. This is a very common case. 2843 if (ElementSize != 1) { 2844 if (ElementSize.isPowerOf2()) { 2845 unsigned Amt = ElementSize.logBase2(); 2846 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2847 N.getValueType(), IdxN, 2848 DAG.getConstant(Amt, TLI.getPointerTy())); 2849 } else { 2850 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2851 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2852 N.getValueType(), IdxN, Scale); 2853 } 2854 } 2855 2856 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2857 N.getValueType(), N, IdxN); 2858 } 2859 } 2860 2861 setValue(&I, N); 2862} 2863 2864void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2865 // If this is a fixed sized alloca in the entry block of the function, 2866 // allocate it statically on the stack. 2867 if (FuncInfo.StaticAllocaMap.count(&I)) 2868 return; // getValue will auto-populate this. 2869 2870 const Type *Ty = I.getAllocatedType(); 2871 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2872 unsigned Align = 2873 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2874 I.getAlignment()); 2875 2876 SDValue AllocSize = getValue(I.getArraySize()); 2877 2878 EVT IntPtr = TLI.getPointerTy(); 2879 if (AllocSize.getValueType() != IntPtr) 2880 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2881 2882 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2883 AllocSize, 2884 DAG.getConstant(TySize, IntPtr)); 2885 2886 // Handle alignment. If the requested alignment is less than or equal to 2887 // the stack alignment, ignore it. If the size is greater than or equal to 2888 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2889 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2890 if (Align <= StackAlign) 2891 Align = 0; 2892 2893 // Round the size of the allocation up to the stack alignment size 2894 // by add SA-1 to the size. 2895 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2896 AllocSize.getValueType(), AllocSize, 2897 DAG.getIntPtrConstant(StackAlign-1)); 2898 2899 // Mask out the low bits for alignment purposes. 2900 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2901 AllocSize.getValueType(), AllocSize, 2902 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2903 2904 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2905 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2906 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2907 VTs, Ops, 3); 2908 setValue(&I, DSA); 2909 DAG.setRoot(DSA.getValue(1)); 2910 2911 // Inform the Frame Information that we have just allocated a variable-sized 2912 // object. 2913 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2914} 2915 2916void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2917 const Value *SV = I.getOperand(0); 2918 SDValue Ptr = getValue(SV); 2919 2920 const Type *Ty = I.getType(); 2921 2922 bool isVolatile = I.isVolatile(); 2923 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2924 unsigned Alignment = I.getAlignment(); 2925 2926 SmallVector<EVT, 4> ValueVTs; 2927 SmallVector<uint64_t, 4> Offsets; 2928 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2929 unsigned NumValues = ValueVTs.size(); 2930 if (NumValues == 0) 2931 return; 2932 2933 SDValue Root; 2934 bool ConstantMemory = false; 2935 if (I.isVolatile()) 2936 // Serialize volatile loads with other side effects. 2937 Root = getRoot(); 2938 else if (AA->pointsToConstantMemory(SV)) { 2939 // Do not serialize (non-volatile) loads of constant memory with anything. 2940 Root = DAG.getEntryNode(); 2941 ConstantMemory = true; 2942 } else { 2943 // Do not serialize non-volatile loads against each other. 2944 Root = DAG.getRoot(); 2945 } 2946 2947 SmallVector<SDValue, 4> Values(NumValues); 2948 SmallVector<SDValue, 4> Chains(NumValues); 2949 EVT PtrVT = Ptr.getValueType(); 2950 for (unsigned i = 0; i != NumValues; ++i) { 2951 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2952 PtrVT, Ptr, 2953 DAG.getConstant(Offsets[i], PtrVT)); 2954 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2955 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 2956 isNonTemporal, Alignment); 2957 2958 Values[i] = L; 2959 Chains[i] = L.getValue(1); 2960 } 2961 2962 if (!ConstantMemory) { 2963 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2964 MVT::Other, &Chains[0], NumValues); 2965 if (isVolatile) 2966 DAG.setRoot(Chain); 2967 else 2968 PendingLoads.push_back(Chain); 2969 } 2970 2971 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2972 DAG.getVTList(&ValueVTs[0], NumValues), 2973 &Values[0], NumValues)); 2974} 2975 2976void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2977 const Value *SrcV = I.getOperand(0); 2978 const Value *PtrV = I.getOperand(1); 2979 2980 SmallVector<EVT, 4> ValueVTs; 2981 SmallVector<uint64_t, 4> Offsets; 2982 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2983 unsigned NumValues = ValueVTs.size(); 2984 if (NumValues == 0) 2985 return; 2986 2987 // Get the lowered operands. Note that we do this after 2988 // checking if NumResults is zero, because with zero results 2989 // the operands won't have values in the map. 2990 SDValue Src = getValue(SrcV); 2991 SDValue Ptr = getValue(PtrV); 2992 2993 SDValue Root = getRoot(); 2994 SmallVector<SDValue, 4> Chains(NumValues); 2995 EVT PtrVT = Ptr.getValueType(); 2996 bool isVolatile = I.isVolatile(); 2997 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2998 unsigned Alignment = I.getAlignment(); 2999 3000 for (unsigned i = 0; i != NumValues; ++i) { 3001 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3002 DAG.getConstant(Offsets[i], PtrVT)); 3003 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 3004 SDValue(Src.getNode(), Src.getResNo() + i), 3005 Add, MachinePointerInfo(PtrV, Offsets[i]), 3006 isVolatile, isNonTemporal, Alignment); 3007 } 3008 3009 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3010 MVT::Other, &Chains[0], NumValues)); 3011} 3012 3013/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3014/// node. 3015void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3016 unsigned Intrinsic) { 3017 bool HasChain = !I.doesNotAccessMemory(); 3018 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3019 3020 // Build the operand list. 3021 SmallVector<SDValue, 8> Ops; 3022 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3023 if (OnlyLoad) { 3024 // We don't need to serialize loads against other loads. 3025 Ops.push_back(DAG.getRoot()); 3026 } else { 3027 Ops.push_back(getRoot()); 3028 } 3029 } 3030 3031 // Info is set by getTgtMemInstrinsic 3032 TargetLowering::IntrinsicInfo Info; 3033 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3034 3035 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3036 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3037 Info.opc == ISD::INTRINSIC_W_CHAIN) 3038 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3039 3040 // Add all operands of the call to the operand list. 3041 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3042 SDValue Op = getValue(I.getArgOperand(i)); 3043 assert(TLI.isTypeLegal(Op.getValueType()) && 3044 "Intrinsic uses a non-legal type?"); 3045 Ops.push_back(Op); 3046 } 3047 3048 SmallVector<EVT, 4> ValueVTs; 3049 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3050#ifndef NDEBUG 3051 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3052 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3053 "Intrinsic uses a non-legal type?"); 3054 } 3055#endif // NDEBUG 3056 3057 if (HasChain) 3058 ValueVTs.push_back(MVT::Other); 3059 3060 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3061 3062 // Create the node. 3063 SDValue Result; 3064 if (IsTgtIntrinsic) { 3065 // This is target intrinsic that touches memory 3066 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3067 VTs, &Ops[0], Ops.size(), 3068 Info.memVT, 3069 MachinePointerInfo(Info.ptrVal, Info.offset), 3070 Info.align, Info.vol, 3071 Info.readMem, Info.writeMem); 3072 } else if (!HasChain) { 3073 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3074 VTs, &Ops[0], Ops.size()); 3075 } else if (!I.getType()->isVoidTy()) { 3076 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3077 VTs, &Ops[0], Ops.size()); 3078 } else { 3079 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3080 VTs, &Ops[0], Ops.size()); 3081 } 3082 3083 if (HasChain) { 3084 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3085 if (OnlyLoad) 3086 PendingLoads.push_back(Chain); 3087 else 3088 DAG.setRoot(Chain); 3089 } 3090 3091 if (!I.getType()->isVoidTy()) { 3092 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3093 EVT VT = TLI.getValueType(PTy); 3094 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3095 } 3096 3097 setValue(&I, Result); 3098 } 3099} 3100 3101/// GetSignificand - Get the significand and build it into a floating-point 3102/// number with exponent of 1: 3103/// 3104/// Op = (Op & 0x007fffff) | 0x3f800000; 3105/// 3106/// where Op is the hexidecimal representation of floating point value. 3107static SDValue 3108GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3109 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3110 DAG.getConstant(0x007fffff, MVT::i32)); 3111 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3112 DAG.getConstant(0x3f800000, MVT::i32)); 3113 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3114} 3115 3116/// GetExponent - Get the exponent: 3117/// 3118/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3119/// 3120/// where Op is the hexidecimal representation of floating point value. 3121static SDValue 3122GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3123 DebugLoc dl) { 3124 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3125 DAG.getConstant(0x7f800000, MVT::i32)); 3126 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3127 DAG.getConstant(23, TLI.getPointerTy())); 3128 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3129 DAG.getConstant(127, MVT::i32)); 3130 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3131} 3132 3133/// getF32Constant - Get 32-bit floating point constant. 3134static SDValue 3135getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3136 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3137} 3138 3139/// Inlined utility function to implement binary input atomic intrinsics for 3140/// visitIntrinsicCall: I is a call instruction 3141/// Op is the associated NodeType for I 3142const char * 3143SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3144 ISD::NodeType Op) { 3145 SDValue Root = getRoot(); 3146 SDValue L = 3147 DAG.getAtomic(Op, getCurDebugLoc(), 3148 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3149 Root, 3150 getValue(I.getArgOperand(0)), 3151 getValue(I.getArgOperand(1)), 3152 I.getArgOperand(0)); 3153 setValue(&I, L); 3154 DAG.setRoot(L.getValue(1)); 3155 return 0; 3156} 3157 3158// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3159const char * 3160SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3161 SDValue Op1 = getValue(I.getArgOperand(0)); 3162 SDValue Op2 = getValue(I.getArgOperand(1)); 3163 3164 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3165 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3166 return 0; 3167} 3168 3169/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3170/// limited-precision mode. 3171void 3172SelectionDAGBuilder::visitExp(const CallInst &I) { 3173 SDValue result; 3174 DebugLoc dl = getCurDebugLoc(); 3175 3176 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3177 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3178 SDValue Op = getValue(I.getArgOperand(0)); 3179 3180 // Put the exponent in the right bit position for later addition to the 3181 // final result: 3182 // 3183 // #define LOG2OFe 1.4426950f 3184 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3185 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3186 getF32Constant(DAG, 0x3fb8aa3b)); 3187 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3188 3189 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3190 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3191 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3192 3193 // IntegerPartOfX <<= 23; 3194 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3195 DAG.getConstant(23, TLI.getPointerTy())); 3196 3197 if (LimitFloatPrecision <= 6) { 3198 // For floating-point precision of 6: 3199 // 3200 // TwoToFractionalPartOfX = 3201 // 0.997535578f + 3202 // (0.735607626f + 0.252464424f * x) * x; 3203 // 3204 // error 0.0144103317, which is 6 bits 3205 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3206 getF32Constant(DAG, 0x3e814304)); 3207 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3208 getF32Constant(DAG, 0x3f3c50c8)); 3209 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3210 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3211 getF32Constant(DAG, 0x3f7f5e7e)); 3212 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3213 3214 // Add the exponent into the result in integer domain. 3215 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3216 TwoToFracPartOfX, IntegerPartOfX); 3217 3218 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3219 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3220 // For floating-point precision of 12: 3221 // 3222 // TwoToFractionalPartOfX = 3223 // 0.999892986f + 3224 // (0.696457318f + 3225 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3226 // 3227 // 0.000107046256 error, which is 13 to 14 bits 3228 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3229 getF32Constant(DAG, 0x3da235e3)); 3230 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3231 getF32Constant(DAG, 0x3e65b8f3)); 3232 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3233 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3234 getF32Constant(DAG, 0x3f324b07)); 3235 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3236 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3237 getF32Constant(DAG, 0x3f7ff8fd)); 3238 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3239 3240 // Add the exponent into the result in integer domain. 3241 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3242 TwoToFracPartOfX, IntegerPartOfX); 3243 3244 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3245 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3246 // For floating-point precision of 18: 3247 // 3248 // TwoToFractionalPartOfX = 3249 // 0.999999982f + 3250 // (0.693148872f + 3251 // (0.240227044f + 3252 // (0.554906021e-1f + 3253 // (0.961591928e-2f + 3254 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3255 // 3256 // error 2.47208000*10^(-7), which is better than 18 bits 3257 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3258 getF32Constant(DAG, 0x3924b03e)); 3259 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3260 getF32Constant(DAG, 0x3ab24b87)); 3261 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3262 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3263 getF32Constant(DAG, 0x3c1d8c17)); 3264 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3265 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3266 getF32Constant(DAG, 0x3d634a1d)); 3267 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3268 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3269 getF32Constant(DAG, 0x3e75fe14)); 3270 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3271 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3272 getF32Constant(DAG, 0x3f317234)); 3273 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3274 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3275 getF32Constant(DAG, 0x3f800000)); 3276 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3277 MVT::i32, t13); 3278 3279 // Add the exponent into the result in integer domain. 3280 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3281 TwoToFracPartOfX, IntegerPartOfX); 3282 3283 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3284 } 3285 } else { 3286 // No special expansion. 3287 result = DAG.getNode(ISD::FEXP, dl, 3288 getValue(I.getArgOperand(0)).getValueType(), 3289 getValue(I.getArgOperand(0))); 3290 } 3291 3292 setValue(&I, result); 3293} 3294 3295/// visitLog - Lower a log intrinsic. Handles the special sequences for 3296/// limited-precision mode. 3297void 3298SelectionDAGBuilder::visitLog(const CallInst &I) { 3299 SDValue result; 3300 DebugLoc dl = getCurDebugLoc(); 3301 3302 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3303 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3304 SDValue Op = getValue(I.getArgOperand(0)); 3305 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3306 3307 // Scale the exponent by log(2) [0.69314718f]. 3308 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3309 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3310 getF32Constant(DAG, 0x3f317218)); 3311 3312 // Get the significand and build it into a floating-point number with 3313 // exponent of 1. 3314 SDValue X = GetSignificand(DAG, Op1, dl); 3315 3316 if (LimitFloatPrecision <= 6) { 3317 // For floating-point precision of 6: 3318 // 3319 // LogofMantissa = 3320 // -1.1609546f + 3321 // (1.4034025f - 0.23903021f * x) * x; 3322 // 3323 // error 0.0034276066, which is better than 8 bits 3324 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3325 getF32Constant(DAG, 0xbe74c456)); 3326 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3327 getF32Constant(DAG, 0x3fb3a2b1)); 3328 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3329 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3330 getF32Constant(DAG, 0x3f949a29)); 3331 3332 result = DAG.getNode(ISD::FADD, dl, 3333 MVT::f32, LogOfExponent, LogOfMantissa); 3334 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3335 // For floating-point precision of 12: 3336 // 3337 // LogOfMantissa = 3338 // -1.7417939f + 3339 // (2.8212026f + 3340 // (-1.4699568f + 3341 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3342 // 3343 // error 0.000061011436, which is 14 bits 3344 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3345 getF32Constant(DAG, 0xbd67b6d6)); 3346 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3347 getF32Constant(DAG, 0x3ee4f4b8)); 3348 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3349 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3350 getF32Constant(DAG, 0x3fbc278b)); 3351 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3352 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3353 getF32Constant(DAG, 0x40348e95)); 3354 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3355 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3356 getF32Constant(DAG, 0x3fdef31a)); 3357 3358 result = DAG.getNode(ISD::FADD, dl, 3359 MVT::f32, LogOfExponent, LogOfMantissa); 3360 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3361 // For floating-point precision of 18: 3362 // 3363 // LogOfMantissa = 3364 // -2.1072184f + 3365 // (4.2372794f + 3366 // (-3.7029485f + 3367 // (2.2781945f + 3368 // (-0.87823314f + 3369 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3370 // 3371 // error 0.0000023660568, which is better than 18 bits 3372 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3373 getF32Constant(DAG, 0xbc91e5ac)); 3374 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3375 getF32Constant(DAG, 0x3e4350aa)); 3376 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3377 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3378 getF32Constant(DAG, 0x3f60d3e3)); 3379 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3380 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3381 getF32Constant(DAG, 0x4011cdf0)); 3382 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3383 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3384 getF32Constant(DAG, 0x406cfd1c)); 3385 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3386 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3387 getF32Constant(DAG, 0x408797cb)); 3388 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3389 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3390 getF32Constant(DAG, 0x4006dcab)); 3391 3392 result = DAG.getNode(ISD::FADD, dl, 3393 MVT::f32, LogOfExponent, LogOfMantissa); 3394 } 3395 } else { 3396 // No special expansion. 3397 result = DAG.getNode(ISD::FLOG, dl, 3398 getValue(I.getArgOperand(0)).getValueType(), 3399 getValue(I.getArgOperand(0))); 3400 } 3401 3402 setValue(&I, result); 3403} 3404 3405/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3406/// limited-precision mode. 3407void 3408SelectionDAGBuilder::visitLog2(const CallInst &I) { 3409 SDValue result; 3410 DebugLoc dl = getCurDebugLoc(); 3411 3412 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3413 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3414 SDValue Op = getValue(I.getArgOperand(0)); 3415 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3416 3417 // Get the exponent. 3418 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3419 3420 // Get the significand and build it into a floating-point number with 3421 // exponent of 1. 3422 SDValue X = GetSignificand(DAG, Op1, dl); 3423 3424 // Different possible minimax approximations of significand in 3425 // floating-point for various degrees of accuracy over [1,2]. 3426 if (LimitFloatPrecision <= 6) { 3427 // For floating-point precision of 6: 3428 // 3429 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3430 // 3431 // error 0.0049451742, which is more than 7 bits 3432 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3433 getF32Constant(DAG, 0xbeb08fe0)); 3434 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3435 getF32Constant(DAG, 0x40019463)); 3436 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3437 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3438 getF32Constant(DAG, 0x3fd6633d)); 3439 3440 result = DAG.getNode(ISD::FADD, dl, 3441 MVT::f32, LogOfExponent, Log2ofMantissa); 3442 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3443 // For floating-point precision of 12: 3444 // 3445 // Log2ofMantissa = 3446 // -2.51285454f + 3447 // (4.07009056f + 3448 // (-2.12067489f + 3449 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3450 // 3451 // error 0.0000876136000, which is better than 13 bits 3452 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3453 getF32Constant(DAG, 0xbda7262e)); 3454 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3455 getF32Constant(DAG, 0x3f25280b)); 3456 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3457 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3458 getF32Constant(DAG, 0x4007b923)); 3459 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3460 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3461 getF32Constant(DAG, 0x40823e2f)); 3462 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3463 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3464 getF32Constant(DAG, 0x4020d29c)); 3465 3466 result = DAG.getNode(ISD::FADD, dl, 3467 MVT::f32, LogOfExponent, Log2ofMantissa); 3468 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3469 // For floating-point precision of 18: 3470 // 3471 // Log2ofMantissa = 3472 // -3.0400495f + 3473 // (6.1129976f + 3474 // (-5.3420409f + 3475 // (3.2865683f + 3476 // (-1.2669343f + 3477 // (0.27515199f - 3478 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3479 // 3480 // error 0.0000018516, which is better than 18 bits 3481 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3482 getF32Constant(DAG, 0xbcd2769e)); 3483 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3484 getF32Constant(DAG, 0x3e8ce0b9)); 3485 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3486 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3487 getF32Constant(DAG, 0x3fa22ae7)); 3488 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3489 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3490 getF32Constant(DAG, 0x40525723)); 3491 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3492 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3493 getF32Constant(DAG, 0x40aaf200)); 3494 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3495 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3496 getF32Constant(DAG, 0x40c39dad)); 3497 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3498 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3499 getF32Constant(DAG, 0x4042902c)); 3500 3501 result = DAG.getNode(ISD::FADD, dl, 3502 MVT::f32, LogOfExponent, Log2ofMantissa); 3503 } 3504 } else { 3505 // No special expansion. 3506 result = DAG.getNode(ISD::FLOG2, dl, 3507 getValue(I.getArgOperand(0)).getValueType(), 3508 getValue(I.getArgOperand(0))); 3509 } 3510 3511 setValue(&I, result); 3512} 3513 3514/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3515/// limited-precision mode. 3516void 3517SelectionDAGBuilder::visitLog10(const CallInst &I) { 3518 SDValue result; 3519 DebugLoc dl = getCurDebugLoc(); 3520 3521 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3522 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3523 SDValue Op = getValue(I.getArgOperand(0)); 3524 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3525 3526 // Scale the exponent by log10(2) [0.30102999f]. 3527 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3528 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3529 getF32Constant(DAG, 0x3e9a209a)); 3530 3531 // Get the significand and build it into a floating-point number with 3532 // exponent of 1. 3533 SDValue X = GetSignificand(DAG, Op1, dl); 3534 3535 if (LimitFloatPrecision <= 6) { 3536 // For floating-point precision of 6: 3537 // 3538 // Log10ofMantissa = 3539 // -0.50419619f + 3540 // (0.60948995f - 0.10380950f * x) * x; 3541 // 3542 // error 0.0014886165, which is 6 bits 3543 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3544 getF32Constant(DAG, 0xbdd49a13)); 3545 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3546 getF32Constant(DAG, 0x3f1c0789)); 3547 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3548 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3549 getF32Constant(DAG, 0x3f011300)); 3550 3551 result = DAG.getNode(ISD::FADD, dl, 3552 MVT::f32, LogOfExponent, Log10ofMantissa); 3553 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3554 // For floating-point precision of 12: 3555 // 3556 // Log10ofMantissa = 3557 // -0.64831180f + 3558 // (0.91751397f + 3559 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3560 // 3561 // error 0.00019228036, which is better than 12 bits 3562 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3563 getF32Constant(DAG, 0x3d431f31)); 3564 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3565 getF32Constant(DAG, 0x3ea21fb2)); 3566 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3567 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3568 getF32Constant(DAG, 0x3f6ae232)); 3569 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3570 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3571 getF32Constant(DAG, 0x3f25f7c3)); 3572 3573 result = DAG.getNode(ISD::FADD, dl, 3574 MVT::f32, LogOfExponent, Log10ofMantissa); 3575 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3576 // For floating-point precision of 18: 3577 // 3578 // Log10ofMantissa = 3579 // -0.84299375f + 3580 // (1.5327582f + 3581 // (-1.0688956f + 3582 // (0.49102474f + 3583 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3584 // 3585 // error 0.0000037995730, which is better than 18 bits 3586 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3587 getF32Constant(DAG, 0x3c5d51ce)); 3588 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3589 getF32Constant(DAG, 0x3e00685a)); 3590 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3591 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3592 getF32Constant(DAG, 0x3efb6798)); 3593 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3594 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3595 getF32Constant(DAG, 0x3f88d192)); 3596 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3597 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3598 getF32Constant(DAG, 0x3fc4316c)); 3599 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3600 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3601 getF32Constant(DAG, 0x3f57ce70)); 3602 3603 result = DAG.getNode(ISD::FADD, dl, 3604 MVT::f32, LogOfExponent, Log10ofMantissa); 3605 } 3606 } else { 3607 // No special expansion. 3608 result = DAG.getNode(ISD::FLOG10, dl, 3609 getValue(I.getArgOperand(0)).getValueType(), 3610 getValue(I.getArgOperand(0))); 3611 } 3612 3613 setValue(&I, result); 3614} 3615 3616/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3617/// limited-precision mode. 3618void 3619SelectionDAGBuilder::visitExp2(const CallInst &I) { 3620 SDValue result; 3621 DebugLoc dl = getCurDebugLoc(); 3622 3623 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3624 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3625 SDValue Op = getValue(I.getArgOperand(0)); 3626 3627 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3628 3629 // FractionalPartOfX = x - (float)IntegerPartOfX; 3630 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3631 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3632 3633 // IntegerPartOfX <<= 23; 3634 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3635 DAG.getConstant(23, TLI.getPointerTy())); 3636 3637 if (LimitFloatPrecision <= 6) { 3638 // For floating-point precision of 6: 3639 // 3640 // TwoToFractionalPartOfX = 3641 // 0.997535578f + 3642 // (0.735607626f + 0.252464424f * x) * x; 3643 // 3644 // error 0.0144103317, which is 6 bits 3645 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3646 getF32Constant(DAG, 0x3e814304)); 3647 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3648 getF32Constant(DAG, 0x3f3c50c8)); 3649 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3650 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3651 getF32Constant(DAG, 0x3f7f5e7e)); 3652 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3653 SDValue TwoToFractionalPartOfX = 3654 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3655 3656 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3657 MVT::f32, TwoToFractionalPartOfX); 3658 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3659 // For floating-point precision of 12: 3660 // 3661 // TwoToFractionalPartOfX = 3662 // 0.999892986f + 3663 // (0.696457318f + 3664 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3665 // 3666 // error 0.000107046256, which is 13 to 14 bits 3667 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3668 getF32Constant(DAG, 0x3da235e3)); 3669 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3670 getF32Constant(DAG, 0x3e65b8f3)); 3671 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3672 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3673 getF32Constant(DAG, 0x3f324b07)); 3674 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3675 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3676 getF32Constant(DAG, 0x3f7ff8fd)); 3677 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3678 SDValue TwoToFractionalPartOfX = 3679 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3680 3681 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3682 MVT::f32, TwoToFractionalPartOfX); 3683 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3684 // For floating-point precision of 18: 3685 // 3686 // TwoToFractionalPartOfX = 3687 // 0.999999982f + 3688 // (0.693148872f + 3689 // (0.240227044f + 3690 // (0.554906021e-1f + 3691 // (0.961591928e-2f + 3692 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3693 // error 2.47208000*10^(-7), which is better than 18 bits 3694 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3695 getF32Constant(DAG, 0x3924b03e)); 3696 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3697 getF32Constant(DAG, 0x3ab24b87)); 3698 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3699 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3700 getF32Constant(DAG, 0x3c1d8c17)); 3701 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3702 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3703 getF32Constant(DAG, 0x3d634a1d)); 3704 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3705 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3706 getF32Constant(DAG, 0x3e75fe14)); 3707 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3708 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3709 getF32Constant(DAG, 0x3f317234)); 3710 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3711 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3712 getF32Constant(DAG, 0x3f800000)); 3713 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3714 SDValue TwoToFractionalPartOfX = 3715 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3716 3717 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3718 MVT::f32, TwoToFractionalPartOfX); 3719 } 3720 } else { 3721 // No special expansion. 3722 result = DAG.getNode(ISD::FEXP2, dl, 3723 getValue(I.getArgOperand(0)).getValueType(), 3724 getValue(I.getArgOperand(0))); 3725 } 3726 3727 setValue(&I, result); 3728} 3729 3730/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3731/// limited-precision mode with x == 10.0f. 3732void 3733SelectionDAGBuilder::visitPow(const CallInst &I) { 3734 SDValue result; 3735 const Value *Val = I.getArgOperand(0); 3736 DebugLoc dl = getCurDebugLoc(); 3737 bool IsExp10 = false; 3738 3739 if (getValue(Val).getValueType() == MVT::f32 && 3740 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3741 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3742 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3743 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3744 APFloat Ten(10.0f); 3745 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3746 } 3747 } 3748 } 3749 3750 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3751 SDValue Op = getValue(I.getArgOperand(1)); 3752 3753 // Put the exponent in the right bit position for later addition to the 3754 // final result: 3755 // 3756 // #define LOG2OF10 3.3219281f 3757 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3758 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3759 getF32Constant(DAG, 0x40549a78)); 3760 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3761 3762 // FractionalPartOfX = x - (float)IntegerPartOfX; 3763 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3764 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3765 3766 // IntegerPartOfX <<= 23; 3767 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3768 DAG.getConstant(23, TLI.getPointerTy())); 3769 3770 if (LimitFloatPrecision <= 6) { 3771 // For floating-point precision of 6: 3772 // 3773 // twoToFractionalPartOfX = 3774 // 0.997535578f + 3775 // (0.735607626f + 0.252464424f * x) * x; 3776 // 3777 // error 0.0144103317, which is 6 bits 3778 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3779 getF32Constant(DAG, 0x3e814304)); 3780 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3781 getF32Constant(DAG, 0x3f3c50c8)); 3782 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3783 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3784 getF32Constant(DAG, 0x3f7f5e7e)); 3785 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3786 SDValue TwoToFractionalPartOfX = 3787 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3788 3789 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3790 MVT::f32, TwoToFractionalPartOfX); 3791 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3792 // For floating-point precision of 12: 3793 // 3794 // TwoToFractionalPartOfX = 3795 // 0.999892986f + 3796 // (0.696457318f + 3797 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3798 // 3799 // error 0.000107046256, which is 13 to 14 bits 3800 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3801 getF32Constant(DAG, 0x3da235e3)); 3802 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3803 getF32Constant(DAG, 0x3e65b8f3)); 3804 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3805 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3806 getF32Constant(DAG, 0x3f324b07)); 3807 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3808 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3809 getF32Constant(DAG, 0x3f7ff8fd)); 3810 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3811 SDValue TwoToFractionalPartOfX = 3812 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3813 3814 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3815 MVT::f32, TwoToFractionalPartOfX); 3816 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3817 // For floating-point precision of 18: 3818 // 3819 // TwoToFractionalPartOfX = 3820 // 0.999999982f + 3821 // (0.693148872f + 3822 // (0.240227044f + 3823 // (0.554906021e-1f + 3824 // (0.961591928e-2f + 3825 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3826 // error 2.47208000*10^(-7), which is better than 18 bits 3827 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3828 getF32Constant(DAG, 0x3924b03e)); 3829 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3830 getF32Constant(DAG, 0x3ab24b87)); 3831 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3832 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3833 getF32Constant(DAG, 0x3c1d8c17)); 3834 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3835 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3836 getF32Constant(DAG, 0x3d634a1d)); 3837 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3838 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3839 getF32Constant(DAG, 0x3e75fe14)); 3840 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3841 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3842 getF32Constant(DAG, 0x3f317234)); 3843 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3844 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3845 getF32Constant(DAG, 0x3f800000)); 3846 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3847 SDValue TwoToFractionalPartOfX = 3848 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3849 3850 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3851 MVT::f32, TwoToFractionalPartOfX); 3852 } 3853 } else { 3854 // No special expansion. 3855 result = DAG.getNode(ISD::FPOW, dl, 3856 getValue(I.getArgOperand(0)).getValueType(), 3857 getValue(I.getArgOperand(0)), 3858 getValue(I.getArgOperand(1))); 3859 } 3860 3861 setValue(&I, result); 3862} 3863 3864 3865/// ExpandPowI - Expand a llvm.powi intrinsic. 3866static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3867 SelectionDAG &DAG) { 3868 // If RHS is a constant, we can expand this out to a multiplication tree, 3869 // otherwise we end up lowering to a call to __powidf2 (for example). When 3870 // optimizing for size, we only want to do this if the expansion would produce 3871 // a small number of multiplies, otherwise we do the full expansion. 3872 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3873 // Get the exponent as a positive value. 3874 unsigned Val = RHSC->getSExtValue(); 3875 if ((int)Val < 0) Val = -Val; 3876 3877 // powi(x, 0) -> 1.0 3878 if (Val == 0) 3879 return DAG.getConstantFP(1.0, LHS.getValueType()); 3880 3881 const Function *F = DAG.getMachineFunction().getFunction(); 3882 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3883 // If optimizing for size, don't insert too many multiplies. This 3884 // inserts up to 5 multiplies. 3885 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3886 // We use the simple binary decomposition method to generate the multiply 3887 // sequence. There are more optimal ways to do this (for example, 3888 // powi(x,15) generates one more multiply than it should), but this has 3889 // the benefit of being both really simple and much better than a libcall. 3890 SDValue Res; // Logically starts equal to 1.0 3891 SDValue CurSquare = LHS; 3892 while (Val) { 3893 if (Val & 1) { 3894 if (Res.getNode()) 3895 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3896 else 3897 Res = CurSquare; // 1.0*CurSquare. 3898 } 3899 3900 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3901 CurSquare, CurSquare); 3902 Val >>= 1; 3903 } 3904 3905 // If the original was negative, invert the result, producing 1/(x*x*x). 3906 if (RHSC->getSExtValue() < 0) 3907 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3908 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3909 return Res; 3910 } 3911 } 3912 3913 // Otherwise, expand to a libcall. 3914 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3915} 3916 3917/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3918/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3919/// At the end of instruction selection, they will be inserted to the entry BB. 3920bool 3921SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 3922 int64_t Offset, 3923 const SDValue &N) { 3924 const Argument *Arg = dyn_cast<Argument>(V); 3925 if (!Arg) 3926 return false; 3927 3928 MachineFunction &MF = DAG.getMachineFunction(); 3929 // Ignore inlined function arguments here. 3930 DIVariable DV(Variable); 3931 if (DV.isInlinedFnArgument(MF.getFunction())) 3932 return false; 3933 3934 MachineBasicBlock *MBB = FuncInfo.MBB; 3935 if (MBB != &MF.front()) 3936 return false; 3937 3938 unsigned Reg = 0; 3939 if (Arg->hasByValAttr()) { 3940 // Byval arguments' frame index is recorded during argument lowering. 3941 // Use this info directly. 3942 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3943 Reg = TRI->getFrameRegister(MF); 3944 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 3945 } 3946 3947 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 3948 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3949 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3950 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3951 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3952 if (PR) 3953 Reg = PR; 3954 } 3955 } 3956 3957 if (!Reg) { 3958 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3959 if (VMI == FuncInfo.ValueMap.end()) 3960 return false; 3961 Reg = VMI->second; 3962 } 3963 3964 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3965 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3966 TII->get(TargetOpcode::DBG_VALUE)) 3967 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 3968 FuncInfo.ArgDbgValues.push_back(&*MIB); 3969 return true; 3970} 3971 3972// VisualStudio defines setjmp as _setjmp 3973#if defined(_MSC_VER) && defined(setjmp) 3974#define setjmp_undefined_for_visual_studio 3975#undef setjmp 3976#endif 3977 3978/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3979/// we want to emit this as a call to a named external function, return the name 3980/// otherwise lower it and return null. 3981const char * 3982SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3983 DebugLoc dl = getCurDebugLoc(); 3984 SDValue Res; 3985 3986 switch (Intrinsic) { 3987 default: 3988 // By default, turn this into a target intrinsic node. 3989 visitTargetIntrinsic(I, Intrinsic); 3990 return 0; 3991 case Intrinsic::vastart: visitVAStart(I); return 0; 3992 case Intrinsic::vaend: visitVAEnd(I); return 0; 3993 case Intrinsic::vacopy: visitVACopy(I); return 0; 3994 case Intrinsic::returnaddress: 3995 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3996 getValue(I.getArgOperand(0)))); 3997 return 0; 3998 case Intrinsic::frameaddress: 3999 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4000 getValue(I.getArgOperand(0)))); 4001 return 0; 4002 case Intrinsic::setjmp: 4003 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4004 case Intrinsic::longjmp: 4005 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4006 case Intrinsic::memcpy: { 4007 // Assert for address < 256 since we support only user defined address 4008 // spaces. 4009 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4010 < 256 && 4011 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4012 < 256 && 4013 "Unknown address space"); 4014 SDValue Op1 = getValue(I.getArgOperand(0)); 4015 SDValue Op2 = getValue(I.getArgOperand(1)); 4016 SDValue Op3 = getValue(I.getArgOperand(2)); 4017 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4018 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4019 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4020 MachinePointerInfo(I.getArgOperand(0)), 4021 MachinePointerInfo(I.getArgOperand(1)))); 4022 return 0; 4023 } 4024 case Intrinsic::memset: { 4025 // Assert for address < 256 since we support only user defined address 4026 // spaces. 4027 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4028 < 256 && 4029 "Unknown address space"); 4030 SDValue Op1 = getValue(I.getArgOperand(0)); 4031 SDValue Op2 = getValue(I.getArgOperand(1)); 4032 SDValue Op3 = getValue(I.getArgOperand(2)); 4033 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4034 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4035 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4036 MachinePointerInfo(I.getArgOperand(0)))); 4037 return 0; 4038 } 4039 case Intrinsic::memmove: { 4040 // Assert for address < 256 since we support only user defined address 4041 // spaces. 4042 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4043 < 256 && 4044 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4045 < 256 && 4046 "Unknown address space"); 4047 SDValue Op1 = getValue(I.getArgOperand(0)); 4048 SDValue Op2 = getValue(I.getArgOperand(1)); 4049 SDValue Op3 = getValue(I.getArgOperand(2)); 4050 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4051 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4052 4053 // If the source and destination are known to not be aliases, we can 4054 // lower memmove as memcpy. 4055 uint64_t Size = -1ULL; 4056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4057 Size = C->getZExtValue(); 4058 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == 4059 AliasAnalysis::NoAlias) { 4060 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4061 false, MachinePointerInfo(I.getArgOperand(0)), 4062 MachinePointerInfo(I.getArgOperand(1)))); 4063 return 0; 4064 } 4065 4066 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4067 MachinePointerInfo(I.getArgOperand(0)), 4068 MachinePointerInfo(I.getArgOperand(1)))); 4069 return 0; 4070 } 4071 case Intrinsic::dbg_declare: { 4072 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4073 MDNode *Variable = DI.getVariable(); 4074 const Value *Address = DI.getAddress(); 4075 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4076 return 0; 4077 4078 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4079 // but do not always have a corresponding SDNode built. The SDNodeOrder 4080 // absolute, but not relative, values are different depending on whether 4081 // debug info exists. 4082 ++SDNodeOrder; 4083 4084 // Check if address has undef value. 4085 if (isa<UndefValue>(Address) || 4086 (Address->use_empty() && !isa<Argument>(Address))) { 4087 SDDbgValue*SDV = 4088 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4089 0, dl, SDNodeOrder); 4090 DAG.AddDbgValue(SDV, 0, false); 4091 return 0; 4092 } 4093 4094 SDValue &N = NodeMap[Address]; 4095 if (!N.getNode() && isa<Argument>(Address)) 4096 // Check unused arguments map. 4097 N = UnusedArgNodeMap[Address]; 4098 SDDbgValue *SDV; 4099 if (N.getNode()) { 4100 // Parameters are handled specially. 4101 bool isParameter = 4102 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4103 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4104 Address = BCI->getOperand(0); 4105 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4106 4107 if (isParameter && !AI) { 4108 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4109 if (FINode) 4110 // Byval parameter. We have a frame index at this point. 4111 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4112 0, dl, SDNodeOrder); 4113 else 4114 // Can't do anything with other non-AI cases yet. This might be a 4115 // parameter of a callee function that got inlined, for example. 4116 return 0; 4117 } else if (AI) 4118 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4119 0, dl, SDNodeOrder); 4120 else 4121 // Can't do anything with other non-AI cases yet. 4122 return 0; 4123 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4124 } else { 4125 // If Address is an arugment then try to emits its dbg value using 4126 // virtual register info from the FuncInfo.ValueMap. 4127 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4128 // If variable is pinned by a alloca in dominating bb then 4129 // use StaticAllocaMap. 4130 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4131 if (AI->getParent() != DI.getParent()) { 4132 DenseMap<const AllocaInst*, int>::iterator SI = 4133 FuncInfo.StaticAllocaMap.find(AI); 4134 if (SI != FuncInfo.StaticAllocaMap.end()) { 4135 SDV = DAG.getDbgValue(Variable, SI->second, 4136 0, dl, SDNodeOrder); 4137 DAG.AddDbgValue(SDV, 0, false); 4138 return 0; 4139 } 4140 } 4141 } 4142 // Otherwise add undef to help track missing debug info. 4143 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4144 0, dl, SDNodeOrder); 4145 DAG.AddDbgValue(SDV, 0, false); 4146 } 4147 } 4148 return 0; 4149 } 4150 case Intrinsic::dbg_value: { 4151 const DbgValueInst &DI = cast<DbgValueInst>(I); 4152 if (!DIVariable(DI.getVariable()).Verify()) 4153 return 0; 4154 4155 MDNode *Variable = DI.getVariable(); 4156 uint64_t Offset = DI.getOffset(); 4157 const Value *V = DI.getValue(); 4158 if (!V) 4159 return 0; 4160 4161 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4162 // but do not always have a corresponding SDNode built. The SDNodeOrder 4163 // absolute, but not relative, values are different depending on whether 4164 // debug info exists. 4165 ++SDNodeOrder; 4166 SDDbgValue *SDV; 4167 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4168 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4169 DAG.AddDbgValue(SDV, 0, false); 4170 } else { 4171 // Do not use getValue() in here; we don't want to generate code at 4172 // this point if it hasn't been done yet. 4173 SDValue N = NodeMap[V]; 4174 if (!N.getNode() && isa<Argument>(V)) 4175 // Check unused arguments map. 4176 N = UnusedArgNodeMap[V]; 4177 if (N.getNode()) { 4178 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4179 SDV = DAG.getDbgValue(Variable, N.getNode(), 4180 N.getResNo(), Offset, dl, SDNodeOrder); 4181 DAG.AddDbgValue(SDV, N.getNode(), false); 4182 } 4183 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4184 // Do not call getValue(V) yet, as we don't want to generate code. 4185 // Remember it for later. 4186 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4187 DanglingDebugInfoMap[V] = DDI; 4188 } else { 4189 // We may expand this to cover more cases. One case where we have no 4190 // data available is an unreferenced parameter; we need this fallback. 4191 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4192 Offset, dl, SDNodeOrder); 4193 DAG.AddDbgValue(SDV, 0, false); 4194 } 4195 } 4196 4197 // Build a debug info table entry. 4198 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4199 V = BCI->getOperand(0); 4200 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4201 // Don't handle byval struct arguments or VLAs, for example. 4202 if (!AI) 4203 return 0; 4204 DenseMap<const AllocaInst*, int>::iterator SI = 4205 FuncInfo.StaticAllocaMap.find(AI); 4206 if (SI == FuncInfo.StaticAllocaMap.end()) 4207 return 0; // VLAs. 4208 int FI = SI->second; 4209 4210 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4211 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4212 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4213 return 0; 4214 } 4215 case Intrinsic::eh_exception: { 4216 // Insert the EXCEPTIONADDR instruction. 4217 assert(FuncInfo.MBB->isLandingPad() && 4218 "Call to eh.exception not in landing pad!"); 4219 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4220 SDValue Ops[1]; 4221 Ops[0] = DAG.getRoot(); 4222 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4223 setValue(&I, Op); 4224 DAG.setRoot(Op.getValue(1)); 4225 return 0; 4226 } 4227 4228 case Intrinsic::eh_selector: { 4229 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4230 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4231 if (CallMBB->isLandingPad()) 4232 AddCatchInfo(I, &MMI, CallMBB); 4233 else { 4234#ifndef NDEBUG 4235 FuncInfo.CatchInfoLost.insert(&I); 4236#endif 4237 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4238 unsigned Reg = TLI.getExceptionSelectorRegister(); 4239 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4240 } 4241 4242 // Insert the EHSELECTION instruction. 4243 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4244 SDValue Ops[2]; 4245 Ops[0] = getValue(I.getArgOperand(0)); 4246 Ops[1] = getRoot(); 4247 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4248 DAG.setRoot(Op.getValue(1)); 4249 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4250 return 0; 4251 } 4252 4253 case Intrinsic::eh_typeid_for: { 4254 // Find the type id for the given typeinfo. 4255 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4256 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4257 Res = DAG.getConstant(TypeID, MVT::i32); 4258 setValue(&I, Res); 4259 return 0; 4260 } 4261 4262 case Intrinsic::eh_return_i32: 4263 case Intrinsic::eh_return_i64: 4264 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4265 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4266 MVT::Other, 4267 getControlRoot(), 4268 getValue(I.getArgOperand(0)), 4269 getValue(I.getArgOperand(1)))); 4270 return 0; 4271 case Intrinsic::eh_unwind_init: 4272 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4273 return 0; 4274 case Intrinsic::eh_dwarf_cfa: { 4275 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4276 TLI.getPointerTy()); 4277 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4278 TLI.getPointerTy(), 4279 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4280 TLI.getPointerTy()), 4281 CfaArg); 4282 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4283 TLI.getPointerTy(), 4284 DAG.getConstant(0, TLI.getPointerTy())); 4285 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4286 FA, Offset)); 4287 return 0; 4288 } 4289 case Intrinsic::eh_sjlj_callsite: { 4290 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4291 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4292 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4293 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4294 4295 MMI.setCurrentCallSite(CI->getZExtValue()); 4296 return 0; 4297 } 4298 case Intrinsic::eh_sjlj_setjmp: { 4299 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4300 getValue(I.getArgOperand(0)))); 4301 return 0; 4302 } 4303 case Intrinsic::eh_sjlj_longjmp: { 4304 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4305 getRoot(), 4306 getValue(I.getArgOperand(0)))); 4307 return 0; 4308 } 4309 4310 case Intrinsic::convertff: 4311 case Intrinsic::convertfsi: 4312 case Intrinsic::convertfui: 4313 case Intrinsic::convertsif: 4314 case Intrinsic::convertuif: 4315 case Intrinsic::convertss: 4316 case Intrinsic::convertsu: 4317 case Intrinsic::convertus: 4318 case Intrinsic::convertuu: { 4319 ISD::CvtCode Code = ISD::CVT_INVALID; 4320 switch (Intrinsic) { 4321 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4322 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4323 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4324 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4325 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4326 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4327 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4328 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4329 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4330 } 4331 EVT DestVT = TLI.getValueType(I.getType()); 4332 const Value *Op1 = I.getArgOperand(0); 4333 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4334 DAG.getValueType(DestVT), 4335 DAG.getValueType(getValue(Op1).getValueType()), 4336 getValue(I.getArgOperand(1)), 4337 getValue(I.getArgOperand(2)), 4338 Code); 4339 setValue(&I, Res); 4340 return 0; 4341 } 4342 case Intrinsic::sqrt: 4343 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4344 getValue(I.getArgOperand(0)).getValueType(), 4345 getValue(I.getArgOperand(0)))); 4346 return 0; 4347 case Intrinsic::powi: 4348 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4349 getValue(I.getArgOperand(1)), DAG)); 4350 return 0; 4351 case Intrinsic::sin: 4352 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4353 getValue(I.getArgOperand(0)).getValueType(), 4354 getValue(I.getArgOperand(0)))); 4355 return 0; 4356 case Intrinsic::cos: 4357 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4358 getValue(I.getArgOperand(0)).getValueType(), 4359 getValue(I.getArgOperand(0)))); 4360 return 0; 4361 case Intrinsic::log: 4362 visitLog(I); 4363 return 0; 4364 case Intrinsic::log2: 4365 visitLog2(I); 4366 return 0; 4367 case Intrinsic::log10: 4368 visitLog10(I); 4369 return 0; 4370 case Intrinsic::exp: 4371 visitExp(I); 4372 return 0; 4373 case Intrinsic::exp2: 4374 visitExp2(I); 4375 return 0; 4376 case Intrinsic::pow: 4377 visitPow(I); 4378 return 0; 4379 case Intrinsic::convert_to_fp16: 4380 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4381 MVT::i16, getValue(I.getArgOperand(0)))); 4382 return 0; 4383 case Intrinsic::convert_from_fp16: 4384 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4385 MVT::f32, getValue(I.getArgOperand(0)))); 4386 return 0; 4387 case Intrinsic::pcmarker: { 4388 SDValue Tmp = getValue(I.getArgOperand(0)); 4389 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4390 return 0; 4391 } 4392 case Intrinsic::readcyclecounter: { 4393 SDValue Op = getRoot(); 4394 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4395 DAG.getVTList(MVT::i64, MVT::Other), 4396 &Op, 1); 4397 setValue(&I, Res); 4398 DAG.setRoot(Res.getValue(1)); 4399 return 0; 4400 } 4401 case Intrinsic::bswap: 4402 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4403 getValue(I.getArgOperand(0)).getValueType(), 4404 getValue(I.getArgOperand(0)))); 4405 return 0; 4406 case Intrinsic::cttz: { 4407 SDValue Arg = getValue(I.getArgOperand(0)); 4408 EVT Ty = Arg.getValueType(); 4409 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4410 return 0; 4411 } 4412 case Intrinsic::ctlz: { 4413 SDValue Arg = getValue(I.getArgOperand(0)); 4414 EVT Ty = Arg.getValueType(); 4415 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4416 return 0; 4417 } 4418 case Intrinsic::ctpop: { 4419 SDValue Arg = getValue(I.getArgOperand(0)); 4420 EVT Ty = Arg.getValueType(); 4421 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4422 return 0; 4423 } 4424 case Intrinsic::stacksave: { 4425 SDValue Op = getRoot(); 4426 Res = DAG.getNode(ISD::STACKSAVE, dl, 4427 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4428 setValue(&I, Res); 4429 DAG.setRoot(Res.getValue(1)); 4430 return 0; 4431 } 4432 case Intrinsic::stackrestore: { 4433 Res = getValue(I.getArgOperand(0)); 4434 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4435 return 0; 4436 } 4437 case Intrinsic::stackprotector: { 4438 // Emit code into the DAG to store the stack guard onto the stack. 4439 MachineFunction &MF = DAG.getMachineFunction(); 4440 MachineFrameInfo *MFI = MF.getFrameInfo(); 4441 EVT PtrTy = TLI.getPointerTy(); 4442 4443 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4444 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4445 4446 int FI = FuncInfo.StaticAllocaMap[Slot]; 4447 MFI->setStackProtectorIndex(FI); 4448 4449 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4450 4451 // Store the stack protector onto the stack. 4452 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4453 MachinePointerInfo::getFixedStack(FI), 4454 true, false, 0); 4455 setValue(&I, Res); 4456 DAG.setRoot(Res); 4457 return 0; 4458 } 4459 case Intrinsic::objectsize: { 4460 // If we don't know by now, we're never going to know. 4461 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4462 4463 assert(CI && "Non-constant type in __builtin_object_size?"); 4464 4465 SDValue Arg = getValue(I.getCalledValue()); 4466 EVT Ty = Arg.getValueType(); 4467 4468 if (CI->isZero()) 4469 Res = DAG.getConstant(-1ULL, Ty); 4470 else 4471 Res = DAG.getConstant(0, Ty); 4472 4473 setValue(&I, Res); 4474 return 0; 4475 } 4476 case Intrinsic::var_annotation: 4477 // Discard annotate attributes 4478 return 0; 4479 4480 case Intrinsic::init_trampoline: { 4481 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4482 4483 SDValue Ops[6]; 4484 Ops[0] = getRoot(); 4485 Ops[1] = getValue(I.getArgOperand(0)); 4486 Ops[2] = getValue(I.getArgOperand(1)); 4487 Ops[3] = getValue(I.getArgOperand(2)); 4488 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4489 Ops[5] = DAG.getSrcValue(F); 4490 4491 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4492 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4493 Ops, 6); 4494 4495 setValue(&I, Res); 4496 DAG.setRoot(Res.getValue(1)); 4497 return 0; 4498 } 4499 case Intrinsic::gcroot: 4500 if (GFI) { 4501 const Value *Alloca = I.getArgOperand(0); 4502 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4503 4504 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4505 GFI->addStackRoot(FI->getIndex(), TypeMap); 4506 } 4507 return 0; 4508 case Intrinsic::gcread: 4509 case Intrinsic::gcwrite: 4510 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4511 return 0; 4512 case Intrinsic::flt_rounds: 4513 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4514 return 0; 4515 case Intrinsic::trap: 4516 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4517 return 0; 4518 case Intrinsic::uadd_with_overflow: 4519 return implVisitAluOverflow(I, ISD::UADDO); 4520 case Intrinsic::sadd_with_overflow: 4521 return implVisitAluOverflow(I, ISD::SADDO); 4522 case Intrinsic::usub_with_overflow: 4523 return implVisitAluOverflow(I, ISD::USUBO); 4524 case Intrinsic::ssub_with_overflow: 4525 return implVisitAluOverflow(I, ISD::SSUBO); 4526 case Intrinsic::umul_with_overflow: 4527 return implVisitAluOverflow(I, ISD::UMULO); 4528 case Intrinsic::smul_with_overflow: 4529 return implVisitAluOverflow(I, ISD::SMULO); 4530 4531 case Intrinsic::prefetch: { 4532 SDValue Ops[4]; 4533 Ops[0] = getRoot(); 4534 Ops[1] = getValue(I.getArgOperand(0)); 4535 Ops[2] = getValue(I.getArgOperand(1)); 4536 Ops[3] = getValue(I.getArgOperand(2)); 4537 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4538 return 0; 4539 } 4540 4541 case Intrinsic::memory_barrier: { 4542 SDValue Ops[6]; 4543 Ops[0] = getRoot(); 4544 for (int x = 1; x < 6; ++x) 4545 Ops[x] = getValue(I.getArgOperand(x - 1)); 4546 4547 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4548 return 0; 4549 } 4550 case Intrinsic::atomic_cmp_swap: { 4551 SDValue Root = getRoot(); 4552 SDValue L = 4553 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4554 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4555 Root, 4556 getValue(I.getArgOperand(0)), 4557 getValue(I.getArgOperand(1)), 4558 getValue(I.getArgOperand(2)), 4559 MachinePointerInfo(I.getArgOperand(0))); 4560 setValue(&I, L); 4561 DAG.setRoot(L.getValue(1)); 4562 return 0; 4563 } 4564 case Intrinsic::atomic_load_add: 4565 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4566 case Intrinsic::atomic_load_sub: 4567 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4568 case Intrinsic::atomic_load_or: 4569 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4570 case Intrinsic::atomic_load_xor: 4571 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4572 case Intrinsic::atomic_load_and: 4573 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4574 case Intrinsic::atomic_load_nand: 4575 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4576 case Intrinsic::atomic_load_max: 4577 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4578 case Intrinsic::atomic_load_min: 4579 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4580 case Intrinsic::atomic_load_umin: 4581 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4582 case Intrinsic::atomic_load_umax: 4583 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4584 case Intrinsic::atomic_swap: 4585 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4586 4587 case Intrinsic::invariant_start: 4588 case Intrinsic::lifetime_start: 4589 // Discard region information. 4590 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4591 return 0; 4592 case Intrinsic::invariant_end: 4593 case Intrinsic::lifetime_end: 4594 // Discard region information. 4595 return 0; 4596 } 4597} 4598 4599void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4600 bool isTailCall, 4601 MachineBasicBlock *LandingPad) { 4602 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4603 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4604 const Type *RetTy = FTy->getReturnType(); 4605 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4606 MCSymbol *BeginLabel = 0; 4607 4608 TargetLowering::ArgListTy Args; 4609 TargetLowering::ArgListEntry Entry; 4610 Args.reserve(CS.arg_size()); 4611 4612 // Check whether the function can return without sret-demotion. 4613 SmallVector<ISD::OutputArg, 4> Outs; 4614 SmallVector<uint64_t, 4> Offsets; 4615 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4616 Outs, TLI, &Offsets); 4617 4618 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4619 FTy->isVarArg(), Outs, FTy->getContext()); 4620 4621 SDValue DemoteStackSlot; 4622 int DemoteStackIdx = -100; 4623 4624 if (!CanLowerReturn) { 4625 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4626 FTy->getReturnType()); 4627 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4628 FTy->getReturnType()); 4629 MachineFunction &MF = DAG.getMachineFunction(); 4630 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4631 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4632 4633 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4634 Entry.Node = DemoteStackSlot; 4635 Entry.Ty = StackSlotPtrType; 4636 Entry.isSExt = false; 4637 Entry.isZExt = false; 4638 Entry.isInReg = false; 4639 Entry.isSRet = true; 4640 Entry.isNest = false; 4641 Entry.isByVal = false; 4642 Entry.Alignment = Align; 4643 Args.push_back(Entry); 4644 RetTy = Type::getVoidTy(FTy->getContext()); 4645 } 4646 4647 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4648 i != e; ++i) { 4649 SDValue ArgNode = getValue(*i); 4650 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4651 4652 unsigned attrInd = i - CS.arg_begin() + 1; 4653 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4654 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4655 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4656 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4657 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4658 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4659 Entry.Alignment = CS.getParamAlignment(attrInd); 4660 Args.push_back(Entry); 4661 } 4662 4663 if (LandingPad) { 4664 // Insert a label before the invoke call to mark the try range. This can be 4665 // used to detect deletion of the invoke via the MachineModuleInfo. 4666 BeginLabel = MMI.getContext().CreateTempSymbol(); 4667 4668 // For SjLj, keep track of which landing pads go with which invokes 4669 // so as to maintain the ordering of pads in the LSDA. 4670 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4671 if (CallSiteIndex) { 4672 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4673 // Now that the call site is handled, stop tracking it. 4674 MMI.setCurrentCallSite(0); 4675 } 4676 4677 // Both PendingLoads and PendingExports must be flushed here; 4678 // this call might not return. 4679 (void)getRoot(); 4680 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4681 } 4682 4683 // Check if target-independent constraints permit a tail call here. 4684 // Target-dependent constraints are checked within TLI.LowerCallTo. 4685 if (isTailCall && 4686 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4687 isTailCall = false; 4688 4689 // If there's a possibility that fast-isel has already selected some amount 4690 // of the current basic block, don't emit a tail call. 4691 if (isTailCall && EnableFastISel) 4692 isTailCall = false; 4693 4694 std::pair<SDValue,SDValue> Result = 4695 TLI.LowerCallTo(getRoot(), RetTy, 4696 CS.paramHasAttr(0, Attribute::SExt), 4697 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4698 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4699 CS.getCallingConv(), 4700 isTailCall, 4701 !CS.getInstruction()->use_empty(), 4702 Callee, Args, DAG, getCurDebugLoc()); 4703 assert((isTailCall || Result.second.getNode()) && 4704 "Non-null chain expected with non-tail call!"); 4705 assert((Result.second.getNode() || !Result.first.getNode()) && 4706 "Null value expected with tail call!"); 4707 if (Result.first.getNode()) { 4708 setValue(CS.getInstruction(), Result.first); 4709 } else if (!CanLowerReturn && Result.second.getNode()) { 4710 // The instruction result is the result of loading from the 4711 // hidden sret parameter. 4712 SmallVector<EVT, 1> PVTs; 4713 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4714 4715 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4716 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4717 EVT PtrVT = PVTs[0]; 4718 unsigned NumValues = Outs.size(); 4719 SmallVector<SDValue, 4> Values(NumValues); 4720 SmallVector<SDValue, 4> Chains(NumValues); 4721 4722 for (unsigned i = 0; i < NumValues; ++i) { 4723 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4724 DemoteStackSlot, 4725 DAG.getConstant(Offsets[i], PtrVT)); 4726 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4727 Add, 4728 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4729 false, false, 1); 4730 Values[i] = L; 4731 Chains[i] = L.getValue(1); 4732 } 4733 4734 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4735 MVT::Other, &Chains[0], NumValues); 4736 PendingLoads.push_back(Chain); 4737 4738 // Collect the legal value parts into potentially illegal values 4739 // that correspond to the original function's return values. 4740 SmallVector<EVT, 4> RetTys; 4741 RetTy = FTy->getReturnType(); 4742 ComputeValueVTs(TLI, RetTy, RetTys); 4743 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4744 SmallVector<SDValue, 4> ReturnValues; 4745 unsigned CurReg = 0; 4746 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4747 EVT VT = RetTys[I]; 4748 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4749 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4750 4751 SDValue ReturnValue = 4752 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4753 RegisterVT, VT, AssertOp); 4754 ReturnValues.push_back(ReturnValue); 4755 CurReg += NumRegs; 4756 } 4757 4758 setValue(CS.getInstruction(), 4759 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4760 DAG.getVTList(&RetTys[0], RetTys.size()), 4761 &ReturnValues[0], ReturnValues.size())); 4762 4763 } 4764 4765 // As a special case, a null chain means that a tail call has been emitted and 4766 // the DAG root is already updated. 4767 if (Result.second.getNode()) 4768 DAG.setRoot(Result.second); 4769 else 4770 HasTailCall = true; 4771 4772 if (LandingPad) { 4773 // Insert a label at the end of the invoke call to mark the try range. This 4774 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4775 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4776 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4777 4778 // Inform MachineModuleInfo of range. 4779 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4780 } 4781} 4782 4783/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4784/// value is equal or not-equal to zero. 4785static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4786 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4787 UI != E; ++UI) { 4788 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4789 if (IC->isEquality()) 4790 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4791 if (C->isNullValue()) 4792 continue; 4793 // Unknown instruction. 4794 return false; 4795 } 4796 return true; 4797} 4798 4799static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4800 const Type *LoadTy, 4801 SelectionDAGBuilder &Builder) { 4802 4803 // Check to see if this load can be trivially constant folded, e.g. if the 4804 // input is from a string literal. 4805 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4806 // Cast pointer to the type we really want to load. 4807 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4808 PointerType::getUnqual(LoadTy)); 4809 4810 if (const Constant *LoadCst = 4811 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4812 Builder.TD)) 4813 return Builder.getValue(LoadCst); 4814 } 4815 4816 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4817 // still constant memory, the input chain can be the entry node. 4818 SDValue Root; 4819 bool ConstantMemory = false; 4820 4821 // Do not serialize (non-volatile) loads of constant memory with anything. 4822 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4823 Root = Builder.DAG.getEntryNode(); 4824 ConstantMemory = true; 4825 } else { 4826 // Do not serialize non-volatile loads against each other. 4827 Root = Builder.DAG.getRoot(); 4828 } 4829 4830 SDValue Ptr = Builder.getValue(PtrVal); 4831 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4832 Ptr, MachinePointerInfo(PtrVal), 4833 false /*volatile*/, 4834 false /*nontemporal*/, 1 /* align=1 */); 4835 4836 if (!ConstantMemory) 4837 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4838 return LoadVal; 4839} 4840 4841 4842/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4843/// If so, return true and lower it, otherwise return false and it will be 4844/// lowered like a normal call. 4845bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4846 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4847 if (I.getNumArgOperands() != 3) 4848 return false; 4849 4850 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 4851 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4852 !I.getArgOperand(2)->getType()->isIntegerTy() || 4853 !I.getType()->isIntegerTy()) 4854 return false; 4855 4856 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 4857 4858 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4859 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4860 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4861 bool ActuallyDoIt = true; 4862 MVT LoadVT; 4863 const Type *LoadTy; 4864 switch (Size->getZExtValue()) { 4865 default: 4866 LoadVT = MVT::Other; 4867 LoadTy = 0; 4868 ActuallyDoIt = false; 4869 break; 4870 case 2: 4871 LoadVT = MVT::i16; 4872 LoadTy = Type::getInt16Ty(Size->getContext()); 4873 break; 4874 case 4: 4875 LoadVT = MVT::i32; 4876 LoadTy = Type::getInt32Ty(Size->getContext()); 4877 break; 4878 case 8: 4879 LoadVT = MVT::i64; 4880 LoadTy = Type::getInt64Ty(Size->getContext()); 4881 break; 4882 /* 4883 case 16: 4884 LoadVT = MVT::v4i32; 4885 LoadTy = Type::getInt32Ty(Size->getContext()); 4886 LoadTy = VectorType::get(LoadTy, 4); 4887 break; 4888 */ 4889 } 4890 4891 // This turns into unaligned loads. We only do this if the target natively 4892 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4893 // we'll only produce a small number of byte loads. 4894 4895 // Require that we can find a legal MVT, and only do this if the target 4896 // supports unaligned loads of that type. Expanding into byte loads would 4897 // bloat the code. 4898 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4899 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4900 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4901 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4902 ActuallyDoIt = false; 4903 } 4904 4905 if (ActuallyDoIt) { 4906 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4907 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4908 4909 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4910 ISD::SETNE); 4911 EVT CallVT = TLI.getValueType(I.getType(), true); 4912 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4913 return true; 4914 } 4915 } 4916 4917 4918 return false; 4919} 4920 4921 4922void SelectionDAGBuilder::visitCall(const CallInst &I) { 4923 // Handle inline assembly differently. 4924 if (isa<InlineAsm>(I.getCalledValue())) { 4925 visitInlineAsm(&I); 4926 return; 4927 } 4928 4929 const char *RenameFn = 0; 4930 if (Function *F = I.getCalledFunction()) { 4931 if (F->isDeclaration()) { 4932 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 4933 if (unsigned IID = II->getIntrinsicID(F)) { 4934 RenameFn = visitIntrinsicCall(I, IID); 4935 if (!RenameFn) 4936 return; 4937 } 4938 } 4939 if (unsigned IID = F->getIntrinsicID()) { 4940 RenameFn = visitIntrinsicCall(I, IID); 4941 if (!RenameFn) 4942 return; 4943 } 4944 } 4945 4946 // Check for well-known libc/libm calls. If the function is internal, it 4947 // can't be a library call. 4948 if (!F->hasLocalLinkage() && F->hasName()) { 4949 StringRef Name = F->getName(); 4950 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4951 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 4952 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4953 I.getType() == I.getArgOperand(0)->getType() && 4954 I.getType() == I.getArgOperand(1)->getType()) { 4955 SDValue LHS = getValue(I.getArgOperand(0)); 4956 SDValue RHS = getValue(I.getArgOperand(1)); 4957 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4958 LHS.getValueType(), LHS, RHS)); 4959 return; 4960 } 4961 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4962 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4963 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4964 I.getType() == I.getArgOperand(0)->getType()) { 4965 SDValue Tmp = getValue(I.getArgOperand(0)); 4966 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4967 Tmp.getValueType(), Tmp)); 4968 return; 4969 } 4970 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4971 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4972 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4973 I.getType() == I.getArgOperand(0)->getType() && 4974 I.onlyReadsMemory()) { 4975 SDValue Tmp = getValue(I.getArgOperand(0)); 4976 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4977 Tmp.getValueType(), Tmp)); 4978 return; 4979 } 4980 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4981 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4982 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4983 I.getType() == I.getArgOperand(0)->getType() && 4984 I.onlyReadsMemory()) { 4985 SDValue Tmp = getValue(I.getArgOperand(0)); 4986 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4987 Tmp.getValueType(), Tmp)); 4988 return; 4989 } 4990 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4991 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4992 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4993 I.getType() == I.getArgOperand(0)->getType() && 4994 I.onlyReadsMemory()) { 4995 SDValue Tmp = getValue(I.getArgOperand(0)); 4996 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4997 Tmp.getValueType(), Tmp)); 4998 return; 4999 } 5000 } else if (Name == "memcmp") { 5001 if (visitMemCmpCall(I)) 5002 return; 5003 } 5004 } 5005 } 5006 5007 SDValue Callee; 5008 if (!RenameFn) 5009 Callee = getValue(I.getCalledValue()); 5010 else 5011 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5012 5013 // Check if we can potentially perform a tail call. More detailed checking is 5014 // be done within LowerCallTo, after more information about the call is known. 5015 LowerCallTo(&I, Callee, I.isTailCall()); 5016} 5017 5018namespace llvm { 5019 5020/// AsmOperandInfo - This contains information for each constraint that we are 5021/// lowering. 5022class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5023 public TargetLowering::AsmOperandInfo { 5024public: 5025 /// CallOperand - If this is the result output operand or a clobber 5026 /// this is null, otherwise it is the incoming operand to the CallInst. 5027 /// This gets modified as the asm is processed. 5028 SDValue CallOperand; 5029 5030 /// AssignedRegs - If this is a register or register class operand, this 5031 /// contains the set of register corresponding to the operand. 5032 RegsForValue AssignedRegs; 5033 5034 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5035 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5036 } 5037 5038 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5039 /// busy in OutputRegs/InputRegs. 5040 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5041 std::set<unsigned> &OutputRegs, 5042 std::set<unsigned> &InputRegs, 5043 const TargetRegisterInfo &TRI) const { 5044 if (isOutReg) { 5045 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5046 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5047 } 5048 if (isInReg) { 5049 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5050 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5051 } 5052 } 5053 5054 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5055 /// corresponds to. If there is no Value* for this operand, it returns 5056 /// MVT::Other. 5057 EVT getCallOperandValEVT(LLVMContext &Context, 5058 const TargetLowering &TLI, 5059 const TargetData *TD) const { 5060 if (CallOperandVal == 0) return MVT::Other; 5061 5062 if (isa<BasicBlock>(CallOperandVal)) 5063 return TLI.getPointerTy(); 5064 5065 const llvm::Type *OpTy = CallOperandVal->getType(); 5066 5067 // If this is an indirect operand, the operand is a pointer to the 5068 // accessed type. 5069 if (isIndirect) { 5070 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5071 if (!PtrTy) 5072 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5073 OpTy = PtrTy->getElementType(); 5074 } 5075 5076 // If OpTy is not a single value, it may be a struct/union that we 5077 // can tile with integers. 5078 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5079 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5080 switch (BitSize) { 5081 default: break; 5082 case 1: 5083 case 8: 5084 case 16: 5085 case 32: 5086 case 64: 5087 case 128: 5088 OpTy = IntegerType::get(Context, BitSize); 5089 break; 5090 } 5091 } 5092 5093 return TLI.getValueType(OpTy, true); 5094 } 5095 5096private: 5097 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5098 /// specified set. 5099 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5100 const TargetRegisterInfo &TRI) { 5101 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5102 Regs.insert(Reg); 5103 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5104 for (; *Aliases; ++Aliases) 5105 Regs.insert(*Aliases); 5106 } 5107}; 5108 5109} // end llvm namespace. 5110 5111/// isAllocatableRegister - If the specified register is safe to allocate, 5112/// i.e. it isn't a stack pointer or some other special register, return the 5113/// register class for the register. Otherwise, return null. 5114static const TargetRegisterClass * 5115isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5116 const TargetLowering &TLI, 5117 const TargetRegisterInfo *TRI) { 5118 EVT FoundVT = MVT::Other; 5119 const TargetRegisterClass *FoundRC = 0; 5120 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5121 E = TRI->regclass_end(); RCI != E; ++RCI) { 5122 EVT ThisVT = MVT::Other; 5123 5124 const TargetRegisterClass *RC = *RCI; 5125 // If none of the value types for this register class are valid, we 5126 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5127 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5128 I != E; ++I) { 5129 if (TLI.isTypeLegal(*I)) { 5130 // If we have already found this register in a different register class, 5131 // choose the one with the largest VT specified. For example, on 5132 // PowerPC, we favor f64 register classes over f32. 5133 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5134 ThisVT = *I; 5135 break; 5136 } 5137 } 5138 } 5139 5140 if (ThisVT == MVT::Other) continue; 5141 5142 // NOTE: This isn't ideal. In particular, this might allocate the 5143 // frame pointer in functions that need it (due to them not being taken 5144 // out of allocation, because a variable sized allocation hasn't been seen 5145 // yet). This is a slight code pessimization, but should still work. 5146 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5147 E = RC->allocation_order_end(MF); I != E; ++I) 5148 if (*I == Reg) { 5149 // We found a matching register class. Keep looking at others in case 5150 // we find one with larger registers that this physreg is also in. 5151 FoundRC = RC; 5152 FoundVT = ThisVT; 5153 break; 5154 } 5155 } 5156 return FoundRC; 5157} 5158 5159/// GetRegistersForValue - Assign registers (virtual or physical) for the 5160/// specified operand. We prefer to assign virtual registers, to allow the 5161/// register allocator to handle the assignment process. However, if the asm 5162/// uses features that we can't model on machineinstrs, we have SDISel do the 5163/// allocation. This produces generally horrible, but correct, code. 5164/// 5165/// OpInfo describes the operand. 5166/// Input and OutputRegs are the set of already allocated physical registers. 5167/// 5168void SelectionDAGBuilder:: 5169GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5170 std::set<unsigned> &OutputRegs, 5171 std::set<unsigned> &InputRegs) { 5172 LLVMContext &Context = FuncInfo.Fn->getContext(); 5173 5174 // Compute whether this value requires an input register, an output register, 5175 // or both. 5176 bool isOutReg = false; 5177 bool isInReg = false; 5178 switch (OpInfo.Type) { 5179 case InlineAsm::isOutput: 5180 isOutReg = true; 5181 5182 // If there is an input constraint that matches this, we need to reserve 5183 // the input register so no other inputs allocate to it. 5184 isInReg = OpInfo.hasMatchingInput(); 5185 break; 5186 case InlineAsm::isInput: 5187 isInReg = true; 5188 isOutReg = false; 5189 break; 5190 case InlineAsm::isClobber: 5191 isOutReg = true; 5192 isInReg = true; 5193 break; 5194 } 5195 5196 5197 MachineFunction &MF = DAG.getMachineFunction(); 5198 SmallVector<unsigned, 4> Regs; 5199 5200 // If this is a constraint for a single physreg, or a constraint for a 5201 // register class, find it. 5202 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5203 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5204 OpInfo.ConstraintVT); 5205 5206 unsigned NumRegs = 1; 5207 if (OpInfo.ConstraintVT != MVT::Other) { 5208 // If this is a FP input in an integer register (or visa versa) insert a bit 5209 // cast of the input value. More generally, handle any case where the input 5210 // value disagrees with the register class we plan to stick this in. 5211 if (OpInfo.Type == InlineAsm::isInput && 5212 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5213 // Try to convert to the first EVT that the reg class contains. If the 5214 // types are identical size, use a bitcast to convert (e.g. two differing 5215 // vector types). 5216 EVT RegVT = *PhysReg.second->vt_begin(); 5217 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5218 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5219 RegVT, OpInfo.CallOperand); 5220 OpInfo.ConstraintVT = RegVT; 5221 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5222 // If the input is a FP value and we want it in FP registers, do a 5223 // bitcast to the corresponding integer type. This turns an f64 value 5224 // into i64, which can be passed with two i32 values on a 32-bit 5225 // machine. 5226 RegVT = EVT::getIntegerVT(Context, 5227 OpInfo.ConstraintVT.getSizeInBits()); 5228 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5229 RegVT, OpInfo.CallOperand); 5230 OpInfo.ConstraintVT = RegVT; 5231 } 5232 } 5233 5234 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5235 } 5236 5237 EVT RegVT; 5238 EVT ValueVT = OpInfo.ConstraintVT; 5239 5240 // If this is a constraint for a specific physical register, like {r17}, 5241 // assign it now. 5242 if (unsigned AssignedReg = PhysReg.first) { 5243 const TargetRegisterClass *RC = PhysReg.second; 5244 if (OpInfo.ConstraintVT == MVT::Other) 5245 ValueVT = *RC->vt_begin(); 5246 5247 // Get the actual register value type. This is important, because the user 5248 // may have asked for (e.g.) the AX register in i32 type. We need to 5249 // remember that AX is actually i16 to get the right extension. 5250 RegVT = *RC->vt_begin(); 5251 5252 // This is a explicit reference to a physical register. 5253 Regs.push_back(AssignedReg); 5254 5255 // If this is an expanded reference, add the rest of the regs to Regs. 5256 if (NumRegs != 1) { 5257 TargetRegisterClass::iterator I = RC->begin(); 5258 for (; *I != AssignedReg; ++I) 5259 assert(I != RC->end() && "Didn't find reg!"); 5260 5261 // Already added the first reg. 5262 --NumRegs; ++I; 5263 for (; NumRegs; --NumRegs, ++I) { 5264 assert(I != RC->end() && "Ran out of registers to allocate!"); 5265 Regs.push_back(*I); 5266 } 5267 } 5268 5269 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5270 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5271 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5272 return; 5273 } 5274 5275 // Otherwise, if this was a reference to an LLVM register class, create vregs 5276 // for this reference. 5277 if (const TargetRegisterClass *RC = PhysReg.second) { 5278 RegVT = *RC->vt_begin(); 5279 if (OpInfo.ConstraintVT == MVT::Other) 5280 ValueVT = RegVT; 5281 5282 // Create the appropriate number of virtual registers. 5283 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5284 for (; NumRegs; --NumRegs) 5285 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5286 5287 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5288 return; 5289 } 5290 5291 // This is a reference to a register class that doesn't directly correspond 5292 // to an LLVM register class. Allocate NumRegs consecutive, available, 5293 // registers from the class. 5294 std::vector<unsigned> RegClassRegs 5295 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5296 OpInfo.ConstraintVT); 5297 5298 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5299 unsigned NumAllocated = 0; 5300 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5301 unsigned Reg = RegClassRegs[i]; 5302 // See if this register is available. 5303 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5304 (isInReg && InputRegs.count(Reg))) { // Already used. 5305 // Make sure we find consecutive registers. 5306 NumAllocated = 0; 5307 continue; 5308 } 5309 5310 // Check to see if this register is allocatable (i.e. don't give out the 5311 // stack pointer). 5312 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5313 if (!RC) { // Couldn't allocate this register. 5314 // Reset NumAllocated to make sure we return consecutive registers. 5315 NumAllocated = 0; 5316 continue; 5317 } 5318 5319 // Okay, this register is good, we can use it. 5320 ++NumAllocated; 5321 5322 // If we allocated enough consecutive registers, succeed. 5323 if (NumAllocated == NumRegs) { 5324 unsigned RegStart = (i-NumAllocated)+1; 5325 unsigned RegEnd = i+1; 5326 // Mark all of the allocated registers used. 5327 for (unsigned i = RegStart; i != RegEnd; ++i) 5328 Regs.push_back(RegClassRegs[i]); 5329 5330 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5331 OpInfo.ConstraintVT); 5332 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5333 return; 5334 } 5335 } 5336 5337 // Otherwise, we couldn't allocate enough registers for this. 5338} 5339 5340/// visitInlineAsm - Handle a call to an InlineAsm object. 5341/// 5342void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5343 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5344 5345 /// ConstraintOperands - Information about all of the constraints. 5346 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5347 5348 std::set<unsigned> OutputRegs, InputRegs; 5349 5350 std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(CS); 5351 bool hasMemory = false; 5352 5353 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5354 unsigned ResNo = 0; // ResNo - The result number of the next output. 5355 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5356 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5357 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5358 5359 EVT OpVT = MVT::Other; 5360 5361 // Compute the value type for each operand. 5362 switch (OpInfo.Type) { 5363 case InlineAsm::isOutput: 5364 // Indirect outputs just consume an argument. 5365 if (OpInfo.isIndirect) { 5366 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5367 break; 5368 } 5369 5370 // The return value of the call is this value. As such, there is no 5371 // corresponding argument. 5372 assert(!CS.getType()->isVoidTy() && 5373 "Bad inline asm!"); 5374 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5375 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5376 } else { 5377 assert(ResNo == 0 && "Asm only has one result!"); 5378 OpVT = TLI.getValueType(CS.getType()); 5379 } 5380 ++ResNo; 5381 break; 5382 case InlineAsm::isInput: 5383 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5384 break; 5385 case InlineAsm::isClobber: 5386 // Nothing to do. 5387 break; 5388 } 5389 5390 // If this is an input or an indirect output, process the call argument. 5391 // BasicBlocks are labels, currently appearing only in asm's. 5392 if (OpInfo.CallOperandVal) { 5393 // Strip bitcasts, if any. This mostly comes up for functions. 5394 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5395 5396 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5397 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5398 } else { 5399 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5400 } 5401 5402 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5403 } 5404 5405 OpInfo.ConstraintVT = OpVT; 5406 5407 // Indirect operand accesses access memory. 5408 if (OpInfo.isIndirect) 5409 hasMemory = true; 5410 else { 5411 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5412 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5413 if (CType == TargetLowering::C_Memory) { 5414 hasMemory = true; 5415 break; 5416 } 5417 } 5418 } 5419 } 5420 5421 SDValue Chain, Flag; 5422 5423 // We won't need to flush pending loads if this asm doesn't touch 5424 // memory and is nonvolatile. 5425 if (hasMemory || IA->hasSideEffects()) 5426 Chain = getRoot(); 5427 else 5428 Chain = DAG.getRoot(); 5429 5430 // Second pass over the constraints: compute which constraint option to use 5431 // and assign registers to constraints that want a specific physreg. 5432 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5433 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5434 5435 // Compute the constraint code and ConstraintType to use. 5436 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5437 5438 // If this is a memory input, and if the operand is not indirect, do what we 5439 // need to to provide an address for the memory input. 5440 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5441 !OpInfo.isIndirect) { 5442 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5443 "Can only indirectify direct input operands!"); 5444 5445 // Memory operands really want the address of the value. If we don't have 5446 // an indirect input, put it in the constpool if we can, otherwise spill 5447 // it to a stack slot. 5448 5449 // If the operand is a float, integer, or vector constant, spill to a 5450 // constant pool entry to get its address. 5451 const Value *OpVal = OpInfo.CallOperandVal; 5452 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5453 isa<ConstantVector>(OpVal)) { 5454 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5455 TLI.getPointerTy()); 5456 } else { 5457 // Otherwise, create a stack slot and emit a store to it before the 5458 // asm. 5459 const Type *Ty = OpVal->getType(); 5460 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5461 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5462 MachineFunction &MF = DAG.getMachineFunction(); 5463 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5464 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5465 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5466 OpInfo.CallOperand, StackSlot, 5467 MachinePointerInfo::getFixedStack(SSFI), 5468 false, false, 0); 5469 OpInfo.CallOperand = StackSlot; 5470 } 5471 5472 // There is no longer a Value* corresponding to this operand. 5473 OpInfo.CallOperandVal = 0; 5474 5475 // It is now an indirect operand. 5476 OpInfo.isIndirect = true; 5477 } 5478 5479 // If this constraint is for a specific register, allocate it before 5480 // anything else. 5481 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5482 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5483 } 5484 5485 // Second pass - Loop over all of the operands, assigning virtual or physregs 5486 // to register class operands. 5487 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5488 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5489 5490 // C_Register operands have already been allocated, Other/Memory don't need 5491 // to be. 5492 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5493 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5494 } 5495 5496 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5497 std::vector<SDValue> AsmNodeOperands; 5498 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5499 AsmNodeOperands.push_back( 5500 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5501 TLI.getPointerTy())); 5502 5503 // If we have a !srcloc metadata node associated with it, we want to attach 5504 // this to the ultimately generated inline asm machineinstr. To do this, we 5505 // pass in the third operand as this (potentially null) inline asm MDNode. 5506 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5507 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5508 5509 // Remember the AlignStack bit as operand 3. 5510 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5511 MVT::i1)); 5512 5513 // Loop over all of the inputs, copying the operand values into the 5514 // appropriate registers and processing the output regs. 5515 RegsForValue RetValRegs; 5516 5517 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5518 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5519 5520 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5521 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5522 5523 switch (OpInfo.Type) { 5524 case InlineAsm::isOutput: { 5525 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5526 OpInfo.ConstraintType != TargetLowering::C_Register) { 5527 // Memory output, or 'other' output (e.g. 'X' constraint). 5528 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5529 5530 // Add information to the INLINEASM node to know about this output. 5531 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5532 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5533 TLI.getPointerTy())); 5534 AsmNodeOperands.push_back(OpInfo.CallOperand); 5535 break; 5536 } 5537 5538 // Otherwise, this is a register or register class output. 5539 5540 // Copy the output from the appropriate register. Find a register that 5541 // we can use. 5542 if (OpInfo.AssignedRegs.Regs.empty()) 5543 report_fatal_error("Couldn't allocate output reg for constraint '" + 5544 Twine(OpInfo.ConstraintCode) + "'!"); 5545 5546 // If this is an indirect operand, store through the pointer after the 5547 // asm. 5548 if (OpInfo.isIndirect) { 5549 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5550 OpInfo.CallOperandVal)); 5551 } else { 5552 // This is the result value of the call. 5553 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5554 // Concatenate this output onto the outputs list. 5555 RetValRegs.append(OpInfo.AssignedRegs); 5556 } 5557 5558 // Add information to the INLINEASM node to know that this register is 5559 // set. 5560 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5561 InlineAsm::Kind_RegDefEarlyClobber : 5562 InlineAsm::Kind_RegDef, 5563 false, 5564 0, 5565 DAG, 5566 AsmNodeOperands); 5567 break; 5568 } 5569 case InlineAsm::isInput: { 5570 SDValue InOperandVal = OpInfo.CallOperand; 5571 5572 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5573 // If this is required to match an output register we have already set, 5574 // just use its register. 5575 unsigned OperandNo = OpInfo.getMatchedOperand(); 5576 5577 // Scan until we find the definition we already emitted of this operand. 5578 // When we find it, create a RegsForValue operand. 5579 unsigned CurOp = InlineAsm::Op_FirstOperand; 5580 for (; OperandNo; --OperandNo) { 5581 // Advance to the next operand. 5582 unsigned OpFlag = 5583 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5584 assert((InlineAsm::isRegDefKind(OpFlag) || 5585 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5586 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5587 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5588 } 5589 5590 unsigned OpFlag = 5591 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5592 if (InlineAsm::isRegDefKind(OpFlag) || 5593 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5594 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5595 if (OpInfo.isIndirect) { 5596 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5597 LLVMContext &Ctx = *DAG.getContext(); 5598 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5599 " don't know how to handle tied " 5600 "indirect register inputs"); 5601 } 5602 5603 RegsForValue MatchedRegs; 5604 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5605 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5606 MatchedRegs.RegVTs.push_back(RegVT); 5607 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5608 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5609 i != e; ++i) 5610 MatchedRegs.Regs.push_back 5611 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5612 5613 // Use the produced MatchedRegs object to 5614 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5615 Chain, &Flag); 5616 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5617 true, OpInfo.getMatchedOperand(), 5618 DAG, AsmNodeOperands); 5619 break; 5620 } 5621 5622 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5623 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5624 "Unexpected number of operands"); 5625 // Add information to the INLINEASM node to know about this input. 5626 // See InlineAsm.h isUseOperandTiedToDef. 5627 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5628 OpInfo.getMatchedOperand()); 5629 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5630 TLI.getPointerTy())); 5631 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5632 break; 5633 } 5634 5635 // Treat indirect 'X' constraint as memory. 5636 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5637 OpInfo.isIndirect) 5638 OpInfo.ConstraintType = TargetLowering::C_Memory; 5639 5640 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5641 std::vector<SDValue> Ops; 5642 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5643 Ops, DAG); 5644 if (Ops.empty()) 5645 report_fatal_error("Invalid operand for inline asm constraint '" + 5646 Twine(OpInfo.ConstraintCode) + "'!"); 5647 5648 // Add information to the INLINEASM node to know about this input. 5649 unsigned ResOpType = 5650 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5651 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5652 TLI.getPointerTy())); 5653 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5654 break; 5655 } 5656 5657 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5658 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5659 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5660 "Memory operands expect pointer values"); 5661 5662 // Add information to the INLINEASM node to know about this input. 5663 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5664 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5665 TLI.getPointerTy())); 5666 AsmNodeOperands.push_back(InOperandVal); 5667 break; 5668 } 5669 5670 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5671 OpInfo.ConstraintType == TargetLowering::C_Register) && 5672 "Unknown constraint type!"); 5673 assert(!OpInfo.isIndirect && 5674 "Don't know how to handle indirect register inputs yet!"); 5675 5676 // Copy the input into the appropriate registers. 5677 if (OpInfo.AssignedRegs.Regs.empty() || 5678 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5679 report_fatal_error("Couldn't allocate input reg for constraint '" + 5680 Twine(OpInfo.ConstraintCode) + "'!"); 5681 5682 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5683 Chain, &Flag); 5684 5685 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5686 DAG, AsmNodeOperands); 5687 break; 5688 } 5689 case InlineAsm::isClobber: { 5690 // Add the clobbered value to the operand list, so that the register 5691 // allocator is aware that the physreg got clobbered. 5692 if (!OpInfo.AssignedRegs.Regs.empty()) 5693 OpInfo.AssignedRegs.AddInlineAsmOperands( 5694 InlineAsm::Kind_RegDefEarlyClobber, 5695 false, 0, DAG, 5696 AsmNodeOperands); 5697 break; 5698 } 5699 } 5700 } 5701 5702 // Finish up input operands. Set the input chain and add the flag last. 5703 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5704 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5705 5706 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5707 DAG.getVTList(MVT::Other, MVT::Flag), 5708 &AsmNodeOperands[0], AsmNodeOperands.size()); 5709 Flag = Chain.getValue(1); 5710 5711 // If this asm returns a register value, copy the result from that register 5712 // and set it as the value of the call. 5713 if (!RetValRegs.Regs.empty()) { 5714 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5715 Chain, &Flag); 5716 5717 // FIXME: Why don't we do this for inline asms with MRVs? 5718 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5719 EVT ResultType = TLI.getValueType(CS.getType()); 5720 5721 // If any of the results of the inline asm is a vector, it may have the 5722 // wrong width/num elts. This can happen for register classes that can 5723 // contain multiple different value types. The preg or vreg allocated may 5724 // not have the same VT as was expected. Convert it to the right type 5725 // with bit_convert. 5726 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5727 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5728 ResultType, Val); 5729 5730 } else if (ResultType != Val.getValueType() && 5731 ResultType.isInteger() && Val.getValueType().isInteger()) { 5732 // If a result value was tied to an input value, the computed result may 5733 // have a wider width than the expected result. Extract the relevant 5734 // portion. 5735 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5736 } 5737 5738 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5739 } 5740 5741 setValue(CS.getInstruction(), Val); 5742 // Don't need to use this as a chain in this case. 5743 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5744 return; 5745 } 5746 5747 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5748 5749 // Process indirect outputs, first output all of the flagged copies out of 5750 // physregs. 5751 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5752 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5753 const Value *Ptr = IndirectStoresToEmit[i].second; 5754 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5755 Chain, &Flag); 5756 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5757 } 5758 5759 // Emit the non-flagged stores from the physregs. 5760 SmallVector<SDValue, 8> OutChains; 5761 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5762 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5763 StoresToEmit[i].first, 5764 getValue(StoresToEmit[i].second), 5765 MachinePointerInfo(StoresToEmit[i].second), 5766 false, false, 0); 5767 OutChains.push_back(Val); 5768 } 5769 5770 if (!OutChains.empty()) 5771 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5772 &OutChains[0], OutChains.size()); 5773 5774 DAG.setRoot(Chain); 5775} 5776 5777void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5778 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5779 MVT::Other, getRoot(), 5780 getValue(I.getArgOperand(0)), 5781 DAG.getSrcValue(I.getArgOperand(0)))); 5782} 5783 5784void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5785 const TargetData &TD = *TLI.getTargetData(); 5786 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5787 getRoot(), getValue(I.getOperand(0)), 5788 DAG.getSrcValue(I.getOperand(0)), 5789 TD.getABITypeAlignment(I.getType())); 5790 setValue(&I, V); 5791 DAG.setRoot(V.getValue(1)); 5792} 5793 5794void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5795 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5796 MVT::Other, getRoot(), 5797 getValue(I.getArgOperand(0)), 5798 DAG.getSrcValue(I.getArgOperand(0)))); 5799} 5800 5801void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5802 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5803 MVT::Other, getRoot(), 5804 getValue(I.getArgOperand(0)), 5805 getValue(I.getArgOperand(1)), 5806 DAG.getSrcValue(I.getArgOperand(0)), 5807 DAG.getSrcValue(I.getArgOperand(1)))); 5808} 5809 5810/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5811/// implementation, which just calls LowerCall. 5812/// FIXME: When all targets are 5813/// migrated to using LowerCall, this hook should be integrated into SDISel. 5814std::pair<SDValue, SDValue> 5815TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5816 bool RetSExt, bool RetZExt, bool isVarArg, 5817 bool isInreg, unsigned NumFixedArgs, 5818 CallingConv::ID CallConv, bool isTailCall, 5819 bool isReturnValueUsed, 5820 SDValue Callee, 5821 ArgListTy &Args, SelectionDAG &DAG, 5822 DebugLoc dl) const { 5823 // Handle all of the outgoing arguments. 5824 SmallVector<ISD::OutputArg, 32> Outs; 5825 SmallVector<SDValue, 32> OutVals; 5826 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5827 SmallVector<EVT, 4> ValueVTs; 5828 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5829 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5830 Value != NumValues; ++Value) { 5831 EVT VT = ValueVTs[Value]; 5832 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5833 SDValue Op = SDValue(Args[i].Node.getNode(), 5834 Args[i].Node.getResNo() + Value); 5835 ISD::ArgFlagsTy Flags; 5836 unsigned OriginalAlignment = 5837 getTargetData()->getABITypeAlignment(ArgTy); 5838 5839 if (Args[i].isZExt) 5840 Flags.setZExt(); 5841 if (Args[i].isSExt) 5842 Flags.setSExt(); 5843 if (Args[i].isInReg) 5844 Flags.setInReg(); 5845 if (Args[i].isSRet) 5846 Flags.setSRet(); 5847 if (Args[i].isByVal) { 5848 Flags.setByVal(); 5849 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5850 const Type *ElementTy = Ty->getElementType(); 5851 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5852 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5853 // For ByVal, alignment should come from FE. BE will guess if this 5854 // info is not there but there are cases it cannot get right. 5855 if (Args[i].Alignment) 5856 FrameAlign = Args[i].Alignment; 5857 Flags.setByValAlign(FrameAlign); 5858 Flags.setByValSize(FrameSize); 5859 } 5860 if (Args[i].isNest) 5861 Flags.setNest(); 5862 Flags.setOrigAlign(OriginalAlignment); 5863 5864 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5865 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5866 SmallVector<SDValue, 4> Parts(NumParts); 5867 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5868 5869 if (Args[i].isSExt) 5870 ExtendKind = ISD::SIGN_EXTEND; 5871 else if (Args[i].isZExt) 5872 ExtendKind = ISD::ZERO_EXTEND; 5873 5874 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5875 PartVT, ExtendKind); 5876 5877 for (unsigned j = 0; j != NumParts; ++j) { 5878 // if it isn't first piece, alignment must be 1 5879 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 5880 i < NumFixedArgs); 5881 if (NumParts > 1 && j == 0) 5882 MyFlags.Flags.setSplit(); 5883 else if (j != 0) 5884 MyFlags.Flags.setOrigAlign(1); 5885 5886 Outs.push_back(MyFlags); 5887 OutVals.push_back(Parts[j]); 5888 } 5889 } 5890 } 5891 5892 // Handle the incoming return values from the call. 5893 SmallVector<ISD::InputArg, 32> Ins; 5894 SmallVector<EVT, 4> RetTys; 5895 ComputeValueVTs(*this, RetTy, RetTys); 5896 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5897 EVT VT = RetTys[I]; 5898 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5899 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5900 for (unsigned i = 0; i != NumRegs; ++i) { 5901 ISD::InputArg MyFlags; 5902 MyFlags.VT = RegisterVT; 5903 MyFlags.Used = isReturnValueUsed; 5904 if (RetSExt) 5905 MyFlags.Flags.setSExt(); 5906 if (RetZExt) 5907 MyFlags.Flags.setZExt(); 5908 if (isInreg) 5909 MyFlags.Flags.setInReg(); 5910 Ins.push_back(MyFlags); 5911 } 5912 } 5913 5914 SmallVector<SDValue, 4> InVals; 5915 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5916 Outs, OutVals, Ins, dl, DAG, InVals); 5917 5918 // Verify that the target's LowerCall behaved as expected. 5919 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5920 "LowerCall didn't return a valid chain!"); 5921 assert((!isTailCall || InVals.empty()) && 5922 "LowerCall emitted a return value for a tail call!"); 5923 assert((isTailCall || InVals.size() == Ins.size()) && 5924 "LowerCall didn't emit the correct number of values!"); 5925 5926 // For a tail call, the return value is merely live-out and there aren't 5927 // any nodes in the DAG representing it. Return a special value to 5928 // indicate that a tail call has been emitted and no more Instructions 5929 // should be processed in the current block. 5930 if (isTailCall) { 5931 DAG.setRoot(Chain); 5932 return std::make_pair(SDValue(), SDValue()); 5933 } 5934 5935 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5936 assert(InVals[i].getNode() && 5937 "LowerCall emitted a null value!"); 5938 assert(Ins[i].VT == InVals[i].getValueType() && 5939 "LowerCall emitted a value with the wrong type!"); 5940 }); 5941 5942 // Collect the legal value parts into potentially illegal values 5943 // that correspond to the original function's return values. 5944 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5945 if (RetSExt) 5946 AssertOp = ISD::AssertSext; 5947 else if (RetZExt) 5948 AssertOp = ISD::AssertZext; 5949 SmallVector<SDValue, 4> ReturnValues; 5950 unsigned CurReg = 0; 5951 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5952 EVT VT = RetTys[I]; 5953 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5954 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5955 5956 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5957 NumRegs, RegisterVT, VT, 5958 AssertOp)); 5959 CurReg += NumRegs; 5960 } 5961 5962 // For a function returning void, there is no return value. We can't create 5963 // such a node, so we just return a null return value in that case. In 5964 // that case, nothing will actualy look at the value. 5965 if (ReturnValues.empty()) 5966 return std::make_pair(SDValue(), Chain); 5967 5968 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5969 DAG.getVTList(&RetTys[0], RetTys.size()), 5970 &ReturnValues[0], ReturnValues.size()); 5971 return std::make_pair(Res, Chain); 5972} 5973 5974void TargetLowering::LowerOperationWrapper(SDNode *N, 5975 SmallVectorImpl<SDValue> &Results, 5976 SelectionDAG &DAG) const { 5977 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5978 if (Res.getNode()) 5979 Results.push_back(Res); 5980} 5981 5982SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5983 llvm_unreachable("LowerOperation not implemented for this target!"); 5984 return SDValue(); 5985} 5986 5987void 5988SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 5989 SDValue Op = getNonRegisterValue(V); 5990 assert((Op.getOpcode() != ISD::CopyFromReg || 5991 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5992 "Copy from a reg to the same reg!"); 5993 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5994 5995 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5996 SDValue Chain = DAG.getEntryNode(); 5997 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5998 PendingExports.push_back(Chain); 5999} 6000 6001#include "llvm/CodeGen/SelectionDAGISel.h" 6002 6003void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6004 // If this is the entry block, emit arguments. 6005 const Function &F = *LLVMBB->getParent(); 6006 SelectionDAG &DAG = SDB->DAG; 6007 DebugLoc dl = SDB->getCurDebugLoc(); 6008 const TargetData *TD = TLI.getTargetData(); 6009 SmallVector<ISD::InputArg, 16> Ins; 6010 6011 // Check whether the function can return without sret-demotion. 6012 SmallVector<ISD::OutputArg, 4> Outs; 6013 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6014 Outs, TLI); 6015 6016 if (!FuncInfo->CanLowerReturn) { 6017 // Put in an sret pointer parameter before all the other parameters. 6018 SmallVector<EVT, 1> ValueVTs; 6019 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6020 6021 // NOTE: Assuming that a pointer will never break down to more than one VT 6022 // or one register. 6023 ISD::ArgFlagsTy Flags; 6024 Flags.setSRet(); 6025 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6026 ISD::InputArg RetArg(Flags, RegisterVT, true); 6027 Ins.push_back(RetArg); 6028 } 6029 6030 // Set up the incoming argument description vector. 6031 unsigned Idx = 1; 6032 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6033 I != E; ++I, ++Idx) { 6034 SmallVector<EVT, 4> ValueVTs; 6035 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6036 bool isArgValueUsed = !I->use_empty(); 6037 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6038 Value != NumValues; ++Value) { 6039 EVT VT = ValueVTs[Value]; 6040 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6041 ISD::ArgFlagsTy Flags; 6042 unsigned OriginalAlignment = 6043 TD->getABITypeAlignment(ArgTy); 6044 6045 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6046 Flags.setZExt(); 6047 if (F.paramHasAttr(Idx, Attribute::SExt)) 6048 Flags.setSExt(); 6049 if (F.paramHasAttr(Idx, Attribute::InReg)) 6050 Flags.setInReg(); 6051 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6052 Flags.setSRet(); 6053 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6054 Flags.setByVal(); 6055 const PointerType *Ty = cast<PointerType>(I->getType()); 6056 const Type *ElementTy = Ty->getElementType(); 6057 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6058 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6059 // For ByVal, alignment should be passed from FE. BE will guess if 6060 // this info is not there but there are cases it cannot get right. 6061 if (F.getParamAlignment(Idx)) 6062 FrameAlign = F.getParamAlignment(Idx); 6063 Flags.setByValAlign(FrameAlign); 6064 Flags.setByValSize(FrameSize); 6065 } 6066 if (F.paramHasAttr(Idx, Attribute::Nest)) 6067 Flags.setNest(); 6068 Flags.setOrigAlign(OriginalAlignment); 6069 6070 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6071 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6072 for (unsigned i = 0; i != NumRegs; ++i) { 6073 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6074 if (NumRegs > 1 && i == 0) 6075 MyFlags.Flags.setSplit(); 6076 // if it isn't first piece, alignment must be 1 6077 else if (i > 0) 6078 MyFlags.Flags.setOrigAlign(1); 6079 Ins.push_back(MyFlags); 6080 } 6081 } 6082 } 6083 6084 // Call the target to set up the argument values. 6085 SmallVector<SDValue, 8> InVals; 6086 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6087 F.isVarArg(), Ins, 6088 dl, DAG, InVals); 6089 6090 // Verify that the target's LowerFormalArguments behaved as expected. 6091 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6092 "LowerFormalArguments didn't return a valid chain!"); 6093 assert(InVals.size() == Ins.size() && 6094 "LowerFormalArguments didn't emit the correct number of values!"); 6095 DEBUG({ 6096 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6097 assert(InVals[i].getNode() && 6098 "LowerFormalArguments emitted a null value!"); 6099 assert(Ins[i].VT == InVals[i].getValueType() && 6100 "LowerFormalArguments emitted a value with the wrong type!"); 6101 } 6102 }); 6103 6104 // Update the DAG with the new chain value resulting from argument lowering. 6105 DAG.setRoot(NewRoot); 6106 6107 // Set up the argument values. 6108 unsigned i = 0; 6109 Idx = 1; 6110 if (!FuncInfo->CanLowerReturn) { 6111 // Create a virtual register for the sret pointer, and put in a copy 6112 // from the sret argument into it. 6113 SmallVector<EVT, 1> ValueVTs; 6114 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6115 EVT VT = ValueVTs[0]; 6116 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6117 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6118 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6119 RegVT, VT, AssertOp); 6120 6121 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6122 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6123 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6124 FuncInfo->DemoteRegister = SRetReg; 6125 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6126 SRetReg, ArgValue); 6127 DAG.setRoot(NewRoot); 6128 6129 // i indexes lowered arguments. Bump it past the hidden sret argument. 6130 // Idx indexes LLVM arguments. Don't touch it. 6131 ++i; 6132 } 6133 6134 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6135 ++I, ++Idx) { 6136 SmallVector<SDValue, 4> ArgValues; 6137 SmallVector<EVT, 4> ValueVTs; 6138 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6139 unsigned NumValues = ValueVTs.size(); 6140 6141 // If this argument is unused then remember its value. It is used to generate 6142 // debugging information. 6143 if (I->use_empty() && NumValues) 6144 SDB->setUnusedArgValue(I, InVals[i]); 6145 6146 for (unsigned Value = 0; Value != NumValues; ++Value) { 6147 EVT VT = ValueVTs[Value]; 6148 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6149 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6150 6151 if (!I->use_empty()) { 6152 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6153 if (F.paramHasAttr(Idx, Attribute::SExt)) 6154 AssertOp = ISD::AssertSext; 6155 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6156 AssertOp = ISD::AssertZext; 6157 6158 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6159 NumParts, PartVT, VT, 6160 AssertOp)); 6161 } 6162 6163 i += NumParts; 6164 } 6165 6166 // Note down frame index for byval arguments. 6167 if (I->hasByValAttr() && !ArgValues.empty()) 6168 if (FrameIndexSDNode *FI = 6169 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6170 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6171 6172 if (!I->use_empty()) { 6173 SDValue Res; 6174 if (!ArgValues.empty()) 6175 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6176 SDB->getCurDebugLoc()); 6177 SDB->setValue(I, Res); 6178 6179 // If this argument is live outside of the entry block, insert a copy from 6180 // whereever we got it to the vreg that other BB's will reference it as. 6181 SDB->CopyToExportRegsIfNeeded(I); 6182 } 6183 } 6184 6185 assert(i == InVals.size() && "Argument register count mismatch!"); 6186 6187 // Finally, if the target has anything special to do, allow it to do so. 6188 // FIXME: this should insert code into the DAG! 6189 EmitFunctionEntryCode(); 6190} 6191 6192/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6193/// ensure constants are generated when needed. Remember the virtual registers 6194/// that need to be added to the Machine PHI nodes as input. We cannot just 6195/// directly add them, because expansion might result in multiple MBB's for one 6196/// BB. As such, the start of the BB might correspond to a different MBB than 6197/// the end. 6198/// 6199void 6200SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6201 const TerminatorInst *TI = LLVMBB->getTerminator(); 6202 6203 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6204 6205 // Check successor nodes' PHI nodes that expect a constant to be available 6206 // from this block. 6207 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6208 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6209 if (!isa<PHINode>(SuccBB->begin())) continue; 6210 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6211 6212 // If this terminator has multiple identical successors (common for 6213 // switches), only handle each succ once. 6214 if (!SuccsHandled.insert(SuccMBB)) continue; 6215 6216 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6217 6218 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6219 // nodes and Machine PHI nodes, but the incoming operands have not been 6220 // emitted yet. 6221 for (BasicBlock::const_iterator I = SuccBB->begin(); 6222 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6223 // Ignore dead phi's. 6224 if (PN->use_empty()) continue; 6225 6226 unsigned Reg; 6227 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6228 6229 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6230 unsigned &RegOut = ConstantsOut[C]; 6231 if (RegOut == 0) { 6232 RegOut = FuncInfo.CreateRegs(C->getType()); 6233 CopyValueToVirtualRegister(C, RegOut); 6234 } 6235 Reg = RegOut; 6236 } else { 6237 DenseMap<const Value *, unsigned>::iterator I = 6238 FuncInfo.ValueMap.find(PHIOp); 6239 if (I != FuncInfo.ValueMap.end()) 6240 Reg = I->second; 6241 else { 6242 assert(isa<AllocaInst>(PHIOp) && 6243 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6244 "Didn't codegen value into a register!??"); 6245 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6246 CopyValueToVirtualRegister(PHIOp, Reg); 6247 } 6248 } 6249 6250 // Remember that this register needs to added to the machine PHI node as 6251 // the input for this MBB. 6252 SmallVector<EVT, 4> ValueVTs; 6253 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6254 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6255 EVT VT = ValueVTs[vti]; 6256 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6257 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6258 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6259 Reg += NumRegisters; 6260 } 6261 } 6262 } 6263 ConstantsOut.clear(); 6264} 6265