SelectionDAGBuilder.cpp revision 462f6b57b6276502e1279d0e508c0b9fc24feb50
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73/// getCopyFromParts - Create a value that contains the specified legal parts 74/// combined into the value they represent. If the parts combine to a type 75/// larger then ValueVT then AssertOp can be used to specify whether the extra 76/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 77/// (ISD::AssertSext). 78static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, 79 const SDValue *Parts, 80 unsigned NumParts, EVT PartVT, EVT ValueVT, 81 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 82 assert(NumParts > 0 && "No parts to assemble!"); 83 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 84 SDValue Val = Parts[0]; 85 86 if (NumParts > 1) { 87 // Assemble the value from multiple parts. 88 if (!ValueVT.isVector() && ValueVT.isInteger()) { 89 unsigned PartBits = PartVT.getSizeInBits(); 90 unsigned ValueBits = ValueVT.getSizeInBits(); 91 92 // Assemble the power of 2 part. 93 unsigned RoundParts = NumParts & (NumParts - 1) ? 94 1 << Log2_32(NumParts) : NumParts; 95 unsigned RoundBits = PartBits * RoundParts; 96 EVT RoundVT = RoundBits == ValueBits ? 97 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 98 SDValue Lo, Hi; 99 100 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 101 102 if (RoundParts > 2) { 103 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2, 104 PartVT, HalfVT); 105 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2, 106 RoundParts / 2, PartVT, HalfVT); 107 } else { 108 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); 109 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); 110 } 111 112 if (TLI.isBigEndian()) 113 std::swap(Lo, Hi); 114 115 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); 116 117 if (RoundParts < NumParts) { 118 // Assemble the trailing non-power-of-2 part. 119 unsigned OddParts = NumParts - RoundParts; 120 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 121 Hi = getCopyFromParts(DAG, dl, 122 Parts + RoundParts, OddParts, PartVT, OddVT); 123 124 // Combine the round and odd parts. 125 Lo = Val; 126 if (TLI.isBigEndian()) 127 std::swap(Lo, Hi); 128 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 129 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); 130 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, 131 DAG.getConstant(Lo.getValueType().getSizeInBits(), 132 TLI.getPointerTy())); 133 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); 134 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); 135 } 136 } else if (ValueVT.isVector()) { 137 // Handle a multi-element vector. 138 EVT IntermediateVT, RegisterVT; 139 unsigned NumIntermediates; 140 unsigned NumRegs = 141 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 142 NumIntermediates, RegisterVT); 143 assert(NumRegs == NumParts 144 && "Part count doesn't match vector breakdown!"); 145 NumParts = NumRegs; // Silence a compiler warning. 146 assert(RegisterVT == PartVT 147 && "Part type doesn't match vector breakdown!"); 148 assert(RegisterVT == Parts[0].getValueType() && 149 "Part type doesn't match part!"); 150 151 // Assemble the parts into intermediate operands. 152 SmallVector<SDValue, 8> Ops(NumIntermediates); 153 if (NumIntermediates == NumParts) { 154 // If the register was not expanded, truncate or copy the value, 155 // as appropriate. 156 for (unsigned i = 0; i != NumParts; ++i) 157 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, 158 PartVT, IntermediateVT); 159 } else if (NumParts > 0) { 160 // If the intermediate type was expanded, build the intermediate 161 // operands from the parts. 162 assert(NumParts % NumIntermediates == 0 && 163 "Must expand into a divisible number of parts!"); 164 unsigned Factor = NumParts / NumIntermediates; 165 for (unsigned i = 0; i != NumIntermediates; ++i) 166 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, 167 PartVT, IntermediateVT); 168 } 169 170 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 171 // intermediate operands. 172 Val = DAG.getNode(IntermediateVT.isVector() ? 173 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, 174 ValueVT, &Ops[0], NumIntermediates); 175 } else if (PartVT.isFloatingPoint()) { 176 // FP split into multiple FP parts (for ppcf128) 177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 178 "Unexpected split"); 179 SDValue Lo, Hi; 180 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]); 181 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]); 182 if (TLI.isBigEndian()) 183 std::swap(Lo, Hi); 184 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi); 185 } else { 186 // FP split into integer parts (soft fp) 187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 188 !PartVT.isVector() && "Unexpected split"); 189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 190 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT); 191 } 192 } 193 194 // There is now one part, held in Val. Correct it to match ValueVT. 195 PartVT = Val.getValueType(); 196 197 if (PartVT == ValueVT) 198 return Val; 199 200 if (PartVT.isVector()) { 201 assert(ValueVT.isVector() && "Unknown vector conversion!"); 202 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 203 } 204 205 if (ValueVT.isVector()) { 206 assert(ValueVT.getVectorElementType() == PartVT && 207 ValueVT.getVectorNumElements() == 1 && 208 "Only trivial scalar-to-vector conversions should get here!"); 209 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); 210 } 211 212 if (PartVT.isInteger() && 213 ValueVT.isInteger()) { 214 if (ValueVT.bitsLT(PartVT)) { 215 // For a truncate, see if we have any information to 216 // indicate whether the truncated bits will always be 217 // zero or sign-extension. 218 if (AssertOp != ISD::DELETED_NODE) 219 Val = DAG.getNode(AssertOp, dl, PartVT, Val, 220 DAG.getValueType(ValueVT)); 221 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 222 } else { 223 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); 224 } 225 } 226 227 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 228 if (ValueVT.bitsLT(Val.getValueType())) { 229 // FP_ROUND's are always exact here. 230 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, 231 DAG.getIntPtrConstant(1)); 232 } 233 234 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); 235 } 236 237 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 238 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 239 240 llvm_unreachable("Unknown mismatch!"); 241 return SDValue(); 242} 243 244/// getCopyToParts - Create a series of nodes that contain the specified value 245/// split into legal parts. If the parts contain more bits than Val, then, for 246/// integers, ExtendKind can be used to specify how to generate the extra bits. 247static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, 248 SDValue Val, SDValue *Parts, unsigned NumParts, 249 EVT PartVT, 250 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 251 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 252 EVT PtrVT = TLI.getPointerTy(); 253 EVT ValueVT = Val.getValueType(); 254 unsigned PartBits = PartVT.getSizeInBits(); 255 unsigned OrigNumParts = NumParts; 256 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 257 258 if (!NumParts) 259 return; 260 261 if (!ValueVT.isVector()) { 262 if (PartVT == ValueVT) { 263 assert(NumParts == 1 && "No-op copy with multiple parts!"); 264 Parts[0] = Val; 265 return; 266 } 267 268 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 269 // If the parts cover more bits than the value has, promote the value. 270 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 271 assert(NumParts == 1 && "Do not know what to promote to!"); 272 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); 273 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 274 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 275 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); 276 } else { 277 llvm_unreachable("Unknown mismatch!"); 278 } 279 } else if (PartBits == ValueVT.getSizeInBits()) { 280 // Different types of the same size. 281 assert(NumParts == 1 && PartVT != ValueVT); 282 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 283 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 284 // If the parts cover less bits than value has, truncate the value. 285 if (PartVT.isInteger() && ValueVT.isInteger()) { 286 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 287 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 288 } else { 289 llvm_unreachable("Unknown mismatch!"); 290 } 291 } 292 293 // The value may have changed - recompute ValueVT. 294 ValueVT = Val.getValueType(); 295 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 296 "Failed to tile the value with PartVT!"); 297 298 if (NumParts == 1) { 299 assert(PartVT == ValueVT && "Type conversion failed!"); 300 Parts[0] = Val; 301 return; 302 } 303 304 // Expand the value into multiple parts. 305 if (NumParts & (NumParts - 1)) { 306 // The number of parts is not a power of 2. Split off and copy the tail. 307 assert(PartVT.isInteger() && ValueVT.isInteger() && 308 "Do not know what to expand to!"); 309 unsigned RoundParts = 1 << Log2_32(NumParts); 310 unsigned RoundBits = RoundParts * PartBits; 311 unsigned OddParts = NumParts - RoundParts; 312 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, 313 DAG.getConstant(RoundBits, 314 TLI.getPointerTy())); 315 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, 316 OddParts, PartVT); 317 318 if (TLI.isBigEndian()) 319 // The odd parts were reversed by getCopyToParts - unreverse them. 320 std::reverse(Parts + RoundParts, Parts + NumParts); 321 322 NumParts = RoundParts; 323 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 324 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 325 } 326 327 // The number of parts is a power of 2. Repeatedly bisect the value using 328 // EXTRACT_ELEMENT. 329 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, 330 EVT::getIntegerVT(*DAG.getContext(), 331 ValueVT.getSizeInBits()), 332 Val); 333 334 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 335 for (unsigned i = 0; i < NumParts; i += StepSize) { 336 unsigned ThisBits = StepSize * PartBits / 2; 337 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 338 SDValue &Part0 = Parts[i]; 339 SDValue &Part1 = Parts[i+StepSize/2]; 340 341 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 342 ThisVT, Part0, 343 DAG.getConstant(1, PtrVT)); 344 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 345 ThisVT, Part0, 346 DAG.getConstant(0, PtrVT)); 347 348 if (ThisBits == PartBits && ThisVT != PartVT) { 349 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, 350 PartVT, Part0); 351 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, 352 PartVT, Part1); 353 } 354 } 355 } 356 357 if (TLI.isBigEndian()) 358 std::reverse(Parts, Parts + OrigNumParts); 359 360 return; 361 } 362 363 // Vector ValueVT. 364 if (NumParts == 1) { 365 if (PartVT != ValueVT) { 366 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 367 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 368 } else { 369 assert(ValueVT.getVectorElementType() == PartVT && 370 ValueVT.getVectorNumElements() == 1 && 371 "Only trivial vector-to-scalar conversions should get here!"); 372 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 373 PartVT, Val, 374 DAG.getConstant(0, PtrVT)); 375 } 376 } 377 378 Parts[0] = Val; 379 return; 380 } 381 382 // Handle a multi-element vector. 383 EVT IntermediateVT, RegisterVT; 384 unsigned NumIntermediates; 385 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 386 IntermediateVT, NumIntermediates, RegisterVT); 387 unsigned NumElements = ValueVT.getVectorNumElements(); 388 389 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 390 NumParts = NumRegs; // Silence a compiler warning. 391 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 392 393 // Split the vector into intermediate operands. 394 SmallVector<SDValue, 8> Ops(NumIntermediates); 395 for (unsigned i = 0; i != NumIntermediates; ++i) { 396 if (IntermediateVT.isVector()) 397 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 398 IntermediateVT, Val, 399 DAG.getConstant(i * (NumElements / NumIntermediates), 400 PtrVT)); 401 else 402 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 403 IntermediateVT, Val, 404 DAG.getConstant(i, PtrVT)); 405 } 406 407 // Split the intermediate operands into legal parts. 408 if (NumParts == NumIntermediates) { 409 // If the register was not expanded, promote or copy the value, 410 // as appropriate. 411 for (unsigned i = 0; i != NumParts; ++i) 412 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); 413 } else if (NumParts > 0) { 414 // If the intermediate type was expanded, split each the value into 415 // legal parts. 416 assert(NumParts % NumIntermediates == 0 && 417 "Must expand into a divisible number of parts!"); 418 unsigned Factor = NumParts / NumIntermediates; 419 for (unsigned i = 0; i != NumIntermediates; ++i) 420 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT); 421 } 422} 423 424namespace { 425 /// RegsForValue - This struct represents the registers (physical or virtual) 426 /// that a particular set of values is assigned, and the type information 427 /// about the value. The most common situation is to represent one value at a 428 /// time, but struct or array values are handled element-wise as multiple 429 /// values. The splitting of aggregates is performed recursively, so that we 430 /// never have aggregate-typed registers. The values at this point do not 431 /// necessarily have legal types, so each value may require one or more 432 /// registers of some legal type. 433 /// 434 struct RegsForValue { 435 /// ValueVTs - The value types of the values, which may not be legal, and 436 /// may need be promoted or synthesized from one or more registers. 437 /// 438 SmallVector<EVT, 4> ValueVTs; 439 440 /// RegVTs - The value types of the registers. This is the same size as 441 /// ValueVTs and it records, for each value, what the type of the assigned 442 /// register or registers are. (Individual values are never synthesized 443 /// from more than one type of register.) 444 /// 445 /// With virtual registers, the contents of RegVTs is redundant with TLI's 446 /// getRegisterType member function, however when with physical registers 447 /// it is necessary to have a separate record of the types. 448 /// 449 SmallVector<EVT, 4> RegVTs; 450 451 /// Regs - This list holds the registers assigned to the values. 452 /// Each legal or promoted value requires one register, and each 453 /// expanded value requires multiple registers. 454 /// 455 SmallVector<unsigned, 4> Regs; 456 457 RegsForValue() {} 458 459 RegsForValue(const SmallVector<unsigned, 4> ®s, 460 EVT regvt, EVT valuevt) 461 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 462 463 RegsForValue(const SmallVector<unsigned, 4> ®s, 464 const SmallVector<EVT, 4> ®vts, 465 const SmallVector<EVT, 4> &valuevts) 466 : ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 467 468 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 469 unsigned Reg, const Type *Ty) { 470 ComputeValueVTs(tli, Ty, ValueVTs); 471 472 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 473 EVT ValueVT = ValueVTs[Value]; 474 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 475 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 476 for (unsigned i = 0; i != NumRegs; ++i) 477 Regs.push_back(Reg + i); 478 RegVTs.push_back(RegisterVT); 479 Reg += NumRegs; 480 } 481 } 482 483 /// areValueTypesLegal - Return true if types of all the values are legal. 484 bool areValueTypesLegal(const TargetLowering &TLI) { 485 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 486 EVT RegisterVT = RegVTs[Value]; 487 if (!TLI.isTypeLegal(RegisterVT)) 488 return false; 489 } 490 return true; 491 } 492 493 /// append - Add the specified values to this one. 494 void append(const RegsForValue &RHS) { 495 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 496 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 497 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 498 } 499 500 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 501 /// this value and returns the result as a ValueVTs value. This uses 502 /// Chain/Flag as the input and updates them for the output Chain/Flag. 503 /// If the Flag pointer is NULL, no flag is used. 504 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 505 DebugLoc dl, 506 SDValue &Chain, SDValue *Flag) const; 507 508 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 509 /// specified value into the registers specified by this object. This uses 510 /// Chain/Flag as the input and updates them for the output Chain/Flag. 511 /// If the Flag pointer is NULL, no flag is used. 512 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 513 SDValue &Chain, SDValue *Flag) const; 514 515 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 516 /// operand list. This adds the code marker, matching input operand index 517 /// (if applicable), and includes the number of values added into it. 518 void AddInlineAsmOperands(unsigned Kind, 519 bool HasMatching, unsigned MatchingIdx, 520 SelectionDAG &DAG, 521 std::vector<SDValue> &Ops) const; 522 }; 523} 524 525/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 526/// this value and returns the result as a ValueVT value. This uses 527/// Chain/Flag as the input and updates them for the output Chain/Flag. 528/// If the Flag pointer is NULL, no flag is used. 529SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 530 FunctionLoweringInfo &FuncInfo, 531 DebugLoc dl, 532 SDValue &Chain, SDValue *Flag) const { 533 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 534 535 // Assemble the legal parts into the final values. 536 SmallVector<SDValue, 4> Values(ValueVTs.size()); 537 SmallVector<SDValue, 8> Parts; 538 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 539 // Copy the legal parts from the registers. 540 EVT ValueVT = ValueVTs[Value]; 541 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 542 EVT RegisterVT = RegVTs[Value]; 543 544 Parts.resize(NumRegs); 545 for (unsigned i = 0; i != NumRegs; ++i) { 546 SDValue P; 547 if (Flag == 0) { 548 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 549 } else { 550 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 551 *Flag = P.getValue(2); 552 } 553 554 Chain = P.getValue(1); 555 556 // If the source register was virtual and if we know something about it, 557 // add an assert node. 558 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 559 RegisterVT.isInteger() && !RegisterVT.isVector()) { 560 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 561 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 562 const FunctionLoweringInfo::LiveOutInfo &LOI = 563 FuncInfo.LiveOutRegInfo[SlotNo]; 564 565 unsigned RegSize = RegisterVT.getSizeInBits(); 566 unsigned NumSignBits = LOI.NumSignBits; 567 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 568 569 // FIXME: We capture more information than the dag can represent. For 570 // now, just use the tightest assertzext/assertsext possible. 571 bool isSExt = true; 572 EVT FromVT(MVT::Other); 573 if (NumSignBits == RegSize) 574 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 575 else if (NumZeroBits >= RegSize-1) 576 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 577 else if (NumSignBits > RegSize-8) 578 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 579 else if (NumZeroBits >= RegSize-8) 580 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 581 else if (NumSignBits > RegSize-16) 582 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 583 else if (NumZeroBits >= RegSize-16) 584 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 585 else if (NumSignBits > RegSize-32) 586 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 587 else if (NumZeroBits >= RegSize-32) 588 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 589 590 if (FromVT != MVT::Other) 591 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 592 RegisterVT, P, DAG.getValueType(FromVT)); 593 } 594 } 595 596 Parts[i] = P; 597 } 598 599 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 600 NumRegs, RegisterVT, ValueVT); 601 Part += NumRegs; 602 Parts.clear(); 603 } 604 605 return DAG.getNode(ISD::MERGE_VALUES, dl, 606 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 607 &Values[0], ValueVTs.size()); 608} 609 610/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 611/// specified value into the registers specified by this object. This uses 612/// Chain/Flag as the input and updates them for the output Chain/Flag. 613/// If the Flag pointer is NULL, no flag is used. 614void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 615 SDValue &Chain, SDValue *Flag) const { 616 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 617 618 // Get the list of the values's legal parts. 619 unsigned NumRegs = Regs.size(); 620 SmallVector<SDValue, 8> Parts(NumRegs); 621 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 622 EVT ValueVT = ValueVTs[Value]; 623 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 624 EVT RegisterVT = RegVTs[Value]; 625 626 getCopyToParts(DAG, dl, 627 Val.getValue(Val.getResNo() + Value), 628 &Parts[Part], NumParts, RegisterVT); 629 Part += NumParts; 630 } 631 632 // Copy the parts into the registers. 633 SmallVector<SDValue, 8> Chains(NumRegs); 634 for (unsigned i = 0; i != NumRegs; ++i) { 635 SDValue Part; 636 if (Flag == 0) { 637 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 638 } else { 639 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 640 *Flag = Part.getValue(1); 641 } 642 643 Chains[i] = Part.getValue(0); 644 } 645 646 if (NumRegs == 1 || Flag) 647 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 648 // flagged to it. That is the CopyToReg nodes and the user are considered 649 // a single scheduling unit. If we create a TokenFactor and return it as 650 // chain, then the TokenFactor is both a predecessor (operand) of the 651 // user as well as a successor (the TF operands are flagged to the user). 652 // c1, f1 = CopyToReg 653 // c2, f2 = CopyToReg 654 // c3 = TokenFactor c1, c2 655 // ... 656 // = op c3, ..., f2 657 Chain = Chains[NumRegs-1]; 658 else 659 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 660} 661 662/// AddInlineAsmOperands - Add this value to the specified inlineasm node 663/// operand list. This adds the code marker and includes the number of 664/// values added into it. 665void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 666 unsigned MatchingIdx, 667 SelectionDAG &DAG, 668 std::vector<SDValue> &Ops) const { 669 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 670 671 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 672 if (HasMatching) 673 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 674 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 675 Ops.push_back(Res); 676 677 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 678 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 679 EVT RegisterVT = RegVTs[Value]; 680 for (unsigned i = 0; i != NumRegs; ++i) { 681 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 682 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 683 } 684 } 685} 686 687void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 688 AA = &aa; 689 GFI = gfi; 690 TD = DAG.getTarget().getTargetData(); 691} 692 693/// clear - Clear out the current SelectionDAG and the associated 694/// state and prepare this SelectionDAGBuilder object to be used 695/// for a new block. This doesn't clear out information about 696/// additional blocks that are needed to complete switch lowering 697/// or PHI node updating; that information is cleared out as it is 698/// consumed. 699void SelectionDAGBuilder::clear() { 700 NodeMap.clear(); 701 PendingLoads.clear(); 702 PendingExports.clear(); 703 CurDebugLoc = DebugLoc(); 704 HasTailCall = false; 705} 706 707/// getRoot - Return the current virtual root of the Selection DAG, 708/// flushing any PendingLoad items. This must be done before emitting 709/// a store or any other node that may need to be ordered after any 710/// prior load instructions. 711/// 712SDValue SelectionDAGBuilder::getRoot() { 713 if (PendingLoads.empty()) 714 return DAG.getRoot(); 715 716 if (PendingLoads.size() == 1) { 717 SDValue Root = PendingLoads[0]; 718 DAG.setRoot(Root); 719 PendingLoads.clear(); 720 return Root; 721 } 722 723 // Otherwise, we have to make a token factor node. 724 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 725 &PendingLoads[0], PendingLoads.size()); 726 PendingLoads.clear(); 727 DAG.setRoot(Root); 728 return Root; 729} 730 731/// getControlRoot - Similar to getRoot, but instead of flushing all the 732/// PendingLoad items, flush all the PendingExports items. It is necessary 733/// to do this before emitting a terminator instruction. 734/// 735SDValue SelectionDAGBuilder::getControlRoot() { 736 SDValue Root = DAG.getRoot(); 737 738 if (PendingExports.empty()) 739 return Root; 740 741 // Turn all of the CopyToReg chains into one factored node. 742 if (Root.getOpcode() != ISD::EntryToken) { 743 unsigned i = 0, e = PendingExports.size(); 744 for (; i != e; ++i) { 745 assert(PendingExports[i].getNode()->getNumOperands() > 1); 746 if (PendingExports[i].getNode()->getOperand(0) == Root) 747 break; // Don't add the root if we already indirectly depend on it. 748 } 749 750 if (i == e) 751 PendingExports.push_back(Root); 752 } 753 754 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 755 &PendingExports[0], 756 PendingExports.size()); 757 PendingExports.clear(); 758 DAG.setRoot(Root); 759 return Root; 760} 761 762void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 763 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 764 DAG.AssignOrdering(Node, SDNodeOrder); 765 766 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 767 AssignOrderingToNode(Node->getOperand(I).getNode()); 768} 769 770void SelectionDAGBuilder::visit(const Instruction &I) { 771 // Set up outgoing PHI node register values before emitting the terminator. 772 if (isa<TerminatorInst>(&I)) 773 HandlePHINodesInSuccessorBlocks(I.getParent()); 774 775 CurDebugLoc = I.getDebugLoc(); 776 777 visit(I.getOpcode(), I); 778 779 if (!isa<TerminatorInst>(&I) && !HasTailCall) 780 CopyToExportRegsIfNeeded(&I); 781 782 CurDebugLoc = DebugLoc(); 783} 784 785void SelectionDAGBuilder::visitPHI(const PHINode &) { 786 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 787} 788 789void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 790 // Note: this doesn't use InstVisitor, because it has to work with 791 // ConstantExpr's in addition to instructions. 792 switch (Opcode) { 793 default: llvm_unreachable("Unknown instruction type encountered!"); 794 // Build the switch statement using the Instruction.def file. 795#define HANDLE_INST(NUM, OPCODE, CLASS) \ 796 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 797#include "llvm/Instruction.def" 798 } 799 800 // Assign the ordering to the freshly created DAG nodes. 801 if (NodeMap.count(&I)) { 802 ++SDNodeOrder; 803 AssignOrderingToNode(getValue(&I).getNode()); 804 } 805} 806 807SDValue SelectionDAGBuilder::getValue(const Value *V) { 808 SDValue &N = NodeMap[V]; 809 if (N.getNode()) return N; 810 811 if (const Constant *C = dyn_cast<Constant>(V)) { 812 EVT VT = TLI.getValueType(V->getType(), true); 813 814 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 815 return N = DAG.getConstant(*CI, VT); 816 817 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 818 return N = DAG.getGlobalAddress(GV, VT); 819 820 if (isa<ConstantPointerNull>(C)) 821 return N = DAG.getConstant(0, TLI.getPointerTy()); 822 823 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 824 return N = DAG.getConstantFP(*CFP, VT); 825 826 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 827 return N = DAG.getUNDEF(VT); 828 829 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 830 visit(CE->getOpcode(), *CE); 831 SDValue N1 = NodeMap[V]; 832 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 833 return N1; 834 } 835 836 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 837 SmallVector<SDValue, 4> Constants; 838 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 839 OI != OE; ++OI) { 840 SDNode *Val = getValue(*OI).getNode(); 841 // If the operand is an empty aggregate, there are no values. 842 if (!Val) continue; 843 // Add each leaf value from the operand to the Constants list 844 // to form a flattened list of all the values. 845 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 846 Constants.push_back(SDValue(Val, i)); 847 } 848 849 return DAG.getMergeValues(&Constants[0], Constants.size(), 850 getCurDebugLoc()); 851 } 852 853 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 854 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 855 "Unknown struct or array constant!"); 856 857 SmallVector<EVT, 4> ValueVTs; 858 ComputeValueVTs(TLI, C->getType(), ValueVTs); 859 unsigned NumElts = ValueVTs.size(); 860 if (NumElts == 0) 861 return SDValue(); // empty struct 862 SmallVector<SDValue, 4> Constants(NumElts); 863 for (unsigned i = 0; i != NumElts; ++i) { 864 EVT EltVT = ValueVTs[i]; 865 if (isa<UndefValue>(C)) 866 Constants[i] = DAG.getUNDEF(EltVT); 867 else if (EltVT.isFloatingPoint()) 868 Constants[i] = DAG.getConstantFP(0, EltVT); 869 else 870 Constants[i] = DAG.getConstant(0, EltVT); 871 } 872 873 return DAG.getMergeValues(&Constants[0], NumElts, 874 getCurDebugLoc()); 875 } 876 877 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 878 return DAG.getBlockAddress(BA, VT); 879 880 const VectorType *VecTy = cast<VectorType>(V->getType()); 881 unsigned NumElements = VecTy->getNumElements(); 882 883 // Now that we know the number and type of the elements, get that number of 884 // elements into the Ops array based on what kind of constant it is. 885 SmallVector<SDValue, 16> Ops; 886 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 887 for (unsigned i = 0; i != NumElements; ++i) 888 Ops.push_back(getValue(CP->getOperand(i))); 889 } else { 890 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 891 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 892 893 SDValue Op; 894 if (EltVT.isFloatingPoint()) 895 Op = DAG.getConstantFP(0, EltVT); 896 else 897 Op = DAG.getConstant(0, EltVT); 898 Ops.assign(NumElements, Op); 899 } 900 901 // Create a BUILD_VECTOR node. 902 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 903 VT, &Ops[0], Ops.size()); 904 } 905 906 // If this is a static alloca, generate it as the frameindex instead of 907 // computation. 908 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 909 DenseMap<const AllocaInst*, int>::iterator SI = 910 FuncInfo.StaticAllocaMap.find(AI); 911 if (SI != FuncInfo.StaticAllocaMap.end()) 912 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 913 } 914 915 unsigned InReg = FuncInfo.ValueMap[V]; 916 assert(InReg && "Value not in map!"); 917 918 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 919 SDValue Chain = DAG.getEntryNode(); 920 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 921} 922 923/// Get the EVTs and ArgFlags collections that represent the legalized return 924/// type of the given function. This does not require a DAG or a return value, 925/// and is suitable for use before any DAGs for the function are constructed. 926static void getReturnInfo(const Type* ReturnType, 927 Attributes attr, SmallVectorImpl<EVT> &OutVTs, 928 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags, 929 const TargetLowering &TLI, 930 SmallVectorImpl<uint64_t> *Offsets = 0) { 931 SmallVector<EVT, 4> ValueVTs; 932 ComputeValueVTs(TLI, ReturnType, ValueVTs); 933 unsigned NumValues = ValueVTs.size(); 934 if (NumValues == 0) return; 935 unsigned Offset = 0; 936 937 for (unsigned j = 0, f = NumValues; j != f; ++j) { 938 EVT VT = ValueVTs[j]; 939 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 940 941 if (attr & Attribute::SExt) 942 ExtendKind = ISD::SIGN_EXTEND; 943 else if (attr & Attribute::ZExt) 944 ExtendKind = ISD::ZERO_EXTEND; 945 946 // FIXME: C calling convention requires the return type to be promoted to 947 // at least 32-bit. But this is not necessary for non-C calling 948 // conventions. The frontend should mark functions whose return values 949 // require promoting with signext or zeroext attributes. 950 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 951 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 952 if (VT.bitsLT(MinVT)) 953 VT = MinVT; 954 } 955 956 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 957 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 958 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 959 PartVT.getTypeForEVT(ReturnType->getContext())); 960 961 // 'inreg' on function refers to return value 962 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 963 if (attr & Attribute::InReg) 964 Flags.setInReg(); 965 966 // Propagate extension type if any 967 if (attr & Attribute::SExt) 968 Flags.setSExt(); 969 else if (attr & Attribute::ZExt) 970 Flags.setZExt(); 971 972 for (unsigned i = 0; i < NumParts; ++i) { 973 OutVTs.push_back(PartVT); 974 OutFlags.push_back(Flags); 975 if (Offsets) 976 { 977 Offsets->push_back(Offset); 978 Offset += PartSize; 979 } 980 } 981 } 982} 983 984void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 985 SDValue Chain = getControlRoot(); 986 SmallVector<ISD::OutputArg, 8> Outs; 987 988 if (!FuncInfo.CanLowerReturn) { 989 unsigned DemoteReg = FuncInfo.DemoteRegister; 990 const Function *F = I.getParent()->getParent(); 991 992 // Emit a store of the return value through the virtual register. 993 // Leave Outs empty so that LowerReturn won't try to load return 994 // registers the usual way. 995 SmallVector<EVT, 1> PtrValueVTs; 996 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 997 PtrValueVTs); 998 999 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1000 SDValue RetOp = getValue(I.getOperand(0)); 1001 1002 SmallVector<EVT, 4> ValueVTs; 1003 SmallVector<uint64_t, 4> Offsets; 1004 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1005 unsigned NumValues = ValueVTs.size(); 1006 1007 SmallVector<SDValue, 4> Chains(NumValues); 1008 EVT PtrVT = PtrValueVTs[0]; 1009 for (unsigned i = 0; i != NumValues; ++i) { 1010 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr, 1011 DAG.getConstant(Offsets[i], PtrVT)); 1012 Chains[i] = 1013 DAG.getStore(Chain, getCurDebugLoc(), 1014 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1015 Add, NULL, Offsets[i], false, false, 0); 1016 } 1017 1018 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1019 MVT::Other, &Chains[0], NumValues); 1020 } else if (I.getNumOperands() != 0) { 1021 SmallVector<EVT, 4> ValueVTs; 1022 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1023 unsigned NumValues = ValueVTs.size(); 1024 if (NumValues) { 1025 SDValue RetOp = getValue(I.getOperand(0)); 1026 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1027 EVT VT = ValueVTs[j]; 1028 1029 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1030 1031 const Function *F = I.getParent()->getParent(); 1032 if (F->paramHasAttr(0, Attribute::SExt)) 1033 ExtendKind = ISD::SIGN_EXTEND; 1034 else if (F->paramHasAttr(0, Attribute::ZExt)) 1035 ExtendKind = ISD::ZERO_EXTEND; 1036 1037 // FIXME: C calling convention requires the return type to be promoted 1038 // to at least 32-bit. But this is not necessary for non-C calling 1039 // conventions. The frontend should mark functions whose return values 1040 // require promoting with signext or zeroext attributes. 1041 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1042 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1043 if (VT.bitsLT(MinVT)) 1044 VT = MinVT; 1045 } 1046 1047 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1048 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1049 SmallVector<SDValue, 4> Parts(NumParts); 1050 getCopyToParts(DAG, getCurDebugLoc(), 1051 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1052 &Parts[0], NumParts, PartVT, ExtendKind); 1053 1054 // 'inreg' on function refers to return value 1055 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1056 if (F->paramHasAttr(0, Attribute::InReg)) 1057 Flags.setInReg(); 1058 1059 // Propagate extension type if any 1060 if (F->paramHasAttr(0, Attribute::SExt)) 1061 Flags.setSExt(); 1062 else if (F->paramHasAttr(0, Attribute::ZExt)) 1063 Flags.setZExt(); 1064 1065 for (unsigned i = 0; i < NumParts; ++i) 1066 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true)); 1067 } 1068 } 1069 } 1070 1071 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1072 CallingConv::ID CallConv = 1073 DAG.getMachineFunction().getFunction()->getCallingConv(); 1074 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1075 Outs, getCurDebugLoc(), DAG); 1076 1077 // Verify that the target's LowerReturn behaved as expected. 1078 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1079 "LowerReturn didn't return a valid chain!"); 1080 1081 // Update the DAG with the new chain value resulting from return lowering. 1082 DAG.setRoot(Chain); 1083} 1084 1085/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1086/// created for it, emit nodes to copy the value into the virtual 1087/// registers. 1088void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1089 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1090 if (VMI != FuncInfo.ValueMap.end()) { 1091 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1092 CopyValueToVirtualRegister(V, VMI->second); 1093 } 1094} 1095 1096/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1097/// the current basic block, add it to ValueMap now so that we'll get a 1098/// CopyTo/FromReg. 1099void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1100 // No need to export constants. 1101 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1102 1103 // Already exported? 1104 if (FuncInfo.isExportedInst(V)) return; 1105 1106 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1107 CopyValueToVirtualRegister(V, Reg); 1108} 1109 1110bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1111 const BasicBlock *FromBB) { 1112 // The operands of the setcc have to be in this block. We don't know 1113 // how to export them from some other block. 1114 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1115 // Can export from current BB. 1116 if (VI->getParent() == FromBB) 1117 return true; 1118 1119 // Is already exported, noop. 1120 return FuncInfo.isExportedInst(V); 1121 } 1122 1123 // If this is an argument, we can export it if the BB is the entry block or 1124 // if it is already exported. 1125 if (isa<Argument>(V)) { 1126 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1127 return true; 1128 1129 // Otherwise, can only export this if it is already exported. 1130 return FuncInfo.isExportedInst(V); 1131 } 1132 1133 // Otherwise, constants can always be exported. 1134 return true; 1135} 1136 1137static bool InBlock(const Value *V, const BasicBlock *BB) { 1138 if (const Instruction *I = dyn_cast<Instruction>(V)) 1139 return I->getParent() == BB; 1140 return true; 1141} 1142 1143/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1144/// This function emits a branch and is used at the leaves of an OR or an 1145/// AND operator tree. 1146/// 1147void 1148SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1149 MachineBasicBlock *TBB, 1150 MachineBasicBlock *FBB, 1151 MachineBasicBlock *CurBB, 1152 MachineBasicBlock *SwitchBB) { 1153 const BasicBlock *BB = CurBB->getBasicBlock(); 1154 1155 // If the leaf of the tree is a comparison, merge the condition into 1156 // the caseblock. 1157 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1158 // The operands of the cmp have to be in this block. We don't know 1159 // how to export them from some other block. If this is the first block 1160 // of the sequence, no exporting is needed. 1161 if (CurBB == SwitchBB || 1162 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1163 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1164 ISD::CondCode Condition; 1165 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1166 Condition = getICmpCondCode(IC->getPredicate()); 1167 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1168 Condition = getFCmpCondCode(FC->getPredicate()); 1169 } else { 1170 Condition = ISD::SETEQ; // silence warning. 1171 llvm_unreachable("Unknown compare instruction"); 1172 } 1173 1174 CaseBlock CB(Condition, BOp->getOperand(0), 1175 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1176 SwitchCases.push_back(CB); 1177 return; 1178 } 1179 } 1180 1181 // Create a CaseBlock record representing this branch. 1182 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1183 NULL, TBB, FBB, CurBB); 1184 SwitchCases.push_back(CB); 1185} 1186 1187/// FindMergedConditions - If Cond is an expression like 1188void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1189 MachineBasicBlock *TBB, 1190 MachineBasicBlock *FBB, 1191 MachineBasicBlock *CurBB, 1192 MachineBasicBlock *SwitchBB, 1193 unsigned Opc) { 1194 // If this node is not part of the or/and tree, emit it as a branch. 1195 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1196 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1197 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1198 BOp->getParent() != CurBB->getBasicBlock() || 1199 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1200 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1201 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1202 return; 1203 } 1204 1205 // Create TmpBB after CurBB. 1206 MachineFunction::iterator BBI = CurBB; 1207 MachineFunction &MF = DAG.getMachineFunction(); 1208 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1209 CurBB->getParent()->insert(++BBI, TmpBB); 1210 1211 if (Opc == Instruction::Or) { 1212 // Codegen X | Y as: 1213 // jmp_if_X TBB 1214 // jmp TmpBB 1215 // TmpBB: 1216 // jmp_if_Y TBB 1217 // jmp FBB 1218 // 1219 1220 // Emit the LHS condition. 1221 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1222 1223 // Emit the RHS condition into TmpBB. 1224 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1225 } else { 1226 assert(Opc == Instruction::And && "Unknown merge op!"); 1227 // Codegen X & Y as: 1228 // jmp_if_X TmpBB 1229 // jmp FBB 1230 // TmpBB: 1231 // jmp_if_Y TBB 1232 // jmp FBB 1233 // 1234 // This requires creation of TmpBB after CurBB. 1235 1236 // Emit the LHS condition. 1237 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1238 1239 // Emit the RHS condition into TmpBB. 1240 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1241 } 1242} 1243 1244/// If the set of cases should be emitted as a series of branches, return true. 1245/// If we should emit this as a bunch of and/or'd together conditions, return 1246/// false. 1247bool 1248SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1249 if (Cases.size() != 2) return true; 1250 1251 // If this is two comparisons of the same values or'd or and'd together, they 1252 // will get folded into a single comparison, so don't emit two blocks. 1253 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1254 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1255 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1256 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1257 return false; 1258 } 1259 1260 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1261 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1262 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1263 Cases[0].CC == Cases[1].CC && 1264 isa<Constant>(Cases[0].CmpRHS) && 1265 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1266 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1267 return false; 1268 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1269 return false; 1270 } 1271 1272 return true; 1273} 1274 1275void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1276 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()]; 1277 1278 // Update machine-CFG edges. 1279 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1280 1281 // Figure out which block is immediately after the current one. 1282 MachineBasicBlock *NextBlock = 0; 1283 MachineFunction::iterator BBI = BrMBB; 1284 if (++BBI != FuncInfo.MF->end()) 1285 NextBlock = BBI; 1286 1287 if (I.isUnconditional()) { 1288 // Update machine-CFG edges. 1289 BrMBB->addSuccessor(Succ0MBB); 1290 1291 // If this is not a fall-through branch, emit the branch. 1292 if (Succ0MBB != NextBlock) 1293 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1294 MVT::Other, getControlRoot(), 1295 DAG.getBasicBlock(Succ0MBB))); 1296 1297 return; 1298 } 1299 1300 // If this condition is one of the special cases we handle, do special stuff 1301 // now. 1302 const Value *CondVal = I.getCondition(); 1303 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1304 1305 // If this is a series of conditions that are or'd or and'd together, emit 1306 // this as a sequence of branches instead of setcc's with and/or operations. 1307 // For example, instead of something like: 1308 // cmp A, B 1309 // C = seteq 1310 // cmp D, E 1311 // F = setle 1312 // or C, F 1313 // jnz foo 1314 // Emit: 1315 // cmp A, B 1316 // je foo 1317 // cmp D, E 1318 // jle foo 1319 // 1320 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1321 if (BOp->hasOneUse() && 1322 (BOp->getOpcode() == Instruction::And || 1323 BOp->getOpcode() == Instruction::Or)) { 1324 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1325 BOp->getOpcode()); 1326 // If the compares in later blocks need to use values not currently 1327 // exported from this block, export them now. This block should always 1328 // be the first entry. 1329 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1330 1331 // Allow some cases to be rejected. 1332 if (ShouldEmitAsBranches(SwitchCases)) { 1333 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1334 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1335 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1336 } 1337 1338 // Emit the branch for this block. 1339 visitSwitchCase(SwitchCases[0], BrMBB); 1340 SwitchCases.erase(SwitchCases.begin()); 1341 return; 1342 } 1343 1344 // Okay, we decided not to do this, remove any inserted MBB's and clear 1345 // SwitchCases. 1346 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1347 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1348 1349 SwitchCases.clear(); 1350 } 1351 } 1352 1353 // Create a CaseBlock record representing this branch. 1354 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1355 NULL, Succ0MBB, Succ1MBB, BrMBB); 1356 1357 // Use visitSwitchCase to actually insert the fast branch sequence for this 1358 // cond branch. 1359 visitSwitchCase(CB, BrMBB); 1360} 1361 1362/// visitSwitchCase - Emits the necessary code to represent a single node in 1363/// the binary search tree resulting from lowering a switch instruction. 1364void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1365 MachineBasicBlock *SwitchBB) { 1366 SDValue Cond; 1367 SDValue CondLHS = getValue(CB.CmpLHS); 1368 DebugLoc dl = getCurDebugLoc(); 1369 1370 // Build the setcc now. 1371 if (CB.CmpMHS == NULL) { 1372 // Fold "(X == true)" to X and "(X == false)" to !X to 1373 // handle common cases produced by branch lowering. 1374 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1375 CB.CC == ISD::SETEQ) 1376 Cond = CondLHS; 1377 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1378 CB.CC == ISD::SETEQ) { 1379 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1380 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1381 } else 1382 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1383 } else { 1384 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1385 1386 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1387 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1388 1389 SDValue CmpOp = getValue(CB.CmpMHS); 1390 EVT VT = CmpOp.getValueType(); 1391 1392 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1393 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1394 ISD::SETLE); 1395 } else { 1396 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1397 VT, CmpOp, DAG.getConstant(Low, VT)); 1398 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1399 DAG.getConstant(High-Low, VT), ISD::SETULE); 1400 } 1401 } 1402 1403 // Update successor info 1404 SwitchBB->addSuccessor(CB.TrueBB); 1405 SwitchBB->addSuccessor(CB.FalseBB); 1406 1407 // Set NextBlock to be the MBB immediately after the current one, if any. 1408 // This is used to avoid emitting unnecessary branches to the next block. 1409 MachineBasicBlock *NextBlock = 0; 1410 MachineFunction::iterator BBI = SwitchBB; 1411 if (++BBI != FuncInfo.MF->end()) 1412 NextBlock = BBI; 1413 1414 // If the lhs block is the next block, invert the condition so that we can 1415 // fall through to the lhs instead of the rhs block. 1416 if (CB.TrueBB == NextBlock) { 1417 std::swap(CB.TrueBB, CB.FalseBB); 1418 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1419 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1420 } 1421 1422 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1423 MVT::Other, getControlRoot(), Cond, 1424 DAG.getBasicBlock(CB.TrueBB)); 1425 1426 // If the branch was constant folded, fix up the CFG. 1427 if (BrCond.getOpcode() == ISD::BR) { 1428 SwitchBB->removeSuccessor(CB.FalseBB); 1429 } else { 1430 // Otherwise, go ahead and insert the false branch. 1431 if (BrCond == getControlRoot()) 1432 SwitchBB->removeSuccessor(CB.TrueBB); 1433 1434 if (CB.FalseBB != NextBlock) 1435 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1436 DAG.getBasicBlock(CB.FalseBB)); 1437 } 1438 1439 DAG.setRoot(BrCond); 1440} 1441 1442/// visitJumpTable - Emit JumpTable node in the current MBB 1443void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1444 // Emit the code for the jump table 1445 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1446 EVT PTy = TLI.getPointerTy(); 1447 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1448 JT.Reg, PTy); 1449 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1450 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1451 MVT::Other, Index.getValue(1), 1452 Table, Index); 1453 DAG.setRoot(BrJumpTable); 1454} 1455 1456/// visitJumpTableHeader - This function emits necessary code to produce index 1457/// in the JumpTable from switch case. 1458void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1459 JumpTableHeader &JTH, 1460 MachineBasicBlock *SwitchBB) { 1461 // Subtract the lowest switch case value from the value being switched on and 1462 // conditional branch to default mbb if the result is greater than the 1463 // difference between smallest and largest cases. 1464 SDValue SwitchOp = getValue(JTH.SValue); 1465 EVT VT = SwitchOp.getValueType(); 1466 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1467 DAG.getConstant(JTH.First, VT)); 1468 1469 // The SDNode we just created, which holds the value being switched on minus 1470 // the smallest case value, needs to be copied to a virtual register so it 1471 // can be used as an index into the jump table in a subsequent basic block. 1472 // This value may be smaller or larger than the target's pointer type, and 1473 // therefore require extension or truncating. 1474 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1475 1476 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1477 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1478 JumpTableReg, SwitchOp); 1479 JT.Reg = JumpTableReg; 1480 1481 // Emit the range check for the jump table, and branch to the default block 1482 // for the switch statement if the value being switched on exceeds the largest 1483 // case in the switch. 1484 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1485 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1486 DAG.getConstant(JTH.Last-JTH.First,VT), 1487 ISD::SETUGT); 1488 1489 // Set NextBlock to be the MBB immediately after the current one, if any. 1490 // This is used to avoid emitting unnecessary branches to the next block. 1491 MachineBasicBlock *NextBlock = 0; 1492 MachineFunction::iterator BBI = SwitchBB; 1493 1494 if (++BBI != FuncInfo.MF->end()) 1495 NextBlock = BBI; 1496 1497 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1498 MVT::Other, CopyTo, CMP, 1499 DAG.getBasicBlock(JT.Default)); 1500 1501 if (JT.MBB != NextBlock) 1502 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1503 DAG.getBasicBlock(JT.MBB)); 1504 1505 DAG.setRoot(BrCond); 1506} 1507 1508/// visitBitTestHeader - This function emits necessary code to produce value 1509/// suitable for "bit tests" 1510void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1511 MachineBasicBlock *SwitchBB) { 1512 // Subtract the minimum value 1513 SDValue SwitchOp = getValue(B.SValue); 1514 EVT VT = SwitchOp.getValueType(); 1515 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1516 DAG.getConstant(B.First, VT)); 1517 1518 // Check range 1519 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1520 TLI.getSetCCResultType(Sub.getValueType()), 1521 Sub, DAG.getConstant(B.Range, VT), 1522 ISD::SETUGT); 1523 1524 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1525 TLI.getPointerTy()); 1526 1527 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); 1528 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1529 B.Reg, ShiftOp); 1530 1531 // Set NextBlock to be the MBB immediately after the current one, if any. 1532 // This is used to avoid emitting unnecessary branches to the next block. 1533 MachineBasicBlock *NextBlock = 0; 1534 MachineFunction::iterator BBI = SwitchBB; 1535 if (++BBI != FuncInfo.MF->end()) 1536 NextBlock = BBI; 1537 1538 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1539 1540 SwitchBB->addSuccessor(B.Default); 1541 SwitchBB->addSuccessor(MBB); 1542 1543 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1544 MVT::Other, CopyTo, RangeCmp, 1545 DAG.getBasicBlock(B.Default)); 1546 1547 if (MBB != NextBlock) 1548 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1549 DAG.getBasicBlock(MBB)); 1550 1551 DAG.setRoot(BrRange); 1552} 1553 1554/// visitBitTestCase - this function produces one "bit test" 1555void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1556 unsigned Reg, 1557 BitTestCase &B, 1558 MachineBasicBlock *SwitchBB) { 1559 // Make desired shift 1560 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1561 TLI.getPointerTy()); 1562 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1563 TLI.getPointerTy(), 1564 DAG.getConstant(1, TLI.getPointerTy()), 1565 ShiftOp); 1566 1567 // Emit bit tests and jumps 1568 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1569 TLI.getPointerTy(), SwitchVal, 1570 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1571 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), 1572 TLI.getSetCCResultType(AndOp.getValueType()), 1573 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1574 ISD::SETNE); 1575 1576 SwitchBB->addSuccessor(B.TargetBB); 1577 SwitchBB->addSuccessor(NextMBB); 1578 1579 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1580 MVT::Other, getControlRoot(), 1581 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1582 1583 // Set NextBlock to be the MBB immediately after the current one, if any. 1584 // This is used to avoid emitting unnecessary branches to the next block. 1585 MachineBasicBlock *NextBlock = 0; 1586 MachineFunction::iterator BBI = SwitchBB; 1587 if (++BBI != FuncInfo.MF->end()) 1588 NextBlock = BBI; 1589 1590 if (NextMBB != NextBlock) 1591 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1592 DAG.getBasicBlock(NextMBB)); 1593 1594 DAG.setRoot(BrAnd); 1595} 1596 1597void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1598 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()]; 1599 1600 // Retrieve successors. 1601 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1602 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1603 1604 const Value *Callee(I.getCalledValue()); 1605 if (isa<InlineAsm>(Callee)) 1606 visitInlineAsm(&I); 1607 else 1608 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1609 1610 // If the value of the invoke is used outside of its defining block, make it 1611 // available as a virtual register. 1612 CopyToExportRegsIfNeeded(&I); 1613 1614 // Update successor info 1615 InvokeMBB->addSuccessor(Return); 1616 InvokeMBB->addSuccessor(LandingPad); 1617 1618 // Drop into normal successor. 1619 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1620 MVT::Other, getControlRoot(), 1621 DAG.getBasicBlock(Return))); 1622} 1623 1624void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1625} 1626 1627/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1628/// small case ranges). 1629bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1630 CaseRecVector& WorkList, 1631 const Value* SV, 1632 MachineBasicBlock *Default, 1633 MachineBasicBlock *SwitchBB) { 1634 Case& BackCase = *(CR.Range.second-1); 1635 1636 // Size is the number of Cases represented by this range. 1637 size_t Size = CR.Range.second - CR.Range.first; 1638 if (Size > 3) 1639 return false; 1640 1641 // Get the MachineFunction which holds the current MBB. This is used when 1642 // inserting any additional MBBs necessary to represent the switch. 1643 MachineFunction *CurMF = FuncInfo.MF; 1644 1645 // Figure out which block is immediately after the current one. 1646 MachineBasicBlock *NextBlock = 0; 1647 MachineFunction::iterator BBI = CR.CaseBB; 1648 1649 if (++BBI != FuncInfo.MF->end()) 1650 NextBlock = BBI; 1651 1652 // TODO: If any two of the cases has the same destination, and if one value 1653 // is the same as the other, but has one bit unset that the other has set, 1654 // use bit manipulation to do two compares at once. For example: 1655 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1656 1657 // Rearrange the case blocks so that the last one falls through if possible. 1658 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1659 // The last case block won't fall through into 'NextBlock' if we emit the 1660 // branches in this order. See if rearranging a case value would help. 1661 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1662 if (I->BB == NextBlock) { 1663 std::swap(*I, BackCase); 1664 break; 1665 } 1666 } 1667 } 1668 1669 // Create a CaseBlock record representing a conditional branch to 1670 // the Case's target mbb if the value being switched on SV is equal 1671 // to C. 1672 MachineBasicBlock *CurBlock = CR.CaseBB; 1673 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1674 MachineBasicBlock *FallThrough; 1675 if (I != E-1) { 1676 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1677 CurMF->insert(BBI, FallThrough); 1678 1679 // Put SV in a virtual register to make it available from the new blocks. 1680 ExportFromCurrentBlock(SV); 1681 } else { 1682 // If the last case doesn't match, go to the default block. 1683 FallThrough = Default; 1684 } 1685 1686 const Value *RHS, *LHS, *MHS; 1687 ISD::CondCode CC; 1688 if (I->High == I->Low) { 1689 // This is just small small case range :) containing exactly 1 case 1690 CC = ISD::SETEQ; 1691 LHS = SV; RHS = I->High; MHS = NULL; 1692 } else { 1693 CC = ISD::SETLE; 1694 LHS = I->Low; MHS = SV; RHS = I->High; 1695 } 1696 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1697 1698 // If emitting the first comparison, just call visitSwitchCase to emit the 1699 // code into the current block. Otherwise, push the CaseBlock onto the 1700 // vector to be later processed by SDISel, and insert the node's MBB 1701 // before the next MBB. 1702 if (CurBlock == SwitchBB) 1703 visitSwitchCase(CB, SwitchBB); 1704 else 1705 SwitchCases.push_back(CB); 1706 1707 CurBlock = FallThrough; 1708 } 1709 1710 return true; 1711} 1712 1713static inline bool areJTsAllowed(const TargetLowering &TLI) { 1714 return !DisableJumpTables && 1715 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1716 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1717} 1718 1719static APInt ComputeRange(const APInt &First, const APInt &Last) { 1720 APInt LastExt(Last), FirstExt(First); 1721 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1722 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1723 return (LastExt - FirstExt + 1ULL); 1724} 1725 1726/// handleJTSwitchCase - Emit jumptable for current switch case range 1727bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1728 CaseRecVector& WorkList, 1729 const Value* SV, 1730 MachineBasicBlock* Default, 1731 MachineBasicBlock *SwitchBB) { 1732 Case& FrontCase = *CR.Range.first; 1733 Case& BackCase = *(CR.Range.second-1); 1734 1735 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1736 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1737 1738 APInt TSize(First.getBitWidth(), 0); 1739 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1740 I!=E; ++I) 1741 TSize += I->size(); 1742 1743 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1744 return false; 1745 1746 APInt Range = ComputeRange(First, Last); 1747 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1748 if (Density < 0.4) 1749 return false; 1750 1751 DEBUG(dbgs() << "Lowering jump table\n" 1752 << "First entry: " << First << ". Last entry: " << Last << '\n' 1753 << "Range: " << Range 1754 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1755 1756 // Get the MachineFunction which holds the current MBB. This is used when 1757 // inserting any additional MBBs necessary to represent the switch. 1758 MachineFunction *CurMF = FuncInfo.MF; 1759 1760 // Figure out which block is immediately after the current one. 1761 MachineFunction::iterator BBI = CR.CaseBB; 1762 ++BBI; 1763 1764 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1765 1766 // Create a new basic block to hold the code for loading the address 1767 // of the jump table, and jumping to it. Update successor information; 1768 // we will either branch to the default case for the switch, or the jump 1769 // table. 1770 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1771 CurMF->insert(BBI, JumpTableBB); 1772 CR.CaseBB->addSuccessor(Default); 1773 CR.CaseBB->addSuccessor(JumpTableBB); 1774 1775 // Build a vector of destination BBs, corresponding to each target 1776 // of the jump table. If the value of the jump table slot corresponds to 1777 // a case statement, push the case's BB onto the vector, otherwise, push 1778 // the default BB. 1779 std::vector<MachineBasicBlock*> DestBBs; 1780 APInt TEI = First; 1781 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1782 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1783 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1784 1785 if (Low.sle(TEI) && TEI.sle(High)) { 1786 DestBBs.push_back(I->BB); 1787 if (TEI==High) 1788 ++I; 1789 } else { 1790 DestBBs.push_back(Default); 1791 } 1792 } 1793 1794 // Update successor info. Add one edge to each unique successor. 1795 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1796 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1797 E = DestBBs.end(); I != E; ++I) { 1798 if (!SuccsHandled[(*I)->getNumber()]) { 1799 SuccsHandled[(*I)->getNumber()] = true; 1800 JumpTableBB->addSuccessor(*I); 1801 } 1802 } 1803 1804 // Create a jump table index for this jump table. 1805 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1806 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1807 ->createJumpTableIndex(DestBBs); 1808 1809 // Set the jump table information so that we can codegen it as a second 1810 // MachineBasicBlock 1811 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1812 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1813 if (CR.CaseBB == SwitchBB) 1814 visitJumpTableHeader(JT, JTH, SwitchBB); 1815 1816 JTCases.push_back(JumpTableBlock(JTH, JT)); 1817 1818 return true; 1819} 1820 1821/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1822/// 2 subtrees. 1823bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1824 CaseRecVector& WorkList, 1825 const Value* SV, 1826 MachineBasicBlock *Default, 1827 MachineBasicBlock *SwitchBB) { 1828 // Get the MachineFunction which holds the current MBB. This is used when 1829 // inserting any additional MBBs necessary to represent the switch. 1830 MachineFunction *CurMF = FuncInfo.MF; 1831 1832 // Figure out which block is immediately after the current one. 1833 MachineFunction::iterator BBI = CR.CaseBB; 1834 ++BBI; 1835 1836 Case& FrontCase = *CR.Range.first; 1837 Case& BackCase = *(CR.Range.second-1); 1838 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1839 1840 // Size is the number of Cases represented by this range. 1841 unsigned Size = CR.Range.second - CR.Range.first; 1842 1843 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1844 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1845 double FMetric = 0; 1846 CaseItr Pivot = CR.Range.first + Size/2; 1847 1848 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1849 // (heuristically) allow us to emit JumpTable's later. 1850 APInt TSize(First.getBitWidth(), 0); 1851 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1852 I!=E; ++I) 1853 TSize += I->size(); 1854 1855 APInt LSize = FrontCase.size(); 1856 APInt RSize = TSize-LSize; 1857 DEBUG(dbgs() << "Selecting best pivot: \n" 1858 << "First: " << First << ", Last: " << Last <<'\n' 1859 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1860 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1861 J!=E; ++I, ++J) { 1862 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1863 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1864 APInt Range = ComputeRange(LEnd, RBegin); 1865 assert((Range - 2ULL).isNonNegative() && 1866 "Invalid case distance"); 1867 double LDensity = (double)LSize.roundToDouble() / 1868 (LEnd - First + 1ULL).roundToDouble(); 1869 double RDensity = (double)RSize.roundToDouble() / 1870 (Last - RBegin + 1ULL).roundToDouble(); 1871 double Metric = Range.logBase2()*(LDensity+RDensity); 1872 // Should always split in some non-trivial place 1873 DEBUG(dbgs() <<"=>Step\n" 1874 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1875 << "LDensity: " << LDensity 1876 << ", RDensity: " << RDensity << '\n' 1877 << "Metric: " << Metric << '\n'); 1878 if (FMetric < Metric) { 1879 Pivot = J; 1880 FMetric = Metric; 1881 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1882 } 1883 1884 LSize += J->size(); 1885 RSize -= J->size(); 1886 } 1887 if (areJTsAllowed(TLI)) { 1888 // If our case is dense we *really* should handle it earlier! 1889 assert((FMetric > 0) && "Should handle dense range earlier!"); 1890 } else { 1891 Pivot = CR.Range.first + Size/2; 1892 } 1893 1894 CaseRange LHSR(CR.Range.first, Pivot); 1895 CaseRange RHSR(Pivot, CR.Range.second); 1896 Constant *C = Pivot->Low; 1897 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1898 1899 // We know that we branch to the LHS if the Value being switched on is 1900 // less than the Pivot value, C. We use this to optimize our binary 1901 // tree a bit, by recognizing that if SV is greater than or equal to the 1902 // LHS's Case Value, and that Case Value is exactly one less than the 1903 // Pivot's Value, then we can branch directly to the LHS's Target, 1904 // rather than creating a leaf node for it. 1905 if ((LHSR.second - LHSR.first) == 1 && 1906 LHSR.first->High == CR.GE && 1907 cast<ConstantInt>(C)->getValue() == 1908 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1909 TrueBB = LHSR.first->BB; 1910 } else { 1911 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1912 CurMF->insert(BBI, TrueBB); 1913 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1914 1915 // Put SV in a virtual register to make it available from the new blocks. 1916 ExportFromCurrentBlock(SV); 1917 } 1918 1919 // Similar to the optimization above, if the Value being switched on is 1920 // known to be less than the Constant CR.LT, and the current Case Value 1921 // is CR.LT - 1, then we can branch directly to the target block for 1922 // the current Case Value, rather than emitting a RHS leaf node for it. 1923 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1924 cast<ConstantInt>(RHSR.first->Low)->getValue() == 1925 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 1926 FalseBB = RHSR.first->BB; 1927 } else { 1928 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1929 CurMF->insert(BBI, FalseBB); 1930 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1931 1932 // Put SV in a virtual register to make it available from the new blocks. 1933 ExportFromCurrentBlock(SV); 1934 } 1935 1936 // Create a CaseBlock record representing a conditional branch to 1937 // the LHS node if the value being switched on SV is less than C. 1938 // Otherwise, branch to LHS. 1939 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 1940 1941 if (CR.CaseBB == SwitchBB) 1942 visitSwitchCase(CB, SwitchBB); 1943 else 1944 SwitchCases.push_back(CB); 1945 1946 return true; 1947} 1948 1949/// handleBitTestsSwitchCase - if current case range has few destination and 1950/// range span less, than machine word bitwidth, encode case range into series 1951/// of masks and emit bit tests with these masks. 1952bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 1953 CaseRecVector& WorkList, 1954 const Value* SV, 1955 MachineBasicBlock* Default, 1956 MachineBasicBlock *SwitchBB){ 1957 EVT PTy = TLI.getPointerTy(); 1958 unsigned IntPtrBits = PTy.getSizeInBits(); 1959 1960 Case& FrontCase = *CR.Range.first; 1961 Case& BackCase = *(CR.Range.second-1); 1962 1963 // Get the MachineFunction which holds the current MBB. This is used when 1964 // inserting any additional MBBs necessary to represent the switch. 1965 MachineFunction *CurMF = FuncInfo.MF; 1966 1967 // If target does not have legal shift left, do not emit bit tests at all. 1968 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 1969 return false; 1970 1971 size_t numCmps = 0; 1972 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1973 I!=E; ++I) { 1974 // Single case counts one, case range - two. 1975 numCmps += (I->Low == I->High ? 1 : 2); 1976 } 1977 1978 // Count unique destinations 1979 SmallSet<MachineBasicBlock*, 4> Dests; 1980 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1981 Dests.insert(I->BB); 1982 if (Dests.size() > 3) 1983 // Don't bother the code below, if there are too much unique destinations 1984 return false; 1985 } 1986 DEBUG(dbgs() << "Total number of unique destinations: " 1987 << Dests.size() << '\n' 1988 << "Total number of comparisons: " << numCmps << '\n'); 1989 1990 // Compute span of values. 1991 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 1992 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 1993 APInt cmpRange = maxValue - minValue; 1994 1995 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 1996 << "Low bound: " << minValue << '\n' 1997 << "High bound: " << maxValue << '\n'); 1998 1999 if (cmpRange.uge(IntPtrBits) || 2000 (!(Dests.size() == 1 && numCmps >= 3) && 2001 !(Dests.size() == 2 && numCmps >= 5) && 2002 !(Dests.size() >= 3 && numCmps >= 6))) 2003 return false; 2004 2005 DEBUG(dbgs() << "Emitting bit tests\n"); 2006 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2007 2008 // Optimize the case where all the case values fit in a 2009 // word without having to subtract minValue. In this case, 2010 // we can optimize away the subtraction. 2011 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2012 cmpRange = maxValue; 2013 } else { 2014 lowBound = minValue; 2015 } 2016 2017 CaseBitsVector CasesBits; 2018 unsigned i, count = 0; 2019 2020 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2021 MachineBasicBlock* Dest = I->BB; 2022 for (i = 0; i < count; ++i) 2023 if (Dest == CasesBits[i].BB) 2024 break; 2025 2026 if (i == count) { 2027 assert((count < 3) && "Too much destinations to test!"); 2028 CasesBits.push_back(CaseBits(0, Dest, 0)); 2029 count++; 2030 } 2031 2032 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2033 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2034 2035 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2036 uint64_t hi = (highValue - lowBound).getZExtValue(); 2037 2038 for (uint64_t j = lo; j <= hi; j++) { 2039 CasesBits[i].Mask |= 1ULL << j; 2040 CasesBits[i].Bits++; 2041 } 2042 2043 } 2044 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2045 2046 BitTestInfo BTC; 2047 2048 // Figure out which block is immediately after the current one. 2049 MachineFunction::iterator BBI = CR.CaseBB; 2050 ++BBI; 2051 2052 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2053 2054 DEBUG(dbgs() << "Cases:\n"); 2055 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2056 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2057 << ", Bits: " << CasesBits[i].Bits 2058 << ", BB: " << CasesBits[i].BB << '\n'); 2059 2060 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2061 CurMF->insert(BBI, CaseBB); 2062 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2063 CaseBB, 2064 CasesBits[i].BB)); 2065 2066 // Put SV in a virtual register to make it available from the new blocks. 2067 ExportFromCurrentBlock(SV); 2068 } 2069 2070 BitTestBlock BTB(lowBound, cmpRange, SV, 2071 -1U, (CR.CaseBB == SwitchBB), 2072 CR.CaseBB, Default, BTC); 2073 2074 if (CR.CaseBB == SwitchBB) 2075 visitBitTestHeader(BTB, SwitchBB); 2076 2077 BitTestCases.push_back(BTB); 2078 2079 return true; 2080} 2081 2082/// Clusterify - Transform simple list of Cases into list of CaseRange's 2083size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2084 const SwitchInst& SI) { 2085 size_t numCmps = 0; 2086 2087 // Start with "simple" cases 2088 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2089 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2090 Cases.push_back(Case(SI.getSuccessorValue(i), 2091 SI.getSuccessorValue(i), 2092 SMBB)); 2093 } 2094 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2095 2096 // Merge case into clusters 2097 if (Cases.size() >= 2) 2098 // Must recompute end() each iteration because it may be 2099 // invalidated by erase if we hold on to it 2100 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2101 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2102 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2103 MachineBasicBlock* nextBB = J->BB; 2104 MachineBasicBlock* currentBB = I->BB; 2105 2106 // If the two neighboring cases go to the same destination, merge them 2107 // into a single case. 2108 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2109 I->High = J->High; 2110 J = Cases.erase(J); 2111 } else { 2112 I = J++; 2113 } 2114 } 2115 2116 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2117 if (I->Low != I->High) 2118 // A range counts double, since it requires two compares. 2119 ++numCmps; 2120 } 2121 2122 return numCmps; 2123} 2124 2125void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2126 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()]; 2127 2128 // Figure out which block is immediately after the current one. 2129 MachineBasicBlock *NextBlock = 0; 2130 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2131 2132 // If there is only the default destination, branch to it if it is not the 2133 // next basic block. Otherwise, just fall through. 2134 if (SI.getNumOperands() == 2) { 2135 // Update machine-CFG edges. 2136 2137 // If this is not a fall-through branch, emit the branch. 2138 SwitchMBB->addSuccessor(Default); 2139 if (Default != NextBlock) 2140 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2141 MVT::Other, getControlRoot(), 2142 DAG.getBasicBlock(Default))); 2143 2144 return; 2145 } 2146 2147 // If there are any non-default case statements, create a vector of Cases 2148 // representing each one, and sort the vector so that we can efficiently 2149 // create a binary search tree from them. 2150 CaseVector Cases; 2151 size_t numCmps = Clusterify(Cases, SI); 2152 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2153 << ". Total compares: " << numCmps << '\n'); 2154 numCmps = 0; 2155 2156 // Get the Value to be switched on and default basic blocks, which will be 2157 // inserted into CaseBlock records, representing basic blocks in the binary 2158 // search tree. 2159 const Value *SV = SI.getOperand(0); 2160 2161 // Push the initial CaseRec onto the worklist 2162 CaseRecVector WorkList; 2163 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2164 CaseRange(Cases.begin(),Cases.end()))); 2165 2166 while (!WorkList.empty()) { 2167 // Grab a record representing a case range to process off the worklist 2168 CaseRec CR = WorkList.back(); 2169 WorkList.pop_back(); 2170 2171 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2172 continue; 2173 2174 // If the range has few cases (two or less) emit a series of specific 2175 // tests. 2176 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2177 continue; 2178 2179 // If the switch has more than 5 blocks, and at least 40% dense, and the 2180 // target supports indirect branches, then emit a jump table rather than 2181 // lowering the switch to a binary tree of conditional branches. 2182 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2183 continue; 2184 2185 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2186 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2187 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2188 } 2189} 2190 2191void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2192 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()]; 2193 2194 // Update machine-CFG edges with unique successors. 2195 SmallVector<BasicBlock*, 32> succs; 2196 succs.reserve(I.getNumSuccessors()); 2197 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2198 succs.push_back(I.getSuccessor(i)); 2199 array_pod_sort(succs.begin(), succs.end()); 2200 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2201 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2202 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2203 2204 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2205 MVT::Other, getControlRoot(), 2206 getValue(I.getAddress()))); 2207} 2208 2209void SelectionDAGBuilder::visitFSub(const User &I) { 2210 // -0.0 - X --> fneg 2211 const Type *Ty = I.getType(); 2212 if (Ty->isVectorTy()) { 2213 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2214 const VectorType *DestTy = cast<VectorType>(I.getType()); 2215 const Type *ElTy = DestTy->getElementType(); 2216 unsigned VL = DestTy->getNumElements(); 2217 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2218 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2219 if (CV == CNZ) { 2220 SDValue Op2 = getValue(I.getOperand(1)); 2221 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2222 Op2.getValueType(), Op2)); 2223 return; 2224 } 2225 } 2226 } 2227 2228 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2229 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2230 SDValue Op2 = getValue(I.getOperand(1)); 2231 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2232 Op2.getValueType(), Op2)); 2233 return; 2234 } 2235 2236 visitBinary(I, ISD::FSUB); 2237} 2238 2239void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2240 SDValue Op1 = getValue(I.getOperand(0)); 2241 SDValue Op2 = getValue(I.getOperand(1)); 2242 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2243 Op1.getValueType(), Op1, Op2)); 2244} 2245 2246void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2247 SDValue Op1 = getValue(I.getOperand(0)); 2248 SDValue Op2 = getValue(I.getOperand(1)); 2249 if (!I.getType()->isVectorTy() && 2250 Op2.getValueType() != TLI.getShiftAmountTy()) { 2251 // If the operand is smaller than the shift count type, promote it. 2252 EVT PTy = TLI.getPointerTy(); 2253 EVT STy = TLI.getShiftAmountTy(); 2254 if (STy.bitsGT(Op2.getValueType())) 2255 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2256 TLI.getShiftAmountTy(), Op2); 2257 // If the operand is larger than the shift count type but the shift 2258 // count type has enough bits to represent any shift value, truncate 2259 // it now. This is a common case and it exposes the truncate to 2260 // optimization early. 2261 else if (STy.getSizeInBits() >= 2262 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2263 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2264 TLI.getShiftAmountTy(), Op2); 2265 // Otherwise we'll need to temporarily settle for some other 2266 // convenient type; type legalization will make adjustments as 2267 // needed. 2268 else if (PTy.bitsLT(Op2.getValueType())) 2269 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2270 TLI.getPointerTy(), Op2); 2271 else if (PTy.bitsGT(Op2.getValueType())) 2272 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2273 TLI.getPointerTy(), Op2); 2274 } 2275 2276 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2277 Op1.getValueType(), Op1, Op2)); 2278} 2279 2280void SelectionDAGBuilder::visitICmp(const User &I) { 2281 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2282 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2283 predicate = IC->getPredicate(); 2284 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2285 predicate = ICmpInst::Predicate(IC->getPredicate()); 2286 SDValue Op1 = getValue(I.getOperand(0)); 2287 SDValue Op2 = getValue(I.getOperand(1)); 2288 ISD::CondCode Opcode = getICmpCondCode(predicate); 2289 2290 EVT DestVT = TLI.getValueType(I.getType()); 2291 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2292} 2293 2294void SelectionDAGBuilder::visitFCmp(const User &I) { 2295 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2296 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2297 predicate = FC->getPredicate(); 2298 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2299 predicate = FCmpInst::Predicate(FC->getPredicate()); 2300 SDValue Op1 = getValue(I.getOperand(0)); 2301 SDValue Op2 = getValue(I.getOperand(1)); 2302 ISD::CondCode Condition = getFCmpCondCode(predicate); 2303 EVT DestVT = TLI.getValueType(I.getType()); 2304 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2305} 2306 2307void SelectionDAGBuilder::visitSelect(const User &I) { 2308 SmallVector<EVT, 4> ValueVTs; 2309 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2310 unsigned NumValues = ValueVTs.size(); 2311 if (NumValues == 0) return; 2312 2313 SmallVector<SDValue, 4> Values(NumValues); 2314 SDValue Cond = getValue(I.getOperand(0)); 2315 SDValue TrueVal = getValue(I.getOperand(1)); 2316 SDValue FalseVal = getValue(I.getOperand(2)); 2317 2318 for (unsigned i = 0; i != NumValues; ++i) 2319 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2320 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2321 Cond, 2322 SDValue(TrueVal.getNode(), 2323 TrueVal.getResNo() + i), 2324 SDValue(FalseVal.getNode(), 2325 FalseVal.getResNo() + i)); 2326 2327 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2328 DAG.getVTList(&ValueVTs[0], NumValues), 2329 &Values[0], NumValues)); 2330} 2331 2332void SelectionDAGBuilder::visitTrunc(const User &I) { 2333 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2334 SDValue N = getValue(I.getOperand(0)); 2335 EVT DestVT = TLI.getValueType(I.getType()); 2336 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2337} 2338 2339void SelectionDAGBuilder::visitZExt(const User &I) { 2340 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2341 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2342 SDValue N = getValue(I.getOperand(0)); 2343 EVT DestVT = TLI.getValueType(I.getType()); 2344 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2345} 2346 2347void SelectionDAGBuilder::visitSExt(const User &I) { 2348 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2349 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2350 SDValue N = getValue(I.getOperand(0)); 2351 EVT DestVT = TLI.getValueType(I.getType()); 2352 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2353} 2354 2355void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2356 // FPTrunc is never a no-op cast, no need to check 2357 SDValue N = getValue(I.getOperand(0)); 2358 EVT DestVT = TLI.getValueType(I.getType()); 2359 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2360 DestVT, N, DAG.getIntPtrConstant(0))); 2361} 2362 2363void SelectionDAGBuilder::visitFPExt(const User &I){ 2364 // FPTrunc is never a no-op cast, no need to check 2365 SDValue N = getValue(I.getOperand(0)); 2366 EVT DestVT = TLI.getValueType(I.getType()); 2367 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2368} 2369 2370void SelectionDAGBuilder::visitFPToUI(const User &I) { 2371 // FPToUI is never a no-op cast, no need to check 2372 SDValue N = getValue(I.getOperand(0)); 2373 EVT DestVT = TLI.getValueType(I.getType()); 2374 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2375} 2376 2377void SelectionDAGBuilder::visitFPToSI(const User &I) { 2378 // FPToSI is never a no-op cast, no need to check 2379 SDValue N = getValue(I.getOperand(0)); 2380 EVT DestVT = TLI.getValueType(I.getType()); 2381 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2382} 2383 2384void SelectionDAGBuilder::visitUIToFP(const User &I) { 2385 // UIToFP is never a no-op cast, no need to check 2386 SDValue N = getValue(I.getOperand(0)); 2387 EVT DestVT = TLI.getValueType(I.getType()); 2388 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2389} 2390 2391void SelectionDAGBuilder::visitSIToFP(const User &I){ 2392 // SIToFP is never a no-op cast, no need to check 2393 SDValue N = getValue(I.getOperand(0)); 2394 EVT DestVT = TLI.getValueType(I.getType()); 2395 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2396} 2397 2398void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2399 // What to do depends on the size of the integer and the size of the pointer. 2400 // We can either truncate, zero extend, or no-op, accordingly. 2401 SDValue N = getValue(I.getOperand(0)); 2402 EVT SrcVT = N.getValueType(); 2403 EVT DestVT = TLI.getValueType(I.getType()); 2404 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2405} 2406 2407void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2408 // What to do depends on the size of the integer and the size of the pointer. 2409 // We can either truncate, zero extend, or no-op, accordingly. 2410 SDValue N = getValue(I.getOperand(0)); 2411 EVT SrcVT = N.getValueType(); 2412 EVT DestVT = TLI.getValueType(I.getType()); 2413 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2414} 2415 2416void SelectionDAGBuilder::visitBitCast(const User &I) { 2417 SDValue N = getValue(I.getOperand(0)); 2418 EVT DestVT = TLI.getValueType(I.getType()); 2419 2420 // BitCast assures us that source and destination are the same size so this is 2421 // either a BIT_CONVERT or a no-op. 2422 if (DestVT != N.getValueType()) 2423 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2424 DestVT, N)); // convert types. 2425 else 2426 setValue(&I, N); // noop cast. 2427} 2428 2429void SelectionDAGBuilder::visitInsertElement(const User &I) { 2430 SDValue InVec = getValue(I.getOperand(0)); 2431 SDValue InVal = getValue(I.getOperand(1)); 2432 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2433 TLI.getPointerTy(), 2434 getValue(I.getOperand(2))); 2435 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2436 TLI.getValueType(I.getType()), 2437 InVec, InVal, InIdx)); 2438} 2439 2440void SelectionDAGBuilder::visitExtractElement(const User &I) { 2441 SDValue InVec = getValue(I.getOperand(0)); 2442 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2443 TLI.getPointerTy(), 2444 getValue(I.getOperand(1))); 2445 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2446 TLI.getValueType(I.getType()), InVec, InIdx)); 2447} 2448 2449// Utility for visitShuffleVector - Returns true if the mask is mask starting 2450// from SIndx and increasing to the element length (undefs are allowed). 2451static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2452 unsigned MaskNumElts = Mask.size(); 2453 for (unsigned i = 0; i != MaskNumElts; ++i) 2454 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2455 return false; 2456 return true; 2457} 2458 2459void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2460 SmallVector<int, 8> Mask; 2461 SDValue Src1 = getValue(I.getOperand(0)); 2462 SDValue Src2 = getValue(I.getOperand(1)); 2463 2464 // Convert the ConstantVector mask operand into an array of ints, with -1 2465 // representing undef values. 2466 SmallVector<Constant*, 8> MaskElts; 2467 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2468 unsigned MaskNumElts = MaskElts.size(); 2469 for (unsigned i = 0; i != MaskNumElts; ++i) { 2470 if (isa<UndefValue>(MaskElts[i])) 2471 Mask.push_back(-1); 2472 else 2473 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2474 } 2475 2476 EVT VT = TLI.getValueType(I.getType()); 2477 EVT SrcVT = Src1.getValueType(); 2478 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2479 2480 if (SrcNumElts == MaskNumElts) { 2481 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2482 &Mask[0])); 2483 return; 2484 } 2485 2486 // Normalize the shuffle vector since mask and vector length don't match. 2487 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2488 // Mask is longer than the source vectors and is a multiple of the source 2489 // vectors. We can use concatenate vector to make the mask and vectors 2490 // lengths match. 2491 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2492 // The shuffle is concatenating two vectors together. 2493 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2494 VT, Src1, Src2)); 2495 return; 2496 } 2497 2498 // Pad both vectors with undefs to make them the same length as the mask. 2499 unsigned NumConcat = MaskNumElts / SrcNumElts; 2500 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2501 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2502 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2503 2504 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2505 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2506 MOps1[0] = Src1; 2507 MOps2[0] = Src2; 2508 2509 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2510 getCurDebugLoc(), VT, 2511 &MOps1[0], NumConcat); 2512 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2513 getCurDebugLoc(), VT, 2514 &MOps2[0], NumConcat); 2515 2516 // Readjust mask for new input vector length. 2517 SmallVector<int, 8> MappedOps; 2518 for (unsigned i = 0; i != MaskNumElts; ++i) { 2519 int Idx = Mask[i]; 2520 if (Idx < (int)SrcNumElts) 2521 MappedOps.push_back(Idx); 2522 else 2523 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2524 } 2525 2526 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2527 &MappedOps[0])); 2528 return; 2529 } 2530 2531 if (SrcNumElts > MaskNumElts) { 2532 // Analyze the access pattern of the vector to see if we can extract 2533 // two subvectors and do the shuffle. The analysis is done by calculating 2534 // the range of elements the mask access on both vectors. 2535 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2536 int MaxRange[2] = {-1, -1}; 2537 2538 for (unsigned i = 0; i != MaskNumElts; ++i) { 2539 int Idx = Mask[i]; 2540 int Input = 0; 2541 if (Idx < 0) 2542 continue; 2543 2544 if (Idx >= (int)SrcNumElts) { 2545 Input = 1; 2546 Idx -= SrcNumElts; 2547 } 2548 if (Idx > MaxRange[Input]) 2549 MaxRange[Input] = Idx; 2550 if (Idx < MinRange[Input]) 2551 MinRange[Input] = Idx; 2552 } 2553 2554 // Check if the access is smaller than the vector size and can we find 2555 // a reasonable extract index. 2556 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2557 // Extract. 2558 int StartIdx[2]; // StartIdx to extract from 2559 for (int Input=0; Input < 2; ++Input) { 2560 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2561 RangeUse[Input] = 0; // Unused 2562 StartIdx[Input] = 0; 2563 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2564 // Fits within range but we should see if we can find a good 2565 // start index that is a multiple of the mask length. 2566 if (MaxRange[Input] < (int)MaskNumElts) { 2567 RangeUse[Input] = 1; // Extract from beginning of the vector 2568 StartIdx[Input] = 0; 2569 } else { 2570 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2571 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2572 StartIdx[Input] + MaskNumElts < SrcNumElts) 2573 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2574 } 2575 } 2576 } 2577 2578 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2579 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2580 return; 2581 } 2582 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2583 // Extract appropriate subvector and generate a vector shuffle 2584 for (int Input=0; Input < 2; ++Input) { 2585 SDValue &Src = Input == 0 ? Src1 : Src2; 2586 if (RangeUse[Input] == 0) 2587 Src = DAG.getUNDEF(VT); 2588 else 2589 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2590 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2591 } 2592 2593 // Calculate new mask. 2594 SmallVector<int, 8> MappedOps; 2595 for (unsigned i = 0; i != MaskNumElts; ++i) { 2596 int Idx = Mask[i]; 2597 if (Idx < 0) 2598 MappedOps.push_back(Idx); 2599 else if (Idx < (int)SrcNumElts) 2600 MappedOps.push_back(Idx - StartIdx[0]); 2601 else 2602 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2603 } 2604 2605 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2606 &MappedOps[0])); 2607 return; 2608 } 2609 } 2610 2611 // We can't use either concat vectors or extract subvectors so fall back to 2612 // replacing the shuffle with extract and build vector. 2613 // to insert and build vector. 2614 EVT EltVT = VT.getVectorElementType(); 2615 EVT PtrVT = TLI.getPointerTy(); 2616 SmallVector<SDValue,8> Ops; 2617 for (unsigned i = 0; i != MaskNumElts; ++i) { 2618 if (Mask[i] < 0) { 2619 Ops.push_back(DAG.getUNDEF(EltVT)); 2620 } else { 2621 int Idx = Mask[i]; 2622 SDValue Res; 2623 2624 if (Idx < (int)SrcNumElts) 2625 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2626 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2627 else 2628 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2629 EltVT, Src2, 2630 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2631 2632 Ops.push_back(Res); 2633 } 2634 } 2635 2636 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2637 VT, &Ops[0], Ops.size())); 2638} 2639 2640void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2641 const Value *Op0 = I.getOperand(0); 2642 const Value *Op1 = I.getOperand(1); 2643 const Type *AggTy = I.getType(); 2644 const Type *ValTy = Op1->getType(); 2645 bool IntoUndef = isa<UndefValue>(Op0); 2646 bool FromUndef = isa<UndefValue>(Op1); 2647 2648 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2649 I.idx_begin(), I.idx_end()); 2650 2651 SmallVector<EVT, 4> AggValueVTs; 2652 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2653 SmallVector<EVT, 4> ValValueVTs; 2654 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2655 2656 unsigned NumAggValues = AggValueVTs.size(); 2657 unsigned NumValValues = ValValueVTs.size(); 2658 SmallVector<SDValue, 4> Values(NumAggValues); 2659 2660 SDValue Agg = getValue(Op0); 2661 SDValue Val = getValue(Op1); 2662 unsigned i = 0; 2663 // Copy the beginning value(s) from the original aggregate. 2664 for (; i != LinearIndex; ++i) 2665 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2666 SDValue(Agg.getNode(), Agg.getResNo() + i); 2667 // Copy values from the inserted value(s). 2668 for (; i != LinearIndex + NumValValues; ++i) 2669 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2670 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2671 // Copy remaining value(s) from the original aggregate. 2672 for (; i != NumAggValues; ++i) 2673 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2674 SDValue(Agg.getNode(), Agg.getResNo() + i); 2675 2676 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2677 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2678 &Values[0], NumAggValues)); 2679} 2680 2681void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2682 const Value *Op0 = I.getOperand(0); 2683 const Type *AggTy = Op0->getType(); 2684 const Type *ValTy = I.getType(); 2685 bool OutOfUndef = isa<UndefValue>(Op0); 2686 2687 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2688 I.idx_begin(), I.idx_end()); 2689 2690 SmallVector<EVT, 4> ValValueVTs; 2691 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2692 2693 unsigned NumValValues = ValValueVTs.size(); 2694 SmallVector<SDValue, 4> Values(NumValValues); 2695 2696 SDValue Agg = getValue(Op0); 2697 // Copy out the selected value(s). 2698 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2699 Values[i - LinearIndex] = 2700 OutOfUndef ? 2701 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2702 SDValue(Agg.getNode(), Agg.getResNo() + i); 2703 2704 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2705 DAG.getVTList(&ValValueVTs[0], NumValValues), 2706 &Values[0], NumValValues)); 2707} 2708 2709void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2710 SDValue N = getValue(I.getOperand(0)); 2711 const Type *Ty = I.getOperand(0)->getType(); 2712 2713 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2714 OI != E; ++OI) { 2715 const Value *Idx = *OI; 2716 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2717 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2718 if (Field) { 2719 // N = N + Offset 2720 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2721 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2722 DAG.getIntPtrConstant(Offset)); 2723 } 2724 2725 Ty = StTy->getElementType(Field); 2726 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) { 2727 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2728 2729 // Offset canonically 0 for unions, but type changes 2730 Ty = UnTy->getElementType(Field); 2731 } else { 2732 Ty = cast<SequentialType>(Ty)->getElementType(); 2733 2734 // If this is a constant subscript, handle it quickly. 2735 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2736 if (CI->getZExtValue() == 0) continue; 2737 uint64_t Offs = 2738 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2739 SDValue OffsVal; 2740 EVT PTy = TLI.getPointerTy(); 2741 unsigned PtrBits = PTy.getSizeInBits(); 2742 if (PtrBits < 64) 2743 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2744 TLI.getPointerTy(), 2745 DAG.getConstant(Offs, MVT::i64)); 2746 else 2747 OffsVal = DAG.getIntPtrConstant(Offs); 2748 2749 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2750 OffsVal); 2751 continue; 2752 } 2753 2754 // N = N + Idx * ElementSize; 2755 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2756 TD->getTypeAllocSize(Ty)); 2757 SDValue IdxN = getValue(Idx); 2758 2759 // If the index is smaller or larger than intptr_t, truncate or extend 2760 // it. 2761 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2762 2763 // If this is a multiply by a power of two, turn it into a shl 2764 // immediately. This is a very common case. 2765 if (ElementSize != 1) { 2766 if (ElementSize.isPowerOf2()) { 2767 unsigned Amt = ElementSize.logBase2(); 2768 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2769 N.getValueType(), IdxN, 2770 DAG.getConstant(Amt, TLI.getPointerTy())); 2771 } else { 2772 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2773 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2774 N.getValueType(), IdxN, Scale); 2775 } 2776 } 2777 2778 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2779 N.getValueType(), N, IdxN); 2780 } 2781 } 2782 2783 setValue(&I, N); 2784} 2785 2786void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2787 // If this is a fixed sized alloca in the entry block of the function, 2788 // allocate it statically on the stack. 2789 if (FuncInfo.StaticAllocaMap.count(&I)) 2790 return; // getValue will auto-populate this. 2791 2792 const Type *Ty = I.getAllocatedType(); 2793 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2794 unsigned Align = 2795 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2796 I.getAlignment()); 2797 2798 SDValue AllocSize = getValue(I.getArraySize()); 2799 2800 EVT IntPtr = TLI.getPointerTy(); 2801 if (AllocSize.getValueType() != IntPtr) 2802 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2803 2804 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2805 AllocSize, 2806 DAG.getConstant(TySize, IntPtr)); 2807 2808 // Handle alignment. If the requested alignment is less than or equal to 2809 // the stack alignment, ignore it. If the size is greater than or equal to 2810 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2811 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2812 if (Align <= StackAlign) 2813 Align = 0; 2814 2815 // Round the size of the allocation up to the stack alignment size 2816 // by add SA-1 to the size. 2817 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2818 AllocSize.getValueType(), AllocSize, 2819 DAG.getIntPtrConstant(StackAlign-1)); 2820 2821 // Mask out the low bits for alignment purposes. 2822 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2823 AllocSize.getValueType(), AllocSize, 2824 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2825 2826 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2827 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2828 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2829 VTs, Ops, 3); 2830 setValue(&I, DSA); 2831 DAG.setRoot(DSA.getValue(1)); 2832 2833 // Inform the Frame Information that we have just allocated a variable-sized 2834 // object. 2835 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); 2836} 2837 2838void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2839 const Value *SV = I.getOperand(0); 2840 SDValue Ptr = getValue(SV); 2841 2842 const Type *Ty = I.getType(); 2843 2844 bool isVolatile = I.isVolatile(); 2845 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2846 unsigned Alignment = I.getAlignment(); 2847 2848 SmallVector<EVT, 4> ValueVTs; 2849 SmallVector<uint64_t, 4> Offsets; 2850 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2851 unsigned NumValues = ValueVTs.size(); 2852 if (NumValues == 0) 2853 return; 2854 2855 SDValue Root; 2856 bool ConstantMemory = false; 2857 if (I.isVolatile()) 2858 // Serialize volatile loads with other side effects. 2859 Root = getRoot(); 2860 else if (AA->pointsToConstantMemory(SV)) { 2861 // Do not serialize (non-volatile) loads of constant memory with anything. 2862 Root = DAG.getEntryNode(); 2863 ConstantMemory = true; 2864 } else { 2865 // Do not serialize non-volatile loads against each other. 2866 Root = DAG.getRoot(); 2867 } 2868 2869 SmallVector<SDValue, 4> Values(NumValues); 2870 SmallVector<SDValue, 4> Chains(NumValues); 2871 EVT PtrVT = Ptr.getValueType(); 2872 for (unsigned i = 0; i != NumValues; ++i) { 2873 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2874 PtrVT, Ptr, 2875 DAG.getConstant(Offsets[i], PtrVT)); 2876 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2877 A, SV, Offsets[i], isVolatile, 2878 isNonTemporal, Alignment); 2879 2880 Values[i] = L; 2881 Chains[i] = L.getValue(1); 2882 } 2883 2884 if (!ConstantMemory) { 2885 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2886 MVT::Other, &Chains[0], NumValues); 2887 if (isVolatile) 2888 DAG.setRoot(Chain); 2889 else 2890 PendingLoads.push_back(Chain); 2891 } 2892 2893 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2894 DAG.getVTList(&ValueVTs[0], NumValues), 2895 &Values[0], NumValues)); 2896} 2897 2898void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2899 const Value *SrcV = I.getOperand(0); 2900 const Value *PtrV = I.getOperand(1); 2901 2902 SmallVector<EVT, 4> ValueVTs; 2903 SmallVector<uint64_t, 4> Offsets; 2904 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2905 unsigned NumValues = ValueVTs.size(); 2906 if (NumValues == 0) 2907 return; 2908 2909 // Get the lowered operands. Note that we do this after 2910 // checking if NumResults is zero, because with zero results 2911 // the operands won't have values in the map. 2912 SDValue Src = getValue(SrcV); 2913 SDValue Ptr = getValue(PtrV); 2914 2915 SDValue Root = getRoot(); 2916 SmallVector<SDValue, 4> Chains(NumValues); 2917 EVT PtrVT = Ptr.getValueType(); 2918 bool isVolatile = I.isVolatile(); 2919 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2920 unsigned Alignment = I.getAlignment(); 2921 2922 for (unsigned i = 0; i != NumValues; ++i) { 2923 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 2924 DAG.getConstant(Offsets[i], PtrVT)); 2925 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 2926 SDValue(Src.getNode(), Src.getResNo() + i), 2927 Add, PtrV, Offsets[i], isVolatile, 2928 isNonTemporal, Alignment); 2929 } 2930 2931 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2932 MVT::Other, &Chains[0], NumValues)); 2933} 2934 2935/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2936/// node. 2937void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 2938 unsigned Intrinsic) { 2939 bool HasChain = !I.doesNotAccessMemory(); 2940 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2941 2942 // Build the operand list. 2943 SmallVector<SDValue, 8> Ops; 2944 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2945 if (OnlyLoad) { 2946 // We don't need to serialize loads against other loads. 2947 Ops.push_back(DAG.getRoot()); 2948 } else { 2949 Ops.push_back(getRoot()); 2950 } 2951 } 2952 2953 // Info is set by getTgtMemInstrinsic 2954 TargetLowering::IntrinsicInfo Info; 2955 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 2956 2957 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 2958 if (!IsTgtIntrinsic) 2959 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2960 2961 // Add all operands of the call to the operand list. 2962 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2963 SDValue Op = getValue(I.getOperand(i)); 2964 assert(TLI.isTypeLegal(Op.getValueType()) && 2965 "Intrinsic uses a non-legal type?"); 2966 Ops.push_back(Op); 2967 } 2968 2969 SmallVector<EVT, 4> ValueVTs; 2970 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2971#ifndef NDEBUG 2972 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 2973 assert(TLI.isTypeLegal(ValueVTs[Val]) && 2974 "Intrinsic uses a non-legal type?"); 2975 } 2976#endif // NDEBUG 2977 2978 if (HasChain) 2979 ValueVTs.push_back(MVT::Other); 2980 2981 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 2982 2983 // Create the node. 2984 SDValue Result; 2985 if (IsTgtIntrinsic) { 2986 // This is target intrinsic that touches memory 2987 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 2988 VTs, &Ops[0], Ops.size(), 2989 Info.memVT, Info.ptrVal, Info.offset, 2990 Info.align, Info.vol, 2991 Info.readMem, Info.writeMem); 2992 } else if (!HasChain) { 2993 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 2994 VTs, &Ops[0], Ops.size()); 2995 } else if (!I.getType()->isVoidTy()) { 2996 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 2997 VTs, &Ops[0], Ops.size()); 2998 } else { 2999 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3000 VTs, &Ops[0], Ops.size()); 3001 } 3002 3003 if (HasChain) { 3004 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3005 if (OnlyLoad) 3006 PendingLoads.push_back(Chain); 3007 else 3008 DAG.setRoot(Chain); 3009 } 3010 3011 if (!I.getType()->isVoidTy()) { 3012 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3013 EVT VT = TLI.getValueType(PTy); 3014 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3015 } 3016 3017 setValue(&I, Result); 3018 } 3019} 3020 3021/// GetSignificand - Get the significand and build it into a floating-point 3022/// number with exponent of 1: 3023/// 3024/// Op = (Op & 0x007fffff) | 0x3f800000; 3025/// 3026/// where Op is the hexidecimal representation of floating point value. 3027static SDValue 3028GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3029 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3030 DAG.getConstant(0x007fffff, MVT::i32)); 3031 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3032 DAG.getConstant(0x3f800000, MVT::i32)); 3033 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3034} 3035 3036/// GetExponent - Get the exponent: 3037/// 3038/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3039/// 3040/// where Op is the hexidecimal representation of floating point value. 3041static SDValue 3042GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3043 DebugLoc dl) { 3044 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3045 DAG.getConstant(0x7f800000, MVT::i32)); 3046 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3047 DAG.getConstant(23, TLI.getPointerTy())); 3048 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3049 DAG.getConstant(127, MVT::i32)); 3050 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3051} 3052 3053/// getF32Constant - Get 32-bit floating point constant. 3054static SDValue 3055getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3056 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3057} 3058 3059/// Inlined utility function to implement binary input atomic intrinsics for 3060/// visitIntrinsicCall: I is a call instruction 3061/// Op is the associated NodeType for I 3062const char * 3063SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3064 ISD::NodeType Op) { 3065 SDValue Root = getRoot(); 3066 SDValue L = 3067 DAG.getAtomic(Op, getCurDebugLoc(), 3068 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 3069 Root, 3070 getValue(I.getOperand(1)), 3071 getValue(I.getOperand(2)), 3072 I.getOperand(1)); 3073 setValue(&I, L); 3074 DAG.setRoot(L.getValue(1)); 3075 return 0; 3076} 3077 3078// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3079const char * 3080SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3081 SDValue Op1 = getValue(I.getOperand(1)); 3082 SDValue Op2 = getValue(I.getOperand(2)); 3083 3084 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3085 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3086 return 0; 3087} 3088 3089/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3090/// limited-precision mode. 3091void 3092SelectionDAGBuilder::visitExp(const CallInst &I) { 3093 SDValue result; 3094 DebugLoc dl = getCurDebugLoc(); 3095 3096 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3097 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3098 SDValue Op = getValue(I.getOperand(1)); 3099 3100 // Put the exponent in the right bit position for later addition to the 3101 // final result: 3102 // 3103 // #define LOG2OFe 1.4426950f 3104 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3105 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3106 getF32Constant(DAG, 0x3fb8aa3b)); 3107 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3108 3109 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3110 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3111 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3112 3113 // IntegerPartOfX <<= 23; 3114 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3115 DAG.getConstant(23, TLI.getPointerTy())); 3116 3117 if (LimitFloatPrecision <= 6) { 3118 // For floating-point precision of 6: 3119 // 3120 // TwoToFractionalPartOfX = 3121 // 0.997535578f + 3122 // (0.735607626f + 0.252464424f * x) * x; 3123 // 3124 // error 0.0144103317, which is 6 bits 3125 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3126 getF32Constant(DAG, 0x3e814304)); 3127 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3128 getF32Constant(DAG, 0x3f3c50c8)); 3129 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3130 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3131 getF32Constant(DAG, 0x3f7f5e7e)); 3132 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3133 3134 // Add the exponent into the result in integer domain. 3135 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3136 TwoToFracPartOfX, IntegerPartOfX); 3137 3138 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3139 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3140 // For floating-point precision of 12: 3141 // 3142 // TwoToFractionalPartOfX = 3143 // 0.999892986f + 3144 // (0.696457318f + 3145 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3146 // 3147 // 0.000107046256 error, which is 13 to 14 bits 3148 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3149 getF32Constant(DAG, 0x3da235e3)); 3150 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3151 getF32Constant(DAG, 0x3e65b8f3)); 3152 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3153 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3154 getF32Constant(DAG, 0x3f324b07)); 3155 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3156 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3157 getF32Constant(DAG, 0x3f7ff8fd)); 3158 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3159 3160 // Add the exponent into the result in integer domain. 3161 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3162 TwoToFracPartOfX, IntegerPartOfX); 3163 3164 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3165 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3166 // For floating-point precision of 18: 3167 // 3168 // TwoToFractionalPartOfX = 3169 // 0.999999982f + 3170 // (0.693148872f + 3171 // (0.240227044f + 3172 // (0.554906021e-1f + 3173 // (0.961591928e-2f + 3174 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3175 // 3176 // error 2.47208000*10^(-7), which is better than 18 bits 3177 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3178 getF32Constant(DAG, 0x3924b03e)); 3179 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3180 getF32Constant(DAG, 0x3ab24b87)); 3181 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3182 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3183 getF32Constant(DAG, 0x3c1d8c17)); 3184 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3185 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3186 getF32Constant(DAG, 0x3d634a1d)); 3187 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3188 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3189 getF32Constant(DAG, 0x3e75fe14)); 3190 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3191 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3192 getF32Constant(DAG, 0x3f317234)); 3193 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3194 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3195 getF32Constant(DAG, 0x3f800000)); 3196 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3197 MVT::i32, t13); 3198 3199 // Add the exponent into the result in integer domain. 3200 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3201 TwoToFracPartOfX, IntegerPartOfX); 3202 3203 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3204 } 3205 } else { 3206 // No special expansion. 3207 result = DAG.getNode(ISD::FEXP, dl, 3208 getValue(I.getOperand(1)).getValueType(), 3209 getValue(I.getOperand(1))); 3210 } 3211 3212 setValue(&I, result); 3213} 3214 3215/// visitLog - Lower a log intrinsic. Handles the special sequences for 3216/// limited-precision mode. 3217void 3218SelectionDAGBuilder::visitLog(const CallInst &I) { 3219 SDValue result; 3220 DebugLoc dl = getCurDebugLoc(); 3221 3222 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3223 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3224 SDValue Op = getValue(I.getOperand(1)); 3225 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3226 3227 // Scale the exponent by log(2) [0.69314718f]. 3228 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3229 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3230 getF32Constant(DAG, 0x3f317218)); 3231 3232 // Get the significand and build it into a floating-point number with 3233 // exponent of 1. 3234 SDValue X = GetSignificand(DAG, Op1, dl); 3235 3236 if (LimitFloatPrecision <= 6) { 3237 // For floating-point precision of 6: 3238 // 3239 // LogofMantissa = 3240 // -1.1609546f + 3241 // (1.4034025f - 0.23903021f * x) * x; 3242 // 3243 // error 0.0034276066, which is better than 8 bits 3244 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3245 getF32Constant(DAG, 0xbe74c456)); 3246 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3247 getF32Constant(DAG, 0x3fb3a2b1)); 3248 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3249 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3250 getF32Constant(DAG, 0x3f949a29)); 3251 3252 result = DAG.getNode(ISD::FADD, dl, 3253 MVT::f32, LogOfExponent, LogOfMantissa); 3254 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3255 // For floating-point precision of 12: 3256 // 3257 // LogOfMantissa = 3258 // -1.7417939f + 3259 // (2.8212026f + 3260 // (-1.4699568f + 3261 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3262 // 3263 // error 0.000061011436, which is 14 bits 3264 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3265 getF32Constant(DAG, 0xbd67b6d6)); 3266 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3267 getF32Constant(DAG, 0x3ee4f4b8)); 3268 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3269 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3270 getF32Constant(DAG, 0x3fbc278b)); 3271 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3272 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3273 getF32Constant(DAG, 0x40348e95)); 3274 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3275 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3276 getF32Constant(DAG, 0x3fdef31a)); 3277 3278 result = DAG.getNode(ISD::FADD, dl, 3279 MVT::f32, LogOfExponent, LogOfMantissa); 3280 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3281 // For floating-point precision of 18: 3282 // 3283 // LogOfMantissa = 3284 // -2.1072184f + 3285 // (4.2372794f + 3286 // (-3.7029485f + 3287 // (2.2781945f + 3288 // (-0.87823314f + 3289 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3290 // 3291 // error 0.0000023660568, which is better than 18 bits 3292 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3293 getF32Constant(DAG, 0xbc91e5ac)); 3294 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3295 getF32Constant(DAG, 0x3e4350aa)); 3296 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3297 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3298 getF32Constant(DAG, 0x3f60d3e3)); 3299 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3300 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3301 getF32Constant(DAG, 0x4011cdf0)); 3302 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3303 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3304 getF32Constant(DAG, 0x406cfd1c)); 3305 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3306 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3307 getF32Constant(DAG, 0x408797cb)); 3308 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3309 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3310 getF32Constant(DAG, 0x4006dcab)); 3311 3312 result = DAG.getNode(ISD::FADD, dl, 3313 MVT::f32, LogOfExponent, LogOfMantissa); 3314 } 3315 } else { 3316 // No special expansion. 3317 result = DAG.getNode(ISD::FLOG, dl, 3318 getValue(I.getOperand(1)).getValueType(), 3319 getValue(I.getOperand(1))); 3320 } 3321 3322 setValue(&I, result); 3323} 3324 3325/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3326/// limited-precision mode. 3327void 3328SelectionDAGBuilder::visitLog2(const CallInst &I) { 3329 SDValue result; 3330 DebugLoc dl = getCurDebugLoc(); 3331 3332 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3333 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3334 SDValue Op = getValue(I.getOperand(1)); 3335 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3336 3337 // Get the exponent. 3338 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3339 3340 // Get the significand and build it into a floating-point number with 3341 // exponent of 1. 3342 SDValue X = GetSignificand(DAG, Op1, dl); 3343 3344 // Different possible minimax approximations of significand in 3345 // floating-point for various degrees of accuracy over [1,2]. 3346 if (LimitFloatPrecision <= 6) { 3347 // For floating-point precision of 6: 3348 // 3349 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3350 // 3351 // error 0.0049451742, which is more than 7 bits 3352 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3353 getF32Constant(DAG, 0xbeb08fe0)); 3354 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3355 getF32Constant(DAG, 0x40019463)); 3356 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3357 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3358 getF32Constant(DAG, 0x3fd6633d)); 3359 3360 result = DAG.getNode(ISD::FADD, dl, 3361 MVT::f32, LogOfExponent, Log2ofMantissa); 3362 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3363 // For floating-point precision of 12: 3364 // 3365 // Log2ofMantissa = 3366 // -2.51285454f + 3367 // (4.07009056f + 3368 // (-2.12067489f + 3369 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3370 // 3371 // error 0.0000876136000, which is better than 13 bits 3372 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3373 getF32Constant(DAG, 0xbda7262e)); 3374 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3375 getF32Constant(DAG, 0x3f25280b)); 3376 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3377 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3378 getF32Constant(DAG, 0x4007b923)); 3379 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3380 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3381 getF32Constant(DAG, 0x40823e2f)); 3382 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3383 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3384 getF32Constant(DAG, 0x4020d29c)); 3385 3386 result = DAG.getNode(ISD::FADD, dl, 3387 MVT::f32, LogOfExponent, Log2ofMantissa); 3388 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3389 // For floating-point precision of 18: 3390 // 3391 // Log2ofMantissa = 3392 // -3.0400495f + 3393 // (6.1129976f + 3394 // (-5.3420409f + 3395 // (3.2865683f + 3396 // (-1.2669343f + 3397 // (0.27515199f - 3398 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3399 // 3400 // error 0.0000018516, which is better than 18 bits 3401 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3402 getF32Constant(DAG, 0xbcd2769e)); 3403 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3404 getF32Constant(DAG, 0x3e8ce0b9)); 3405 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3406 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3407 getF32Constant(DAG, 0x3fa22ae7)); 3408 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3409 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3410 getF32Constant(DAG, 0x40525723)); 3411 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3412 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3413 getF32Constant(DAG, 0x40aaf200)); 3414 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3415 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3416 getF32Constant(DAG, 0x40c39dad)); 3417 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3418 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3419 getF32Constant(DAG, 0x4042902c)); 3420 3421 result = DAG.getNode(ISD::FADD, dl, 3422 MVT::f32, LogOfExponent, Log2ofMantissa); 3423 } 3424 } else { 3425 // No special expansion. 3426 result = DAG.getNode(ISD::FLOG2, dl, 3427 getValue(I.getOperand(1)).getValueType(), 3428 getValue(I.getOperand(1))); 3429 } 3430 3431 setValue(&I, result); 3432} 3433 3434/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3435/// limited-precision mode. 3436void 3437SelectionDAGBuilder::visitLog10(const CallInst &I) { 3438 SDValue result; 3439 DebugLoc dl = getCurDebugLoc(); 3440 3441 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3442 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3443 SDValue Op = getValue(I.getOperand(1)); 3444 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3445 3446 // Scale the exponent by log10(2) [0.30102999f]. 3447 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3448 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3449 getF32Constant(DAG, 0x3e9a209a)); 3450 3451 // Get the significand and build it into a floating-point number with 3452 // exponent of 1. 3453 SDValue X = GetSignificand(DAG, Op1, dl); 3454 3455 if (LimitFloatPrecision <= 6) { 3456 // For floating-point precision of 6: 3457 // 3458 // Log10ofMantissa = 3459 // -0.50419619f + 3460 // (0.60948995f - 0.10380950f * x) * x; 3461 // 3462 // error 0.0014886165, which is 6 bits 3463 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3464 getF32Constant(DAG, 0xbdd49a13)); 3465 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3466 getF32Constant(DAG, 0x3f1c0789)); 3467 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3468 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3469 getF32Constant(DAG, 0x3f011300)); 3470 3471 result = DAG.getNode(ISD::FADD, dl, 3472 MVT::f32, LogOfExponent, Log10ofMantissa); 3473 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3474 // For floating-point precision of 12: 3475 // 3476 // Log10ofMantissa = 3477 // -0.64831180f + 3478 // (0.91751397f + 3479 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3480 // 3481 // error 0.00019228036, which is better than 12 bits 3482 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3483 getF32Constant(DAG, 0x3d431f31)); 3484 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3485 getF32Constant(DAG, 0x3ea21fb2)); 3486 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3487 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3488 getF32Constant(DAG, 0x3f6ae232)); 3489 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3490 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3491 getF32Constant(DAG, 0x3f25f7c3)); 3492 3493 result = DAG.getNode(ISD::FADD, dl, 3494 MVT::f32, LogOfExponent, Log10ofMantissa); 3495 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3496 // For floating-point precision of 18: 3497 // 3498 // Log10ofMantissa = 3499 // -0.84299375f + 3500 // (1.5327582f + 3501 // (-1.0688956f + 3502 // (0.49102474f + 3503 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3504 // 3505 // error 0.0000037995730, which is better than 18 bits 3506 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3507 getF32Constant(DAG, 0x3c5d51ce)); 3508 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3509 getF32Constant(DAG, 0x3e00685a)); 3510 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3511 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3512 getF32Constant(DAG, 0x3efb6798)); 3513 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3514 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3515 getF32Constant(DAG, 0x3f88d192)); 3516 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3517 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3518 getF32Constant(DAG, 0x3fc4316c)); 3519 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3520 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3521 getF32Constant(DAG, 0x3f57ce70)); 3522 3523 result = DAG.getNode(ISD::FADD, dl, 3524 MVT::f32, LogOfExponent, Log10ofMantissa); 3525 } 3526 } else { 3527 // No special expansion. 3528 result = DAG.getNode(ISD::FLOG10, dl, 3529 getValue(I.getOperand(1)).getValueType(), 3530 getValue(I.getOperand(1))); 3531 } 3532 3533 setValue(&I, result); 3534} 3535 3536/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3537/// limited-precision mode. 3538void 3539SelectionDAGBuilder::visitExp2(const CallInst &I) { 3540 SDValue result; 3541 DebugLoc dl = getCurDebugLoc(); 3542 3543 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3544 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3545 SDValue Op = getValue(I.getOperand(1)); 3546 3547 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3548 3549 // FractionalPartOfX = x - (float)IntegerPartOfX; 3550 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3551 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3552 3553 // IntegerPartOfX <<= 23; 3554 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3555 DAG.getConstant(23, TLI.getPointerTy())); 3556 3557 if (LimitFloatPrecision <= 6) { 3558 // For floating-point precision of 6: 3559 // 3560 // TwoToFractionalPartOfX = 3561 // 0.997535578f + 3562 // (0.735607626f + 0.252464424f * x) * x; 3563 // 3564 // error 0.0144103317, which is 6 bits 3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3566 getF32Constant(DAG, 0x3e814304)); 3567 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3568 getF32Constant(DAG, 0x3f3c50c8)); 3569 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3570 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3571 getF32Constant(DAG, 0x3f7f5e7e)); 3572 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3573 SDValue TwoToFractionalPartOfX = 3574 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3575 3576 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3577 MVT::f32, TwoToFractionalPartOfX); 3578 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3579 // For floating-point precision of 12: 3580 // 3581 // TwoToFractionalPartOfX = 3582 // 0.999892986f + 3583 // (0.696457318f + 3584 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3585 // 3586 // error 0.000107046256, which is 13 to 14 bits 3587 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3588 getF32Constant(DAG, 0x3da235e3)); 3589 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3590 getF32Constant(DAG, 0x3e65b8f3)); 3591 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3592 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3593 getF32Constant(DAG, 0x3f324b07)); 3594 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3595 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3596 getF32Constant(DAG, 0x3f7ff8fd)); 3597 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3598 SDValue TwoToFractionalPartOfX = 3599 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3600 3601 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3602 MVT::f32, TwoToFractionalPartOfX); 3603 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3604 // For floating-point precision of 18: 3605 // 3606 // TwoToFractionalPartOfX = 3607 // 0.999999982f + 3608 // (0.693148872f + 3609 // (0.240227044f + 3610 // (0.554906021e-1f + 3611 // (0.961591928e-2f + 3612 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3613 // error 2.47208000*10^(-7), which is better than 18 bits 3614 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3615 getF32Constant(DAG, 0x3924b03e)); 3616 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3617 getF32Constant(DAG, 0x3ab24b87)); 3618 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3619 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3620 getF32Constant(DAG, 0x3c1d8c17)); 3621 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3622 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3623 getF32Constant(DAG, 0x3d634a1d)); 3624 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3625 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3626 getF32Constant(DAG, 0x3e75fe14)); 3627 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3628 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3629 getF32Constant(DAG, 0x3f317234)); 3630 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3631 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3632 getF32Constant(DAG, 0x3f800000)); 3633 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3634 SDValue TwoToFractionalPartOfX = 3635 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3636 3637 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3638 MVT::f32, TwoToFractionalPartOfX); 3639 } 3640 } else { 3641 // No special expansion. 3642 result = DAG.getNode(ISD::FEXP2, dl, 3643 getValue(I.getOperand(1)).getValueType(), 3644 getValue(I.getOperand(1))); 3645 } 3646 3647 setValue(&I, result); 3648} 3649 3650/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3651/// limited-precision mode with x == 10.0f. 3652void 3653SelectionDAGBuilder::visitPow(const CallInst &I) { 3654 SDValue result; 3655 const Value *Val = I.getOperand(1); 3656 DebugLoc dl = getCurDebugLoc(); 3657 bool IsExp10 = false; 3658 3659 if (getValue(Val).getValueType() == MVT::f32 && 3660 getValue(I.getOperand(2)).getValueType() == MVT::f32 && 3661 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3662 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3663 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3664 APFloat Ten(10.0f); 3665 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3666 } 3667 } 3668 } 3669 3670 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3671 SDValue Op = getValue(I.getOperand(2)); 3672 3673 // Put the exponent in the right bit position for later addition to the 3674 // final result: 3675 // 3676 // #define LOG2OF10 3.3219281f 3677 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3678 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3679 getF32Constant(DAG, 0x40549a78)); 3680 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3681 3682 // FractionalPartOfX = x - (float)IntegerPartOfX; 3683 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3684 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3685 3686 // IntegerPartOfX <<= 23; 3687 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3688 DAG.getConstant(23, TLI.getPointerTy())); 3689 3690 if (LimitFloatPrecision <= 6) { 3691 // For floating-point precision of 6: 3692 // 3693 // twoToFractionalPartOfX = 3694 // 0.997535578f + 3695 // (0.735607626f + 0.252464424f * x) * x; 3696 // 3697 // error 0.0144103317, which is 6 bits 3698 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3699 getF32Constant(DAG, 0x3e814304)); 3700 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3701 getF32Constant(DAG, 0x3f3c50c8)); 3702 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3703 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3704 getF32Constant(DAG, 0x3f7f5e7e)); 3705 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3706 SDValue TwoToFractionalPartOfX = 3707 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3708 3709 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3710 MVT::f32, TwoToFractionalPartOfX); 3711 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3712 // For floating-point precision of 12: 3713 // 3714 // TwoToFractionalPartOfX = 3715 // 0.999892986f + 3716 // (0.696457318f + 3717 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3718 // 3719 // error 0.000107046256, which is 13 to 14 bits 3720 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3721 getF32Constant(DAG, 0x3da235e3)); 3722 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3723 getF32Constant(DAG, 0x3e65b8f3)); 3724 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3725 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3726 getF32Constant(DAG, 0x3f324b07)); 3727 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3728 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3729 getF32Constant(DAG, 0x3f7ff8fd)); 3730 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3731 SDValue TwoToFractionalPartOfX = 3732 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3733 3734 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3735 MVT::f32, TwoToFractionalPartOfX); 3736 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3737 // For floating-point precision of 18: 3738 // 3739 // TwoToFractionalPartOfX = 3740 // 0.999999982f + 3741 // (0.693148872f + 3742 // (0.240227044f + 3743 // (0.554906021e-1f + 3744 // (0.961591928e-2f + 3745 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3746 // error 2.47208000*10^(-7), which is better than 18 bits 3747 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3748 getF32Constant(DAG, 0x3924b03e)); 3749 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3750 getF32Constant(DAG, 0x3ab24b87)); 3751 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3752 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3753 getF32Constant(DAG, 0x3c1d8c17)); 3754 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3755 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3756 getF32Constant(DAG, 0x3d634a1d)); 3757 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3758 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3759 getF32Constant(DAG, 0x3e75fe14)); 3760 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3761 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3762 getF32Constant(DAG, 0x3f317234)); 3763 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3764 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3765 getF32Constant(DAG, 0x3f800000)); 3766 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3767 SDValue TwoToFractionalPartOfX = 3768 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3769 3770 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3771 MVT::f32, TwoToFractionalPartOfX); 3772 } 3773 } else { 3774 // No special expansion. 3775 result = DAG.getNode(ISD::FPOW, dl, 3776 getValue(I.getOperand(1)).getValueType(), 3777 getValue(I.getOperand(1)), 3778 getValue(I.getOperand(2))); 3779 } 3780 3781 setValue(&I, result); 3782} 3783 3784 3785/// ExpandPowI - Expand a llvm.powi intrinsic. 3786static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3787 SelectionDAG &DAG) { 3788 // If RHS is a constant, we can expand this out to a multiplication tree, 3789 // otherwise we end up lowering to a call to __powidf2 (for example). When 3790 // optimizing for size, we only want to do this if the expansion would produce 3791 // a small number of multiplies, otherwise we do the full expansion. 3792 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3793 // Get the exponent as a positive value. 3794 unsigned Val = RHSC->getSExtValue(); 3795 if ((int)Val < 0) Val = -Val; 3796 3797 // powi(x, 0) -> 1.0 3798 if (Val == 0) 3799 return DAG.getConstantFP(1.0, LHS.getValueType()); 3800 3801 const Function *F = DAG.getMachineFunction().getFunction(); 3802 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3803 // If optimizing for size, don't insert too many multiplies. This 3804 // inserts up to 5 multiplies. 3805 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3806 // We use the simple binary decomposition method to generate the multiply 3807 // sequence. There are more optimal ways to do this (for example, 3808 // powi(x,15) generates one more multiply than it should), but this has 3809 // the benefit of being both really simple and much better than a libcall. 3810 SDValue Res; // Logically starts equal to 1.0 3811 SDValue CurSquare = LHS; 3812 while (Val) { 3813 if (Val & 1) { 3814 if (Res.getNode()) 3815 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3816 else 3817 Res = CurSquare; // 1.0*CurSquare. 3818 } 3819 3820 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3821 CurSquare, CurSquare); 3822 Val >>= 1; 3823 } 3824 3825 // If the original was negative, invert the result, producing 1/(x*x*x). 3826 if (RHSC->getSExtValue() < 0) 3827 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3828 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3829 return Res; 3830 } 3831 } 3832 3833 // Otherwise, expand to a libcall. 3834 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3835} 3836 3837/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3838/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3839/// At the end of instruction selection, they will be inserted to the entry BB. 3840bool 3841SelectionDAGBuilder::EmitFuncArgumentDbgValue(const DbgValueInst &DI, 3842 const Value *V, MDNode *Variable, 3843 uint64_t Offset, 3844 const SDValue &N) { 3845 if (!isa<Argument>(V)) 3846 return false; 3847 3848 MachineFunction &MF = DAG.getMachineFunction(); 3849 // Ignore inlined function arguments here. 3850 DIVariable DV(Variable); 3851 if (DV.isInlinedFnArgument(MF.getFunction())) 3852 return false; 3853 3854 MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()]; 3855 if (MBB != &MF.front()) 3856 return false; 3857 3858 unsigned Reg = 0; 3859 if (N.getOpcode() == ISD::CopyFromReg) { 3860 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3861 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3862 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3863 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3864 if (PR) 3865 Reg = PR; 3866 } 3867 } 3868 3869 if (!Reg) { 3870 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3871 if (VMI == FuncInfo.ValueMap.end()) 3872 return false; 3873 Reg = VMI->second; 3874 } 3875 3876 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3877 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3878 TII->get(TargetOpcode::DBG_VALUE)) 3879 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 3880 FuncInfo.ArgDbgValues.push_back(&*MIB); 3881 return true; 3882} 3883 3884// VisualStudio defines setjmp as _setjmp 3885#if defined(_MSC_VER) && defined(setjmp) 3886#define setjmp_undefined_for_visual_studio 3887#undef setjmp 3888#endif 3889 3890/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3891/// we want to emit this as a call to a named external function, return the name 3892/// otherwise lower it and return null. 3893const char * 3894SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3895 DebugLoc dl = getCurDebugLoc(); 3896 SDValue Res; 3897 3898 switch (Intrinsic) { 3899 default: 3900 // By default, turn this into a target intrinsic node. 3901 visitTargetIntrinsic(I, Intrinsic); 3902 return 0; 3903 case Intrinsic::vastart: visitVAStart(I); return 0; 3904 case Intrinsic::vaend: visitVAEnd(I); return 0; 3905 case Intrinsic::vacopy: visitVACopy(I); return 0; 3906 case Intrinsic::returnaddress: 3907 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3908 getValue(I.getOperand(1)))); 3909 return 0; 3910 case Intrinsic::frameaddress: 3911 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3912 getValue(I.getOperand(1)))); 3913 return 0; 3914 case Intrinsic::setjmp: 3915 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3916 case Intrinsic::longjmp: 3917 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3918 case Intrinsic::memcpy: { 3919 // Assert for address < 256 since we support only user defined address 3920 // spaces. 3921 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3922 < 256 && 3923 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace() 3924 < 256 && 3925 "Unknown address space"); 3926 SDValue Op1 = getValue(I.getOperand(1)); 3927 SDValue Op2 = getValue(I.getOperand(2)); 3928 SDValue Op3 = getValue(I.getOperand(3)); 3929 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3930 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3931 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 3932 I.getOperand(1), 0, I.getOperand(2), 0)); 3933 return 0; 3934 } 3935 case Intrinsic::memset: { 3936 // Assert for address < 256 since we support only user defined address 3937 // spaces. 3938 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3939 < 256 && 3940 "Unknown address space"); 3941 SDValue Op1 = getValue(I.getOperand(1)); 3942 SDValue Op2 = getValue(I.getOperand(2)); 3943 SDValue Op3 = getValue(I.getOperand(3)); 3944 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3945 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3946 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3947 I.getOperand(1), 0)); 3948 return 0; 3949 } 3950 case Intrinsic::memmove: { 3951 // Assert for address < 256 since we support only user defined address 3952 // spaces. 3953 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3954 < 256 && 3955 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace() 3956 < 256 && 3957 "Unknown address space"); 3958 SDValue Op1 = getValue(I.getOperand(1)); 3959 SDValue Op2 = getValue(I.getOperand(2)); 3960 SDValue Op3 = getValue(I.getOperand(3)); 3961 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3962 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3963 3964 // If the source and destination are known to not be aliases, we can 3965 // lower memmove as memcpy. 3966 uint64_t Size = -1ULL; 3967 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3968 Size = C->getZExtValue(); 3969 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3970 AliasAnalysis::NoAlias) { 3971 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3972 false, I.getOperand(1), 0, I.getOperand(2), 0)); 3973 return 0; 3974 } 3975 3976 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3977 I.getOperand(1), 0, I.getOperand(2), 0)); 3978 return 0; 3979 } 3980 case Intrinsic::dbg_declare: { 3981 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3982 if (!DIVariable(DI.getVariable()).Verify()) 3983 return 0; 3984 3985 MDNode *Variable = DI.getVariable(); 3986 // Parameters are handled specially. 3987 bool isParameter = 3988 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 3989 const Value *Address = DI.getAddress(); 3990 if (!Address) 3991 return 0; 3992 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 3993 Address = BCI->getOperand(0); 3994 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 3995 if (AI) { 3996 // Don't handle byval arguments or VLAs, for example. 3997 // Non-byval arguments are handled here (they refer to the stack temporary 3998 // alloca at this point). 3999 DenseMap<const AllocaInst*, int>::iterator SI = 4000 FuncInfo.StaticAllocaMap.find(AI); 4001 if (SI == FuncInfo.StaticAllocaMap.end()) 4002 return 0; // VLAs. 4003 int FI = SI->second; 4004 4005 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4006 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4007 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4008 } 4009 4010 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4011 // but do not always have a corresponding SDNode built. The SDNodeOrder 4012 // absolute, but not relative, values are different depending on whether 4013 // debug info exists. 4014 ++SDNodeOrder; 4015 SDValue &N = NodeMap[Address]; 4016 SDDbgValue *SDV; 4017 if (N.getNode()) { 4018 if (isParameter && !AI) { 4019 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4020 if (FINode) 4021 // Byval parameter. We have a frame index at this point. 4022 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4023 0, dl, SDNodeOrder); 4024 else 4025 // Can't do anything with other non-AI cases yet. This might be a 4026 // parameter of a callee function that got inlined, for example. 4027 return 0; 4028 } else if (AI) 4029 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4030 0, dl, SDNodeOrder); 4031 else 4032 // Can't do anything with other non-AI cases yet. 4033 return 0; 4034 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4035 } else { 4036 // This isn't useful, but it shows what we're missing. 4037 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4038 0, dl, SDNodeOrder); 4039 DAG.AddDbgValue(SDV, 0, isParameter); 4040 } 4041 return 0; 4042 } 4043 case Intrinsic::dbg_value: { 4044 const DbgValueInst &DI = cast<DbgValueInst>(I); 4045 if (!DIVariable(DI.getVariable()).Verify()) 4046 return 0; 4047 4048 MDNode *Variable = DI.getVariable(); 4049 uint64_t Offset = DI.getOffset(); 4050 const Value *V = DI.getValue(); 4051 if (!V) 4052 return 0; 4053 4054 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4055 // but do not always have a corresponding SDNode built. The SDNodeOrder 4056 // absolute, but not relative, values are different depending on whether 4057 // debug info exists. 4058 ++SDNodeOrder; 4059 SDDbgValue *SDV; 4060 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4061 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4062 DAG.AddDbgValue(SDV, 0, false); 4063 } else { 4064 bool createUndef = false; 4065 // FIXME : Why not use getValue() directly ? 4066 SDValue &N = NodeMap[V]; 4067 if (N.getNode()) { 4068 if (!EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N)) { 4069 SDV = DAG.getDbgValue(Variable, N.getNode(), 4070 N.getResNo(), Offset, dl, SDNodeOrder); 4071 DAG.AddDbgValue(SDV, N.getNode(), false); 4072 } 4073 } else if (isa<PHINode>(V) && !V->use_empty()) { 4074 SDValue N = getValue(V); 4075 if (N.getNode()) { 4076 if (!EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N)) { 4077 SDV = DAG.getDbgValue(Variable, N.getNode(), 4078 N.getResNo(), Offset, dl, SDNodeOrder); 4079 DAG.AddDbgValue(SDV, N.getNode(), false); 4080 } 4081 } else 4082 createUndef = true; 4083 } else 4084 createUndef = true; 4085 if (createUndef) { 4086 // We may expand this to cover more cases. One case where we have no 4087 // data available is an unreferenced parameter; we need this fallback. 4088 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4089 Offset, dl, SDNodeOrder); 4090 DAG.AddDbgValue(SDV, 0, false); 4091 } 4092 } 4093 4094 // Build a debug info table entry. 4095 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4096 V = BCI->getOperand(0); 4097 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4098 // Don't handle byval struct arguments or VLAs, for example. 4099 if (!AI) 4100 return 0; 4101 DenseMap<const AllocaInst*, int>::iterator SI = 4102 FuncInfo.StaticAllocaMap.find(AI); 4103 if (SI == FuncInfo.StaticAllocaMap.end()) 4104 return 0; // VLAs. 4105 int FI = SI->second; 4106 4107 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4108 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4109 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4110 return 0; 4111 } 4112 case Intrinsic::eh_exception: { 4113 // Insert the EXCEPTIONADDR instruction. 4114 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() && 4115 "Call to eh.exception not in landing pad!"); 4116 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4117 SDValue Ops[1]; 4118 Ops[0] = DAG.getRoot(); 4119 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4120 setValue(&I, Op); 4121 DAG.setRoot(Op.getValue(1)); 4122 return 0; 4123 } 4124 4125 case Intrinsic::eh_selector: { 4126 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()]; 4127 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4128 if (CallMBB->isLandingPad()) 4129 AddCatchInfo(I, &MMI, CallMBB); 4130 else { 4131#ifndef NDEBUG 4132 FuncInfo.CatchInfoLost.insert(&I); 4133#endif 4134 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4135 unsigned Reg = TLI.getExceptionSelectorRegister(); 4136 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg); 4137 } 4138 4139 // Insert the EHSELECTION instruction. 4140 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4141 SDValue Ops[2]; 4142 Ops[0] = getValue(I.getOperand(1)); 4143 Ops[1] = getRoot(); 4144 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4145 DAG.setRoot(Op.getValue(1)); 4146 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4147 return 0; 4148 } 4149 4150 case Intrinsic::eh_typeid_for: { 4151 // Find the type id for the given typeinfo. 4152 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 4153 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4154 Res = DAG.getConstant(TypeID, MVT::i32); 4155 setValue(&I, Res); 4156 return 0; 4157 } 4158 4159 case Intrinsic::eh_return_i32: 4160 case Intrinsic::eh_return_i64: 4161 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4162 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4163 MVT::Other, 4164 getControlRoot(), 4165 getValue(I.getOperand(1)), 4166 getValue(I.getOperand(2)))); 4167 return 0; 4168 case Intrinsic::eh_unwind_init: 4169 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4170 return 0; 4171 case Intrinsic::eh_dwarf_cfa: { 4172 EVT VT = getValue(I.getOperand(1)).getValueType(); 4173 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl, 4174 TLI.getPointerTy()); 4175 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4176 TLI.getPointerTy(), 4177 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4178 TLI.getPointerTy()), 4179 CfaArg); 4180 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4181 TLI.getPointerTy(), 4182 DAG.getConstant(0, TLI.getPointerTy())); 4183 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4184 FA, Offset)); 4185 return 0; 4186 } 4187 case Intrinsic::eh_sjlj_callsite: { 4188 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4189 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 4190 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4191 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4192 4193 MMI.setCurrentCallSite(CI->getZExtValue()); 4194 return 0; 4195 } 4196 case Intrinsic::eh_sjlj_setjmp: { 4197 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4198 getValue(I.getOperand(1)))); 4199 return 0; 4200 } 4201 case Intrinsic::eh_sjlj_longjmp: { 4202 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4203 getRoot(), 4204 getValue(I.getOperand(1)))); 4205 return 0; 4206 } 4207 4208 case Intrinsic::convertff: 4209 case Intrinsic::convertfsi: 4210 case Intrinsic::convertfui: 4211 case Intrinsic::convertsif: 4212 case Intrinsic::convertuif: 4213 case Intrinsic::convertss: 4214 case Intrinsic::convertsu: 4215 case Intrinsic::convertus: 4216 case Intrinsic::convertuu: { 4217 ISD::CvtCode Code = ISD::CVT_INVALID; 4218 switch (Intrinsic) { 4219 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4220 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4221 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4222 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4223 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4224 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4225 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4226 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4227 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4228 } 4229 EVT DestVT = TLI.getValueType(I.getType()); 4230 const Value *Op1 = I.getOperand(1); 4231 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4232 DAG.getValueType(DestVT), 4233 DAG.getValueType(getValue(Op1).getValueType()), 4234 getValue(I.getOperand(2)), 4235 getValue(I.getOperand(3)), 4236 Code); 4237 setValue(&I, Res); 4238 return 0; 4239 } 4240 case Intrinsic::sqrt: 4241 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4242 getValue(I.getOperand(1)).getValueType(), 4243 getValue(I.getOperand(1)))); 4244 return 0; 4245 case Intrinsic::powi: 4246 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)), 4247 getValue(I.getOperand(2)), DAG)); 4248 return 0; 4249 case Intrinsic::sin: 4250 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4251 getValue(I.getOperand(1)).getValueType(), 4252 getValue(I.getOperand(1)))); 4253 return 0; 4254 case Intrinsic::cos: 4255 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4256 getValue(I.getOperand(1)).getValueType(), 4257 getValue(I.getOperand(1)))); 4258 return 0; 4259 case Intrinsic::log: 4260 visitLog(I); 4261 return 0; 4262 case Intrinsic::log2: 4263 visitLog2(I); 4264 return 0; 4265 case Intrinsic::log10: 4266 visitLog10(I); 4267 return 0; 4268 case Intrinsic::exp: 4269 visitExp(I); 4270 return 0; 4271 case Intrinsic::exp2: 4272 visitExp2(I); 4273 return 0; 4274 case Intrinsic::pow: 4275 visitPow(I); 4276 return 0; 4277 case Intrinsic::convert_to_fp16: 4278 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4279 MVT::i16, getValue(I.getOperand(1)))); 4280 return 0; 4281 case Intrinsic::convert_from_fp16: 4282 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4283 MVT::f32, getValue(I.getOperand(1)))); 4284 return 0; 4285 case Intrinsic::pcmarker: { 4286 SDValue Tmp = getValue(I.getOperand(1)); 4287 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4288 return 0; 4289 } 4290 case Intrinsic::readcyclecounter: { 4291 SDValue Op = getRoot(); 4292 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4293 DAG.getVTList(MVT::i64, MVT::Other), 4294 &Op, 1); 4295 setValue(&I, Res); 4296 DAG.setRoot(Res.getValue(1)); 4297 return 0; 4298 } 4299 case Intrinsic::bswap: 4300 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4301 getValue(I.getOperand(1)).getValueType(), 4302 getValue(I.getOperand(1)))); 4303 return 0; 4304 case Intrinsic::cttz: { 4305 SDValue Arg = getValue(I.getOperand(1)); 4306 EVT Ty = Arg.getValueType(); 4307 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4308 return 0; 4309 } 4310 case Intrinsic::ctlz: { 4311 SDValue Arg = getValue(I.getOperand(1)); 4312 EVT Ty = Arg.getValueType(); 4313 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4314 return 0; 4315 } 4316 case Intrinsic::ctpop: { 4317 SDValue Arg = getValue(I.getOperand(1)); 4318 EVT Ty = Arg.getValueType(); 4319 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4320 return 0; 4321 } 4322 case Intrinsic::stacksave: { 4323 SDValue Op = getRoot(); 4324 Res = DAG.getNode(ISD::STACKSAVE, dl, 4325 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4326 setValue(&I, Res); 4327 DAG.setRoot(Res.getValue(1)); 4328 return 0; 4329 } 4330 case Intrinsic::stackrestore: { 4331 Res = getValue(I.getOperand(1)); 4332 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4333 return 0; 4334 } 4335 case Intrinsic::stackprotector: { 4336 // Emit code into the DAG to store the stack guard onto the stack. 4337 MachineFunction &MF = DAG.getMachineFunction(); 4338 MachineFrameInfo *MFI = MF.getFrameInfo(); 4339 EVT PtrTy = TLI.getPointerTy(); 4340 4341 SDValue Src = getValue(I.getOperand(1)); // The guard's value. 4342 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 4343 4344 int FI = FuncInfo.StaticAllocaMap[Slot]; 4345 MFI->setStackProtectorIndex(FI); 4346 4347 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4348 4349 // Store the stack protector onto the stack. 4350 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4351 PseudoSourceValue::getFixedStack(FI), 4352 0, true, false, 0); 4353 setValue(&I, Res); 4354 DAG.setRoot(Res); 4355 return 0; 4356 } 4357 case Intrinsic::objectsize: { 4358 // If we don't know by now, we're never going to know. 4359 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 4360 4361 assert(CI && "Non-constant type in __builtin_object_size?"); 4362 4363 SDValue Arg = getValue(I.getOperand(0)); 4364 EVT Ty = Arg.getValueType(); 4365 4366 if (CI->getZExtValue() == 0) 4367 Res = DAG.getConstant(-1ULL, Ty); 4368 else 4369 Res = DAG.getConstant(0, Ty); 4370 4371 setValue(&I, Res); 4372 return 0; 4373 } 4374 case Intrinsic::var_annotation: 4375 // Discard annotate attributes 4376 return 0; 4377 4378 case Intrinsic::init_trampoline: { 4379 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 4380 4381 SDValue Ops[6]; 4382 Ops[0] = getRoot(); 4383 Ops[1] = getValue(I.getOperand(1)); 4384 Ops[2] = getValue(I.getOperand(2)); 4385 Ops[3] = getValue(I.getOperand(3)); 4386 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 4387 Ops[5] = DAG.getSrcValue(F); 4388 4389 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4390 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4391 Ops, 6); 4392 4393 setValue(&I, Res); 4394 DAG.setRoot(Res.getValue(1)); 4395 return 0; 4396 } 4397 case Intrinsic::gcroot: 4398 if (GFI) { 4399 const Value *Alloca = I.getOperand(1); 4400 const Constant *TypeMap = cast<Constant>(I.getOperand(2)); 4401 4402 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4403 GFI->addStackRoot(FI->getIndex(), TypeMap); 4404 } 4405 return 0; 4406 case Intrinsic::gcread: 4407 case Intrinsic::gcwrite: 4408 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4409 return 0; 4410 case Intrinsic::flt_rounds: 4411 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4412 return 0; 4413 case Intrinsic::trap: 4414 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4415 return 0; 4416 case Intrinsic::uadd_with_overflow: 4417 return implVisitAluOverflow(I, ISD::UADDO); 4418 case Intrinsic::sadd_with_overflow: 4419 return implVisitAluOverflow(I, ISD::SADDO); 4420 case Intrinsic::usub_with_overflow: 4421 return implVisitAluOverflow(I, ISD::USUBO); 4422 case Intrinsic::ssub_with_overflow: 4423 return implVisitAluOverflow(I, ISD::SSUBO); 4424 case Intrinsic::umul_with_overflow: 4425 return implVisitAluOverflow(I, ISD::UMULO); 4426 case Intrinsic::smul_with_overflow: 4427 return implVisitAluOverflow(I, ISD::SMULO); 4428 4429 case Intrinsic::prefetch: { 4430 SDValue Ops[4]; 4431 Ops[0] = getRoot(); 4432 Ops[1] = getValue(I.getOperand(1)); 4433 Ops[2] = getValue(I.getOperand(2)); 4434 Ops[3] = getValue(I.getOperand(3)); 4435 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4436 return 0; 4437 } 4438 4439 case Intrinsic::memory_barrier: { 4440 SDValue Ops[6]; 4441 Ops[0] = getRoot(); 4442 for (int x = 1; x < 6; ++x) 4443 Ops[x] = getValue(I.getOperand(x)); 4444 4445 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4446 return 0; 4447 } 4448 case Intrinsic::atomic_cmp_swap: { 4449 SDValue Root = getRoot(); 4450 SDValue L = 4451 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4452 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 4453 Root, 4454 getValue(I.getOperand(1)), 4455 getValue(I.getOperand(2)), 4456 getValue(I.getOperand(3)), 4457 I.getOperand(1)); 4458 setValue(&I, L); 4459 DAG.setRoot(L.getValue(1)); 4460 return 0; 4461 } 4462 case Intrinsic::atomic_load_add: 4463 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4464 case Intrinsic::atomic_load_sub: 4465 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4466 case Intrinsic::atomic_load_or: 4467 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4468 case Intrinsic::atomic_load_xor: 4469 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4470 case Intrinsic::atomic_load_and: 4471 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4472 case Intrinsic::atomic_load_nand: 4473 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4474 case Intrinsic::atomic_load_max: 4475 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4476 case Intrinsic::atomic_load_min: 4477 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4478 case Intrinsic::atomic_load_umin: 4479 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4480 case Intrinsic::atomic_load_umax: 4481 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4482 case Intrinsic::atomic_swap: 4483 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4484 4485 case Intrinsic::invariant_start: 4486 case Intrinsic::lifetime_start: 4487 // Discard region information. 4488 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4489 return 0; 4490 case Intrinsic::invariant_end: 4491 case Intrinsic::lifetime_end: 4492 // Discard region information. 4493 return 0; 4494 } 4495} 4496 4497void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4498 bool isTailCall, 4499 MachineBasicBlock *LandingPad) { 4500 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4501 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4502 const Type *RetTy = FTy->getReturnType(); 4503 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4504 MCSymbol *BeginLabel = 0; 4505 4506 TargetLowering::ArgListTy Args; 4507 TargetLowering::ArgListEntry Entry; 4508 Args.reserve(CS.arg_size()); 4509 4510 // Check whether the function can return without sret-demotion. 4511 SmallVector<EVT, 4> OutVTs; 4512 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 4513 SmallVector<uint64_t, 4> Offsets; 4514 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4515 OutVTs, OutsFlags, TLI, &Offsets); 4516 4517 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4518 FTy->isVarArg(), OutVTs, OutsFlags, DAG); 4519 4520 SDValue DemoteStackSlot; 4521 4522 if (!CanLowerReturn) { 4523 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4524 FTy->getReturnType()); 4525 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4526 FTy->getReturnType()); 4527 MachineFunction &MF = DAG.getMachineFunction(); 4528 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4529 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4530 4531 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4532 Entry.Node = DemoteStackSlot; 4533 Entry.Ty = StackSlotPtrType; 4534 Entry.isSExt = false; 4535 Entry.isZExt = false; 4536 Entry.isInReg = false; 4537 Entry.isSRet = true; 4538 Entry.isNest = false; 4539 Entry.isByVal = false; 4540 Entry.Alignment = Align; 4541 Args.push_back(Entry); 4542 RetTy = Type::getVoidTy(FTy->getContext()); 4543 } 4544 4545 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4546 i != e; ++i) { 4547 SDValue ArgNode = getValue(*i); 4548 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4549 4550 unsigned attrInd = i - CS.arg_begin() + 1; 4551 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4552 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4553 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4554 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4555 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4556 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4557 Entry.Alignment = CS.getParamAlignment(attrInd); 4558 Args.push_back(Entry); 4559 } 4560 4561 if (LandingPad) { 4562 // Insert a label before the invoke call to mark the try range. This can be 4563 // used to detect deletion of the invoke via the MachineModuleInfo. 4564 BeginLabel = MMI.getContext().CreateTempSymbol(); 4565 4566 // For SjLj, keep track of which landing pads go with which invokes 4567 // so as to maintain the ordering of pads in the LSDA. 4568 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4569 if (CallSiteIndex) { 4570 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4571 // Now that the call site is handled, stop tracking it. 4572 MMI.setCurrentCallSite(0); 4573 } 4574 4575 // Both PendingLoads and PendingExports must be flushed here; 4576 // this call might not return. 4577 (void)getRoot(); 4578 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4579 } 4580 4581 // Check if target-independent constraints permit a tail call here. 4582 // Target-dependent constraints are checked within TLI.LowerCallTo. 4583 if (isTailCall && 4584 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4585 isTailCall = false; 4586 4587 std::pair<SDValue,SDValue> Result = 4588 TLI.LowerCallTo(getRoot(), RetTy, 4589 CS.paramHasAttr(0, Attribute::SExt), 4590 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4591 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4592 CS.getCallingConv(), 4593 isTailCall, 4594 !CS.getInstruction()->use_empty(), 4595 Callee, Args, DAG, getCurDebugLoc()); 4596 assert((isTailCall || Result.second.getNode()) && 4597 "Non-null chain expected with non-tail call!"); 4598 assert((Result.second.getNode() || !Result.first.getNode()) && 4599 "Null value expected with tail call!"); 4600 if (Result.first.getNode()) { 4601 setValue(CS.getInstruction(), Result.first); 4602 } else if (!CanLowerReturn && Result.second.getNode()) { 4603 // The instruction result is the result of loading from the 4604 // hidden sret parameter. 4605 SmallVector<EVT, 1> PVTs; 4606 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4607 4608 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4609 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4610 EVT PtrVT = PVTs[0]; 4611 unsigned NumValues = OutVTs.size(); 4612 SmallVector<SDValue, 4> Values(NumValues); 4613 SmallVector<SDValue, 4> Chains(NumValues); 4614 4615 for (unsigned i = 0; i < NumValues; ++i) { 4616 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4617 DemoteStackSlot, 4618 DAG.getConstant(Offsets[i], PtrVT)); 4619 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second, 4620 Add, NULL, Offsets[i], false, false, 1); 4621 Values[i] = L; 4622 Chains[i] = L.getValue(1); 4623 } 4624 4625 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4626 MVT::Other, &Chains[0], NumValues); 4627 PendingLoads.push_back(Chain); 4628 4629 // Collect the legal value parts into potentially illegal values 4630 // that correspond to the original function's return values. 4631 SmallVector<EVT, 4> RetTys; 4632 RetTy = FTy->getReturnType(); 4633 ComputeValueVTs(TLI, RetTy, RetTys); 4634 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4635 SmallVector<SDValue, 4> ReturnValues; 4636 unsigned CurReg = 0; 4637 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4638 EVT VT = RetTys[I]; 4639 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4640 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4641 4642 SDValue ReturnValue = 4643 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4644 RegisterVT, VT, AssertOp); 4645 ReturnValues.push_back(ReturnValue); 4646 CurReg += NumRegs; 4647 } 4648 4649 setValue(CS.getInstruction(), 4650 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4651 DAG.getVTList(&RetTys[0], RetTys.size()), 4652 &ReturnValues[0], ReturnValues.size())); 4653 4654 } 4655 4656 // As a special case, a null chain means that a tail call has been emitted and 4657 // the DAG root is already updated. 4658 if (Result.second.getNode()) 4659 DAG.setRoot(Result.second); 4660 else 4661 HasTailCall = true; 4662 4663 if (LandingPad) { 4664 // Insert a label at the end of the invoke call to mark the try range. This 4665 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4666 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4667 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4668 4669 // Inform MachineModuleInfo of range. 4670 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4671 } 4672} 4673 4674/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4675/// value is equal or not-equal to zero. 4676static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4677 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4678 UI != E; ++UI) { 4679 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4680 if (IC->isEquality()) 4681 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4682 if (C->isNullValue()) 4683 continue; 4684 // Unknown instruction. 4685 return false; 4686 } 4687 return true; 4688} 4689 4690static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4691 const Type *LoadTy, 4692 SelectionDAGBuilder &Builder) { 4693 4694 // Check to see if this load can be trivially constant folded, e.g. if the 4695 // input is from a string literal. 4696 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4697 // Cast pointer to the type we really want to load. 4698 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4699 PointerType::getUnqual(LoadTy)); 4700 4701 if (const Constant *LoadCst = 4702 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4703 Builder.TD)) 4704 return Builder.getValue(LoadCst); 4705 } 4706 4707 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4708 // still constant memory, the input chain can be the entry node. 4709 SDValue Root; 4710 bool ConstantMemory = false; 4711 4712 // Do not serialize (non-volatile) loads of constant memory with anything. 4713 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4714 Root = Builder.DAG.getEntryNode(); 4715 ConstantMemory = true; 4716 } else { 4717 // Do not serialize non-volatile loads against each other. 4718 Root = Builder.DAG.getRoot(); 4719 } 4720 4721 SDValue Ptr = Builder.getValue(PtrVal); 4722 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4723 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/, 4724 false /*volatile*/, 4725 false /*nontemporal*/, 1 /* align=1 */); 4726 4727 if (!ConstantMemory) 4728 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4729 return LoadVal; 4730} 4731 4732 4733/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4734/// If so, return true and lower it, otherwise return false and it will be 4735/// lowered like a normal call. 4736bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4737 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4738 if (I.getNumOperands() != 4) 4739 return false; 4740 4741 const Value *LHS = I.getOperand(1), *RHS = I.getOperand(2); 4742 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4743 !I.getOperand(3)->getType()->isIntegerTy() || 4744 !I.getType()->isIntegerTy()) 4745 return false; 4746 4747 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3)); 4748 4749 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4750 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4751 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4752 bool ActuallyDoIt = true; 4753 MVT LoadVT; 4754 const Type *LoadTy; 4755 switch (Size->getZExtValue()) { 4756 default: 4757 LoadVT = MVT::Other; 4758 LoadTy = 0; 4759 ActuallyDoIt = false; 4760 break; 4761 case 2: 4762 LoadVT = MVT::i16; 4763 LoadTy = Type::getInt16Ty(Size->getContext()); 4764 break; 4765 case 4: 4766 LoadVT = MVT::i32; 4767 LoadTy = Type::getInt32Ty(Size->getContext()); 4768 break; 4769 case 8: 4770 LoadVT = MVT::i64; 4771 LoadTy = Type::getInt64Ty(Size->getContext()); 4772 break; 4773 /* 4774 case 16: 4775 LoadVT = MVT::v4i32; 4776 LoadTy = Type::getInt32Ty(Size->getContext()); 4777 LoadTy = VectorType::get(LoadTy, 4); 4778 break; 4779 */ 4780 } 4781 4782 // This turns into unaligned loads. We only do this if the target natively 4783 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4784 // we'll only produce a small number of byte loads. 4785 4786 // Require that we can find a legal MVT, and only do this if the target 4787 // supports unaligned loads of that type. Expanding into byte loads would 4788 // bloat the code. 4789 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4790 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4791 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4792 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4793 ActuallyDoIt = false; 4794 } 4795 4796 if (ActuallyDoIt) { 4797 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4798 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4799 4800 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4801 ISD::SETNE); 4802 EVT CallVT = TLI.getValueType(I.getType(), true); 4803 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4804 return true; 4805 } 4806 } 4807 4808 4809 return false; 4810} 4811 4812 4813void SelectionDAGBuilder::visitCall(const CallInst &I) { 4814 const char *RenameFn = 0; 4815 if (Function *F = I.getCalledFunction()) { 4816 if (F->isDeclaration()) { 4817 const TargetIntrinsicInfo *II = TM.getIntrinsicInfo(); 4818 if (II) { 4819 if (unsigned IID = II->getIntrinsicID(F)) { 4820 RenameFn = visitIntrinsicCall(I, IID); 4821 if (!RenameFn) 4822 return; 4823 } 4824 } 4825 if (unsigned IID = F->getIntrinsicID()) { 4826 RenameFn = visitIntrinsicCall(I, IID); 4827 if (!RenameFn) 4828 return; 4829 } 4830 } 4831 4832 // Check for well-known libc/libm calls. If the function is internal, it 4833 // can't be a library call. 4834 if (!F->hasLocalLinkage() && F->hasName()) { 4835 StringRef Name = F->getName(); 4836 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4837 if (I.getNumOperands() == 3 && // Basic sanity checks. 4838 I.getOperand(1)->getType()->isFloatingPointTy() && 4839 I.getType() == I.getOperand(1)->getType() && 4840 I.getType() == I.getOperand(2)->getType()) { 4841 SDValue LHS = getValue(I.getOperand(1)); 4842 SDValue RHS = getValue(I.getOperand(2)); 4843 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4844 LHS.getValueType(), LHS, RHS)); 4845 return; 4846 } 4847 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4848 if (I.getNumOperands() == 2 && // Basic sanity checks. 4849 I.getOperand(1)->getType()->isFloatingPointTy() && 4850 I.getType() == I.getOperand(1)->getType()) { 4851 SDValue Tmp = getValue(I.getOperand(1)); 4852 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4853 Tmp.getValueType(), Tmp)); 4854 return; 4855 } 4856 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4857 if (I.getNumOperands() == 2 && // Basic sanity checks. 4858 I.getOperand(1)->getType()->isFloatingPointTy() && 4859 I.getType() == I.getOperand(1)->getType() && 4860 I.onlyReadsMemory()) { 4861 SDValue Tmp = getValue(I.getOperand(1)); 4862 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4863 Tmp.getValueType(), Tmp)); 4864 return; 4865 } 4866 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4867 if (I.getNumOperands() == 2 && // Basic sanity checks. 4868 I.getOperand(1)->getType()->isFloatingPointTy() && 4869 I.getType() == I.getOperand(1)->getType() && 4870 I.onlyReadsMemory()) { 4871 SDValue Tmp = getValue(I.getOperand(1)); 4872 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4873 Tmp.getValueType(), Tmp)); 4874 return; 4875 } 4876 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4877 if (I.getNumOperands() == 2 && // Basic sanity checks. 4878 I.getOperand(1)->getType()->isFloatingPointTy() && 4879 I.getType() == I.getOperand(1)->getType() && 4880 I.onlyReadsMemory()) { 4881 SDValue Tmp = getValue(I.getOperand(1)); 4882 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4883 Tmp.getValueType(), Tmp)); 4884 return; 4885 } 4886 } else if (Name == "memcmp") { 4887 if (visitMemCmpCall(I)) 4888 return; 4889 } 4890 } 4891 } else if (isa<InlineAsm>(I.getOperand(0))) { 4892 visitInlineAsm(&I); 4893 return; 4894 } 4895 4896 SDValue Callee; 4897 if (!RenameFn) 4898 Callee = getValue(I.getOperand(0)); 4899 else 4900 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 4901 4902 // Check if we can potentially perform a tail call. More detailed checking is 4903 // be done within LowerCallTo, after more information about the call is known. 4904 LowerCallTo(&I, Callee, I.isTailCall()); 4905} 4906 4907namespace llvm { 4908 4909/// AsmOperandInfo - This contains information for each constraint that we are 4910/// lowering. 4911class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 4912 public TargetLowering::AsmOperandInfo { 4913public: 4914 /// CallOperand - If this is the result output operand or a clobber 4915 /// this is null, otherwise it is the incoming operand to the CallInst. 4916 /// This gets modified as the asm is processed. 4917 SDValue CallOperand; 4918 4919 /// AssignedRegs - If this is a register or register class operand, this 4920 /// contains the set of register corresponding to the operand. 4921 RegsForValue AssignedRegs; 4922 4923 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 4924 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 4925 } 4926 4927 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 4928 /// busy in OutputRegs/InputRegs. 4929 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 4930 std::set<unsigned> &OutputRegs, 4931 std::set<unsigned> &InputRegs, 4932 const TargetRegisterInfo &TRI) const { 4933 if (isOutReg) { 4934 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4935 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 4936 } 4937 if (isInReg) { 4938 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4939 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 4940 } 4941 } 4942 4943 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 4944 /// corresponds to. If there is no Value* for this operand, it returns 4945 /// MVT::Other. 4946 EVT getCallOperandValEVT(LLVMContext &Context, 4947 const TargetLowering &TLI, 4948 const TargetData *TD) const { 4949 if (CallOperandVal == 0) return MVT::Other; 4950 4951 if (isa<BasicBlock>(CallOperandVal)) 4952 return TLI.getPointerTy(); 4953 4954 const llvm::Type *OpTy = CallOperandVal->getType(); 4955 4956 // If this is an indirect operand, the operand is a pointer to the 4957 // accessed type. 4958 if (isIndirect) { 4959 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 4960 if (!PtrTy) 4961 report_fatal_error("Indirect operand for inline asm not a pointer!"); 4962 OpTy = PtrTy->getElementType(); 4963 } 4964 4965 // If OpTy is not a single value, it may be a struct/union that we 4966 // can tile with integers. 4967 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4968 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4969 switch (BitSize) { 4970 default: break; 4971 case 1: 4972 case 8: 4973 case 16: 4974 case 32: 4975 case 64: 4976 case 128: 4977 OpTy = IntegerType::get(Context, BitSize); 4978 break; 4979 } 4980 } 4981 4982 return TLI.getValueType(OpTy, true); 4983 } 4984 4985private: 4986 /// MarkRegAndAliases - Mark the specified register and all aliases in the 4987 /// specified set. 4988 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 4989 const TargetRegisterInfo &TRI) { 4990 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 4991 Regs.insert(Reg); 4992 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 4993 for (; *Aliases; ++Aliases) 4994 Regs.insert(*Aliases); 4995 } 4996}; 4997 4998} // end llvm namespace. 4999 5000/// isAllocatableRegister - If the specified register is safe to allocate, 5001/// i.e. it isn't a stack pointer or some other special register, return the 5002/// register class for the register. Otherwise, return null. 5003static const TargetRegisterClass * 5004isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5005 const TargetLowering &TLI, 5006 const TargetRegisterInfo *TRI) { 5007 EVT FoundVT = MVT::Other; 5008 const TargetRegisterClass *FoundRC = 0; 5009 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5010 E = TRI->regclass_end(); RCI != E; ++RCI) { 5011 EVT ThisVT = MVT::Other; 5012 5013 const TargetRegisterClass *RC = *RCI; 5014 // If none of the value types for this register class are valid, we 5015 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5016 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5017 I != E; ++I) { 5018 if (TLI.isTypeLegal(*I)) { 5019 // If we have already found this register in a different register class, 5020 // choose the one with the largest VT specified. For example, on 5021 // PowerPC, we favor f64 register classes over f32. 5022 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5023 ThisVT = *I; 5024 break; 5025 } 5026 } 5027 } 5028 5029 if (ThisVT == MVT::Other) continue; 5030 5031 // NOTE: This isn't ideal. In particular, this might allocate the 5032 // frame pointer in functions that need it (due to them not being taken 5033 // out of allocation, because a variable sized allocation hasn't been seen 5034 // yet). This is a slight code pessimization, but should still work. 5035 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5036 E = RC->allocation_order_end(MF); I != E; ++I) 5037 if (*I == Reg) { 5038 // We found a matching register class. Keep looking at others in case 5039 // we find one with larger registers that this physreg is also in. 5040 FoundRC = RC; 5041 FoundVT = ThisVT; 5042 break; 5043 } 5044 } 5045 return FoundRC; 5046} 5047 5048/// GetRegistersForValue - Assign registers (virtual or physical) for the 5049/// specified operand. We prefer to assign virtual registers, to allow the 5050/// register allocator to handle the assignment process. However, if the asm 5051/// uses features that we can't model on machineinstrs, we have SDISel do the 5052/// allocation. This produces generally horrible, but correct, code. 5053/// 5054/// OpInfo describes the operand. 5055/// Input and OutputRegs are the set of already allocated physical registers. 5056/// 5057void SelectionDAGBuilder:: 5058GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5059 std::set<unsigned> &OutputRegs, 5060 std::set<unsigned> &InputRegs) { 5061 LLVMContext &Context = FuncInfo.Fn->getContext(); 5062 5063 // Compute whether this value requires an input register, an output register, 5064 // or both. 5065 bool isOutReg = false; 5066 bool isInReg = false; 5067 switch (OpInfo.Type) { 5068 case InlineAsm::isOutput: 5069 isOutReg = true; 5070 5071 // If there is an input constraint that matches this, we need to reserve 5072 // the input register so no other inputs allocate to it. 5073 isInReg = OpInfo.hasMatchingInput(); 5074 break; 5075 case InlineAsm::isInput: 5076 isInReg = true; 5077 isOutReg = false; 5078 break; 5079 case InlineAsm::isClobber: 5080 isOutReg = true; 5081 isInReg = true; 5082 break; 5083 } 5084 5085 5086 MachineFunction &MF = DAG.getMachineFunction(); 5087 SmallVector<unsigned, 4> Regs; 5088 5089 // If this is a constraint for a single physreg, or a constraint for a 5090 // register class, find it. 5091 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5092 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5093 OpInfo.ConstraintVT); 5094 5095 unsigned NumRegs = 1; 5096 if (OpInfo.ConstraintVT != MVT::Other) { 5097 // If this is a FP input in an integer register (or visa versa) insert a bit 5098 // cast of the input value. More generally, handle any case where the input 5099 // value disagrees with the register class we plan to stick this in. 5100 if (OpInfo.Type == InlineAsm::isInput && 5101 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5102 // Try to convert to the first EVT that the reg class contains. If the 5103 // types are identical size, use a bitcast to convert (e.g. two differing 5104 // vector types). 5105 EVT RegVT = *PhysReg.second->vt_begin(); 5106 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5107 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5108 RegVT, OpInfo.CallOperand); 5109 OpInfo.ConstraintVT = RegVT; 5110 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5111 // If the input is a FP value and we want it in FP registers, do a 5112 // bitcast to the corresponding integer type. This turns an f64 value 5113 // into i64, which can be passed with two i32 values on a 32-bit 5114 // machine. 5115 RegVT = EVT::getIntegerVT(Context, 5116 OpInfo.ConstraintVT.getSizeInBits()); 5117 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5118 RegVT, OpInfo.CallOperand); 5119 OpInfo.ConstraintVT = RegVT; 5120 } 5121 } 5122 5123 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5124 } 5125 5126 EVT RegVT; 5127 EVT ValueVT = OpInfo.ConstraintVT; 5128 5129 // If this is a constraint for a specific physical register, like {r17}, 5130 // assign it now. 5131 if (unsigned AssignedReg = PhysReg.first) { 5132 const TargetRegisterClass *RC = PhysReg.second; 5133 if (OpInfo.ConstraintVT == MVT::Other) 5134 ValueVT = *RC->vt_begin(); 5135 5136 // Get the actual register value type. This is important, because the user 5137 // may have asked for (e.g.) the AX register in i32 type. We need to 5138 // remember that AX is actually i16 to get the right extension. 5139 RegVT = *RC->vt_begin(); 5140 5141 // This is a explicit reference to a physical register. 5142 Regs.push_back(AssignedReg); 5143 5144 // If this is an expanded reference, add the rest of the regs to Regs. 5145 if (NumRegs != 1) { 5146 TargetRegisterClass::iterator I = RC->begin(); 5147 for (; *I != AssignedReg; ++I) 5148 assert(I != RC->end() && "Didn't find reg!"); 5149 5150 // Already added the first reg. 5151 --NumRegs; ++I; 5152 for (; NumRegs; --NumRegs, ++I) { 5153 assert(I != RC->end() && "Ran out of registers to allocate!"); 5154 Regs.push_back(*I); 5155 } 5156 } 5157 5158 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5159 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5160 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5161 return; 5162 } 5163 5164 // Otherwise, if this was a reference to an LLVM register class, create vregs 5165 // for this reference. 5166 if (const TargetRegisterClass *RC = PhysReg.second) { 5167 RegVT = *RC->vt_begin(); 5168 if (OpInfo.ConstraintVT == MVT::Other) 5169 ValueVT = RegVT; 5170 5171 // Create the appropriate number of virtual registers. 5172 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5173 for (; NumRegs; --NumRegs) 5174 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5175 5176 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5177 return; 5178 } 5179 5180 // This is a reference to a register class that doesn't directly correspond 5181 // to an LLVM register class. Allocate NumRegs consecutive, available, 5182 // registers from the class. 5183 std::vector<unsigned> RegClassRegs 5184 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5185 OpInfo.ConstraintVT); 5186 5187 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5188 unsigned NumAllocated = 0; 5189 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5190 unsigned Reg = RegClassRegs[i]; 5191 // See if this register is available. 5192 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5193 (isInReg && InputRegs.count(Reg))) { // Already used. 5194 // Make sure we find consecutive registers. 5195 NumAllocated = 0; 5196 continue; 5197 } 5198 5199 // Check to see if this register is allocatable (i.e. don't give out the 5200 // stack pointer). 5201 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5202 if (!RC) { // Couldn't allocate this register. 5203 // Reset NumAllocated to make sure we return consecutive registers. 5204 NumAllocated = 0; 5205 continue; 5206 } 5207 5208 // Okay, this register is good, we can use it. 5209 ++NumAllocated; 5210 5211 // If we allocated enough consecutive registers, succeed. 5212 if (NumAllocated == NumRegs) { 5213 unsigned RegStart = (i-NumAllocated)+1; 5214 unsigned RegEnd = i+1; 5215 // Mark all of the allocated registers used. 5216 for (unsigned i = RegStart; i != RegEnd; ++i) 5217 Regs.push_back(RegClassRegs[i]); 5218 5219 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5220 OpInfo.ConstraintVT); 5221 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5222 return; 5223 } 5224 } 5225 5226 // Otherwise, we couldn't allocate enough registers for this. 5227} 5228 5229/// visitInlineAsm - Handle a call to an InlineAsm object. 5230/// 5231void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5232 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5233 5234 /// ConstraintOperands - Information about all of the constraints. 5235 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5236 5237 std::set<unsigned> OutputRegs, InputRegs; 5238 5239 // Do a prepass over the constraints, canonicalizing them, and building up the 5240 // ConstraintOperands list. 5241 std::vector<InlineAsm::ConstraintInfo> 5242 ConstraintInfos = IA->ParseConstraints(); 5243 5244 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); 5245 5246 SDValue Chain, Flag; 5247 5248 // We won't need to flush pending loads if this asm doesn't touch 5249 // memory and is nonvolatile. 5250 if (hasMemory || IA->hasSideEffects()) 5251 Chain = getRoot(); 5252 else 5253 Chain = DAG.getRoot(); 5254 5255 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5256 unsigned ResNo = 0; // ResNo - The result number of the next output. 5257 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5258 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 5259 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5260 5261 EVT OpVT = MVT::Other; 5262 5263 // Compute the value type for each operand. 5264 switch (OpInfo.Type) { 5265 case InlineAsm::isOutput: 5266 // Indirect outputs just consume an argument. 5267 if (OpInfo.isIndirect) { 5268 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5269 break; 5270 } 5271 5272 // The return value of the call is this value. As such, there is no 5273 // corresponding argument. 5274 assert(!CS.getType()->isVoidTy() && 5275 "Bad inline asm!"); 5276 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5277 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5278 } else { 5279 assert(ResNo == 0 && "Asm only has one result!"); 5280 OpVT = TLI.getValueType(CS.getType()); 5281 } 5282 ++ResNo; 5283 break; 5284 case InlineAsm::isInput: 5285 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5286 break; 5287 case InlineAsm::isClobber: 5288 // Nothing to do. 5289 break; 5290 } 5291 5292 // If this is an input or an indirect output, process the call argument. 5293 // BasicBlocks are labels, currently appearing only in asm's. 5294 if (OpInfo.CallOperandVal) { 5295 // Strip bitcasts, if any. This mostly comes up for functions. 5296 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5297 5298 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5299 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5300 } else { 5301 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5302 } 5303 5304 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5305 } 5306 5307 OpInfo.ConstraintVT = OpVT; 5308 } 5309 5310 // Second pass over the constraints: compute which constraint option to use 5311 // and assign registers to constraints that want a specific physreg. 5312 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5313 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5314 5315 // If this is an output operand with a matching input operand, look up the 5316 // matching input. If their types mismatch, e.g. one is an integer, the 5317 // other is floating point, or their sizes are different, flag it as an 5318 // error. 5319 if (OpInfo.hasMatchingInput()) { 5320 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5321 5322 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5323 if ((OpInfo.ConstraintVT.isInteger() != 5324 Input.ConstraintVT.isInteger()) || 5325 (OpInfo.ConstraintVT.getSizeInBits() != 5326 Input.ConstraintVT.getSizeInBits())) { 5327 report_fatal_error("Unsupported asm: input constraint" 5328 " with a matching output constraint of" 5329 " incompatible type!"); 5330 } 5331 Input.ConstraintVT = OpInfo.ConstraintVT; 5332 } 5333 } 5334 5335 // Compute the constraint code and ConstraintType to use. 5336 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG); 5337 5338 // If this is a memory input, and if the operand is not indirect, do what we 5339 // need to to provide an address for the memory input. 5340 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5341 !OpInfo.isIndirect) { 5342 assert(OpInfo.Type == InlineAsm::isInput && 5343 "Can only indirectify direct input operands!"); 5344 5345 // Memory operands really want the address of the value. If we don't have 5346 // an indirect input, put it in the constpool if we can, otherwise spill 5347 // it to a stack slot. 5348 5349 // If the operand is a float, integer, or vector constant, spill to a 5350 // constant pool entry to get its address. 5351 const Value *OpVal = OpInfo.CallOperandVal; 5352 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5353 isa<ConstantVector>(OpVal)) { 5354 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5355 TLI.getPointerTy()); 5356 } else { 5357 // Otherwise, create a stack slot and emit a store to it before the 5358 // asm. 5359 const Type *Ty = OpVal->getType(); 5360 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5361 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5362 MachineFunction &MF = DAG.getMachineFunction(); 5363 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5364 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5365 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5366 OpInfo.CallOperand, StackSlot, NULL, 0, 5367 false, false, 0); 5368 OpInfo.CallOperand = StackSlot; 5369 } 5370 5371 // There is no longer a Value* corresponding to this operand. 5372 OpInfo.CallOperandVal = 0; 5373 5374 // It is now an indirect operand. 5375 OpInfo.isIndirect = true; 5376 } 5377 5378 // If this constraint is for a specific register, allocate it before 5379 // anything else. 5380 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5381 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5382 } 5383 5384 ConstraintInfos.clear(); 5385 5386 // Second pass - Loop over all of the operands, assigning virtual or physregs 5387 // to register class operands. 5388 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5389 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5390 5391 // C_Register operands have already been allocated, Other/Memory don't need 5392 // to be. 5393 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5394 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5395 } 5396 5397 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5398 std::vector<SDValue> AsmNodeOperands; 5399 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5400 AsmNodeOperands.push_back( 5401 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5402 TLI.getPointerTy())); 5403 5404 // If we have a !srcloc metadata node associated with it, we want to attach 5405 // this to the ultimately generated inline asm machineinstr. To do this, we 5406 // pass in the third operand as this (potentially null) inline asm MDNode. 5407 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5408 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5409 5410 // Loop over all of the inputs, copying the operand values into the 5411 // appropriate registers and processing the output regs. 5412 RegsForValue RetValRegs; 5413 5414 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5415 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5416 5417 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5418 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5419 5420 switch (OpInfo.Type) { 5421 case InlineAsm::isOutput: { 5422 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5423 OpInfo.ConstraintType != TargetLowering::C_Register) { 5424 // Memory output, or 'other' output (e.g. 'X' constraint). 5425 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5426 5427 // Add information to the INLINEASM node to know about this output. 5428 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5429 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5430 TLI.getPointerTy())); 5431 AsmNodeOperands.push_back(OpInfo.CallOperand); 5432 break; 5433 } 5434 5435 // Otherwise, this is a register or register class output. 5436 5437 // Copy the output from the appropriate register. Find a register that 5438 // we can use. 5439 if (OpInfo.AssignedRegs.Regs.empty()) 5440 report_fatal_error("Couldn't allocate output reg for constraint '" + 5441 Twine(OpInfo.ConstraintCode) + "'!"); 5442 5443 // If this is an indirect operand, store through the pointer after the 5444 // asm. 5445 if (OpInfo.isIndirect) { 5446 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5447 OpInfo.CallOperandVal)); 5448 } else { 5449 // This is the result value of the call. 5450 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5451 // Concatenate this output onto the outputs list. 5452 RetValRegs.append(OpInfo.AssignedRegs); 5453 } 5454 5455 // Add information to the INLINEASM node to know that this register is 5456 // set. 5457 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5458 InlineAsm::Kind_RegDefEarlyClobber : 5459 InlineAsm::Kind_RegDef, 5460 false, 5461 0, 5462 DAG, 5463 AsmNodeOperands); 5464 break; 5465 } 5466 case InlineAsm::isInput: { 5467 SDValue InOperandVal = OpInfo.CallOperand; 5468 5469 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5470 // If this is required to match an output register we have already set, 5471 // just use its register. 5472 unsigned OperandNo = OpInfo.getMatchedOperand(); 5473 5474 // Scan until we find the definition we already emitted of this operand. 5475 // When we find it, create a RegsForValue operand. 5476 unsigned CurOp = InlineAsm::Op_FirstOperand; 5477 for (; OperandNo; --OperandNo) { 5478 // Advance to the next operand. 5479 unsigned OpFlag = 5480 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5481 assert((InlineAsm::isRegDefKind(OpFlag) || 5482 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5483 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5484 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5485 } 5486 5487 unsigned OpFlag = 5488 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5489 if (InlineAsm::isRegDefKind(OpFlag) || 5490 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5491 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5492 if (OpInfo.isIndirect) { 5493 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5494 LLVMContext &Ctx = *DAG.getContext(); 5495 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5496 " don't know how to handle tied " 5497 "indirect register inputs"); 5498 } 5499 5500 RegsForValue MatchedRegs; 5501 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5502 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5503 MatchedRegs.RegVTs.push_back(RegVT); 5504 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5505 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5506 i != e; ++i) 5507 MatchedRegs.Regs.push_back 5508 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5509 5510 // Use the produced MatchedRegs object to 5511 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5512 Chain, &Flag); 5513 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5514 true, OpInfo.getMatchedOperand(), 5515 DAG, AsmNodeOperands); 5516 break; 5517 } 5518 5519 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5520 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5521 "Unexpected number of operands"); 5522 // Add information to the INLINEASM node to know about this input. 5523 // See InlineAsm.h isUseOperandTiedToDef. 5524 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5525 OpInfo.getMatchedOperand()); 5526 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5527 TLI.getPointerTy())); 5528 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5529 break; 5530 } 5531 5532 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5533 assert(!OpInfo.isIndirect && 5534 "Don't know how to handle indirect other inputs yet!"); 5535 5536 std::vector<SDValue> Ops; 5537 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5538 hasMemory, Ops, DAG); 5539 if (Ops.empty()) 5540 report_fatal_error("Invalid operand for inline asm constraint '" + 5541 Twine(OpInfo.ConstraintCode) + "'!"); 5542 5543 // Add information to the INLINEASM node to know about this input. 5544 unsigned ResOpType = 5545 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5546 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5547 TLI.getPointerTy())); 5548 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5549 break; 5550 } 5551 5552 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5553 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5554 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5555 "Memory operands expect pointer values"); 5556 5557 // Add information to the INLINEASM node to know about this input. 5558 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5559 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5560 TLI.getPointerTy())); 5561 AsmNodeOperands.push_back(InOperandVal); 5562 break; 5563 } 5564 5565 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5566 OpInfo.ConstraintType == TargetLowering::C_Register) && 5567 "Unknown constraint type!"); 5568 assert(!OpInfo.isIndirect && 5569 "Don't know how to handle indirect register inputs yet!"); 5570 5571 // Copy the input into the appropriate registers. 5572 if (OpInfo.AssignedRegs.Regs.empty() || 5573 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5574 report_fatal_error("Couldn't allocate input reg for constraint '" + 5575 Twine(OpInfo.ConstraintCode) + "'!"); 5576 5577 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5578 Chain, &Flag); 5579 5580 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5581 DAG, AsmNodeOperands); 5582 break; 5583 } 5584 case InlineAsm::isClobber: { 5585 // Add the clobbered value to the operand list, so that the register 5586 // allocator is aware that the physreg got clobbered. 5587 if (!OpInfo.AssignedRegs.Regs.empty()) 5588 OpInfo.AssignedRegs.AddInlineAsmOperands( 5589 InlineAsm::Kind_RegDefEarlyClobber, 5590 false, 0, DAG, 5591 AsmNodeOperands); 5592 break; 5593 } 5594 } 5595 } 5596 5597 // Finish up input operands. Set the input chain and add the flag last. 5598 AsmNodeOperands[0] = Chain; 5599 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5600 5601 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5602 DAG.getVTList(MVT::Other, MVT::Flag), 5603 &AsmNodeOperands[0], AsmNodeOperands.size()); 5604 Flag = Chain.getValue(1); 5605 5606 // If this asm returns a register value, copy the result from that register 5607 // and set it as the value of the call. 5608 if (!RetValRegs.Regs.empty()) { 5609 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5610 Chain, &Flag); 5611 5612 // FIXME: Why don't we do this for inline asms with MRVs? 5613 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5614 EVT ResultType = TLI.getValueType(CS.getType()); 5615 5616 // If any of the results of the inline asm is a vector, it may have the 5617 // wrong width/num elts. This can happen for register classes that can 5618 // contain multiple different value types. The preg or vreg allocated may 5619 // not have the same VT as was expected. Convert it to the right type 5620 // with bit_convert. 5621 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5622 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5623 ResultType, Val); 5624 5625 } else if (ResultType != Val.getValueType() && 5626 ResultType.isInteger() && Val.getValueType().isInteger()) { 5627 // If a result value was tied to an input value, the computed result may 5628 // have a wider width than the expected result. Extract the relevant 5629 // portion. 5630 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5631 } 5632 5633 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5634 } 5635 5636 setValue(CS.getInstruction(), Val); 5637 // Don't need to use this as a chain in this case. 5638 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5639 return; 5640 } 5641 5642 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5643 5644 // Process indirect outputs, first output all of the flagged copies out of 5645 // physregs. 5646 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5647 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5648 const Value *Ptr = IndirectStoresToEmit[i].second; 5649 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5650 Chain, &Flag); 5651 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5652 } 5653 5654 // Emit the non-flagged stores from the physregs. 5655 SmallVector<SDValue, 8> OutChains; 5656 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5657 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5658 StoresToEmit[i].first, 5659 getValue(StoresToEmit[i].second), 5660 StoresToEmit[i].second, 0, 5661 false, false, 0); 5662 OutChains.push_back(Val); 5663 } 5664 5665 if (!OutChains.empty()) 5666 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5667 &OutChains[0], OutChains.size()); 5668 5669 DAG.setRoot(Chain); 5670} 5671 5672void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5673 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5674 MVT::Other, getRoot(), 5675 getValue(I.getOperand(1)), 5676 DAG.getSrcValue(I.getOperand(1)))); 5677} 5678 5679void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5680 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5681 getRoot(), getValue(I.getOperand(0)), 5682 DAG.getSrcValue(I.getOperand(0))); 5683 setValue(&I, V); 5684 DAG.setRoot(V.getValue(1)); 5685} 5686 5687void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5688 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5689 MVT::Other, getRoot(), 5690 getValue(I.getOperand(1)), 5691 DAG.getSrcValue(I.getOperand(1)))); 5692} 5693 5694void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5695 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5696 MVT::Other, getRoot(), 5697 getValue(I.getOperand(1)), 5698 getValue(I.getOperand(2)), 5699 DAG.getSrcValue(I.getOperand(1)), 5700 DAG.getSrcValue(I.getOperand(2)))); 5701} 5702 5703/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5704/// implementation, which just calls LowerCall. 5705/// FIXME: When all targets are 5706/// migrated to using LowerCall, this hook should be integrated into SDISel. 5707std::pair<SDValue, SDValue> 5708TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5709 bool RetSExt, bool RetZExt, bool isVarArg, 5710 bool isInreg, unsigned NumFixedArgs, 5711 CallingConv::ID CallConv, bool isTailCall, 5712 bool isReturnValueUsed, 5713 SDValue Callee, 5714 ArgListTy &Args, SelectionDAG &DAG, 5715 DebugLoc dl) const { 5716 // Handle all of the outgoing arguments. 5717 SmallVector<ISD::OutputArg, 32> Outs; 5718 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5719 SmallVector<EVT, 4> ValueVTs; 5720 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5721 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5722 Value != NumValues; ++Value) { 5723 EVT VT = ValueVTs[Value]; 5724 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5725 SDValue Op = SDValue(Args[i].Node.getNode(), 5726 Args[i].Node.getResNo() + Value); 5727 ISD::ArgFlagsTy Flags; 5728 unsigned OriginalAlignment = 5729 getTargetData()->getABITypeAlignment(ArgTy); 5730 5731 if (Args[i].isZExt) 5732 Flags.setZExt(); 5733 if (Args[i].isSExt) 5734 Flags.setSExt(); 5735 if (Args[i].isInReg) 5736 Flags.setInReg(); 5737 if (Args[i].isSRet) 5738 Flags.setSRet(); 5739 if (Args[i].isByVal) { 5740 Flags.setByVal(); 5741 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5742 const Type *ElementTy = Ty->getElementType(); 5743 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5744 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5745 // For ByVal, alignment should come from FE. BE will guess if this 5746 // info is not there but there are cases it cannot get right. 5747 if (Args[i].Alignment) 5748 FrameAlign = Args[i].Alignment; 5749 Flags.setByValAlign(FrameAlign); 5750 Flags.setByValSize(FrameSize); 5751 } 5752 if (Args[i].isNest) 5753 Flags.setNest(); 5754 Flags.setOrigAlign(OriginalAlignment); 5755 5756 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5757 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5758 SmallVector<SDValue, 4> Parts(NumParts); 5759 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5760 5761 if (Args[i].isSExt) 5762 ExtendKind = ISD::SIGN_EXTEND; 5763 else if (Args[i].isZExt) 5764 ExtendKind = ISD::ZERO_EXTEND; 5765 5766 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5767 PartVT, ExtendKind); 5768 5769 for (unsigned j = 0; j != NumParts; ++j) { 5770 // if it isn't first piece, alignment must be 1 5771 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs); 5772 if (NumParts > 1 && j == 0) 5773 MyFlags.Flags.setSplit(); 5774 else if (j != 0) 5775 MyFlags.Flags.setOrigAlign(1); 5776 5777 Outs.push_back(MyFlags); 5778 } 5779 } 5780 } 5781 5782 // Handle the incoming return values from the call. 5783 SmallVector<ISD::InputArg, 32> Ins; 5784 SmallVector<EVT, 4> RetTys; 5785 ComputeValueVTs(*this, RetTy, RetTys); 5786 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5787 EVT VT = RetTys[I]; 5788 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5789 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5790 for (unsigned i = 0; i != NumRegs; ++i) { 5791 ISD::InputArg MyFlags; 5792 MyFlags.VT = RegisterVT; 5793 MyFlags.Used = isReturnValueUsed; 5794 if (RetSExt) 5795 MyFlags.Flags.setSExt(); 5796 if (RetZExt) 5797 MyFlags.Flags.setZExt(); 5798 if (isInreg) 5799 MyFlags.Flags.setInReg(); 5800 Ins.push_back(MyFlags); 5801 } 5802 } 5803 5804 SmallVector<SDValue, 4> InVals; 5805 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5806 Outs, Ins, dl, DAG, InVals); 5807 5808 // Verify that the target's LowerCall behaved as expected. 5809 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5810 "LowerCall didn't return a valid chain!"); 5811 assert((!isTailCall || InVals.empty()) && 5812 "LowerCall emitted a return value for a tail call!"); 5813 assert((isTailCall || InVals.size() == Ins.size()) && 5814 "LowerCall didn't emit the correct number of values!"); 5815 5816 // For a tail call, the return value is merely live-out and there aren't 5817 // any nodes in the DAG representing it. Return a special value to 5818 // indicate that a tail call has been emitted and no more Instructions 5819 // should be processed in the current block. 5820 if (isTailCall) { 5821 DAG.setRoot(Chain); 5822 return std::make_pair(SDValue(), SDValue()); 5823 } 5824 5825 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5826 assert(InVals[i].getNode() && 5827 "LowerCall emitted a null value!"); 5828 assert(Ins[i].VT == InVals[i].getValueType() && 5829 "LowerCall emitted a value with the wrong type!"); 5830 }); 5831 5832 // Collect the legal value parts into potentially illegal values 5833 // that correspond to the original function's return values. 5834 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5835 if (RetSExt) 5836 AssertOp = ISD::AssertSext; 5837 else if (RetZExt) 5838 AssertOp = ISD::AssertZext; 5839 SmallVector<SDValue, 4> ReturnValues; 5840 unsigned CurReg = 0; 5841 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5842 EVT VT = RetTys[I]; 5843 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5844 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5845 5846 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5847 NumRegs, RegisterVT, VT, 5848 AssertOp)); 5849 CurReg += NumRegs; 5850 } 5851 5852 // For a function returning void, there is no return value. We can't create 5853 // such a node, so we just return a null return value in that case. In 5854 // that case, nothing will actualy look at the value. 5855 if (ReturnValues.empty()) 5856 return std::make_pair(SDValue(), Chain); 5857 5858 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5859 DAG.getVTList(&RetTys[0], RetTys.size()), 5860 &ReturnValues[0], ReturnValues.size()); 5861 return std::make_pair(Res, Chain); 5862} 5863 5864void TargetLowering::LowerOperationWrapper(SDNode *N, 5865 SmallVectorImpl<SDValue> &Results, 5866 SelectionDAG &DAG) const { 5867 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5868 if (Res.getNode()) 5869 Results.push_back(Res); 5870} 5871 5872SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5873 llvm_unreachable("LowerOperation not implemented for this target!"); 5874 return SDValue(); 5875} 5876 5877void 5878SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 5879 SDValue Op = getValue(V); 5880 assert((Op.getOpcode() != ISD::CopyFromReg || 5881 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5882 "Copy from a reg to the same reg!"); 5883 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5884 5885 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5886 SDValue Chain = DAG.getEntryNode(); 5887 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5888 PendingExports.push_back(Chain); 5889} 5890 5891#include "llvm/CodeGen/SelectionDAGISel.h" 5892 5893void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 5894 // If this is the entry block, emit arguments. 5895 const Function &F = *LLVMBB->getParent(); 5896 SelectionDAG &DAG = SDB->DAG; 5897 SDValue OldRoot = DAG.getRoot(); 5898 DebugLoc dl = SDB->getCurDebugLoc(); 5899 const TargetData *TD = TLI.getTargetData(); 5900 SmallVector<ISD::InputArg, 16> Ins; 5901 5902 // Check whether the function can return without sret-demotion. 5903 SmallVector<EVT, 4> OutVTs; 5904 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 5905 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 5906 OutVTs, OutsFlags, TLI); 5907 5908 FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), 5909 F.isVarArg(), 5910 OutVTs, OutsFlags, DAG); 5911 if (!FuncInfo->CanLowerReturn) { 5912 // Put in an sret pointer parameter before all the other parameters. 5913 SmallVector<EVT, 1> ValueVTs; 5914 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5915 5916 // NOTE: Assuming that a pointer will never break down to more than one VT 5917 // or one register. 5918 ISD::ArgFlagsTy Flags; 5919 Flags.setSRet(); 5920 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 5921 ISD::InputArg RetArg(Flags, RegisterVT, true); 5922 Ins.push_back(RetArg); 5923 } 5924 5925 // Set up the incoming argument description vector. 5926 unsigned Idx = 1; 5927 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 5928 I != E; ++I, ++Idx) { 5929 SmallVector<EVT, 4> ValueVTs; 5930 ComputeValueVTs(TLI, I->getType(), ValueVTs); 5931 bool isArgValueUsed = !I->use_empty(); 5932 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5933 Value != NumValues; ++Value) { 5934 EVT VT = ValueVTs[Value]; 5935 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 5936 ISD::ArgFlagsTy Flags; 5937 unsigned OriginalAlignment = 5938 TD->getABITypeAlignment(ArgTy); 5939 5940 if (F.paramHasAttr(Idx, Attribute::ZExt)) 5941 Flags.setZExt(); 5942 if (F.paramHasAttr(Idx, Attribute::SExt)) 5943 Flags.setSExt(); 5944 if (F.paramHasAttr(Idx, Attribute::InReg)) 5945 Flags.setInReg(); 5946 if (F.paramHasAttr(Idx, Attribute::StructRet)) 5947 Flags.setSRet(); 5948 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 5949 Flags.setByVal(); 5950 const PointerType *Ty = cast<PointerType>(I->getType()); 5951 const Type *ElementTy = Ty->getElementType(); 5952 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 5953 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 5954 // For ByVal, alignment should be passed from FE. BE will guess if 5955 // this info is not there but there are cases it cannot get right. 5956 if (F.getParamAlignment(Idx)) 5957 FrameAlign = F.getParamAlignment(Idx); 5958 Flags.setByValAlign(FrameAlign); 5959 Flags.setByValSize(FrameSize); 5960 } 5961 if (F.paramHasAttr(Idx, Attribute::Nest)) 5962 Flags.setNest(); 5963 Flags.setOrigAlign(OriginalAlignment); 5964 5965 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5966 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 5967 for (unsigned i = 0; i != NumRegs; ++i) { 5968 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 5969 if (NumRegs > 1 && i == 0) 5970 MyFlags.Flags.setSplit(); 5971 // if it isn't first piece, alignment must be 1 5972 else if (i > 0) 5973 MyFlags.Flags.setOrigAlign(1); 5974 Ins.push_back(MyFlags); 5975 } 5976 } 5977 } 5978 5979 // Call the target to set up the argument values. 5980 SmallVector<SDValue, 8> InVals; 5981 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 5982 F.isVarArg(), Ins, 5983 dl, DAG, InVals); 5984 5985 // Verify that the target's LowerFormalArguments behaved as expected. 5986 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 5987 "LowerFormalArguments didn't return a valid chain!"); 5988 assert(InVals.size() == Ins.size() && 5989 "LowerFormalArguments didn't emit the correct number of values!"); 5990 DEBUG({ 5991 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5992 assert(InVals[i].getNode() && 5993 "LowerFormalArguments emitted a null value!"); 5994 assert(Ins[i].VT == InVals[i].getValueType() && 5995 "LowerFormalArguments emitted a value with the wrong type!"); 5996 } 5997 }); 5998 5999 // Update the DAG with the new chain value resulting from argument lowering. 6000 DAG.setRoot(NewRoot); 6001 6002 // Set up the argument values. 6003 unsigned i = 0; 6004 Idx = 1; 6005 if (!FuncInfo->CanLowerReturn) { 6006 // Create a virtual register for the sret pointer, and put in a copy 6007 // from the sret argument into it. 6008 SmallVector<EVT, 1> ValueVTs; 6009 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6010 EVT VT = ValueVTs[0]; 6011 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6012 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6013 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6014 RegVT, VT, AssertOp); 6015 6016 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6017 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6018 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6019 FuncInfo->DemoteRegister = SRetReg; 6020 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6021 SRetReg, ArgValue); 6022 DAG.setRoot(NewRoot); 6023 6024 // i indexes lowered arguments. Bump it past the hidden sret argument. 6025 // Idx indexes LLVM arguments. Don't touch it. 6026 ++i; 6027 } 6028 6029 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6030 ++I, ++Idx) { 6031 SmallVector<SDValue, 4> ArgValues; 6032 SmallVector<EVT, 4> ValueVTs; 6033 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6034 unsigned NumValues = ValueVTs.size(); 6035 for (unsigned Value = 0; Value != NumValues; ++Value) { 6036 EVT VT = ValueVTs[Value]; 6037 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6038 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6039 6040 if (!I->use_empty()) { 6041 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6042 if (F.paramHasAttr(Idx, Attribute::SExt)) 6043 AssertOp = ISD::AssertSext; 6044 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6045 AssertOp = ISD::AssertZext; 6046 6047 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6048 NumParts, PartVT, VT, 6049 AssertOp)); 6050 } 6051 6052 i += NumParts; 6053 } 6054 6055 if (!I->use_empty()) { 6056 SDValue Res; 6057 if (!ArgValues.empty()) 6058 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6059 SDB->getCurDebugLoc()); 6060 SDB->setValue(I, Res); 6061 6062 // If this argument is live outside of the entry block, insert a copy from 6063 // whereever we got it to the vreg that other BB's will reference it as. 6064 SDB->CopyToExportRegsIfNeeded(I); 6065 } 6066 } 6067 6068 assert(i == InVals.size() && "Argument register count mismatch!"); 6069 6070 // Finally, if the target has anything special to do, allow it to do so. 6071 // FIXME: this should insert code into the DAG! 6072 EmitFunctionEntryCode(); 6073} 6074 6075/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6076/// ensure constants are generated when needed. Remember the virtual registers 6077/// that need to be added to the Machine PHI nodes as input. We cannot just 6078/// directly add them, because expansion might result in multiple MBB's for one 6079/// BB. As such, the start of the BB might correspond to a different MBB than 6080/// the end. 6081/// 6082void 6083SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6084 const TerminatorInst *TI = LLVMBB->getTerminator(); 6085 6086 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6087 6088 // Check successor nodes' PHI nodes that expect a constant to be available 6089 // from this block. 6090 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6091 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6092 if (!isa<PHINode>(SuccBB->begin())) continue; 6093 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6094 6095 // If this terminator has multiple identical successors (common for 6096 // switches), only handle each succ once. 6097 if (!SuccsHandled.insert(SuccMBB)) continue; 6098 6099 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6100 6101 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6102 // nodes and Machine PHI nodes, but the incoming operands have not been 6103 // emitted yet. 6104 for (BasicBlock::const_iterator I = SuccBB->begin(); 6105 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6106 // Ignore dead phi's. 6107 if (PN->use_empty()) continue; 6108 6109 unsigned Reg; 6110 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6111 6112 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6113 unsigned &RegOut = ConstantsOut[C]; 6114 if (RegOut == 0) { 6115 RegOut = FuncInfo.CreateRegForValue(C); 6116 CopyValueToVirtualRegister(C, RegOut); 6117 } 6118 Reg = RegOut; 6119 } else { 6120 Reg = FuncInfo.ValueMap[PHIOp]; 6121 if (Reg == 0) { 6122 assert(isa<AllocaInst>(PHIOp) && 6123 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6124 "Didn't codegen value into a register!??"); 6125 Reg = FuncInfo.CreateRegForValue(PHIOp); 6126 CopyValueToVirtualRegister(PHIOp, Reg); 6127 } 6128 } 6129 6130 // Remember that this register needs to added to the machine PHI node as 6131 // the input for this MBB. 6132 SmallVector<EVT, 4> ValueVTs; 6133 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6134 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6135 EVT VT = ValueVTs[vti]; 6136 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6137 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6138 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6139 Reg += NumRegisters; 6140 } 6141 } 6142 } 6143 ConstantsOut.clear(); 6144} 6145