SelectionDAGBuilder.cpp revision 4eb20621438eb98fdbcdb0b224de7609d5ef76f2
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 const BasicBlock *SrcBB = Src->getBasicBlock(); 1281 const BasicBlock *DstBB = Dst->getBasicBlock(); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder:: 1286addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1287 uint32_t Weight /* = 0 */) { 1288 if (!Weight) 1289 Weight = getEdgeWeight(Src, Dst); 1290 Src->addSuccessor(Dst, Weight); 1291} 1292 1293 1294static bool InBlock(const Value *V, const BasicBlock *BB) { 1295 if (const Instruction *I = dyn_cast<Instruction>(V)) 1296 return I->getParent() == BB; 1297 return true; 1298} 1299 1300/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1301/// This function emits a branch and is used at the leaves of an OR or an 1302/// AND operator tree. 1303/// 1304void 1305SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1306 MachineBasicBlock *TBB, 1307 MachineBasicBlock *FBB, 1308 MachineBasicBlock *CurBB, 1309 MachineBasicBlock *SwitchBB) { 1310 const BasicBlock *BB = CurBB->getBasicBlock(); 1311 1312 // If the leaf of the tree is a comparison, merge the condition into 1313 // the caseblock. 1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1315 // The operands of the cmp have to be in this block. We don't know 1316 // how to export them from some other block. If this is the first block 1317 // of the sequence, no exporting is needed. 1318 if (CurBB == SwitchBB || 1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1321 ISD::CondCode Condition; 1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1323 Condition = getICmpCondCode(IC->getPredicate()); 1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1325 Condition = getFCmpCondCode(FC->getPredicate()); 1326 } else { 1327 Condition = ISD::SETEQ; // silence warning. 1328 llvm_unreachable("Unknown compare instruction"); 1329 } 1330 1331 CaseBlock CB(Condition, BOp->getOperand(0), 1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1333 SwitchCases.push_back(CB); 1334 return; 1335 } 1336 } 1337 1338 // Create a CaseBlock record representing this branch. 1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1340 NULL, TBB, FBB, CurBB); 1341 SwitchCases.push_back(CB); 1342} 1343 1344/// FindMergedConditions - If Cond is an expression like 1345void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1346 MachineBasicBlock *TBB, 1347 MachineBasicBlock *FBB, 1348 MachineBasicBlock *CurBB, 1349 MachineBasicBlock *SwitchBB, 1350 unsigned Opc) { 1351 // If this node is not part of the or/and tree, emit it as a branch. 1352 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1355 BOp->getParent() != CurBB->getBasicBlock() || 1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1359 return; 1360 } 1361 1362 // Create TmpBB after CurBB. 1363 MachineFunction::iterator BBI = CurBB; 1364 MachineFunction &MF = DAG.getMachineFunction(); 1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1366 CurBB->getParent()->insert(++BBI, TmpBB); 1367 1368 if (Opc == Instruction::Or) { 1369 // Codegen X | Y as: 1370 // jmp_if_X TBB 1371 // jmp TmpBB 1372 // TmpBB: 1373 // jmp_if_Y TBB 1374 // jmp FBB 1375 // 1376 1377 // Emit the LHS condition. 1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1379 1380 // Emit the RHS condition into TmpBB. 1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1382 } else { 1383 assert(Opc == Instruction::And && "Unknown merge op!"); 1384 // Codegen X & Y as: 1385 // jmp_if_X TmpBB 1386 // jmp FBB 1387 // TmpBB: 1388 // jmp_if_Y TBB 1389 // jmp FBB 1390 // 1391 // This requires creation of TmpBB after CurBB. 1392 1393 // Emit the LHS condition. 1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1395 1396 // Emit the RHS condition into TmpBB. 1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1398 } 1399} 1400 1401/// If the set of cases should be emitted as a series of branches, return true. 1402/// If we should emit this as a bunch of and/or'd together conditions, return 1403/// false. 1404bool 1405SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1406 if (Cases.size() != 2) return true; 1407 1408 // If this is two comparisons of the same values or'd or and'd together, they 1409 // will get folded into a single comparison, so don't emit two blocks. 1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1411 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1412 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1414 return false; 1415 } 1416 1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1420 Cases[0].CC == Cases[1].CC && 1421 isa<Constant>(Cases[0].CmpRHS) && 1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1424 return false; 1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1426 return false; 1427 } 1428 1429 return true; 1430} 1431 1432void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1433 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1434 1435 // Update machine-CFG edges. 1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1437 1438 // Figure out which block is immediately after the current one. 1439 MachineBasicBlock *NextBlock = 0; 1440 MachineFunction::iterator BBI = BrMBB; 1441 if (++BBI != FuncInfo.MF->end()) 1442 NextBlock = BBI; 1443 1444 if (I.isUnconditional()) { 1445 // Update machine-CFG edges. 1446 BrMBB->addSuccessor(Succ0MBB); 1447 1448 // If this is not a fall-through branch, emit the branch. 1449 if (Succ0MBB != NextBlock) 1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1451 MVT::Other, getControlRoot(), 1452 DAG.getBasicBlock(Succ0MBB))); 1453 1454 return; 1455 } 1456 1457 // If this condition is one of the special cases we handle, do special stuff 1458 // now. 1459 const Value *CondVal = I.getCondition(); 1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1461 1462 // If this is a series of conditions that are or'd or and'd together, emit 1463 // this as a sequence of branches instead of setcc's with and/or operations. 1464 // As long as jumps are not expensive, this should improve performance. 1465 // For example, instead of something like: 1466 // cmp A, B 1467 // C = seteq 1468 // cmp D, E 1469 // F = setle 1470 // or C, F 1471 // jnz foo 1472 // Emit: 1473 // cmp A, B 1474 // je foo 1475 // cmp D, E 1476 // jle foo 1477 // 1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1479 if (!TLI.isJumpExpensive() && 1480 BOp->hasOneUse() && 1481 (BOp->getOpcode() == Instruction::And || 1482 BOp->getOpcode() == Instruction::Or)) { 1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1484 BOp->getOpcode()); 1485 // If the compares in later blocks need to use values not currently 1486 // exported from this block, export them now. This block should always 1487 // be the first entry. 1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1489 1490 // Allow some cases to be rejected. 1491 if (ShouldEmitAsBranches(SwitchCases)) { 1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1495 } 1496 1497 // Emit the branch for this block. 1498 visitSwitchCase(SwitchCases[0], BrMBB); 1499 SwitchCases.erase(SwitchCases.begin()); 1500 return; 1501 } 1502 1503 // Okay, we decided not to do this, remove any inserted MBB's and clear 1504 // SwitchCases. 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1507 1508 SwitchCases.clear(); 1509 } 1510 } 1511 1512 // Create a CaseBlock record representing this branch. 1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1514 NULL, Succ0MBB, Succ1MBB, BrMBB); 1515 1516 // Use visitSwitchCase to actually insert the fast branch sequence for this 1517 // cond branch. 1518 visitSwitchCase(CB, BrMBB); 1519} 1520 1521/// visitSwitchCase - Emits the necessary code to represent a single node in 1522/// the binary search tree resulting from lowering a switch instruction. 1523void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1524 MachineBasicBlock *SwitchBB) { 1525 SDValue Cond; 1526 SDValue CondLHS = getValue(CB.CmpLHS); 1527 DebugLoc dl = getCurDebugLoc(); 1528 1529 // Build the setcc now. 1530 if (CB.CmpMHS == NULL) { 1531 // Fold "(X == true)" to X and "(X == false)" to !X to 1532 // handle common cases produced by branch lowering. 1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1534 CB.CC == ISD::SETEQ) 1535 Cond = CondLHS; 1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1537 CB.CC == ISD::SETEQ) { 1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1540 } else 1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1542 } else { 1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1544 1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1547 1548 SDValue CmpOp = getValue(CB.CmpMHS); 1549 EVT VT = CmpOp.getValueType(); 1550 1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1553 ISD::SETLE); 1554 } else { 1555 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1556 VT, CmpOp, DAG.getConstant(Low, VT)); 1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1558 DAG.getConstant(High-Low, VT), ISD::SETULE); 1559 } 1560 } 1561 1562 // Update successor info 1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1565 1566 // Set NextBlock to be the MBB immediately after the current one, if any. 1567 // This is used to avoid emitting unnecessary branches to the next block. 1568 MachineBasicBlock *NextBlock = 0; 1569 MachineFunction::iterator BBI = SwitchBB; 1570 if (++BBI != FuncInfo.MF->end()) 1571 NextBlock = BBI; 1572 1573 // If the lhs block is the next block, invert the condition so that we can 1574 // fall through to the lhs instead of the rhs block. 1575 if (CB.TrueBB == NextBlock) { 1576 std::swap(CB.TrueBB, CB.FalseBB); 1577 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1579 } 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1582 MVT::Other, getControlRoot(), Cond, 1583 DAG.getBasicBlock(CB.TrueBB)); 1584 1585 // Insert the false branch. Do this even if it's a fall through branch, 1586 // this makes it easier to do DAG optimizations which require inverting 1587 // the branch condition. 1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1589 DAG.getBasicBlock(CB.FalseBB)); 1590 1591 DAG.setRoot(BrCond); 1592} 1593 1594/// visitJumpTable - Emit JumpTable node in the current MBB 1595void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1596 // Emit the code for the jump table 1597 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1598 EVT PTy = TLI.getPointerTy(); 1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1600 JT.Reg, PTy); 1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1603 MVT::Other, Index.getValue(1), 1604 Table, Index); 1605 DAG.setRoot(BrJumpTable); 1606} 1607 1608/// visitJumpTableHeader - This function emits necessary code to produce index 1609/// in the JumpTable from switch case. 1610void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1611 JumpTableHeader &JTH, 1612 MachineBasicBlock *SwitchBB) { 1613 // Subtract the lowest switch case value from the value being switched on and 1614 // conditional branch to default mbb if the result is greater than the 1615 // difference between smallest and largest cases. 1616 SDValue SwitchOp = getValue(JTH.SValue); 1617 EVT VT = SwitchOp.getValueType(); 1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1619 DAG.getConstant(JTH.First, VT)); 1620 1621 // The SDNode we just created, which holds the value being switched on minus 1622 // the smallest case value, needs to be copied to a virtual register so it 1623 // can be used as an index into the jump table in a subsequent basic block. 1624 // This value may be smaller or larger than the target's pointer type, and 1625 // therefore require extension or truncating. 1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1627 1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1630 JumpTableReg, SwitchOp); 1631 JT.Reg = JumpTableReg; 1632 1633 // Emit the range check for the jump table, and branch to the default block 1634 // for the switch statement if the value being switched on exceeds the largest 1635 // case in the switch. 1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1638 DAG.getConstant(JTH.Last-JTH.First,VT), 1639 ISD::SETUGT); 1640 1641 // Set NextBlock to be the MBB immediately after the current one, if any. 1642 // This is used to avoid emitting unnecessary branches to the next block. 1643 MachineBasicBlock *NextBlock = 0; 1644 MachineFunction::iterator BBI = SwitchBB; 1645 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1650 MVT::Other, CopyTo, CMP, 1651 DAG.getBasicBlock(JT.Default)); 1652 1653 if (JT.MBB != NextBlock) 1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1655 DAG.getBasicBlock(JT.MBB)); 1656 1657 DAG.setRoot(BrCond); 1658} 1659 1660/// visitBitTestHeader - This function emits necessary code to produce value 1661/// suitable for "bit tests" 1662void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1663 MachineBasicBlock *SwitchBB) { 1664 // Subtract the minimum value 1665 SDValue SwitchOp = getValue(B.SValue); 1666 EVT VT = SwitchOp.getValueType(); 1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1668 DAG.getConstant(B.First, VT)); 1669 1670 // Check range 1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1672 TLI.getSetCCResultType(Sub.getValueType()), 1673 Sub, DAG.getConstant(B.Range, VT), 1674 ISD::SETUGT); 1675 1676 // Determine the type of the test operands. 1677 bool UsePtrType = false; 1678 if (!TLI.isTypeLegal(VT)) 1679 UsePtrType = true; 1680 else { 1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1683 // Switch table case range are encoded into series of masks. 1684 // Just use pointer type, it's guaranteed to fit. 1685 UsePtrType = true; 1686 break; 1687 } 1688 } 1689 if (UsePtrType) { 1690 VT = TLI.getPointerTy(); 1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1692 } 1693 1694 B.RegVT = VT; 1695 B.Reg = FuncInfo.CreateReg(VT); 1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1697 B.Reg, Sub); 1698 1699 // Set NextBlock to be the MBB immediately after the current one, if any. 1700 // This is used to avoid emitting unnecessary branches to the next block. 1701 MachineBasicBlock *NextBlock = 0; 1702 MachineFunction::iterator BBI = SwitchBB; 1703 if (++BBI != FuncInfo.MF->end()) 1704 NextBlock = BBI; 1705 1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1707 1708 addSuccessorWithWeight(SwitchBB, B.Default); 1709 addSuccessorWithWeight(SwitchBB, MBB); 1710 1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1712 MVT::Other, CopyTo, RangeCmp, 1713 DAG.getBasicBlock(B.Default)); 1714 1715 if (MBB != NextBlock) 1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1717 DAG.getBasicBlock(MBB)); 1718 1719 DAG.setRoot(BrRange); 1720} 1721 1722/// visitBitTestCase - this function produces one "bit test" 1723void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1724 MachineBasicBlock* NextMBB, 1725 unsigned Reg, 1726 BitTestCase &B, 1727 MachineBasicBlock *SwitchBB) { 1728 EVT VT = BB.RegVT; 1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1730 Reg, VT); 1731 SDValue Cmp; 1732 unsigned PopCount = CountPopulation_64(B.Mask); 1733 if (PopCount == 1) { 1734 // Testing for a single bit; just compare the shift count with what it 1735 // would need to be to shift a 1 bit in that position. 1736 Cmp = DAG.getSetCC(getCurDebugLoc(), 1737 TLI.getSetCCResultType(VT), 1738 ShiftOp, 1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1740 ISD::SETEQ); 1741 } else if (PopCount == BB.Range) { 1742 // There is only one zero bit in the range, test for it directly. 1743 Cmp = DAG.getSetCC(getCurDebugLoc(), 1744 TLI.getSetCCResultType(VT), 1745 ShiftOp, 1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1747 ISD::SETNE); 1748 } else { 1749 // Make desired shift 1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1751 DAG.getConstant(1, VT), ShiftOp); 1752 1753 // Emit bit tests and jumps 1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 AndOp, DAG.getConstant(0, VT), 1759 ISD::SETNE); 1760 } 1761 1762 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1763 addSuccessorWithWeight(SwitchBB, NextMBB); 1764 1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1766 MVT::Other, getControlRoot(), 1767 Cmp, DAG.getBasicBlock(B.TargetBB)); 1768 1769 // Set NextBlock to be the MBB immediately after the current one, if any. 1770 // This is used to avoid emitting unnecessary branches to the next block. 1771 MachineBasicBlock *NextBlock = 0; 1772 MachineFunction::iterator BBI = SwitchBB; 1773 if (++BBI != FuncInfo.MF->end()) 1774 NextBlock = BBI; 1775 1776 if (NextMBB != NextBlock) 1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1778 DAG.getBasicBlock(NextMBB)); 1779 1780 DAG.setRoot(BrAnd); 1781} 1782 1783void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1785 1786 // Retrieve successors. 1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1789 1790 const Value *Callee(I.getCalledValue()); 1791 if (isa<InlineAsm>(Callee)) 1792 visitInlineAsm(&I); 1793 else 1794 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1795 1796 // If the value of the invoke is used outside of its defining block, make it 1797 // available as a virtual register. 1798 CopyToExportRegsIfNeeded(&I); 1799 1800 // Update successor info 1801 InvokeMBB->addSuccessor(Return); 1802 InvokeMBB->addSuccessor(LandingPad); 1803 1804 // Drop into normal successor. 1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 DAG.getBasicBlock(Return))); 1808} 1809 1810void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1811} 1812 1813void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1815} 1816 1817void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1818 assert(FuncInfo.MBB->isLandingPad() && 1819 "Call to landingpad not in landing pad!"); 1820 1821 MachineBasicBlock *MBB = FuncInfo.MBB; 1822 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1823 AddLandingPadInfo(LP, MMI, MBB); 1824 1825 SmallVector<EVT, 2> ValueVTs; 1826 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1827 1828 // Insert the EXCEPTIONADDR instruction. 1829 assert(FuncInfo.MBB->isLandingPad() && 1830 "Call to eh.exception not in landing pad!"); 1831 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1832 SDValue Ops[2]; 1833 Ops[0] = DAG.getRoot(); 1834 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1835 SDValue Chain = Op1.getValue(1); 1836 1837 // Insert the EHSELECTION instruction. 1838 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1839 Ops[0] = Op1; 1840 Ops[1] = Chain; 1841 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1842 Chain = Op2.getValue(1); 1843 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1844 1845 Ops[0] = Op1; 1846 Ops[1] = Op2; 1847 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1848 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1849 &Ops[0], 2); 1850 1851 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1852 setValue(&LP, RetPair.first); 1853 DAG.setRoot(RetPair.second); 1854} 1855 1856/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1857/// small case ranges). 1858bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1859 CaseRecVector& WorkList, 1860 const Value* SV, 1861 MachineBasicBlock *Default, 1862 MachineBasicBlock *SwitchBB) { 1863 Case& BackCase = *(CR.Range.second-1); 1864 1865 // Size is the number of Cases represented by this range. 1866 size_t Size = CR.Range.second - CR.Range.first; 1867 if (Size > 3) 1868 return false; 1869 1870 // Get the MachineFunction which holds the current MBB. This is used when 1871 // inserting any additional MBBs necessary to represent the switch. 1872 MachineFunction *CurMF = FuncInfo.MF; 1873 1874 // Figure out which block is immediately after the current one. 1875 MachineBasicBlock *NextBlock = 0; 1876 MachineFunction::iterator BBI = CR.CaseBB; 1877 1878 if (++BBI != FuncInfo.MF->end()) 1879 NextBlock = BBI; 1880 1881 // If any two of the cases has the same destination, and if one value 1882 // is the same as the other, but has one bit unset that the other has set, 1883 // use bit manipulation to do two compares at once. For example: 1884 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1885 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1886 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1887 if (Size == 2 && CR.CaseBB == SwitchBB) { 1888 Case &Small = *CR.Range.first; 1889 Case &Big = *(CR.Range.second-1); 1890 1891 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1892 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1893 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1894 1895 // Check that there is only one bit different. 1896 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1897 (SmallValue | BigValue) == BigValue) { 1898 // Isolate the common bit. 1899 APInt CommonBit = BigValue & ~SmallValue; 1900 assert((SmallValue | CommonBit) == BigValue && 1901 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1902 1903 SDValue CondLHS = getValue(SV); 1904 EVT VT = CondLHS.getValueType(); 1905 DebugLoc DL = getCurDebugLoc(); 1906 1907 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1908 DAG.getConstant(CommonBit, VT)); 1909 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1910 Or, DAG.getConstant(BigValue, VT), 1911 ISD::SETEQ); 1912 1913 // Update successor info. 1914 addSuccessorWithWeight(SwitchBB, Small.BB); 1915 addSuccessorWithWeight(SwitchBB, Default); 1916 1917 // Insert the true branch. 1918 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1919 getControlRoot(), Cond, 1920 DAG.getBasicBlock(Small.BB)); 1921 1922 // Insert the false branch. 1923 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1924 DAG.getBasicBlock(Default)); 1925 1926 DAG.setRoot(BrCond); 1927 return true; 1928 } 1929 } 1930 } 1931 1932 // Rearrange the case blocks so that the last one falls through if possible. 1933 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1934 // The last case block won't fall through into 'NextBlock' if we emit the 1935 // branches in this order. See if rearranging a case value would help. 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1937 if (I->BB == NextBlock) { 1938 std::swap(*I, BackCase); 1939 break; 1940 } 1941 } 1942 } 1943 1944 // Create a CaseBlock record representing a conditional branch to 1945 // the Case's target mbb if the value being switched on SV is equal 1946 // to C. 1947 MachineBasicBlock *CurBlock = CR.CaseBB; 1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1949 MachineBasicBlock *FallThrough; 1950 if (I != E-1) { 1951 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1952 CurMF->insert(BBI, FallThrough); 1953 1954 // Put SV in a virtual register to make it available from the new blocks. 1955 ExportFromCurrentBlock(SV); 1956 } else { 1957 // If the last case doesn't match, go to the default block. 1958 FallThrough = Default; 1959 } 1960 1961 const Value *RHS, *LHS, *MHS; 1962 ISD::CondCode CC; 1963 if (I->High == I->Low) { 1964 // This is just small small case range :) containing exactly 1 case 1965 CC = ISD::SETEQ; 1966 LHS = SV; RHS = I->High; MHS = NULL; 1967 } else { 1968 CC = ISD::SETLE; 1969 LHS = I->Low; MHS = SV; RHS = I->High; 1970 } 1971 1972 uint32_t ExtraWeight = I->ExtraWeight; 1973 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1974 /* me */ CurBlock, 1975 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1976 1977 // If emitting the first comparison, just call visitSwitchCase to emit the 1978 // code into the current block. Otherwise, push the CaseBlock onto the 1979 // vector to be later processed by SDISel, and insert the node's MBB 1980 // before the next MBB. 1981 if (CurBlock == SwitchBB) 1982 visitSwitchCase(CB, SwitchBB); 1983 else 1984 SwitchCases.push_back(CB); 1985 1986 CurBlock = FallThrough; 1987 } 1988 1989 return true; 1990} 1991 1992static inline bool areJTsAllowed(const TargetLowering &TLI) { 1993 return !DisableJumpTables && 1994 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1995 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1996} 1997 1998static APInt ComputeRange(const APInt &First, const APInt &Last) { 1999 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2000 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2001 return (LastExt - FirstExt + 1ULL); 2002} 2003 2004/// handleJTSwitchCase - Emit jumptable for current switch case range 2005bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 2006 CaseRecVector& WorkList, 2007 const Value* SV, 2008 MachineBasicBlock* Default, 2009 MachineBasicBlock *SwitchBB) { 2010 Case& FrontCase = *CR.Range.first; 2011 Case& BackCase = *(CR.Range.second-1); 2012 2013 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2014 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2015 2016 APInt TSize(First.getBitWidth(), 0); 2017 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2018 I!=E; ++I) 2019 TSize += I->size(); 2020 2021 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2022 return false; 2023 2024 APInt Range = ComputeRange(First, Last); 2025 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2026 if (Density < 0.4) 2027 return false; 2028 2029 DEBUG(dbgs() << "Lowering jump table\n" 2030 << "First entry: " << First << ". Last entry: " << Last << '\n' 2031 << "Range: " << Range 2032 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2033 2034 // Get the MachineFunction which holds the current MBB. This is used when 2035 // inserting any additional MBBs necessary to represent the switch. 2036 MachineFunction *CurMF = FuncInfo.MF; 2037 2038 // Figure out which block is immediately after the current one. 2039 MachineFunction::iterator BBI = CR.CaseBB; 2040 ++BBI; 2041 2042 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2043 2044 // Create a new basic block to hold the code for loading the address 2045 // of the jump table, and jumping to it. Update successor information; 2046 // we will either branch to the default case for the switch, or the jump 2047 // table. 2048 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2049 CurMF->insert(BBI, JumpTableBB); 2050 2051 addSuccessorWithWeight(CR.CaseBB, Default); 2052 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2053 2054 // Build a vector of destination BBs, corresponding to each target 2055 // of the jump table. If the value of the jump table slot corresponds to 2056 // a case statement, push the case's BB onto the vector, otherwise, push 2057 // the default BB. 2058 std::vector<MachineBasicBlock*> DestBBs; 2059 APInt TEI = First; 2060 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2061 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2062 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2063 2064 if (Low.sle(TEI) && TEI.sle(High)) { 2065 DestBBs.push_back(I->BB); 2066 if (TEI==High) 2067 ++I; 2068 } else { 2069 DestBBs.push_back(Default); 2070 } 2071 } 2072 2073 // Update successor info. Add one edge to each unique successor. 2074 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2075 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2076 E = DestBBs.end(); I != E; ++I) { 2077 if (!SuccsHandled[(*I)->getNumber()]) { 2078 SuccsHandled[(*I)->getNumber()] = true; 2079 addSuccessorWithWeight(JumpTableBB, *I); 2080 } 2081 } 2082 2083 // Create a jump table index for this jump table. 2084 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2085 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2086 ->createJumpTableIndex(DestBBs); 2087 2088 // Set the jump table information so that we can codegen it as a second 2089 // MachineBasicBlock 2090 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2091 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2092 if (CR.CaseBB == SwitchBB) 2093 visitJumpTableHeader(JT, JTH, SwitchBB); 2094 2095 JTCases.push_back(JumpTableBlock(JTH, JT)); 2096 2097 return true; 2098} 2099 2100/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2101/// 2 subtrees. 2102bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2103 CaseRecVector& WorkList, 2104 const Value* SV, 2105 MachineBasicBlock *Default, 2106 MachineBasicBlock *SwitchBB) { 2107 // Get the MachineFunction which holds the current MBB. This is used when 2108 // inserting any additional MBBs necessary to represent the switch. 2109 MachineFunction *CurMF = FuncInfo.MF; 2110 2111 // Figure out which block is immediately after the current one. 2112 MachineFunction::iterator BBI = CR.CaseBB; 2113 ++BBI; 2114 2115 Case& FrontCase = *CR.Range.first; 2116 Case& BackCase = *(CR.Range.second-1); 2117 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2118 2119 // Size is the number of Cases represented by this range. 2120 unsigned Size = CR.Range.second - CR.Range.first; 2121 2122 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2123 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2124 double FMetric = 0; 2125 CaseItr Pivot = CR.Range.first + Size/2; 2126 2127 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2128 // (heuristically) allow us to emit JumpTable's later. 2129 APInt TSize(First.getBitWidth(), 0); 2130 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2131 I!=E; ++I) 2132 TSize += I->size(); 2133 2134 APInt LSize = FrontCase.size(); 2135 APInt RSize = TSize-LSize; 2136 DEBUG(dbgs() << "Selecting best pivot: \n" 2137 << "First: " << First << ", Last: " << Last <<'\n' 2138 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2139 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2140 J!=E; ++I, ++J) { 2141 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2142 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2143 APInt Range = ComputeRange(LEnd, RBegin); 2144 assert((Range - 2ULL).isNonNegative() && 2145 "Invalid case distance"); 2146 // Use volatile double here to avoid excess precision issues on some hosts, 2147 // e.g. that use 80-bit X87 registers. 2148 volatile double LDensity = 2149 (double)LSize.roundToDouble() / 2150 (LEnd - First + 1ULL).roundToDouble(); 2151 volatile double RDensity = 2152 (double)RSize.roundToDouble() / 2153 (Last - RBegin + 1ULL).roundToDouble(); 2154 double Metric = Range.logBase2()*(LDensity+RDensity); 2155 // Should always split in some non-trivial place 2156 DEBUG(dbgs() <<"=>Step\n" 2157 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2158 << "LDensity: " << LDensity 2159 << ", RDensity: " << RDensity << '\n' 2160 << "Metric: " << Metric << '\n'); 2161 if (FMetric < Metric) { 2162 Pivot = J; 2163 FMetric = Metric; 2164 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2165 } 2166 2167 LSize += J->size(); 2168 RSize -= J->size(); 2169 } 2170 if (areJTsAllowed(TLI)) { 2171 // If our case is dense we *really* should handle it earlier! 2172 assert((FMetric > 0) && "Should handle dense range earlier!"); 2173 } else { 2174 Pivot = CR.Range.first + Size/2; 2175 } 2176 2177 CaseRange LHSR(CR.Range.first, Pivot); 2178 CaseRange RHSR(Pivot, CR.Range.second); 2179 Constant *C = Pivot->Low; 2180 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2181 2182 // We know that we branch to the LHS if the Value being switched on is 2183 // less than the Pivot value, C. We use this to optimize our binary 2184 // tree a bit, by recognizing that if SV is greater than or equal to the 2185 // LHS's Case Value, and that Case Value is exactly one less than the 2186 // Pivot's Value, then we can branch directly to the LHS's Target, 2187 // rather than creating a leaf node for it. 2188 if ((LHSR.second - LHSR.first) == 1 && 2189 LHSR.first->High == CR.GE && 2190 cast<ConstantInt>(C)->getValue() == 2191 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2192 TrueBB = LHSR.first->BB; 2193 } else { 2194 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2195 CurMF->insert(BBI, TrueBB); 2196 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2197 2198 // Put SV in a virtual register to make it available from the new blocks. 2199 ExportFromCurrentBlock(SV); 2200 } 2201 2202 // Similar to the optimization above, if the Value being switched on is 2203 // known to be less than the Constant CR.LT, and the current Case Value 2204 // is CR.LT - 1, then we can branch directly to the target block for 2205 // the current Case Value, rather than emitting a RHS leaf node for it. 2206 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2207 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2208 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2209 FalseBB = RHSR.first->BB; 2210 } else { 2211 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2212 CurMF->insert(BBI, FalseBB); 2213 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2214 2215 // Put SV in a virtual register to make it available from the new blocks. 2216 ExportFromCurrentBlock(SV); 2217 } 2218 2219 // Create a CaseBlock record representing a conditional branch to 2220 // the LHS node if the value being switched on SV is less than C. 2221 // Otherwise, branch to LHS. 2222 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2223 2224 if (CR.CaseBB == SwitchBB) 2225 visitSwitchCase(CB, SwitchBB); 2226 else 2227 SwitchCases.push_back(CB); 2228 2229 return true; 2230} 2231 2232/// handleBitTestsSwitchCase - if current case range has few destination and 2233/// range span less, than machine word bitwidth, encode case range into series 2234/// of masks and emit bit tests with these masks. 2235bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2236 CaseRecVector& WorkList, 2237 const Value* SV, 2238 MachineBasicBlock* Default, 2239 MachineBasicBlock *SwitchBB){ 2240 EVT PTy = TLI.getPointerTy(); 2241 unsigned IntPtrBits = PTy.getSizeInBits(); 2242 2243 Case& FrontCase = *CR.Range.first; 2244 Case& BackCase = *(CR.Range.second-1); 2245 2246 // Get the MachineFunction which holds the current MBB. This is used when 2247 // inserting any additional MBBs necessary to represent the switch. 2248 MachineFunction *CurMF = FuncInfo.MF; 2249 2250 // If target does not have legal shift left, do not emit bit tests at all. 2251 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2252 return false; 2253 2254 size_t numCmps = 0; 2255 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2256 I!=E; ++I) { 2257 // Single case counts one, case range - two. 2258 numCmps += (I->Low == I->High ? 1 : 2); 2259 } 2260 2261 // Count unique destinations 2262 SmallSet<MachineBasicBlock*, 4> Dests; 2263 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2264 Dests.insert(I->BB); 2265 if (Dests.size() > 3) 2266 // Don't bother the code below, if there are too much unique destinations 2267 return false; 2268 } 2269 DEBUG(dbgs() << "Total number of unique destinations: " 2270 << Dests.size() << '\n' 2271 << "Total number of comparisons: " << numCmps << '\n'); 2272 2273 // Compute span of values. 2274 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2275 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2276 APInt cmpRange = maxValue - minValue; 2277 2278 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2279 << "Low bound: " << minValue << '\n' 2280 << "High bound: " << maxValue << '\n'); 2281 2282 if (cmpRange.uge(IntPtrBits) || 2283 (!(Dests.size() == 1 && numCmps >= 3) && 2284 !(Dests.size() == 2 && numCmps >= 5) && 2285 !(Dests.size() >= 3 && numCmps >= 6))) 2286 return false; 2287 2288 DEBUG(dbgs() << "Emitting bit tests\n"); 2289 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2290 2291 // Optimize the case where all the case values fit in a 2292 // word without having to subtract minValue. In this case, 2293 // we can optimize away the subtraction. 2294 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2295 cmpRange = maxValue; 2296 } else { 2297 lowBound = minValue; 2298 } 2299 2300 CaseBitsVector CasesBits; 2301 unsigned i, count = 0; 2302 2303 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2304 MachineBasicBlock* Dest = I->BB; 2305 for (i = 0; i < count; ++i) 2306 if (Dest == CasesBits[i].BB) 2307 break; 2308 2309 if (i == count) { 2310 assert((count < 3) && "Too much destinations to test!"); 2311 CasesBits.push_back(CaseBits(0, Dest, 0)); 2312 count++; 2313 } 2314 2315 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2316 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2317 2318 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2319 uint64_t hi = (highValue - lowBound).getZExtValue(); 2320 2321 for (uint64_t j = lo; j <= hi; j++) { 2322 CasesBits[i].Mask |= 1ULL << j; 2323 CasesBits[i].Bits++; 2324 } 2325 2326 } 2327 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2328 2329 BitTestInfo BTC; 2330 2331 // Figure out which block is immediately after the current one. 2332 MachineFunction::iterator BBI = CR.CaseBB; 2333 ++BBI; 2334 2335 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2336 2337 DEBUG(dbgs() << "Cases:\n"); 2338 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2339 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2340 << ", Bits: " << CasesBits[i].Bits 2341 << ", BB: " << CasesBits[i].BB << '\n'); 2342 2343 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2344 CurMF->insert(BBI, CaseBB); 2345 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2346 CaseBB, 2347 CasesBits[i].BB)); 2348 2349 // Put SV in a virtual register to make it available from the new blocks. 2350 ExportFromCurrentBlock(SV); 2351 } 2352 2353 BitTestBlock BTB(lowBound, cmpRange, SV, 2354 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2355 CR.CaseBB, Default, BTC); 2356 2357 if (CR.CaseBB == SwitchBB) 2358 visitBitTestHeader(BTB, SwitchBB); 2359 2360 BitTestCases.push_back(BTB); 2361 2362 return true; 2363} 2364 2365/// Clusterify - Transform simple list of Cases into list of CaseRange's 2366size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2367 const SwitchInst& SI) { 2368 size_t numCmps = 0; 2369 2370 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2371 // Start with "simple" cases 2372 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2373 BasicBlock *SuccBB = SI.getSuccessor(i); 2374 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2375 2376 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2377 2378 Cases.push_back(Case(SI.getSuccessorValue(i), 2379 SI.getSuccessorValue(i), 2380 SMBB, ExtraWeight)); 2381 } 2382 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2383 2384 // Merge case into clusters 2385 if (Cases.size() >= 2) 2386 // Must recompute end() each iteration because it may be 2387 // invalidated by erase if we hold on to it 2388 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2389 J != Cases.end(); ) { 2390 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2391 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2392 MachineBasicBlock* nextBB = J->BB; 2393 MachineBasicBlock* currentBB = I->BB; 2394 2395 // If the two neighboring cases go to the same destination, merge them 2396 // into a single case. 2397 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2398 I->High = J->High; 2399 J = Cases.erase(J); 2400 2401 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2402 uint32_t CurWeight = currentBB->getBasicBlock() ? 2403 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2404 uint32_t NextWeight = nextBB->getBasicBlock() ? 2405 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2406 2407 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2408 CurWeight + NextWeight); 2409 } 2410 } else { 2411 I = J++; 2412 } 2413 } 2414 2415 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2416 if (I->Low != I->High) 2417 // A range counts double, since it requires two compares. 2418 ++numCmps; 2419 } 2420 2421 return numCmps; 2422} 2423 2424void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2425 MachineBasicBlock *Last) { 2426 // Update JTCases. 2427 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2428 if (JTCases[i].first.HeaderBB == First) 2429 JTCases[i].first.HeaderBB = Last; 2430 2431 // Update BitTestCases. 2432 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2433 if (BitTestCases[i].Parent == First) 2434 BitTestCases[i].Parent = Last; 2435} 2436 2437void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2438 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2439 2440 // Figure out which block is immediately after the current one. 2441 MachineBasicBlock *NextBlock = 0; 2442 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2443 2444 // If there is only the default destination, branch to it if it is not the 2445 // next basic block. Otherwise, just fall through. 2446 if (SI.getNumOperands() == 2) { 2447 // Update machine-CFG edges. 2448 2449 // If this is not a fall-through branch, emit the branch. 2450 SwitchMBB->addSuccessor(Default); 2451 if (Default != NextBlock) 2452 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2453 MVT::Other, getControlRoot(), 2454 DAG.getBasicBlock(Default))); 2455 2456 return; 2457 } 2458 2459 // If there are any non-default case statements, create a vector of Cases 2460 // representing each one, and sort the vector so that we can efficiently 2461 // create a binary search tree from them. 2462 CaseVector Cases; 2463 size_t numCmps = Clusterify(Cases, SI); 2464 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2465 << ". Total compares: " << numCmps << '\n'); 2466 numCmps = 0; 2467 2468 // Get the Value to be switched on and default basic blocks, which will be 2469 // inserted into CaseBlock records, representing basic blocks in the binary 2470 // search tree. 2471 const Value *SV = SI.getOperand(0); 2472 2473 // Push the initial CaseRec onto the worklist 2474 CaseRecVector WorkList; 2475 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2476 CaseRange(Cases.begin(),Cases.end()))); 2477 2478 while (!WorkList.empty()) { 2479 // Grab a record representing a case range to process off the worklist 2480 CaseRec CR = WorkList.back(); 2481 WorkList.pop_back(); 2482 2483 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2484 continue; 2485 2486 // If the range has few cases (two or less) emit a series of specific 2487 // tests. 2488 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2489 continue; 2490 2491 // If the switch has more than 5 blocks, and at least 40% dense, and the 2492 // target supports indirect branches, then emit a jump table rather than 2493 // lowering the switch to a binary tree of conditional branches. 2494 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2495 continue; 2496 2497 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2498 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2499 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2500 } 2501} 2502 2503void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2504 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2505 2506 // Update machine-CFG edges with unique successors. 2507 SmallVector<BasicBlock*, 32> succs; 2508 succs.reserve(I.getNumSuccessors()); 2509 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2510 succs.push_back(I.getSuccessor(i)); 2511 array_pod_sort(succs.begin(), succs.end()); 2512 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2513 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2514 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2515 addSuccessorWithWeight(IndirectBrMBB, Succ); 2516 } 2517 2518 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2519 MVT::Other, getControlRoot(), 2520 getValue(I.getAddress()))); 2521} 2522 2523void SelectionDAGBuilder::visitFSub(const User &I) { 2524 // -0.0 - X --> fneg 2525 Type *Ty = I.getType(); 2526 if (isa<Constant>(I.getOperand(0)) && 2527 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2528 SDValue Op2 = getValue(I.getOperand(1)); 2529 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2530 Op2.getValueType(), Op2)); 2531 return; 2532 } 2533 2534 visitBinary(I, ISD::FSUB); 2535} 2536 2537void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2538 SDValue Op1 = getValue(I.getOperand(0)); 2539 SDValue Op2 = getValue(I.getOperand(1)); 2540 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2541 Op1.getValueType(), Op1, Op2)); 2542} 2543 2544void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2545 SDValue Op1 = getValue(I.getOperand(0)); 2546 SDValue Op2 = getValue(I.getOperand(1)); 2547 2548 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2549 2550 // Coerce the shift amount to the right type if we can. 2551 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2552 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2553 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2554 DebugLoc DL = getCurDebugLoc(); 2555 2556 // If the operand is smaller than the shift count type, promote it. 2557 if (ShiftSize > Op2Size) 2558 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2559 2560 // If the operand is larger than the shift count type but the shift 2561 // count type has enough bits to represent any shift value, truncate 2562 // it now. This is a common case and it exposes the truncate to 2563 // optimization early. 2564 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2565 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2566 // Otherwise we'll need to temporarily settle for some other convenient 2567 // type. Type legalization will make adjustments once the shiftee is split. 2568 else 2569 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2570 } 2571 2572 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2573 Op1.getValueType(), Op1, Op2)); 2574} 2575 2576void SelectionDAGBuilder::visitSDiv(const User &I) { 2577 SDValue Op1 = getValue(I.getOperand(0)); 2578 SDValue Op2 = getValue(I.getOperand(1)); 2579 2580 // Turn exact SDivs into multiplications. 2581 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2582 // exact bit. 2583 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2584 !isa<ConstantSDNode>(Op1) && 2585 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2586 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2587 else 2588 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2589 Op1, Op2)); 2590} 2591 2592void SelectionDAGBuilder::visitICmp(const User &I) { 2593 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2594 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2595 predicate = IC->getPredicate(); 2596 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2597 predicate = ICmpInst::Predicate(IC->getPredicate()); 2598 SDValue Op1 = getValue(I.getOperand(0)); 2599 SDValue Op2 = getValue(I.getOperand(1)); 2600 ISD::CondCode Opcode = getICmpCondCode(predicate); 2601 2602 EVT DestVT = TLI.getValueType(I.getType()); 2603 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2604} 2605 2606void SelectionDAGBuilder::visitFCmp(const User &I) { 2607 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2608 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2609 predicate = FC->getPredicate(); 2610 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2611 predicate = FCmpInst::Predicate(FC->getPredicate()); 2612 SDValue Op1 = getValue(I.getOperand(0)); 2613 SDValue Op2 = getValue(I.getOperand(1)); 2614 ISD::CondCode Condition = getFCmpCondCode(predicate); 2615 EVT DestVT = TLI.getValueType(I.getType()); 2616 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2617} 2618 2619void SelectionDAGBuilder::visitSelect(const User &I) { 2620 SmallVector<EVT, 4> ValueVTs; 2621 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2622 unsigned NumValues = ValueVTs.size(); 2623 if (NumValues == 0) return; 2624 2625 SmallVector<SDValue, 4> Values(NumValues); 2626 SDValue Cond = getValue(I.getOperand(0)); 2627 SDValue TrueVal = getValue(I.getOperand(1)); 2628 SDValue FalseVal = getValue(I.getOperand(2)); 2629 2630 for (unsigned i = 0; i != NumValues; ++i) 2631 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2632 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2633 Cond, 2634 SDValue(TrueVal.getNode(), 2635 TrueVal.getResNo() + i), 2636 SDValue(FalseVal.getNode(), 2637 FalseVal.getResNo() + i)); 2638 2639 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2640 DAG.getVTList(&ValueVTs[0], NumValues), 2641 &Values[0], NumValues)); 2642} 2643 2644void SelectionDAGBuilder::visitTrunc(const User &I) { 2645 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2646 SDValue N = getValue(I.getOperand(0)); 2647 EVT DestVT = TLI.getValueType(I.getType()); 2648 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2649} 2650 2651void SelectionDAGBuilder::visitZExt(const User &I) { 2652 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2653 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2654 SDValue N = getValue(I.getOperand(0)); 2655 EVT DestVT = TLI.getValueType(I.getType()); 2656 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2657} 2658 2659void SelectionDAGBuilder::visitSExt(const User &I) { 2660 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2661 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2662 SDValue N = getValue(I.getOperand(0)); 2663 EVT DestVT = TLI.getValueType(I.getType()); 2664 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2665} 2666 2667void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2668 // FPTrunc is never a no-op cast, no need to check 2669 SDValue N = getValue(I.getOperand(0)); 2670 EVT DestVT = TLI.getValueType(I.getType()); 2671 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2672 DestVT, N, DAG.getIntPtrConstant(0))); 2673} 2674 2675void SelectionDAGBuilder::visitFPExt(const User &I){ 2676 // FPTrunc is never a no-op cast, no need to check 2677 SDValue N = getValue(I.getOperand(0)); 2678 EVT DestVT = TLI.getValueType(I.getType()); 2679 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2680} 2681 2682void SelectionDAGBuilder::visitFPToUI(const User &I) { 2683 // FPToUI is never a no-op cast, no need to check 2684 SDValue N = getValue(I.getOperand(0)); 2685 EVT DestVT = TLI.getValueType(I.getType()); 2686 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2687} 2688 2689void SelectionDAGBuilder::visitFPToSI(const User &I) { 2690 // FPToSI is never a no-op cast, no need to check 2691 SDValue N = getValue(I.getOperand(0)); 2692 EVT DestVT = TLI.getValueType(I.getType()); 2693 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2694} 2695 2696void SelectionDAGBuilder::visitUIToFP(const User &I) { 2697 // UIToFP is never a no-op cast, no need to check 2698 SDValue N = getValue(I.getOperand(0)); 2699 EVT DestVT = TLI.getValueType(I.getType()); 2700 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2701} 2702 2703void SelectionDAGBuilder::visitSIToFP(const User &I){ 2704 // SIToFP is never a no-op cast, no need to check 2705 SDValue N = getValue(I.getOperand(0)); 2706 EVT DestVT = TLI.getValueType(I.getType()); 2707 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2708} 2709 2710void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2711 // What to do depends on the size of the integer and the size of the pointer. 2712 // We can either truncate, zero extend, or no-op, accordingly. 2713 SDValue N = getValue(I.getOperand(0)); 2714 EVT DestVT = TLI.getValueType(I.getType()); 2715 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2716} 2717 2718void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2719 // What to do depends on the size of the integer and the size of the pointer. 2720 // We can either truncate, zero extend, or no-op, accordingly. 2721 SDValue N = getValue(I.getOperand(0)); 2722 EVT DestVT = TLI.getValueType(I.getType()); 2723 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2724} 2725 2726void SelectionDAGBuilder::visitBitCast(const User &I) { 2727 SDValue N = getValue(I.getOperand(0)); 2728 EVT DestVT = TLI.getValueType(I.getType()); 2729 2730 // BitCast assures us that source and destination are the same size so this is 2731 // either a BITCAST or a no-op. 2732 if (DestVT != N.getValueType()) 2733 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2734 DestVT, N)); // convert types. 2735 else 2736 setValue(&I, N); // noop cast. 2737} 2738 2739void SelectionDAGBuilder::visitInsertElement(const User &I) { 2740 SDValue InVec = getValue(I.getOperand(0)); 2741 SDValue InVal = getValue(I.getOperand(1)); 2742 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2743 TLI.getPointerTy(), 2744 getValue(I.getOperand(2))); 2745 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2746 TLI.getValueType(I.getType()), 2747 InVec, InVal, InIdx)); 2748} 2749 2750void SelectionDAGBuilder::visitExtractElement(const User &I) { 2751 SDValue InVec = getValue(I.getOperand(0)); 2752 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2753 TLI.getPointerTy(), 2754 getValue(I.getOperand(1))); 2755 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2756 TLI.getValueType(I.getType()), InVec, InIdx)); 2757} 2758 2759// Utility for visitShuffleVector - Returns true if the mask is mask starting 2760// from SIndx and increasing to the element length (undefs are allowed). 2761static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2762 unsigned MaskNumElts = Mask.size(); 2763 for (unsigned i = 0; i != MaskNumElts; ++i) 2764 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2765 return false; 2766 return true; 2767} 2768 2769void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2770 SmallVector<int, 8> Mask; 2771 SDValue Src1 = getValue(I.getOperand(0)); 2772 SDValue Src2 = getValue(I.getOperand(1)); 2773 2774 // Convert the ConstantVector mask operand into an array of ints, with -1 2775 // representing undef values. 2776 SmallVector<Constant*, 8> MaskElts; 2777 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2778 unsigned MaskNumElts = MaskElts.size(); 2779 for (unsigned i = 0; i != MaskNumElts; ++i) { 2780 if (isa<UndefValue>(MaskElts[i])) 2781 Mask.push_back(-1); 2782 else 2783 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2784 } 2785 2786 EVT VT = TLI.getValueType(I.getType()); 2787 EVT SrcVT = Src1.getValueType(); 2788 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2789 2790 if (SrcNumElts == MaskNumElts) { 2791 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2792 &Mask[0])); 2793 return; 2794 } 2795 2796 // Normalize the shuffle vector since mask and vector length don't match. 2797 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2798 // Mask is longer than the source vectors and is a multiple of the source 2799 // vectors. We can use concatenate vector to make the mask and vectors 2800 // lengths match. 2801 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2802 // The shuffle is concatenating two vectors together. 2803 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2804 VT, Src1, Src2)); 2805 return; 2806 } 2807 2808 // Pad both vectors with undefs to make them the same length as the mask. 2809 unsigned NumConcat = MaskNumElts / SrcNumElts; 2810 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2811 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2812 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2813 2814 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2815 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2816 MOps1[0] = Src1; 2817 MOps2[0] = Src2; 2818 2819 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2820 getCurDebugLoc(), VT, 2821 &MOps1[0], NumConcat); 2822 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2823 getCurDebugLoc(), VT, 2824 &MOps2[0], NumConcat); 2825 2826 // Readjust mask for new input vector length. 2827 SmallVector<int, 8> MappedOps; 2828 for (unsigned i = 0; i != MaskNumElts; ++i) { 2829 int Idx = Mask[i]; 2830 if (Idx < (int)SrcNumElts) 2831 MappedOps.push_back(Idx); 2832 else 2833 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2834 } 2835 2836 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2837 &MappedOps[0])); 2838 return; 2839 } 2840 2841 if (SrcNumElts > MaskNumElts) { 2842 // Analyze the access pattern of the vector to see if we can extract 2843 // two subvectors and do the shuffle. The analysis is done by calculating 2844 // the range of elements the mask access on both vectors. 2845 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2846 static_cast<int>(SrcNumElts+1)}; 2847 int MaxRange[2] = {-1, -1}; 2848 2849 for (unsigned i = 0; i != MaskNumElts; ++i) { 2850 int Idx = Mask[i]; 2851 int Input = 0; 2852 if (Idx < 0) 2853 continue; 2854 2855 if (Idx >= (int)SrcNumElts) { 2856 Input = 1; 2857 Idx -= SrcNumElts; 2858 } 2859 if (Idx > MaxRange[Input]) 2860 MaxRange[Input] = Idx; 2861 if (Idx < MinRange[Input]) 2862 MinRange[Input] = Idx; 2863 } 2864 2865 // Check if the access is smaller than the vector size and can we find 2866 // a reasonable extract index. 2867 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2868 // Extract. 2869 int StartIdx[2]; // StartIdx to extract from 2870 for (int Input=0; Input < 2; ++Input) { 2871 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2872 RangeUse[Input] = 0; // Unused 2873 StartIdx[Input] = 0; 2874 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2875 // Fits within range but we should see if we can find a good 2876 // start index that is a multiple of the mask length. 2877 if (MaxRange[Input] < (int)MaskNumElts) { 2878 RangeUse[Input] = 1; // Extract from beginning of the vector 2879 StartIdx[Input] = 0; 2880 } else { 2881 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2882 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2883 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2884 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2885 } 2886 } 2887 } 2888 2889 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2890 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2891 return; 2892 } 2893 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2894 // Extract appropriate subvector and generate a vector shuffle 2895 for (int Input=0; Input < 2; ++Input) { 2896 SDValue &Src = Input == 0 ? Src1 : Src2; 2897 if (RangeUse[Input] == 0) 2898 Src = DAG.getUNDEF(VT); 2899 else 2900 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2901 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2902 } 2903 2904 // Calculate new mask. 2905 SmallVector<int, 8> MappedOps; 2906 for (unsigned i = 0; i != MaskNumElts; ++i) { 2907 int Idx = Mask[i]; 2908 if (Idx < 0) 2909 MappedOps.push_back(Idx); 2910 else if (Idx < (int)SrcNumElts) 2911 MappedOps.push_back(Idx - StartIdx[0]); 2912 else 2913 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2914 } 2915 2916 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2917 &MappedOps[0])); 2918 return; 2919 } 2920 } 2921 2922 // We can't use either concat vectors or extract subvectors so fall back to 2923 // replacing the shuffle with extract and build vector. 2924 // to insert and build vector. 2925 EVT EltVT = VT.getVectorElementType(); 2926 EVT PtrVT = TLI.getPointerTy(); 2927 SmallVector<SDValue,8> Ops; 2928 for (unsigned i = 0; i != MaskNumElts; ++i) { 2929 if (Mask[i] < 0) { 2930 Ops.push_back(DAG.getUNDEF(EltVT)); 2931 } else { 2932 int Idx = Mask[i]; 2933 SDValue Res; 2934 2935 if (Idx < (int)SrcNumElts) 2936 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2937 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2938 else 2939 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2940 EltVT, Src2, 2941 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2942 2943 Ops.push_back(Res); 2944 } 2945 } 2946 2947 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2948 VT, &Ops[0], Ops.size())); 2949} 2950 2951void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2952 const Value *Op0 = I.getOperand(0); 2953 const Value *Op1 = I.getOperand(1); 2954 Type *AggTy = I.getType(); 2955 Type *ValTy = Op1->getType(); 2956 bool IntoUndef = isa<UndefValue>(Op0); 2957 bool FromUndef = isa<UndefValue>(Op1); 2958 2959 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2960 2961 SmallVector<EVT, 4> AggValueVTs; 2962 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2963 SmallVector<EVT, 4> ValValueVTs; 2964 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2965 2966 unsigned NumAggValues = AggValueVTs.size(); 2967 unsigned NumValValues = ValValueVTs.size(); 2968 SmallVector<SDValue, 4> Values(NumAggValues); 2969 2970 SDValue Agg = getValue(Op0); 2971 unsigned i = 0; 2972 // Copy the beginning value(s) from the original aggregate. 2973 for (; i != LinearIndex; ++i) 2974 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2975 SDValue(Agg.getNode(), Agg.getResNo() + i); 2976 // Copy values from the inserted value(s). 2977 if (NumValValues) { 2978 SDValue Val = getValue(Op1); 2979 for (; i != LinearIndex + NumValValues; ++i) 2980 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2981 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2982 } 2983 // Copy remaining value(s) from the original aggregate. 2984 for (; i != NumAggValues; ++i) 2985 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2986 SDValue(Agg.getNode(), Agg.getResNo() + i); 2987 2988 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2989 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2990 &Values[0], NumAggValues)); 2991} 2992 2993void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2994 const Value *Op0 = I.getOperand(0); 2995 Type *AggTy = Op0->getType(); 2996 Type *ValTy = I.getType(); 2997 bool OutOfUndef = isa<UndefValue>(Op0); 2998 2999 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3000 3001 SmallVector<EVT, 4> ValValueVTs; 3002 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3003 3004 unsigned NumValValues = ValValueVTs.size(); 3005 3006 // Ignore a extractvalue that produces an empty object 3007 if (!NumValValues) { 3008 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3009 return; 3010 } 3011 3012 SmallVector<SDValue, 4> Values(NumValValues); 3013 3014 SDValue Agg = getValue(Op0); 3015 // Copy out the selected value(s). 3016 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3017 Values[i - LinearIndex] = 3018 OutOfUndef ? 3019 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3020 SDValue(Agg.getNode(), Agg.getResNo() + i); 3021 3022 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3023 DAG.getVTList(&ValValueVTs[0], NumValValues), 3024 &Values[0], NumValValues)); 3025} 3026 3027void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3028 SDValue N = getValue(I.getOperand(0)); 3029 Type *Ty = I.getOperand(0)->getType(); 3030 3031 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3032 OI != E; ++OI) { 3033 const Value *Idx = *OI; 3034 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3035 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3036 if (Field) { 3037 // N = N + Offset 3038 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3039 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3040 DAG.getIntPtrConstant(Offset)); 3041 } 3042 3043 Ty = StTy->getElementType(Field); 3044 } else { 3045 Ty = cast<SequentialType>(Ty)->getElementType(); 3046 3047 // If this is a constant subscript, handle it quickly. 3048 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3049 if (CI->isZero()) continue; 3050 uint64_t Offs = 3051 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3052 SDValue OffsVal; 3053 EVT PTy = TLI.getPointerTy(); 3054 unsigned PtrBits = PTy.getSizeInBits(); 3055 if (PtrBits < 64) 3056 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3057 TLI.getPointerTy(), 3058 DAG.getConstant(Offs, MVT::i64)); 3059 else 3060 OffsVal = DAG.getIntPtrConstant(Offs); 3061 3062 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3063 OffsVal); 3064 continue; 3065 } 3066 3067 // N = N + Idx * ElementSize; 3068 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3069 TD->getTypeAllocSize(Ty)); 3070 SDValue IdxN = getValue(Idx); 3071 3072 // If the index is smaller or larger than intptr_t, truncate or extend 3073 // it. 3074 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3075 3076 // If this is a multiply by a power of two, turn it into a shl 3077 // immediately. This is a very common case. 3078 if (ElementSize != 1) { 3079 if (ElementSize.isPowerOf2()) { 3080 unsigned Amt = ElementSize.logBase2(); 3081 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3082 N.getValueType(), IdxN, 3083 DAG.getConstant(Amt, TLI.getPointerTy())); 3084 } else { 3085 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3086 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3087 N.getValueType(), IdxN, Scale); 3088 } 3089 } 3090 3091 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3092 N.getValueType(), N, IdxN); 3093 } 3094 } 3095 3096 setValue(&I, N); 3097} 3098 3099void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3100 // If this is a fixed sized alloca in the entry block of the function, 3101 // allocate it statically on the stack. 3102 if (FuncInfo.StaticAllocaMap.count(&I)) 3103 return; // getValue will auto-populate this. 3104 3105 Type *Ty = I.getAllocatedType(); 3106 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3107 unsigned Align = 3108 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3109 I.getAlignment()); 3110 3111 SDValue AllocSize = getValue(I.getArraySize()); 3112 3113 EVT IntPtr = TLI.getPointerTy(); 3114 if (AllocSize.getValueType() != IntPtr) 3115 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3116 3117 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3118 AllocSize, 3119 DAG.getConstant(TySize, IntPtr)); 3120 3121 // Handle alignment. If the requested alignment is less than or equal to 3122 // the stack alignment, ignore it. If the size is greater than or equal to 3123 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3124 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3125 if (Align <= StackAlign) 3126 Align = 0; 3127 3128 // Round the size of the allocation up to the stack alignment size 3129 // by add SA-1 to the size. 3130 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3131 AllocSize.getValueType(), AllocSize, 3132 DAG.getIntPtrConstant(StackAlign-1)); 3133 3134 // Mask out the low bits for alignment purposes. 3135 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3136 AllocSize.getValueType(), AllocSize, 3137 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3138 3139 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3140 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3141 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3142 VTs, Ops, 3); 3143 setValue(&I, DSA); 3144 DAG.setRoot(DSA.getValue(1)); 3145 3146 // Inform the Frame Information that we have just allocated a variable-sized 3147 // object. 3148 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3149} 3150 3151void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3152 const Value *SV = I.getOperand(0); 3153 SDValue Ptr = getValue(SV); 3154 3155 Type *Ty = I.getType(); 3156 3157 bool isVolatile = I.isVolatile(); 3158 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3159 unsigned Alignment = I.getAlignment(); 3160 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3161 3162 SmallVector<EVT, 4> ValueVTs; 3163 SmallVector<uint64_t, 4> Offsets; 3164 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3165 unsigned NumValues = ValueVTs.size(); 3166 if (NumValues == 0) 3167 return; 3168 3169 SDValue Root; 3170 bool ConstantMemory = false; 3171 if (I.isVolatile() || NumValues > MaxParallelChains) 3172 // Serialize volatile loads with other side effects. 3173 Root = getRoot(); 3174 else if (AA->pointsToConstantMemory( 3175 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3176 // Do not serialize (non-volatile) loads of constant memory with anything. 3177 Root = DAG.getEntryNode(); 3178 ConstantMemory = true; 3179 } else { 3180 // Do not serialize non-volatile loads against each other. 3181 Root = DAG.getRoot(); 3182 } 3183 3184 SmallVector<SDValue, 4> Values(NumValues); 3185 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3186 NumValues)); 3187 EVT PtrVT = Ptr.getValueType(); 3188 unsigned ChainI = 0; 3189 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3190 // Serializing loads here may result in excessive register pressure, and 3191 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3192 // could recover a bit by hoisting nodes upward in the chain by recognizing 3193 // they are side-effect free or do not alias. The optimizer should really 3194 // avoid this case by converting large object/array copies to llvm.memcpy 3195 // (MaxParallelChains should always remain as failsafe). 3196 if (ChainI == MaxParallelChains) { 3197 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3198 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3199 MVT::Other, &Chains[0], ChainI); 3200 Root = Chain; 3201 ChainI = 0; 3202 } 3203 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3204 PtrVT, Ptr, 3205 DAG.getConstant(Offsets[i], PtrVT)); 3206 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3207 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3208 isNonTemporal, Alignment, TBAAInfo); 3209 3210 Values[i] = L; 3211 Chains[ChainI] = L.getValue(1); 3212 } 3213 3214 if (!ConstantMemory) { 3215 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3216 MVT::Other, &Chains[0], ChainI); 3217 if (isVolatile) 3218 DAG.setRoot(Chain); 3219 else 3220 PendingLoads.push_back(Chain); 3221 } 3222 3223 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3224 DAG.getVTList(&ValueVTs[0], NumValues), 3225 &Values[0], NumValues)); 3226} 3227 3228void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3229 const Value *SrcV = I.getOperand(0); 3230 const Value *PtrV = I.getOperand(1); 3231 3232 SmallVector<EVT, 4> ValueVTs; 3233 SmallVector<uint64_t, 4> Offsets; 3234 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3235 unsigned NumValues = ValueVTs.size(); 3236 if (NumValues == 0) 3237 return; 3238 3239 // Get the lowered operands. Note that we do this after 3240 // checking if NumResults is zero, because with zero results 3241 // the operands won't have values in the map. 3242 SDValue Src = getValue(SrcV); 3243 SDValue Ptr = getValue(PtrV); 3244 3245 SDValue Root = getRoot(); 3246 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3247 NumValues)); 3248 EVT PtrVT = Ptr.getValueType(); 3249 bool isVolatile = I.isVolatile(); 3250 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3251 unsigned Alignment = I.getAlignment(); 3252 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3253 3254 unsigned ChainI = 0; 3255 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3256 // See visitLoad comments. 3257 if (ChainI == MaxParallelChains) { 3258 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3259 MVT::Other, &Chains[0], ChainI); 3260 Root = Chain; 3261 ChainI = 0; 3262 } 3263 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3264 DAG.getConstant(Offsets[i], PtrVT)); 3265 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3266 SDValue(Src.getNode(), Src.getResNo() + i), 3267 Add, MachinePointerInfo(PtrV, Offsets[i]), 3268 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3269 Chains[ChainI] = St; 3270 } 3271 3272 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3273 MVT::Other, &Chains[0], ChainI); 3274 ++SDNodeOrder; 3275 AssignOrderingToNode(StoreNode.getNode()); 3276 DAG.setRoot(StoreNode); 3277} 3278 3279static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3280 bool Before, DebugLoc dl, 3281 SelectionDAG &DAG, 3282 const TargetLowering &TLI) { 3283 // Fence, if necessary 3284 if (Before) { 3285 if (Order == AcquireRelease) 3286 Order = Release; 3287 else if (Order == Acquire || Order == Monotonic) 3288 return Chain; 3289 } else { 3290 if (Order == AcquireRelease) 3291 Order = Acquire; 3292 else if (Order == Release || Order == Monotonic) 3293 return Chain; 3294 } 3295 SDValue Ops[3]; 3296 Ops[0] = Chain; 3297 Ops[1] = DAG.getConstant(SequentiallyConsistent, TLI.getPointerTy()); 3298 Ops[2] = DAG.getConstant(Order, TLI.getPointerTy()); 3299 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3300} 3301 3302void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3303 DebugLoc dl = getCurDebugLoc(); 3304 AtomicOrdering Order = I.getOrdering(); 3305 3306 SDValue InChain = getRoot(); 3307 3308 if (TLI.getInsertFencesForAtomic()) 3309 InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); 3310 3311 SDValue L = 3312 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3313 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3314 InChain, 3315 getValue(I.getPointerOperand()), 3316 getValue(I.getCompareOperand()), 3317 getValue(I.getNewValOperand()), 3318 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3319 I.getOrdering(), I.getSynchScope()); 3320 3321 SDValue OutChain = L.getValue(1); 3322 3323 if (TLI.getInsertFencesForAtomic()) 3324 OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); 3325 3326 setValue(&I, L); 3327 DAG.setRoot(OutChain); 3328} 3329 3330void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3331 DebugLoc dl = getCurDebugLoc(); 3332 ISD::NodeType NT; 3333 switch (I.getOperation()) { 3334 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3335 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3336 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3337 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3338 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3339 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3340 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3341 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3342 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3343 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3344 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3345 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3346 } 3347 AtomicOrdering Order = I.getOrdering(); 3348 3349 SDValue InChain = getRoot(); 3350 3351 if (TLI.getInsertFencesForAtomic()) 3352 InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); 3353 3354 SDValue L = 3355 DAG.getAtomic(NT, dl, 3356 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3357 InChain, 3358 getValue(I.getPointerOperand()), 3359 getValue(I.getValOperand()), 3360 I.getPointerOperand(), 0 /* Alignment */, 3361 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3362 I.getSynchScope()); 3363 3364 SDValue OutChain = L.getValue(1); 3365 3366 if (TLI.getInsertFencesForAtomic()) 3367 OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); 3368 3369 setValue(&I, L); 3370 DAG.setRoot(OutChain); 3371} 3372 3373void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3374 DebugLoc dl = getCurDebugLoc(); 3375 SDValue Ops[3]; 3376 Ops[0] = getRoot(); 3377 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3378 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3379 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3380} 3381 3382/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3383/// node. 3384void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3385 unsigned Intrinsic) { 3386 bool HasChain = !I.doesNotAccessMemory(); 3387 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3388 3389 // Build the operand list. 3390 SmallVector<SDValue, 8> Ops; 3391 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3392 if (OnlyLoad) { 3393 // We don't need to serialize loads against other loads. 3394 Ops.push_back(DAG.getRoot()); 3395 } else { 3396 Ops.push_back(getRoot()); 3397 } 3398 } 3399 3400 // Info is set by getTgtMemInstrinsic 3401 TargetLowering::IntrinsicInfo Info; 3402 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3403 3404 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3405 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3406 Info.opc == ISD::INTRINSIC_W_CHAIN) 3407 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3408 3409 // Add all operands of the call to the operand list. 3410 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3411 SDValue Op = getValue(I.getArgOperand(i)); 3412 assert(TLI.isTypeLegal(Op.getValueType()) && 3413 "Intrinsic uses a non-legal type?"); 3414 Ops.push_back(Op); 3415 } 3416 3417 SmallVector<EVT, 4> ValueVTs; 3418 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3419#ifndef NDEBUG 3420 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3421 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3422 "Intrinsic uses a non-legal type?"); 3423 } 3424#endif // NDEBUG 3425 3426 if (HasChain) 3427 ValueVTs.push_back(MVT::Other); 3428 3429 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3430 3431 // Create the node. 3432 SDValue Result; 3433 if (IsTgtIntrinsic) { 3434 // This is target intrinsic that touches memory 3435 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3436 VTs, &Ops[0], Ops.size(), 3437 Info.memVT, 3438 MachinePointerInfo(Info.ptrVal, Info.offset), 3439 Info.align, Info.vol, 3440 Info.readMem, Info.writeMem); 3441 } else if (!HasChain) { 3442 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3443 VTs, &Ops[0], Ops.size()); 3444 } else if (!I.getType()->isVoidTy()) { 3445 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3446 VTs, &Ops[0], Ops.size()); 3447 } else { 3448 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3449 VTs, &Ops[0], Ops.size()); 3450 } 3451 3452 if (HasChain) { 3453 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3454 if (OnlyLoad) 3455 PendingLoads.push_back(Chain); 3456 else 3457 DAG.setRoot(Chain); 3458 } 3459 3460 if (!I.getType()->isVoidTy()) { 3461 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3462 EVT VT = TLI.getValueType(PTy); 3463 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3464 } 3465 3466 setValue(&I, Result); 3467 } 3468} 3469 3470/// GetSignificand - Get the significand and build it into a floating-point 3471/// number with exponent of 1: 3472/// 3473/// Op = (Op & 0x007fffff) | 0x3f800000; 3474/// 3475/// where Op is the hexidecimal representation of floating point value. 3476static SDValue 3477GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3478 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3479 DAG.getConstant(0x007fffff, MVT::i32)); 3480 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3481 DAG.getConstant(0x3f800000, MVT::i32)); 3482 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3483} 3484 3485/// GetExponent - Get the exponent: 3486/// 3487/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3488/// 3489/// where Op is the hexidecimal representation of floating point value. 3490static SDValue 3491GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3492 DebugLoc dl) { 3493 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3494 DAG.getConstant(0x7f800000, MVT::i32)); 3495 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3496 DAG.getConstant(23, TLI.getPointerTy())); 3497 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3498 DAG.getConstant(127, MVT::i32)); 3499 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3500} 3501 3502/// getF32Constant - Get 32-bit floating point constant. 3503static SDValue 3504getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3505 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3506} 3507 3508/// Inlined utility function to implement binary input atomic intrinsics for 3509/// visitIntrinsicCall: I is a call instruction 3510/// Op is the associated NodeType for I 3511const char * 3512SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3513 ISD::NodeType Op) { 3514 SDValue Root = getRoot(); 3515 SDValue L = 3516 DAG.getAtomic(Op, getCurDebugLoc(), 3517 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3518 Root, 3519 getValue(I.getArgOperand(0)), 3520 getValue(I.getArgOperand(1)), 3521 I.getArgOperand(0), 0 /* Alignment */, 3522 Monotonic, CrossThread); 3523 setValue(&I, L); 3524 DAG.setRoot(L.getValue(1)); 3525 return 0; 3526} 3527 3528// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3529const char * 3530SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3531 SDValue Op1 = getValue(I.getArgOperand(0)); 3532 SDValue Op2 = getValue(I.getArgOperand(1)); 3533 3534 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3535 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3536 return 0; 3537} 3538 3539/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3540/// limited-precision mode. 3541void 3542SelectionDAGBuilder::visitExp(const CallInst &I) { 3543 SDValue result; 3544 DebugLoc dl = getCurDebugLoc(); 3545 3546 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3547 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3548 SDValue Op = getValue(I.getArgOperand(0)); 3549 3550 // Put the exponent in the right bit position for later addition to the 3551 // final result: 3552 // 3553 // #define LOG2OFe 1.4426950f 3554 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3555 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3556 getF32Constant(DAG, 0x3fb8aa3b)); 3557 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3558 3559 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3560 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3561 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3562 3563 // IntegerPartOfX <<= 23; 3564 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3565 DAG.getConstant(23, TLI.getPointerTy())); 3566 3567 if (LimitFloatPrecision <= 6) { 3568 // For floating-point precision of 6: 3569 // 3570 // TwoToFractionalPartOfX = 3571 // 0.997535578f + 3572 // (0.735607626f + 0.252464424f * x) * x; 3573 // 3574 // error 0.0144103317, which is 6 bits 3575 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3576 getF32Constant(DAG, 0x3e814304)); 3577 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3578 getF32Constant(DAG, 0x3f3c50c8)); 3579 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3580 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3581 getF32Constant(DAG, 0x3f7f5e7e)); 3582 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3583 3584 // Add the exponent into the result in integer domain. 3585 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3586 TwoToFracPartOfX, IntegerPartOfX); 3587 3588 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3589 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3590 // For floating-point precision of 12: 3591 // 3592 // TwoToFractionalPartOfX = 3593 // 0.999892986f + 3594 // (0.696457318f + 3595 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3596 // 3597 // 0.000107046256 error, which is 13 to 14 bits 3598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3599 getF32Constant(DAG, 0x3da235e3)); 3600 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3601 getF32Constant(DAG, 0x3e65b8f3)); 3602 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3603 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3604 getF32Constant(DAG, 0x3f324b07)); 3605 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3606 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3607 getF32Constant(DAG, 0x3f7ff8fd)); 3608 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3609 3610 // Add the exponent into the result in integer domain. 3611 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3612 TwoToFracPartOfX, IntegerPartOfX); 3613 3614 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3615 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3616 // For floating-point precision of 18: 3617 // 3618 // TwoToFractionalPartOfX = 3619 // 0.999999982f + 3620 // (0.693148872f + 3621 // (0.240227044f + 3622 // (0.554906021e-1f + 3623 // (0.961591928e-2f + 3624 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3625 // 3626 // error 2.47208000*10^(-7), which is better than 18 bits 3627 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3628 getF32Constant(DAG, 0x3924b03e)); 3629 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3630 getF32Constant(DAG, 0x3ab24b87)); 3631 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3632 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3633 getF32Constant(DAG, 0x3c1d8c17)); 3634 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3635 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3636 getF32Constant(DAG, 0x3d634a1d)); 3637 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3638 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3639 getF32Constant(DAG, 0x3e75fe14)); 3640 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3641 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3642 getF32Constant(DAG, 0x3f317234)); 3643 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3644 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3645 getF32Constant(DAG, 0x3f800000)); 3646 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3647 MVT::i32, t13); 3648 3649 // Add the exponent into the result in integer domain. 3650 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3651 TwoToFracPartOfX, IntegerPartOfX); 3652 3653 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3654 } 3655 } else { 3656 // No special expansion. 3657 result = DAG.getNode(ISD::FEXP, dl, 3658 getValue(I.getArgOperand(0)).getValueType(), 3659 getValue(I.getArgOperand(0))); 3660 } 3661 3662 setValue(&I, result); 3663} 3664 3665/// visitLog - Lower a log intrinsic. Handles the special sequences for 3666/// limited-precision mode. 3667void 3668SelectionDAGBuilder::visitLog(const CallInst &I) { 3669 SDValue result; 3670 DebugLoc dl = getCurDebugLoc(); 3671 3672 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3673 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3674 SDValue Op = getValue(I.getArgOperand(0)); 3675 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3676 3677 // Scale the exponent by log(2) [0.69314718f]. 3678 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3679 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3680 getF32Constant(DAG, 0x3f317218)); 3681 3682 // Get the significand and build it into a floating-point number with 3683 // exponent of 1. 3684 SDValue X = GetSignificand(DAG, Op1, dl); 3685 3686 if (LimitFloatPrecision <= 6) { 3687 // For floating-point precision of 6: 3688 // 3689 // LogofMantissa = 3690 // -1.1609546f + 3691 // (1.4034025f - 0.23903021f * x) * x; 3692 // 3693 // error 0.0034276066, which is better than 8 bits 3694 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3695 getF32Constant(DAG, 0xbe74c456)); 3696 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3697 getF32Constant(DAG, 0x3fb3a2b1)); 3698 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3699 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3700 getF32Constant(DAG, 0x3f949a29)); 3701 3702 result = DAG.getNode(ISD::FADD, dl, 3703 MVT::f32, LogOfExponent, LogOfMantissa); 3704 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3705 // For floating-point precision of 12: 3706 // 3707 // LogOfMantissa = 3708 // -1.7417939f + 3709 // (2.8212026f + 3710 // (-1.4699568f + 3711 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3712 // 3713 // error 0.000061011436, which is 14 bits 3714 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3715 getF32Constant(DAG, 0xbd67b6d6)); 3716 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3717 getF32Constant(DAG, 0x3ee4f4b8)); 3718 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3719 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3720 getF32Constant(DAG, 0x3fbc278b)); 3721 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3722 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3723 getF32Constant(DAG, 0x40348e95)); 3724 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3725 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3726 getF32Constant(DAG, 0x3fdef31a)); 3727 3728 result = DAG.getNode(ISD::FADD, dl, 3729 MVT::f32, LogOfExponent, LogOfMantissa); 3730 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3731 // For floating-point precision of 18: 3732 // 3733 // LogOfMantissa = 3734 // -2.1072184f + 3735 // (4.2372794f + 3736 // (-3.7029485f + 3737 // (2.2781945f + 3738 // (-0.87823314f + 3739 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3740 // 3741 // error 0.0000023660568, which is better than 18 bits 3742 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3743 getF32Constant(DAG, 0xbc91e5ac)); 3744 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3745 getF32Constant(DAG, 0x3e4350aa)); 3746 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3747 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3748 getF32Constant(DAG, 0x3f60d3e3)); 3749 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3750 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3751 getF32Constant(DAG, 0x4011cdf0)); 3752 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3753 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3754 getF32Constant(DAG, 0x406cfd1c)); 3755 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3756 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3757 getF32Constant(DAG, 0x408797cb)); 3758 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3759 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3760 getF32Constant(DAG, 0x4006dcab)); 3761 3762 result = DAG.getNode(ISD::FADD, dl, 3763 MVT::f32, LogOfExponent, LogOfMantissa); 3764 } 3765 } else { 3766 // No special expansion. 3767 result = DAG.getNode(ISD::FLOG, dl, 3768 getValue(I.getArgOperand(0)).getValueType(), 3769 getValue(I.getArgOperand(0))); 3770 } 3771 3772 setValue(&I, result); 3773} 3774 3775/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3776/// limited-precision mode. 3777void 3778SelectionDAGBuilder::visitLog2(const CallInst &I) { 3779 SDValue result; 3780 DebugLoc dl = getCurDebugLoc(); 3781 3782 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3783 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3784 SDValue Op = getValue(I.getArgOperand(0)); 3785 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3786 3787 // Get the exponent. 3788 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3789 3790 // Get the significand and build it into a floating-point number with 3791 // exponent of 1. 3792 SDValue X = GetSignificand(DAG, Op1, dl); 3793 3794 // Different possible minimax approximations of significand in 3795 // floating-point for various degrees of accuracy over [1,2]. 3796 if (LimitFloatPrecision <= 6) { 3797 // For floating-point precision of 6: 3798 // 3799 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3800 // 3801 // error 0.0049451742, which is more than 7 bits 3802 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3803 getF32Constant(DAG, 0xbeb08fe0)); 3804 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3805 getF32Constant(DAG, 0x40019463)); 3806 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3807 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3808 getF32Constant(DAG, 0x3fd6633d)); 3809 3810 result = DAG.getNode(ISD::FADD, dl, 3811 MVT::f32, LogOfExponent, Log2ofMantissa); 3812 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3813 // For floating-point precision of 12: 3814 // 3815 // Log2ofMantissa = 3816 // -2.51285454f + 3817 // (4.07009056f + 3818 // (-2.12067489f + 3819 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3820 // 3821 // error 0.0000876136000, which is better than 13 bits 3822 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3823 getF32Constant(DAG, 0xbda7262e)); 3824 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3825 getF32Constant(DAG, 0x3f25280b)); 3826 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3827 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3828 getF32Constant(DAG, 0x4007b923)); 3829 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3830 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3831 getF32Constant(DAG, 0x40823e2f)); 3832 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3833 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3834 getF32Constant(DAG, 0x4020d29c)); 3835 3836 result = DAG.getNode(ISD::FADD, dl, 3837 MVT::f32, LogOfExponent, Log2ofMantissa); 3838 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3839 // For floating-point precision of 18: 3840 // 3841 // Log2ofMantissa = 3842 // -3.0400495f + 3843 // (6.1129976f + 3844 // (-5.3420409f + 3845 // (3.2865683f + 3846 // (-1.2669343f + 3847 // (0.27515199f - 3848 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3849 // 3850 // error 0.0000018516, which is better than 18 bits 3851 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3852 getF32Constant(DAG, 0xbcd2769e)); 3853 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3854 getF32Constant(DAG, 0x3e8ce0b9)); 3855 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3856 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3857 getF32Constant(DAG, 0x3fa22ae7)); 3858 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3859 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3860 getF32Constant(DAG, 0x40525723)); 3861 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3862 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3863 getF32Constant(DAG, 0x40aaf200)); 3864 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3865 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3866 getF32Constant(DAG, 0x40c39dad)); 3867 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3868 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3869 getF32Constant(DAG, 0x4042902c)); 3870 3871 result = DAG.getNode(ISD::FADD, dl, 3872 MVT::f32, LogOfExponent, Log2ofMantissa); 3873 } 3874 } else { 3875 // No special expansion. 3876 result = DAG.getNode(ISD::FLOG2, dl, 3877 getValue(I.getArgOperand(0)).getValueType(), 3878 getValue(I.getArgOperand(0))); 3879 } 3880 3881 setValue(&I, result); 3882} 3883 3884/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3885/// limited-precision mode. 3886void 3887SelectionDAGBuilder::visitLog10(const CallInst &I) { 3888 SDValue result; 3889 DebugLoc dl = getCurDebugLoc(); 3890 3891 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3892 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3893 SDValue Op = getValue(I.getArgOperand(0)); 3894 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3895 3896 // Scale the exponent by log10(2) [0.30102999f]. 3897 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3898 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3899 getF32Constant(DAG, 0x3e9a209a)); 3900 3901 // Get the significand and build it into a floating-point number with 3902 // exponent of 1. 3903 SDValue X = GetSignificand(DAG, Op1, dl); 3904 3905 if (LimitFloatPrecision <= 6) { 3906 // For floating-point precision of 6: 3907 // 3908 // Log10ofMantissa = 3909 // -0.50419619f + 3910 // (0.60948995f - 0.10380950f * x) * x; 3911 // 3912 // error 0.0014886165, which is 6 bits 3913 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3914 getF32Constant(DAG, 0xbdd49a13)); 3915 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3916 getF32Constant(DAG, 0x3f1c0789)); 3917 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3918 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3919 getF32Constant(DAG, 0x3f011300)); 3920 3921 result = DAG.getNode(ISD::FADD, dl, 3922 MVT::f32, LogOfExponent, Log10ofMantissa); 3923 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3924 // For floating-point precision of 12: 3925 // 3926 // Log10ofMantissa = 3927 // -0.64831180f + 3928 // (0.91751397f + 3929 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3930 // 3931 // error 0.00019228036, which is better than 12 bits 3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3933 getF32Constant(DAG, 0x3d431f31)); 3934 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3935 getF32Constant(DAG, 0x3ea21fb2)); 3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3937 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3938 getF32Constant(DAG, 0x3f6ae232)); 3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3940 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3941 getF32Constant(DAG, 0x3f25f7c3)); 3942 3943 result = DAG.getNode(ISD::FADD, dl, 3944 MVT::f32, LogOfExponent, Log10ofMantissa); 3945 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3946 // For floating-point precision of 18: 3947 // 3948 // Log10ofMantissa = 3949 // -0.84299375f + 3950 // (1.5327582f + 3951 // (-1.0688956f + 3952 // (0.49102474f + 3953 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3954 // 3955 // error 0.0000037995730, which is better than 18 bits 3956 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3957 getF32Constant(DAG, 0x3c5d51ce)); 3958 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3959 getF32Constant(DAG, 0x3e00685a)); 3960 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3961 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3962 getF32Constant(DAG, 0x3efb6798)); 3963 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3964 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3965 getF32Constant(DAG, 0x3f88d192)); 3966 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3967 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3968 getF32Constant(DAG, 0x3fc4316c)); 3969 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3970 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3971 getF32Constant(DAG, 0x3f57ce70)); 3972 3973 result = DAG.getNode(ISD::FADD, dl, 3974 MVT::f32, LogOfExponent, Log10ofMantissa); 3975 } 3976 } else { 3977 // No special expansion. 3978 result = DAG.getNode(ISD::FLOG10, dl, 3979 getValue(I.getArgOperand(0)).getValueType(), 3980 getValue(I.getArgOperand(0))); 3981 } 3982 3983 setValue(&I, result); 3984} 3985 3986/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3987/// limited-precision mode. 3988void 3989SelectionDAGBuilder::visitExp2(const CallInst &I) { 3990 SDValue result; 3991 DebugLoc dl = getCurDebugLoc(); 3992 3993 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3994 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3995 SDValue Op = getValue(I.getArgOperand(0)); 3996 3997 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3998 3999 // FractionalPartOfX = x - (float)IntegerPartOfX; 4000 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4001 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4002 4003 // IntegerPartOfX <<= 23; 4004 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4005 DAG.getConstant(23, TLI.getPointerTy())); 4006 4007 if (LimitFloatPrecision <= 6) { 4008 // For floating-point precision of 6: 4009 // 4010 // TwoToFractionalPartOfX = 4011 // 0.997535578f + 4012 // (0.735607626f + 0.252464424f * x) * x; 4013 // 4014 // error 0.0144103317, which is 6 bits 4015 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4016 getF32Constant(DAG, 0x3e814304)); 4017 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4018 getF32Constant(DAG, 0x3f3c50c8)); 4019 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4020 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4021 getF32Constant(DAG, 0x3f7f5e7e)); 4022 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4023 SDValue TwoToFractionalPartOfX = 4024 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4025 4026 result = DAG.getNode(ISD::BITCAST, dl, 4027 MVT::f32, TwoToFractionalPartOfX); 4028 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4029 // For floating-point precision of 12: 4030 // 4031 // TwoToFractionalPartOfX = 4032 // 0.999892986f + 4033 // (0.696457318f + 4034 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4035 // 4036 // error 0.000107046256, which is 13 to 14 bits 4037 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4038 getF32Constant(DAG, 0x3da235e3)); 4039 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4040 getF32Constant(DAG, 0x3e65b8f3)); 4041 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4042 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4043 getF32Constant(DAG, 0x3f324b07)); 4044 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4045 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4046 getF32Constant(DAG, 0x3f7ff8fd)); 4047 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4048 SDValue TwoToFractionalPartOfX = 4049 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4050 4051 result = DAG.getNode(ISD::BITCAST, dl, 4052 MVT::f32, TwoToFractionalPartOfX); 4053 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4054 // For floating-point precision of 18: 4055 // 4056 // TwoToFractionalPartOfX = 4057 // 0.999999982f + 4058 // (0.693148872f + 4059 // (0.240227044f + 4060 // (0.554906021e-1f + 4061 // (0.961591928e-2f + 4062 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4063 // error 2.47208000*10^(-7), which is better than 18 bits 4064 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4065 getF32Constant(DAG, 0x3924b03e)); 4066 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4067 getF32Constant(DAG, 0x3ab24b87)); 4068 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4069 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4070 getF32Constant(DAG, 0x3c1d8c17)); 4071 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4072 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4073 getF32Constant(DAG, 0x3d634a1d)); 4074 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4075 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4076 getF32Constant(DAG, 0x3e75fe14)); 4077 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4078 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4079 getF32Constant(DAG, 0x3f317234)); 4080 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4081 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4082 getF32Constant(DAG, 0x3f800000)); 4083 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4084 SDValue TwoToFractionalPartOfX = 4085 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4086 4087 result = DAG.getNode(ISD::BITCAST, dl, 4088 MVT::f32, TwoToFractionalPartOfX); 4089 } 4090 } else { 4091 // No special expansion. 4092 result = DAG.getNode(ISD::FEXP2, dl, 4093 getValue(I.getArgOperand(0)).getValueType(), 4094 getValue(I.getArgOperand(0))); 4095 } 4096 4097 setValue(&I, result); 4098} 4099 4100/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4101/// limited-precision mode with x == 10.0f. 4102void 4103SelectionDAGBuilder::visitPow(const CallInst &I) { 4104 SDValue result; 4105 const Value *Val = I.getArgOperand(0); 4106 DebugLoc dl = getCurDebugLoc(); 4107 bool IsExp10 = false; 4108 4109 if (getValue(Val).getValueType() == MVT::f32 && 4110 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4111 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4112 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4113 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4114 APFloat Ten(10.0f); 4115 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4116 } 4117 } 4118 } 4119 4120 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4121 SDValue Op = getValue(I.getArgOperand(1)); 4122 4123 // Put the exponent in the right bit position for later addition to the 4124 // final result: 4125 // 4126 // #define LOG2OF10 3.3219281f 4127 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4128 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4129 getF32Constant(DAG, 0x40549a78)); 4130 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4131 4132 // FractionalPartOfX = x - (float)IntegerPartOfX; 4133 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4134 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4135 4136 // IntegerPartOfX <<= 23; 4137 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4138 DAG.getConstant(23, TLI.getPointerTy())); 4139 4140 if (LimitFloatPrecision <= 6) { 4141 // For floating-point precision of 6: 4142 // 4143 // twoToFractionalPartOfX = 4144 // 0.997535578f + 4145 // (0.735607626f + 0.252464424f * x) * x; 4146 // 4147 // error 0.0144103317, which is 6 bits 4148 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4149 getF32Constant(DAG, 0x3e814304)); 4150 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4151 getF32Constant(DAG, 0x3f3c50c8)); 4152 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4153 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4154 getF32Constant(DAG, 0x3f7f5e7e)); 4155 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4156 SDValue TwoToFractionalPartOfX = 4157 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4158 4159 result = DAG.getNode(ISD::BITCAST, dl, 4160 MVT::f32, TwoToFractionalPartOfX); 4161 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4162 // For floating-point precision of 12: 4163 // 4164 // TwoToFractionalPartOfX = 4165 // 0.999892986f + 4166 // (0.696457318f + 4167 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4168 // 4169 // error 0.000107046256, which is 13 to 14 bits 4170 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4171 getF32Constant(DAG, 0x3da235e3)); 4172 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4173 getF32Constant(DAG, 0x3e65b8f3)); 4174 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4175 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4176 getF32Constant(DAG, 0x3f324b07)); 4177 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4178 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4179 getF32Constant(DAG, 0x3f7ff8fd)); 4180 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4181 SDValue TwoToFractionalPartOfX = 4182 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4183 4184 result = DAG.getNode(ISD::BITCAST, dl, 4185 MVT::f32, TwoToFractionalPartOfX); 4186 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4187 // For floating-point precision of 18: 4188 // 4189 // TwoToFractionalPartOfX = 4190 // 0.999999982f + 4191 // (0.693148872f + 4192 // (0.240227044f + 4193 // (0.554906021e-1f + 4194 // (0.961591928e-2f + 4195 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4196 // error 2.47208000*10^(-7), which is better than 18 bits 4197 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4198 getF32Constant(DAG, 0x3924b03e)); 4199 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4200 getF32Constant(DAG, 0x3ab24b87)); 4201 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4202 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4203 getF32Constant(DAG, 0x3c1d8c17)); 4204 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4205 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4206 getF32Constant(DAG, 0x3d634a1d)); 4207 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4208 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4209 getF32Constant(DAG, 0x3e75fe14)); 4210 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4211 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4212 getF32Constant(DAG, 0x3f317234)); 4213 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4214 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4215 getF32Constant(DAG, 0x3f800000)); 4216 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4217 SDValue TwoToFractionalPartOfX = 4218 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4219 4220 result = DAG.getNode(ISD::BITCAST, dl, 4221 MVT::f32, TwoToFractionalPartOfX); 4222 } 4223 } else { 4224 // No special expansion. 4225 result = DAG.getNode(ISD::FPOW, dl, 4226 getValue(I.getArgOperand(0)).getValueType(), 4227 getValue(I.getArgOperand(0)), 4228 getValue(I.getArgOperand(1))); 4229 } 4230 4231 setValue(&I, result); 4232} 4233 4234 4235/// ExpandPowI - Expand a llvm.powi intrinsic. 4236static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4237 SelectionDAG &DAG) { 4238 // If RHS is a constant, we can expand this out to a multiplication tree, 4239 // otherwise we end up lowering to a call to __powidf2 (for example). When 4240 // optimizing for size, we only want to do this if the expansion would produce 4241 // a small number of multiplies, otherwise we do the full expansion. 4242 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4243 // Get the exponent as a positive value. 4244 unsigned Val = RHSC->getSExtValue(); 4245 if ((int)Val < 0) Val = -Val; 4246 4247 // powi(x, 0) -> 1.0 4248 if (Val == 0) 4249 return DAG.getConstantFP(1.0, LHS.getValueType()); 4250 4251 const Function *F = DAG.getMachineFunction().getFunction(); 4252 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4253 // If optimizing for size, don't insert too many multiplies. This 4254 // inserts up to 5 multiplies. 4255 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4256 // We use the simple binary decomposition method to generate the multiply 4257 // sequence. There are more optimal ways to do this (for example, 4258 // powi(x,15) generates one more multiply than it should), but this has 4259 // the benefit of being both really simple and much better than a libcall. 4260 SDValue Res; // Logically starts equal to 1.0 4261 SDValue CurSquare = LHS; 4262 while (Val) { 4263 if (Val & 1) { 4264 if (Res.getNode()) 4265 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4266 else 4267 Res = CurSquare; // 1.0*CurSquare. 4268 } 4269 4270 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4271 CurSquare, CurSquare); 4272 Val >>= 1; 4273 } 4274 4275 // If the original was negative, invert the result, producing 1/(x*x*x). 4276 if (RHSC->getSExtValue() < 0) 4277 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4278 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4279 return Res; 4280 } 4281 } 4282 4283 // Otherwise, expand to a libcall. 4284 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4285} 4286 4287// getTruncatedArgReg - Find underlying register used for an truncated 4288// argument. 4289static unsigned getTruncatedArgReg(const SDValue &N) { 4290 if (N.getOpcode() != ISD::TRUNCATE) 4291 return 0; 4292 4293 const SDValue &Ext = N.getOperand(0); 4294 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4295 const SDValue &CFR = Ext.getOperand(0); 4296 if (CFR.getOpcode() == ISD::CopyFromReg) 4297 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4298 else 4299 if (CFR.getOpcode() == ISD::TRUNCATE) 4300 return getTruncatedArgReg(CFR); 4301 } 4302 return 0; 4303} 4304 4305/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4306/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4307/// At the end of instruction selection, they will be inserted to the entry BB. 4308bool 4309SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4310 int64_t Offset, 4311 const SDValue &N) { 4312 const Argument *Arg = dyn_cast<Argument>(V); 4313 if (!Arg) 4314 return false; 4315 4316 MachineFunction &MF = DAG.getMachineFunction(); 4317 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4318 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4319 4320 // Ignore inlined function arguments here. 4321 DIVariable DV(Variable); 4322 if (DV.isInlinedFnArgument(MF.getFunction())) 4323 return false; 4324 4325 unsigned Reg = 0; 4326 if (Arg->hasByValAttr()) { 4327 // Byval arguments' frame index is recorded during argument lowering. 4328 // Use this info directly. 4329 Reg = TRI->getFrameRegister(MF); 4330 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4331 // If byval argument ofset is not recorded then ignore this. 4332 if (!Offset) 4333 Reg = 0; 4334 } 4335 4336 if (N.getNode()) { 4337 if (N.getOpcode() == ISD::CopyFromReg) 4338 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4339 else 4340 Reg = getTruncatedArgReg(N); 4341 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4342 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4343 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4344 if (PR) 4345 Reg = PR; 4346 } 4347 } 4348 4349 if (!Reg) { 4350 // Check if ValueMap has reg number. 4351 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4352 if (VMI != FuncInfo.ValueMap.end()) 4353 Reg = VMI->second; 4354 } 4355 4356 if (!Reg && N.getNode()) { 4357 // Check if frame index is available. 4358 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4359 if (FrameIndexSDNode *FINode = 4360 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4361 Reg = TRI->getFrameRegister(MF); 4362 Offset = FINode->getIndex(); 4363 } 4364 } 4365 4366 if (!Reg) 4367 return false; 4368 4369 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4370 TII->get(TargetOpcode::DBG_VALUE)) 4371 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4372 FuncInfo.ArgDbgValues.push_back(&*MIB); 4373 return true; 4374} 4375 4376// VisualStudio defines setjmp as _setjmp 4377#if defined(_MSC_VER) && defined(setjmp) && \ 4378 !defined(setjmp_undefined_for_msvc) 4379# pragma push_macro("setjmp") 4380# undef setjmp 4381# define setjmp_undefined_for_msvc 4382#endif 4383 4384/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4385/// we want to emit this as a call to a named external function, return the name 4386/// otherwise lower it and return null. 4387const char * 4388SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4389 DebugLoc dl = getCurDebugLoc(); 4390 SDValue Res; 4391 4392 switch (Intrinsic) { 4393 default: 4394 // By default, turn this into a target intrinsic node. 4395 visitTargetIntrinsic(I, Intrinsic); 4396 return 0; 4397 case Intrinsic::vastart: visitVAStart(I); return 0; 4398 case Intrinsic::vaend: visitVAEnd(I); return 0; 4399 case Intrinsic::vacopy: visitVACopy(I); return 0; 4400 case Intrinsic::returnaddress: 4401 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4402 getValue(I.getArgOperand(0)))); 4403 return 0; 4404 case Intrinsic::frameaddress: 4405 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4406 getValue(I.getArgOperand(0)))); 4407 return 0; 4408 case Intrinsic::setjmp: 4409 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4410 case Intrinsic::longjmp: 4411 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4412 case Intrinsic::memcpy: { 4413 // Assert for address < 256 since we support only user defined address 4414 // spaces. 4415 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4416 < 256 && 4417 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4418 < 256 && 4419 "Unknown address space"); 4420 SDValue Op1 = getValue(I.getArgOperand(0)); 4421 SDValue Op2 = getValue(I.getArgOperand(1)); 4422 SDValue Op3 = getValue(I.getArgOperand(2)); 4423 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4424 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4425 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4426 MachinePointerInfo(I.getArgOperand(0)), 4427 MachinePointerInfo(I.getArgOperand(1)))); 4428 return 0; 4429 } 4430 case Intrinsic::memset: { 4431 // Assert for address < 256 since we support only user defined address 4432 // spaces. 4433 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4434 < 256 && 4435 "Unknown address space"); 4436 SDValue Op1 = getValue(I.getArgOperand(0)); 4437 SDValue Op2 = getValue(I.getArgOperand(1)); 4438 SDValue Op3 = getValue(I.getArgOperand(2)); 4439 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4440 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4441 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4442 MachinePointerInfo(I.getArgOperand(0)))); 4443 return 0; 4444 } 4445 case Intrinsic::memmove: { 4446 // Assert for address < 256 since we support only user defined address 4447 // spaces. 4448 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4449 < 256 && 4450 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4451 < 256 && 4452 "Unknown address space"); 4453 SDValue Op1 = getValue(I.getArgOperand(0)); 4454 SDValue Op2 = getValue(I.getArgOperand(1)); 4455 SDValue Op3 = getValue(I.getArgOperand(2)); 4456 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4457 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4458 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4459 MachinePointerInfo(I.getArgOperand(0)), 4460 MachinePointerInfo(I.getArgOperand(1)))); 4461 return 0; 4462 } 4463 case Intrinsic::dbg_declare: { 4464 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4465 MDNode *Variable = DI.getVariable(); 4466 const Value *Address = DI.getAddress(); 4467 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4468 return 0; 4469 4470 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4471 // but do not always have a corresponding SDNode built. The SDNodeOrder 4472 // absolute, but not relative, values are different depending on whether 4473 // debug info exists. 4474 ++SDNodeOrder; 4475 4476 // Check if address has undef value. 4477 if (isa<UndefValue>(Address) || 4478 (Address->use_empty() && !isa<Argument>(Address))) { 4479 DEBUG(dbgs() << "Dropping debug info for " << DI); 4480 return 0; 4481 } 4482 4483 SDValue &N = NodeMap[Address]; 4484 if (!N.getNode() && isa<Argument>(Address)) 4485 // Check unused arguments map. 4486 N = UnusedArgNodeMap[Address]; 4487 SDDbgValue *SDV; 4488 if (N.getNode()) { 4489 // Parameters are handled specially. 4490 bool isParameter = 4491 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4492 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4493 Address = BCI->getOperand(0); 4494 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4495 4496 if (isParameter && !AI) { 4497 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4498 if (FINode) 4499 // Byval parameter. We have a frame index at this point. 4500 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4501 0, dl, SDNodeOrder); 4502 else { 4503 // Address is an argument, so try to emit its dbg value using 4504 // virtual register info from the FuncInfo.ValueMap. 4505 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4506 return 0; 4507 } 4508 } else if (AI) 4509 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4510 0, dl, SDNodeOrder); 4511 else { 4512 // Can't do anything with other non-AI cases yet. 4513 DEBUG(dbgs() << "Dropping debug info for " << DI); 4514 return 0; 4515 } 4516 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4517 } else { 4518 // If Address is an argument then try to emit its dbg value using 4519 // virtual register info from the FuncInfo.ValueMap. 4520 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4521 // If variable is pinned by a alloca in dominating bb then 4522 // use StaticAllocaMap. 4523 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4524 if (AI->getParent() != DI.getParent()) { 4525 DenseMap<const AllocaInst*, int>::iterator SI = 4526 FuncInfo.StaticAllocaMap.find(AI); 4527 if (SI != FuncInfo.StaticAllocaMap.end()) { 4528 SDV = DAG.getDbgValue(Variable, SI->second, 4529 0, dl, SDNodeOrder); 4530 DAG.AddDbgValue(SDV, 0, false); 4531 return 0; 4532 } 4533 } 4534 } 4535 DEBUG(dbgs() << "Dropping debug info for " << DI); 4536 } 4537 } 4538 return 0; 4539 } 4540 case Intrinsic::dbg_value: { 4541 const DbgValueInst &DI = cast<DbgValueInst>(I); 4542 if (!DIVariable(DI.getVariable()).Verify()) 4543 return 0; 4544 4545 MDNode *Variable = DI.getVariable(); 4546 uint64_t Offset = DI.getOffset(); 4547 const Value *V = DI.getValue(); 4548 if (!V) 4549 return 0; 4550 4551 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4552 // but do not always have a corresponding SDNode built. The SDNodeOrder 4553 // absolute, but not relative, values are different depending on whether 4554 // debug info exists. 4555 ++SDNodeOrder; 4556 SDDbgValue *SDV; 4557 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4558 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4559 DAG.AddDbgValue(SDV, 0, false); 4560 } else { 4561 // Do not use getValue() in here; we don't want to generate code at 4562 // this point if it hasn't been done yet. 4563 SDValue N = NodeMap[V]; 4564 if (!N.getNode() && isa<Argument>(V)) 4565 // Check unused arguments map. 4566 N = UnusedArgNodeMap[V]; 4567 if (N.getNode()) { 4568 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4569 SDV = DAG.getDbgValue(Variable, N.getNode(), 4570 N.getResNo(), Offset, dl, SDNodeOrder); 4571 DAG.AddDbgValue(SDV, N.getNode(), false); 4572 } 4573 } else if (!V->use_empty() ) { 4574 // Do not call getValue(V) yet, as we don't want to generate code. 4575 // Remember it for later. 4576 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4577 DanglingDebugInfoMap[V] = DDI; 4578 } else { 4579 // We may expand this to cover more cases. One case where we have no 4580 // data available is an unreferenced parameter. 4581 DEBUG(dbgs() << "Dropping debug info for " << DI); 4582 } 4583 } 4584 4585 // Build a debug info table entry. 4586 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4587 V = BCI->getOperand(0); 4588 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4589 // Don't handle byval struct arguments or VLAs, for example. 4590 if (!AI) 4591 return 0; 4592 DenseMap<const AllocaInst*, int>::iterator SI = 4593 FuncInfo.StaticAllocaMap.find(AI); 4594 if (SI == FuncInfo.StaticAllocaMap.end()) 4595 return 0; // VLAs. 4596 int FI = SI->second; 4597 4598 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4599 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4600 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4601 return 0; 4602 } 4603 case Intrinsic::eh_exception: { 4604 // Insert the EXCEPTIONADDR instruction. 4605 assert(FuncInfo.MBB->isLandingPad() && 4606 "Call to eh.exception not in landing pad!"); 4607 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4608 SDValue Ops[1]; 4609 Ops[0] = DAG.getRoot(); 4610 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4611 setValue(&I, Op); 4612 DAG.setRoot(Op.getValue(1)); 4613 return 0; 4614 } 4615 4616 case Intrinsic::eh_selector: { 4617 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4618 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4619 if (CallMBB->isLandingPad()) 4620 AddCatchInfo(I, &MMI, CallMBB); 4621 else { 4622#ifndef NDEBUG 4623 FuncInfo.CatchInfoLost.insert(&I); 4624#endif 4625 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4626 unsigned Reg = TLI.getExceptionSelectorRegister(); 4627 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4628 } 4629 4630 // Insert the EHSELECTION instruction. 4631 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4632 SDValue Ops[2]; 4633 Ops[0] = getValue(I.getArgOperand(0)); 4634 Ops[1] = getRoot(); 4635 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4636 DAG.setRoot(Op.getValue(1)); 4637 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4638 return 0; 4639 } 4640 4641 case Intrinsic::eh_typeid_for: { 4642 // Find the type id for the given typeinfo. 4643 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4644 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4645 Res = DAG.getConstant(TypeID, MVT::i32); 4646 setValue(&I, Res); 4647 return 0; 4648 } 4649 4650 case Intrinsic::eh_return_i32: 4651 case Intrinsic::eh_return_i64: 4652 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4653 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4654 MVT::Other, 4655 getControlRoot(), 4656 getValue(I.getArgOperand(0)), 4657 getValue(I.getArgOperand(1)))); 4658 return 0; 4659 case Intrinsic::eh_unwind_init: 4660 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4661 return 0; 4662 case Intrinsic::eh_dwarf_cfa: { 4663 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4664 TLI.getPointerTy()); 4665 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4666 TLI.getPointerTy(), 4667 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4668 TLI.getPointerTy()), 4669 CfaArg); 4670 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4671 TLI.getPointerTy(), 4672 DAG.getConstant(0, TLI.getPointerTy())); 4673 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4674 FA, Offset)); 4675 return 0; 4676 } 4677 case Intrinsic::eh_sjlj_callsite: { 4678 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4679 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4680 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4681 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4682 4683 MMI.setCurrentCallSite(CI->getZExtValue()); 4684 return 0; 4685 } 4686 case Intrinsic::eh_sjlj_setjmp: { 4687 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4688 getValue(I.getArgOperand(0)))); 4689 return 0; 4690 } 4691 case Intrinsic::eh_sjlj_longjmp: { 4692 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4693 getRoot(), getValue(I.getArgOperand(0)))); 4694 return 0; 4695 } 4696 case Intrinsic::eh_sjlj_dispatch_setup: { 4697 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4698 getRoot(), getValue(I.getArgOperand(0)))); 4699 return 0; 4700 } 4701 4702 case Intrinsic::x86_mmx_pslli_w: 4703 case Intrinsic::x86_mmx_pslli_d: 4704 case Intrinsic::x86_mmx_pslli_q: 4705 case Intrinsic::x86_mmx_psrli_w: 4706 case Intrinsic::x86_mmx_psrli_d: 4707 case Intrinsic::x86_mmx_psrli_q: 4708 case Intrinsic::x86_mmx_psrai_w: 4709 case Intrinsic::x86_mmx_psrai_d: { 4710 SDValue ShAmt = getValue(I.getArgOperand(1)); 4711 if (isa<ConstantSDNode>(ShAmt)) { 4712 visitTargetIntrinsic(I, Intrinsic); 4713 return 0; 4714 } 4715 unsigned NewIntrinsic = 0; 4716 EVT ShAmtVT = MVT::v2i32; 4717 switch (Intrinsic) { 4718 case Intrinsic::x86_mmx_pslli_w: 4719 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4720 break; 4721 case Intrinsic::x86_mmx_pslli_d: 4722 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4723 break; 4724 case Intrinsic::x86_mmx_pslli_q: 4725 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4726 break; 4727 case Intrinsic::x86_mmx_psrli_w: 4728 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4729 break; 4730 case Intrinsic::x86_mmx_psrli_d: 4731 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4732 break; 4733 case Intrinsic::x86_mmx_psrli_q: 4734 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4735 break; 4736 case Intrinsic::x86_mmx_psrai_w: 4737 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4738 break; 4739 case Intrinsic::x86_mmx_psrai_d: 4740 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4741 break; 4742 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4743 } 4744 4745 // The vector shift intrinsics with scalars uses 32b shift amounts but 4746 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4747 // to be zero. 4748 // We must do this early because v2i32 is not a legal type. 4749 DebugLoc dl = getCurDebugLoc(); 4750 SDValue ShOps[2]; 4751 ShOps[0] = ShAmt; 4752 ShOps[1] = DAG.getConstant(0, MVT::i32); 4753 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4754 EVT DestVT = TLI.getValueType(I.getType()); 4755 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4756 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4757 DAG.getConstant(NewIntrinsic, MVT::i32), 4758 getValue(I.getArgOperand(0)), ShAmt); 4759 setValue(&I, Res); 4760 return 0; 4761 } 4762 case Intrinsic::convertff: 4763 case Intrinsic::convertfsi: 4764 case Intrinsic::convertfui: 4765 case Intrinsic::convertsif: 4766 case Intrinsic::convertuif: 4767 case Intrinsic::convertss: 4768 case Intrinsic::convertsu: 4769 case Intrinsic::convertus: 4770 case Intrinsic::convertuu: { 4771 ISD::CvtCode Code = ISD::CVT_INVALID; 4772 switch (Intrinsic) { 4773 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4774 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4775 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4776 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4777 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4778 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4779 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4780 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4781 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4782 } 4783 EVT DestVT = TLI.getValueType(I.getType()); 4784 const Value *Op1 = I.getArgOperand(0); 4785 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4786 DAG.getValueType(DestVT), 4787 DAG.getValueType(getValue(Op1).getValueType()), 4788 getValue(I.getArgOperand(1)), 4789 getValue(I.getArgOperand(2)), 4790 Code); 4791 setValue(&I, Res); 4792 return 0; 4793 } 4794 case Intrinsic::sqrt: 4795 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4796 getValue(I.getArgOperand(0)).getValueType(), 4797 getValue(I.getArgOperand(0)))); 4798 return 0; 4799 case Intrinsic::powi: 4800 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4801 getValue(I.getArgOperand(1)), DAG)); 4802 return 0; 4803 case Intrinsic::sin: 4804 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4805 getValue(I.getArgOperand(0)).getValueType(), 4806 getValue(I.getArgOperand(0)))); 4807 return 0; 4808 case Intrinsic::cos: 4809 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4810 getValue(I.getArgOperand(0)).getValueType(), 4811 getValue(I.getArgOperand(0)))); 4812 return 0; 4813 case Intrinsic::log: 4814 visitLog(I); 4815 return 0; 4816 case Intrinsic::log2: 4817 visitLog2(I); 4818 return 0; 4819 case Intrinsic::log10: 4820 visitLog10(I); 4821 return 0; 4822 case Intrinsic::exp: 4823 visitExp(I); 4824 return 0; 4825 case Intrinsic::exp2: 4826 visitExp2(I); 4827 return 0; 4828 case Intrinsic::pow: 4829 visitPow(I); 4830 return 0; 4831 case Intrinsic::fma: 4832 setValue(&I, DAG.getNode(ISD::FMA, dl, 4833 getValue(I.getArgOperand(0)).getValueType(), 4834 getValue(I.getArgOperand(0)), 4835 getValue(I.getArgOperand(1)), 4836 getValue(I.getArgOperand(2)))); 4837 return 0; 4838 case Intrinsic::convert_to_fp16: 4839 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4840 MVT::i16, getValue(I.getArgOperand(0)))); 4841 return 0; 4842 case Intrinsic::convert_from_fp16: 4843 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4844 MVT::f32, getValue(I.getArgOperand(0)))); 4845 return 0; 4846 case Intrinsic::pcmarker: { 4847 SDValue Tmp = getValue(I.getArgOperand(0)); 4848 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4849 return 0; 4850 } 4851 case Intrinsic::readcyclecounter: { 4852 SDValue Op = getRoot(); 4853 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4854 DAG.getVTList(MVT::i64, MVT::Other), 4855 &Op, 1); 4856 setValue(&I, Res); 4857 DAG.setRoot(Res.getValue(1)); 4858 return 0; 4859 } 4860 case Intrinsic::bswap: 4861 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4862 getValue(I.getArgOperand(0)).getValueType(), 4863 getValue(I.getArgOperand(0)))); 4864 return 0; 4865 case Intrinsic::cttz: { 4866 SDValue Arg = getValue(I.getArgOperand(0)); 4867 EVT Ty = Arg.getValueType(); 4868 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4869 return 0; 4870 } 4871 case Intrinsic::ctlz: { 4872 SDValue Arg = getValue(I.getArgOperand(0)); 4873 EVT Ty = Arg.getValueType(); 4874 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4875 return 0; 4876 } 4877 case Intrinsic::ctpop: { 4878 SDValue Arg = getValue(I.getArgOperand(0)); 4879 EVT Ty = Arg.getValueType(); 4880 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4881 return 0; 4882 } 4883 case Intrinsic::stacksave: { 4884 SDValue Op = getRoot(); 4885 Res = DAG.getNode(ISD::STACKSAVE, dl, 4886 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4887 setValue(&I, Res); 4888 DAG.setRoot(Res.getValue(1)); 4889 return 0; 4890 } 4891 case Intrinsic::stackrestore: { 4892 Res = getValue(I.getArgOperand(0)); 4893 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4894 return 0; 4895 } 4896 case Intrinsic::stackprotector: { 4897 // Emit code into the DAG to store the stack guard onto the stack. 4898 MachineFunction &MF = DAG.getMachineFunction(); 4899 MachineFrameInfo *MFI = MF.getFrameInfo(); 4900 EVT PtrTy = TLI.getPointerTy(); 4901 4902 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4903 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4904 4905 int FI = FuncInfo.StaticAllocaMap[Slot]; 4906 MFI->setStackProtectorIndex(FI); 4907 4908 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4909 4910 // Store the stack protector onto the stack. 4911 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4912 MachinePointerInfo::getFixedStack(FI), 4913 true, false, 0); 4914 setValue(&I, Res); 4915 DAG.setRoot(Res); 4916 return 0; 4917 } 4918 case Intrinsic::objectsize: { 4919 // If we don't know by now, we're never going to know. 4920 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4921 4922 assert(CI && "Non-constant type in __builtin_object_size?"); 4923 4924 SDValue Arg = getValue(I.getCalledValue()); 4925 EVT Ty = Arg.getValueType(); 4926 4927 if (CI->isZero()) 4928 Res = DAG.getConstant(-1ULL, Ty); 4929 else 4930 Res = DAG.getConstant(0, Ty); 4931 4932 setValue(&I, Res); 4933 return 0; 4934 } 4935 case Intrinsic::var_annotation: 4936 // Discard annotate attributes 4937 return 0; 4938 4939 case Intrinsic::init_trampoline: { 4940 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4941 4942 SDValue Ops[6]; 4943 Ops[0] = getRoot(); 4944 Ops[1] = getValue(I.getArgOperand(0)); 4945 Ops[2] = getValue(I.getArgOperand(1)); 4946 Ops[3] = getValue(I.getArgOperand(2)); 4947 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4948 Ops[5] = DAG.getSrcValue(F); 4949 4950 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4951 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4952 Ops, 6); 4953 4954 setValue(&I, Res); 4955 DAG.setRoot(Res.getValue(1)); 4956 return 0; 4957 } 4958 case Intrinsic::gcroot: 4959 if (GFI) { 4960 const Value *Alloca = I.getArgOperand(0); 4961 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4962 4963 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4964 GFI->addStackRoot(FI->getIndex(), TypeMap); 4965 } 4966 return 0; 4967 case Intrinsic::gcread: 4968 case Intrinsic::gcwrite: 4969 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4970 return 0; 4971 case Intrinsic::flt_rounds: 4972 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4973 return 0; 4974 4975 case Intrinsic::expect: { 4976 // Just replace __builtin_expect(exp, c) with EXP. 4977 setValue(&I, getValue(I.getArgOperand(0))); 4978 return 0; 4979 } 4980 4981 case Intrinsic::trap: { 4982 StringRef TrapFuncName = getTrapFunctionName(); 4983 if (TrapFuncName.empty()) { 4984 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4985 return 0; 4986 } 4987 TargetLowering::ArgListTy Args; 4988 std::pair<SDValue, SDValue> Result = 4989 TLI.LowerCallTo(getRoot(), I.getType(), 4990 false, false, false, false, 0, CallingConv::C, 4991 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4992 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4993 Args, DAG, getCurDebugLoc()); 4994 DAG.setRoot(Result.second); 4995 return 0; 4996 } 4997 case Intrinsic::uadd_with_overflow: 4998 return implVisitAluOverflow(I, ISD::UADDO); 4999 case Intrinsic::sadd_with_overflow: 5000 return implVisitAluOverflow(I, ISD::SADDO); 5001 case Intrinsic::usub_with_overflow: 5002 return implVisitAluOverflow(I, ISD::USUBO); 5003 case Intrinsic::ssub_with_overflow: 5004 return implVisitAluOverflow(I, ISD::SSUBO); 5005 case Intrinsic::umul_with_overflow: 5006 return implVisitAluOverflow(I, ISD::UMULO); 5007 case Intrinsic::smul_with_overflow: 5008 return implVisitAluOverflow(I, ISD::SMULO); 5009 5010 case Intrinsic::prefetch: { 5011 SDValue Ops[5]; 5012 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5013 Ops[0] = getRoot(); 5014 Ops[1] = getValue(I.getArgOperand(0)); 5015 Ops[2] = getValue(I.getArgOperand(1)); 5016 Ops[3] = getValue(I.getArgOperand(2)); 5017 Ops[4] = getValue(I.getArgOperand(3)); 5018 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5019 DAG.getVTList(MVT::Other), 5020 &Ops[0], 5, 5021 EVT::getIntegerVT(*Context, 8), 5022 MachinePointerInfo(I.getArgOperand(0)), 5023 0, /* align */ 5024 false, /* volatile */ 5025 rw==0, /* read */ 5026 rw==1)); /* write */ 5027 return 0; 5028 } 5029 case Intrinsic::memory_barrier: { 5030 SDValue Ops[6]; 5031 Ops[0] = getRoot(); 5032 for (int x = 1; x < 6; ++x) 5033 Ops[x] = getValue(I.getArgOperand(x - 1)); 5034 5035 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 5036 return 0; 5037 } 5038 case Intrinsic::atomic_cmp_swap: { 5039 SDValue Root = getRoot(); 5040 SDValue L = 5041 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 5042 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 5043 Root, 5044 getValue(I.getArgOperand(0)), 5045 getValue(I.getArgOperand(1)), 5046 getValue(I.getArgOperand(2)), 5047 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 5048 Monotonic, CrossThread); 5049 setValue(&I, L); 5050 DAG.setRoot(L.getValue(1)); 5051 return 0; 5052 } 5053 case Intrinsic::atomic_load_add: 5054 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 5055 case Intrinsic::atomic_load_sub: 5056 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 5057 case Intrinsic::atomic_load_or: 5058 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 5059 case Intrinsic::atomic_load_xor: 5060 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 5061 case Intrinsic::atomic_load_and: 5062 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 5063 case Intrinsic::atomic_load_nand: 5064 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 5065 case Intrinsic::atomic_load_max: 5066 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 5067 case Intrinsic::atomic_load_min: 5068 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 5069 case Intrinsic::atomic_load_umin: 5070 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5071 case Intrinsic::atomic_load_umax: 5072 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5073 case Intrinsic::atomic_swap: 5074 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5075 5076 case Intrinsic::invariant_start: 5077 case Intrinsic::lifetime_start: 5078 // Discard region information. 5079 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5080 return 0; 5081 case Intrinsic::invariant_end: 5082 case Intrinsic::lifetime_end: 5083 // Discard region information. 5084 return 0; 5085 } 5086} 5087 5088void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5089 bool isTailCall, 5090 MachineBasicBlock *LandingPad) { 5091 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5092 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5093 Type *RetTy = FTy->getReturnType(); 5094 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5095 MCSymbol *BeginLabel = 0; 5096 5097 TargetLowering::ArgListTy Args; 5098 TargetLowering::ArgListEntry Entry; 5099 Args.reserve(CS.arg_size()); 5100 5101 // Check whether the function can return without sret-demotion. 5102 SmallVector<ISD::OutputArg, 4> Outs; 5103 SmallVector<uint64_t, 4> Offsets; 5104 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5105 Outs, TLI, &Offsets); 5106 5107 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5108 DAG.getMachineFunction(), 5109 FTy->isVarArg(), Outs, 5110 FTy->getContext()); 5111 5112 SDValue DemoteStackSlot; 5113 int DemoteStackIdx = -100; 5114 5115 if (!CanLowerReturn) { 5116 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5117 FTy->getReturnType()); 5118 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5119 FTy->getReturnType()); 5120 MachineFunction &MF = DAG.getMachineFunction(); 5121 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5122 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5123 5124 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5125 Entry.Node = DemoteStackSlot; 5126 Entry.Ty = StackSlotPtrType; 5127 Entry.isSExt = false; 5128 Entry.isZExt = false; 5129 Entry.isInReg = false; 5130 Entry.isSRet = true; 5131 Entry.isNest = false; 5132 Entry.isByVal = false; 5133 Entry.Alignment = Align; 5134 Args.push_back(Entry); 5135 RetTy = Type::getVoidTy(FTy->getContext()); 5136 } 5137 5138 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5139 i != e; ++i) { 5140 const Value *V = *i; 5141 5142 // Skip empty types 5143 if (V->getType()->isEmptyTy()) 5144 continue; 5145 5146 SDValue ArgNode = getValue(V); 5147 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5148 5149 unsigned attrInd = i - CS.arg_begin() + 1; 5150 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5151 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5152 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5153 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5154 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5155 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5156 Entry.Alignment = CS.getParamAlignment(attrInd); 5157 Args.push_back(Entry); 5158 } 5159 5160 if (LandingPad) { 5161 // Insert a label before the invoke call to mark the try range. This can be 5162 // used to detect deletion of the invoke via the MachineModuleInfo. 5163 BeginLabel = MMI.getContext().CreateTempSymbol(); 5164 5165 // For SjLj, keep track of which landing pads go with which invokes 5166 // so as to maintain the ordering of pads in the LSDA. 5167 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5168 if (CallSiteIndex) { 5169 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5170 // Now that the call site is handled, stop tracking it. 5171 MMI.setCurrentCallSite(0); 5172 } 5173 5174 // Both PendingLoads and PendingExports must be flushed here; 5175 // this call might not return. 5176 (void)getRoot(); 5177 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5178 } 5179 5180 // Check if target-independent constraints permit a tail call here. 5181 // Target-dependent constraints are checked within TLI.LowerCallTo. 5182 if (isTailCall && 5183 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5184 isTailCall = false; 5185 5186 // If there's a possibility that fast-isel has already selected some amount 5187 // of the current basic block, don't emit a tail call. 5188 if (isTailCall && EnableFastISel) 5189 isTailCall = false; 5190 5191 std::pair<SDValue,SDValue> Result = 5192 TLI.LowerCallTo(getRoot(), RetTy, 5193 CS.paramHasAttr(0, Attribute::SExt), 5194 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5195 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5196 CS.getCallingConv(), 5197 isTailCall, 5198 !CS.getInstruction()->use_empty(), 5199 Callee, Args, DAG, getCurDebugLoc()); 5200 assert((isTailCall || Result.second.getNode()) && 5201 "Non-null chain expected with non-tail call!"); 5202 assert((Result.second.getNode() || !Result.first.getNode()) && 5203 "Null value expected with tail call!"); 5204 if (Result.first.getNode()) { 5205 setValue(CS.getInstruction(), Result.first); 5206 } else if (!CanLowerReturn && Result.second.getNode()) { 5207 // The instruction result is the result of loading from the 5208 // hidden sret parameter. 5209 SmallVector<EVT, 1> PVTs; 5210 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5211 5212 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5213 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5214 EVT PtrVT = PVTs[0]; 5215 unsigned NumValues = Outs.size(); 5216 SmallVector<SDValue, 4> Values(NumValues); 5217 SmallVector<SDValue, 4> Chains(NumValues); 5218 5219 for (unsigned i = 0; i < NumValues; ++i) { 5220 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5221 DemoteStackSlot, 5222 DAG.getConstant(Offsets[i], PtrVT)); 5223 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5224 Add, 5225 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5226 false, false, 1); 5227 Values[i] = L; 5228 Chains[i] = L.getValue(1); 5229 } 5230 5231 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5232 MVT::Other, &Chains[0], NumValues); 5233 PendingLoads.push_back(Chain); 5234 5235 // Collect the legal value parts into potentially illegal values 5236 // that correspond to the original function's return values. 5237 SmallVector<EVT, 4> RetTys; 5238 RetTy = FTy->getReturnType(); 5239 ComputeValueVTs(TLI, RetTy, RetTys); 5240 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5241 SmallVector<SDValue, 4> ReturnValues; 5242 unsigned CurReg = 0; 5243 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5244 EVT VT = RetTys[I]; 5245 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5246 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5247 5248 SDValue ReturnValue = 5249 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5250 RegisterVT, VT, AssertOp); 5251 ReturnValues.push_back(ReturnValue); 5252 CurReg += NumRegs; 5253 } 5254 5255 setValue(CS.getInstruction(), 5256 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5257 DAG.getVTList(&RetTys[0], RetTys.size()), 5258 &ReturnValues[0], ReturnValues.size())); 5259 } 5260 5261 // Assign order to nodes here. If the call does not produce a result, it won't 5262 // be mapped to a SDNode and visit() will not assign it an order number. 5263 if (!Result.second.getNode()) { 5264 // As a special case, a null chain means that a tail call has been emitted and 5265 // the DAG root is already updated. 5266 HasTailCall = true; 5267 ++SDNodeOrder; 5268 AssignOrderingToNode(DAG.getRoot().getNode()); 5269 } else { 5270 DAG.setRoot(Result.second); 5271 ++SDNodeOrder; 5272 AssignOrderingToNode(Result.second.getNode()); 5273 } 5274 5275 if (LandingPad) { 5276 // Insert a label at the end of the invoke call to mark the try range. This 5277 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5278 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5279 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5280 5281 // Inform MachineModuleInfo of range. 5282 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5283 } 5284} 5285 5286/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5287/// value is equal or not-equal to zero. 5288static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5289 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5290 UI != E; ++UI) { 5291 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5292 if (IC->isEquality()) 5293 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5294 if (C->isNullValue()) 5295 continue; 5296 // Unknown instruction. 5297 return false; 5298 } 5299 return true; 5300} 5301 5302static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5303 Type *LoadTy, 5304 SelectionDAGBuilder &Builder) { 5305 5306 // Check to see if this load can be trivially constant folded, e.g. if the 5307 // input is from a string literal. 5308 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5309 // Cast pointer to the type we really want to load. 5310 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5311 PointerType::getUnqual(LoadTy)); 5312 5313 if (const Constant *LoadCst = 5314 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5315 Builder.TD)) 5316 return Builder.getValue(LoadCst); 5317 } 5318 5319 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5320 // still constant memory, the input chain can be the entry node. 5321 SDValue Root; 5322 bool ConstantMemory = false; 5323 5324 // Do not serialize (non-volatile) loads of constant memory with anything. 5325 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5326 Root = Builder.DAG.getEntryNode(); 5327 ConstantMemory = true; 5328 } else { 5329 // Do not serialize non-volatile loads against each other. 5330 Root = Builder.DAG.getRoot(); 5331 } 5332 5333 SDValue Ptr = Builder.getValue(PtrVal); 5334 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5335 Ptr, MachinePointerInfo(PtrVal), 5336 false /*volatile*/, 5337 false /*nontemporal*/, 1 /* align=1 */); 5338 5339 if (!ConstantMemory) 5340 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5341 return LoadVal; 5342} 5343 5344 5345/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5346/// If so, return true and lower it, otherwise return false and it will be 5347/// lowered like a normal call. 5348bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5349 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5350 if (I.getNumArgOperands() != 3) 5351 return false; 5352 5353 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5354 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5355 !I.getArgOperand(2)->getType()->isIntegerTy() || 5356 !I.getType()->isIntegerTy()) 5357 return false; 5358 5359 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5360 5361 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5362 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5363 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5364 bool ActuallyDoIt = true; 5365 MVT LoadVT; 5366 Type *LoadTy; 5367 switch (Size->getZExtValue()) { 5368 default: 5369 LoadVT = MVT::Other; 5370 LoadTy = 0; 5371 ActuallyDoIt = false; 5372 break; 5373 case 2: 5374 LoadVT = MVT::i16; 5375 LoadTy = Type::getInt16Ty(Size->getContext()); 5376 break; 5377 case 4: 5378 LoadVT = MVT::i32; 5379 LoadTy = Type::getInt32Ty(Size->getContext()); 5380 break; 5381 case 8: 5382 LoadVT = MVT::i64; 5383 LoadTy = Type::getInt64Ty(Size->getContext()); 5384 break; 5385 /* 5386 case 16: 5387 LoadVT = MVT::v4i32; 5388 LoadTy = Type::getInt32Ty(Size->getContext()); 5389 LoadTy = VectorType::get(LoadTy, 4); 5390 break; 5391 */ 5392 } 5393 5394 // This turns into unaligned loads. We only do this if the target natively 5395 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5396 // we'll only produce a small number of byte loads. 5397 5398 // Require that we can find a legal MVT, and only do this if the target 5399 // supports unaligned loads of that type. Expanding into byte loads would 5400 // bloat the code. 5401 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5402 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5403 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5404 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5405 ActuallyDoIt = false; 5406 } 5407 5408 if (ActuallyDoIt) { 5409 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5410 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5411 5412 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5413 ISD::SETNE); 5414 EVT CallVT = TLI.getValueType(I.getType(), true); 5415 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5416 return true; 5417 } 5418 } 5419 5420 5421 return false; 5422} 5423 5424 5425void SelectionDAGBuilder::visitCall(const CallInst &I) { 5426 // Handle inline assembly differently. 5427 if (isa<InlineAsm>(I.getCalledValue())) { 5428 visitInlineAsm(&I); 5429 return; 5430 } 5431 5432 // See if any floating point values are being passed to this function. This is 5433 // used to emit an undefined reference to fltused on Windows. 5434 FunctionType *FT = 5435 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5436 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5437 if (FT->isVarArg() && 5438 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5439 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5440 Type* T = I.getArgOperand(i)->getType(); 5441 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5442 i != e; ++i) { 5443 if (!i->isFloatingPointTy()) continue; 5444 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5445 break; 5446 } 5447 } 5448 } 5449 5450 const char *RenameFn = 0; 5451 if (Function *F = I.getCalledFunction()) { 5452 if (F->isDeclaration()) { 5453 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5454 if (unsigned IID = II->getIntrinsicID(F)) { 5455 RenameFn = visitIntrinsicCall(I, IID); 5456 if (!RenameFn) 5457 return; 5458 } 5459 } 5460 if (unsigned IID = F->getIntrinsicID()) { 5461 RenameFn = visitIntrinsicCall(I, IID); 5462 if (!RenameFn) 5463 return; 5464 } 5465 } 5466 5467 // Check for well-known libc/libm calls. If the function is internal, it 5468 // can't be a library call. 5469 if (!F->hasLocalLinkage() && F->hasName()) { 5470 StringRef Name = F->getName(); 5471 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5472 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5473 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5474 I.getType() == I.getArgOperand(0)->getType() && 5475 I.getType() == I.getArgOperand(1)->getType()) { 5476 SDValue LHS = getValue(I.getArgOperand(0)); 5477 SDValue RHS = getValue(I.getArgOperand(1)); 5478 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5479 LHS.getValueType(), LHS, RHS)); 5480 return; 5481 } 5482 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5483 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5484 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5485 I.getType() == I.getArgOperand(0)->getType()) { 5486 SDValue Tmp = getValue(I.getArgOperand(0)); 5487 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5488 Tmp.getValueType(), Tmp)); 5489 return; 5490 } 5491 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5492 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5493 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5494 I.getType() == I.getArgOperand(0)->getType() && 5495 I.onlyReadsMemory()) { 5496 SDValue Tmp = getValue(I.getArgOperand(0)); 5497 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5498 Tmp.getValueType(), Tmp)); 5499 return; 5500 } 5501 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5502 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5503 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5504 I.getType() == I.getArgOperand(0)->getType() && 5505 I.onlyReadsMemory()) { 5506 SDValue Tmp = getValue(I.getArgOperand(0)); 5507 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5508 Tmp.getValueType(), Tmp)); 5509 return; 5510 } 5511 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5512 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5513 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5514 I.getType() == I.getArgOperand(0)->getType() && 5515 I.onlyReadsMemory()) { 5516 SDValue Tmp = getValue(I.getArgOperand(0)); 5517 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5518 Tmp.getValueType(), Tmp)); 5519 return; 5520 } 5521 } else if (Name == "memcmp") { 5522 if (visitMemCmpCall(I)) 5523 return; 5524 } 5525 } 5526 } 5527 5528 SDValue Callee; 5529 if (!RenameFn) 5530 Callee = getValue(I.getCalledValue()); 5531 else 5532 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5533 5534 // Check if we can potentially perform a tail call. More detailed checking is 5535 // be done within LowerCallTo, after more information about the call is known. 5536 LowerCallTo(&I, Callee, I.isTailCall()); 5537} 5538 5539namespace { 5540 5541/// AsmOperandInfo - This contains information for each constraint that we are 5542/// lowering. 5543class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5544public: 5545 /// CallOperand - If this is the result output operand or a clobber 5546 /// this is null, otherwise it is the incoming operand to the CallInst. 5547 /// This gets modified as the asm is processed. 5548 SDValue CallOperand; 5549 5550 /// AssignedRegs - If this is a register or register class operand, this 5551 /// contains the set of register corresponding to the operand. 5552 RegsForValue AssignedRegs; 5553 5554 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5555 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5556 } 5557 5558 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5559 /// busy in OutputRegs/InputRegs. 5560 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5561 std::set<unsigned> &OutputRegs, 5562 std::set<unsigned> &InputRegs, 5563 const TargetRegisterInfo &TRI) const { 5564 if (isOutReg) { 5565 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5566 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5567 } 5568 if (isInReg) { 5569 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5570 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5571 } 5572 } 5573 5574 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5575 /// corresponds to. If there is no Value* for this operand, it returns 5576 /// MVT::Other. 5577 EVT getCallOperandValEVT(LLVMContext &Context, 5578 const TargetLowering &TLI, 5579 const TargetData *TD) const { 5580 if (CallOperandVal == 0) return MVT::Other; 5581 5582 if (isa<BasicBlock>(CallOperandVal)) 5583 return TLI.getPointerTy(); 5584 5585 llvm::Type *OpTy = CallOperandVal->getType(); 5586 5587 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5588 // If this is an indirect operand, the operand is a pointer to the 5589 // accessed type. 5590 if (isIndirect) { 5591 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5592 if (!PtrTy) 5593 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5594 OpTy = PtrTy->getElementType(); 5595 } 5596 5597 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5598 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5599 if (STy->getNumElements() == 1) 5600 OpTy = STy->getElementType(0); 5601 5602 // If OpTy is not a single value, it may be a struct/union that we 5603 // can tile with integers. 5604 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5605 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5606 switch (BitSize) { 5607 default: break; 5608 case 1: 5609 case 8: 5610 case 16: 5611 case 32: 5612 case 64: 5613 case 128: 5614 OpTy = IntegerType::get(Context, BitSize); 5615 break; 5616 } 5617 } 5618 5619 return TLI.getValueType(OpTy, true); 5620 } 5621 5622private: 5623 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5624 /// specified set. 5625 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5626 const TargetRegisterInfo &TRI) { 5627 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5628 Regs.insert(Reg); 5629 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5630 for (; *Aliases; ++Aliases) 5631 Regs.insert(*Aliases); 5632 } 5633}; 5634 5635typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5636 5637} // end anonymous namespace 5638 5639/// GetRegistersForValue - Assign registers (virtual or physical) for the 5640/// specified operand. We prefer to assign virtual registers, to allow the 5641/// register allocator to handle the assignment process. However, if the asm 5642/// uses features that we can't model on machineinstrs, we have SDISel do the 5643/// allocation. This produces generally horrible, but correct, code. 5644/// 5645/// OpInfo describes the operand. 5646/// Input and OutputRegs are the set of already allocated physical registers. 5647/// 5648static void GetRegistersForValue(SelectionDAG &DAG, 5649 const TargetLowering &TLI, 5650 DebugLoc DL, 5651 SDISelAsmOperandInfo &OpInfo, 5652 std::set<unsigned> &OutputRegs, 5653 std::set<unsigned> &InputRegs) { 5654 LLVMContext &Context = *DAG.getContext(); 5655 5656 // Compute whether this value requires an input register, an output register, 5657 // or both. 5658 bool isOutReg = false; 5659 bool isInReg = false; 5660 switch (OpInfo.Type) { 5661 case InlineAsm::isOutput: 5662 isOutReg = true; 5663 5664 // If there is an input constraint that matches this, we need to reserve 5665 // the input register so no other inputs allocate to it. 5666 isInReg = OpInfo.hasMatchingInput(); 5667 break; 5668 case InlineAsm::isInput: 5669 isInReg = true; 5670 isOutReg = false; 5671 break; 5672 case InlineAsm::isClobber: 5673 isOutReg = true; 5674 isInReg = true; 5675 break; 5676 } 5677 5678 5679 MachineFunction &MF = DAG.getMachineFunction(); 5680 SmallVector<unsigned, 4> Regs; 5681 5682 // If this is a constraint for a single physreg, or a constraint for a 5683 // register class, find it. 5684 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5685 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5686 OpInfo.ConstraintVT); 5687 5688 unsigned NumRegs = 1; 5689 if (OpInfo.ConstraintVT != MVT::Other) { 5690 // If this is a FP input in an integer register (or visa versa) insert a bit 5691 // cast of the input value. More generally, handle any case where the input 5692 // value disagrees with the register class we plan to stick this in. 5693 if (OpInfo.Type == InlineAsm::isInput && 5694 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5695 // Try to convert to the first EVT that the reg class contains. If the 5696 // types are identical size, use a bitcast to convert (e.g. two differing 5697 // vector types). 5698 EVT RegVT = *PhysReg.second->vt_begin(); 5699 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5700 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5701 RegVT, OpInfo.CallOperand); 5702 OpInfo.ConstraintVT = RegVT; 5703 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5704 // If the input is a FP value and we want it in FP registers, do a 5705 // bitcast to the corresponding integer type. This turns an f64 value 5706 // into i64, which can be passed with two i32 values on a 32-bit 5707 // machine. 5708 RegVT = EVT::getIntegerVT(Context, 5709 OpInfo.ConstraintVT.getSizeInBits()); 5710 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5711 RegVT, OpInfo.CallOperand); 5712 OpInfo.ConstraintVT = RegVT; 5713 } 5714 } 5715 5716 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5717 } 5718 5719 EVT RegVT; 5720 EVT ValueVT = OpInfo.ConstraintVT; 5721 5722 // If this is a constraint for a specific physical register, like {r17}, 5723 // assign it now. 5724 if (unsigned AssignedReg = PhysReg.first) { 5725 const TargetRegisterClass *RC = PhysReg.second; 5726 if (OpInfo.ConstraintVT == MVT::Other) 5727 ValueVT = *RC->vt_begin(); 5728 5729 // Get the actual register value type. This is important, because the user 5730 // may have asked for (e.g.) the AX register in i32 type. We need to 5731 // remember that AX is actually i16 to get the right extension. 5732 RegVT = *RC->vt_begin(); 5733 5734 // This is a explicit reference to a physical register. 5735 Regs.push_back(AssignedReg); 5736 5737 // If this is an expanded reference, add the rest of the regs to Regs. 5738 if (NumRegs != 1) { 5739 TargetRegisterClass::iterator I = RC->begin(); 5740 for (; *I != AssignedReg; ++I) 5741 assert(I != RC->end() && "Didn't find reg!"); 5742 5743 // Already added the first reg. 5744 --NumRegs; ++I; 5745 for (; NumRegs; --NumRegs, ++I) { 5746 assert(I != RC->end() && "Ran out of registers to allocate!"); 5747 Regs.push_back(*I); 5748 } 5749 } 5750 5751 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5752 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5753 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5754 return; 5755 } 5756 5757 // Otherwise, if this was a reference to an LLVM register class, create vregs 5758 // for this reference. 5759 if (const TargetRegisterClass *RC = PhysReg.second) { 5760 RegVT = *RC->vt_begin(); 5761 if (OpInfo.ConstraintVT == MVT::Other) 5762 ValueVT = RegVT; 5763 5764 // Create the appropriate number of virtual registers. 5765 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5766 for (; NumRegs; --NumRegs) 5767 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5768 5769 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5770 return; 5771 } 5772 5773 // Otherwise, we couldn't allocate enough registers for this. 5774} 5775 5776/// visitInlineAsm - Handle a call to an InlineAsm object. 5777/// 5778void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5779 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5780 5781 /// ConstraintOperands - Information about all of the constraints. 5782 SDISelAsmOperandInfoVector ConstraintOperands; 5783 5784 std::set<unsigned> OutputRegs, InputRegs; 5785 5786 TargetLowering::AsmOperandInfoVector 5787 TargetConstraints = TLI.ParseConstraints(CS); 5788 5789 bool hasMemory = false; 5790 5791 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5792 unsigned ResNo = 0; // ResNo - The result number of the next output. 5793 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5794 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5795 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5796 5797 EVT OpVT = MVT::Other; 5798 5799 // Compute the value type for each operand. 5800 switch (OpInfo.Type) { 5801 case InlineAsm::isOutput: 5802 // Indirect outputs just consume an argument. 5803 if (OpInfo.isIndirect) { 5804 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5805 break; 5806 } 5807 5808 // The return value of the call is this value. As such, there is no 5809 // corresponding argument. 5810 assert(!CS.getType()->isVoidTy() && 5811 "Bad inline asm!"); 5812 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5813 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5814 } else { 5815 assert(ResNo == 0 && "Asm only has one result!"); 5816 OpVT = TLI.getValueType(CS.getType()); 5817 } 5818 ++ResNo; 5819 break; 5820 case InlineAsm::isInput: 5821 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5822 break; 5823 case InlineAsm::isClobber: 5824 // Nothing to do. 5825 break; 5826 } 5827 5828 // If this is an input or an indirect output, process the call argument. 5829 // BasicBlocks are labels, currently appearing only in asm's. 5830 if (OpInfo.CallOperandVal) { 5831 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5832 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5833 } else { 5834 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5835 } 5836 5837 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5838 } 5839 5840 OpInfo.ConstraintVT = OpVT; 5841 5842 // Indirect operand accesses access memory. 5843 if (OpInfo.isIndirect) 5844 hasMemory = true; 5845 else { 5846 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5847 TargetLowering::ConstraintType 5848 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5849 if (CType == TargetLowering::C_Memory) { 5850 hasMemory = true; 5851 break; 5852 } 5853 } 5854 } 5855 } 5856 5857 SDValue Chain, Flag; 5858 5859 // We won't need to flush pending loads if this asm doesn't touch 5860 // memory and is nonvolatile. 5861 if (hasMemory || IA->hasSideEffects()) 5862 Chain = getRoot(); 5863 else 5864 Chain = DAG.getRoot(); 5865 5866 // Second pass over the constraints: compute which constraint option to use 5867 // and assign registers to constraints that want a specific physreg. 5868 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5869 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5870 5871 // If this is an output operand with a matching input operand, look up the 5872 // matching input. If their types mismatch, e.g. one is an integer, the 5873 // other is floating point, or their sizes are different, flag it as an 5874 // error. 5875 if (OpInfo.hasMatchingInput()) { 5876 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5877 5878 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5879 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5880 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 5881 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5882 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 5883 if ((OpInfo.ConstraintVT.isInteger() != 5884 Input.ConstraintVT.isInteger()) || 5885 (MatchRC.second != InputRC.second)) { 5886 report_fatal_error("Unsupported asm: input constraint" 5887 " with a matching output constraint of" 5888 " incompatible type!"); 5889 } 5890 Input.ConstraintVT = OpInfo.ConstraintVT; 5891 } 5892 } 5893 5894 // Compute the constraint code and ConstraintType to use. 5895 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5896 5897 // If this is a memory input, and if the operand is not indirect, do what we 5898 // need to to provide an address for the memory input. 5899 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5900 !OpInfo.isIndirect) { 5901 assert((OpInfo.isMultipleAlternative || 5902 (OpInfo.Type == InlineAsm::isInput)) && 5903 "Can only indirectify direct input operands!"); 5904 5905 // Memory operands really want the address of the value. If we don't have 5906 // an indirect input, put it in the constpool if we can, otherwise spill 5907 // it to a stack slot. 5908 // TODO: This isn't quite right. We need to handle these according to 5909 // the addressing mode that the constraint wants. Also, this may take 5910 // an additional register for the computation and we don't want that 5911 // either. 5912 5913 // If the operand is a float, integer, or vector constant, spill to a 5914 // constant pool entry to get its address. 5915 const Value *OpVal = OpInfo.CallOperandVal; 5916 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5917 isa<ConstantVector>(OpVal)) { 5918 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5919 TLI.getPointerTy()); 5920 } else { 5921 // Otherwise, create a stack slot and emit a store to it before the 5922 // asm. 5923 Type *Ty = OpVal->getType(); 5924 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5925 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5926 MachineFunction &MF = DAG.getMachineFunction(); 5927 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5928 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5929 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5930 OpInfo.CallOperand, StackSlot, 5931 MachinePointerInfo::getFixedStack(SSFI), 5932 false, false, 0); 5933 OpInfo.CallOperand = StackSlot; 5934 } 5935 5936 // There is no longer a Value* corresponding to this operand. 5937 OpInfo.CallOperandVal = 0; 5938 5939 // It is now an indirect operand. 5940 OpInfo.isIndirect = true; 5941 } 5942 5943 // If this constraint is for a specific register, allocate it before 5944 // anything else. 5945 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5946 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5947 InputRegs); 5948 } 5949 5950 // Second pass - Loop over all of the operands, assigning virtual or physregs 5951 // to register class operands. 5952 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5953 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5954 5955 // C_Register operands have already been allocated, Other/Memory don't need 5956 // to be. 5957 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5958 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5959 InputRegs); 5960 } 5961 5962 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5963 std::vector<SDValue> AsmNodeOperands; 5964 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5965 AsmNodeOperands.push_back( 5966 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5967 TLI.getPointerTy())); 5968 5969 // If we have a !srcloc metadata node associated with it, we want to attach 5970 // this to the ultimately generated inline asm machineinstr. To do this, we 5971 // pass in the third operand as this (potentially null) inline asm MDNode. 5972 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5973 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5974 5975 // Remember the HasSideEffect and AlignStack bits as operand 3. 5976 unsigned ExtraInfo = 0; 5977 if (IA->hasSideEffects()) 5978 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5979 if (IA->isAlignStack()) 5980 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5981 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5982 TLI.getPointerTy())); 5983 5984 // Loop over all of the inputs, copying the operand values into the 5985 // appropriate registers and processing the output regs. 5986 RegsForValue RetValRegs; 5987 5988 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5989 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5990 5991 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5992 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5993 5994 switch (OpInfo.Type) { 5995 case InlineAsm::isOutput: { 5996 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5997 OpInfo.ConstraintType != TargetLowering::C_Register) { 5998 // Memory output, or 'other' output (e.g. 'X' constraint). 5999 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6000 6001 // Add information to the INLINEASM node to know about this output. 6002 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6003 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6004 TLI.getPointerTy())); 6005 AsmNodeOperands.push_back(OpInfo.CallOperand); 6006 break; 6007 } 6008 6009 // Otherwise, this is a register or register class output. 6010 6011 // Copy the output from the appropriate register. Find a register that 6012 // we can use. 6013 if (OpInfo.AssignedRegs.Regs.empty()) 6014 report_fatal_error("Couldn't allocate output reg for constraint '" + 6015 Twine(OpInfo.ConstraintCode) + "'!"); 6016 6017 // If this is an indirect operand, store through the pointer after the 6018 // asm. 6019 if (OpInfo.isIndirect) { 6020 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6021 OpInfo.CallOperandVal)); 6022 } else { 6023 // This is the result value of the call. 6024 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6025 // Concatenate this output onto the outputs list. 6026 RetValRegs.append(OpInfo.AssignedRegs); 6027 } 6028 6029 // Add information to the INLINEASM node to know that this register is 6030 // set. 6031 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6032 InlineAsm::Kind_RegDefEarlyClobber : 6033 InlineAsm::Kind_RegDef, 6034 false, 6035 0, 6036 DAG, 6037 AsmNodeOperands); 6038 break; 6039 } 6040 case InlineAsm::isInput: { 6041 SDValue InOperandVal = OpInfo.CallOperand; 6042 6043 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6044 // If this is required to match an output register we have already set, 6045 // just use its register. 6046 unsigned OperandNo = OpInfo.getMatchedOperand(); 6047 6048 // Scan until we find the definition we already emitted of this operand. 6049 // When we find it, create a RegsForValue operand. 6050 unsigned CurOp = InlineAsm::Op_FirstOperand; 6051 for (; OperandNo; --OperandNo) { 6052 // Advance to the next operand. 6053 unsigned OpFlag = 6054 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6055 assert((InlineAsm::isRegDefKind(OpFlag) || 6056 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6057 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6058 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6059 } 6060 6061 unsigned OpFlag = 6062 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6063 if (InlineAsm::isRegDefKind(OpFlag) || 6064 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6065 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6066 if (OpInfo.isIndirect) { 6067 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6068 LLVMContext &Ctx = *DAG.getContext(); 6069 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6070 " don't know how to handle tied " 6071 "indirect register inputs"); 6072 } 6073 6074 RegsForValue MatchedRegs; 6075 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6076 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6077 MatchedRegs.RegVTs.push_back(RegVT); 6078 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6079 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6080 i != e; ++i) 6081 MatchedRegs.Regs.push_back 6082 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6083 6084 // Use the produced MatchedRegs object to 6085 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6086 Chain, &Flag); 6087 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6088 true, OpInfo.getMatchedOperand(), 6089 DAG, AsmNodeOperands); 6090 break; 6091 } 6092 6093 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6094 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6095 "Unexpected number of operands"); 6096 // Add information to the INLINEASM node to know about this input. 6097 // See InlineAsm.h isUseOperandTiedToDef. 6098 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6099 OpInfo.getMatchedOperand()); 6100 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6101 TLI.getPointerTy())); 6102 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6103 break; 6104 } 6105 6106 // Treat indirect 'X' constraint as memory. 6107 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6108 OpInfo.isIndirect) 6109 OpInfo.ConstraintType = TargetLowering::C_Memory; 6110 6111 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6112 std::vector<SDValue> Ops; 6113 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6114 Ops, DAG); 6115 if (Ops.empty()) 6116 report_fatal_error("Invalid operand for inline asm constraint '" + 6117 Twine(OpInfo.ConstraintCode) + "'!"); 6118 6119 // Add information to the INLINEASM node to know about this input. 6120 unsigned ResOpType = 6121 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6122 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6123 TLI.getPointerTy())); 6124 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6125 break; 6126 } 6127 6128 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6129 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6130 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6131 "Memory operands expect pointer values"); 6132 6133 // Add information to the INLINEASM node to know about this input. 6134 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6135 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6136 TLI.getPointerTy())); 6137 AsmNodeOperands.push_back(InOperandVal); 6138 break; 6139 } 6140 6141 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6142 OpInfo.ConstraintType == TargetLowering::C_Register) && 6143 "Unknown constraint type!"); 6144 assert(!OpInfo.isIndirect && 6145 "Don't know how to handle indirect register inputs yet!"); 6146 6147 // Copy the input into the appropriate registers. 6148 if (OpInfo.AssignedRegs.Regs.empty()) 6149 report_fatal_error("Couldn't allocate input reg for constraint '" + 6150 Twine(OpInfo.ConstraintCode) + "'!"); 6151 6152 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6153 Chain, &Flag); 6154 6155 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6156 DAG, AsmNodeOperands); 6157 break; 6158 } 6159 case InlineAsm::isClobber: { 6160 // Add the clobbered value to the operand list, so that the register 6161 // allocator is aware that the physreg got clobbered. 6162 if (!OpInfo.AssignedRegs.Regs.empty()) 6163 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6164 false, 0, DAG, 6165 AsmNodeOperands); 6166 break; 6167 } 6168 } 6169 } 6170 6171 // Finish up input operands. Set the input chain and add the flag last. 6172 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6173 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6174 6175 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6176 DAG.getVTList(MVT::Other, MVT::Glue), 6177 &AsmNodeOperands[0], AsmNodeOperands.size()); 6178 Flag = Chain.getValue(1); 6179 6180 // If this asm returns a register value, copy the result from that register 6181 // and set it as the value of the call. 6182 if (!RetValRegs.Regs.empty()) { 6183 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6184 Chain, &Flag); 6185 6186 // FIXME: Why don't we do this for inline asms with MRVs? 6187 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6188 EVT ResultType = TLI.getValueType(CS.getType()); 6189 6190 // If any of the results of the inline asm is a vector, it may have the 6191 // wrong width/num elts. This can happen for register classes that can 6192 // contain multiple different value types. The preg or vreg allocated may 6193 // not have the same VT as was expected. Convert it to the right type 6194 // with bit_convert. 6195 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6196 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6197 ResultType, Val); 6198 6199 } else if (ResultType != Val.getValueType() && 6200 ResultType.isInteger() && Val.getValueType().isInteger()) { 6201 // If a result value was tied to an input value, the computed result may 6202 // have a wider width than the expected result. Extract the relevant 6203 // portion. 6204 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6205 } 6206 6207 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6208 } 6209 6210 setValue(CS.getInstruction(), Val); 6211 // Don't need to use this as a chain in this case. 6212 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6213 return; 6214 } 6215 6216 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6217 6218 // Process indirect outputs, first output all of the flagged copies out of 6219 // physregs. 6220 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6221 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6222 const Value *Ptr = IndirectStoresToEmit[i].second; 6223 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6224 Chain, &Flag); 6225 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6226 } 6227 6228 // Emit the non-flagged stores from the physregs. 6229 SmallVector<SDValue, 8> OutChains; 6230 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6231 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6232 StoresToEmit[i].first, 6233 getValue(StoresToEmit[i].second), 6234 MachinePointerInfo(StoresToEmit[i].second), 6235 false, false, 0); 6236 OutChains.push_back(Val); 6237 } 6238 6239 if (!OutChains.empty()) 6240 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6241 &OutChains[0], OutChains.size()); 6242 6243 DAG.setRoot(Chain); 6244} 6245 6246void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6247 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6248 MVT::Other, getRoot(), 6249 getValue(I.getArgOperand(0)), 6250 DAG.getSrcValue(I.getArgOperand(0)))); 6251} 6252 6253void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6254 const TargetData &TD = *TLI.getTargetData(); 6255 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6256 getRoot(), getValue(I.getOperand(0)), 6257 DAG.getSrcValue(I.getOperand(0)), 6258 TD.getABITypeAlignment(I.getType())); 6259 setValue(&I, V); 6260 DAG.setRoot(V.getValue(1)); 6261} 6262 6263void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6264 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6265 MVT::Other, getRoot(), 6266 getValue(I.getArgOperand(0)), 6267 DAG.getSrcValue(I.getArgOperand(0)))); 6268} 6269 6270void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6271 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6272 MVT::Other, getRoot(), 6273 getValue(I.getArgOperand(0)), 6274 getValue(I.getArgOperand(1)), 6275 DAG.getSrcValue(I.getArgOperand(0)), 6276 DAG.getSrcValue(I.getArgOperand(1)))); 6277} 6278 6279/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6280/// implementation, which just calls LowerCall. 6281/// FIXME: When all targets are 6282/// migrated to using LowerCall, this hook should be integrated into SDISel. 6283std::pair<SDValue, SDValue> 6284TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6285 bool RetSExt, bool RetZExt, bool isVarArg, 6286 bool isInreg, unsigned NumFixedArgs, 6287 CallingConv::ID CallConv, bool isTailCall, 6288 bool isReturnValueUsed, 6289 SDValue Callee, 6290 ArgListTy &Args, SelectionDAG &DAG, 6291 DebugLoc dl) const { 6292 // Handle all of the outgoing arguments. 6293 SmallVector<ISD::OutputArg, 32> Outs; 6294 SmallVector<SDValue, 32> OutVals; 6295 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6296 SmallVector<EVT, 4> ValueVTs; 6297 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6298 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6299 Value != NumValues; ++Value) { 6300 EVT VT = ValueVTs[Value]; 6301 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6302 SDValue Op = SDValue(Args[i].Node.getNode(), 6303 Args[i].Node.getResNo() + Value); 6304 ISD::ArgFlagsTy Flags; 6305 unsigned OriginalAlignment = 6306 getTargetData()->getABITypeAlignment(ArgTy); 6307 6308 if (Args[i].isZExt) 6309 Flags.setZExt(); 6310 if (Args[i].isSExt) 6311 Flags.setSExt(); 6312 if (Args[i].isInReg) 6313 Flags.setInReg(); 6314 if (Args[i].isSRet) 6315 Flags.setSRet(); 6316 if (Args[i].isByVal) { 6317 Flags.setByVal(); 6318 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6319 Type *ElementTy = Ty->getElementType(); 6320 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6321 // For ByVal, alignment should come from FE. BE will guess if this 6322 // info is not there but there are cases it cannot get right. 6323 unsigned FrameAlign; 6324 if (Args[i].Alignment) 6325 FrameAlign = Args[i].Alignment; 6326 else 6327 FrameAlign = getByValTypeAlignment(ElementTy); 6328 Flags.setByValAlign(FrameAlign); 6329 } 6330 if (Args[i].isNest) 6331 Flags.setNest(); 6332 Flags.setOrigAlign(OriginalAlignment); 6333 6334 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6335 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6336 SmallVector<SDValue, 4> Parts(NumParts); 6337 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6338 6339 if (Args[i].isSExt) 6340 ExtendKind = ISD::SIGN_EXTEND; 6341 else if (Args[i].isZExt) 6342 ExtendKind = ISD::ZERO_EXTEND; 6343 6344 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6345 PartVT, ExtendKind); 6346 6347 for (unsigned j = 0; j != NumParts; ++j) { 6348 // if it isn't first piece, alignment must be 1 6349 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6350 i < NumFixedArgs); 6351 if (NumParts > 1 && j == 0) 6352 MyFlags.Flags.setSplit(); 6353 else if (j != 0) 6354 MyFlags.Flags.setOrigAlign(1); 6355 6356 Outs.push_back(MyFlags); 6357 OutVals.push_back(Parts[j]); 6358 } 6359 } 6360 } 6361 6362 // Handle the incoming return values from the call. 6363 SmallVector<ISD::InputArg, 32> Ins; 6364 SmallVector<EVT, 4> RetTys; 6365 ComputeValueVTs(*this, RetTy, RetTys); 6366 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6367 EVT VT = RetTys[I]; 6368 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6369 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6370 for (unsigned i = 0; i != NumRegs; ++i) { 6371 ISD::InputArg MyFlags; 6372 MyFlags.VT = RegisterVT.getSimpleVT(); 6373 MyFlags.Used = isReturnValueUsed; 6374 if (RetSExt) 6375 MyFlags.Flags.setSExt(); 6376 if (RetZExt) 6377 MyFlags.Flags.setZExt(); 6378 if (isInreg) 6379 MyFlags.Flags.setInReg(); 6380 Ins.push_back(MyFlags); 6381 } 6382 } 6383 6384 SmallVector<SDValue, 4> InVals; 6385 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6386 Outs, OutVals, Ins, dl, DAG, InVals); 6387 6388 // Verify that the target's LowerCall behaved as expected. 6389 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6390 "LowerCall didn't return a valid chain!"); 6391 assert((!isTailCall || InVals.empty()) && 6392 "LowerCall emitted a return value for a tail call!"); 6393 assert((isTailCall || InVals.size() == Ins.size()) && 6394 "LowerCall didn't emit the correct number of values!"); 6395 6396 // For a tail call, the return value is merely live-out and there aren't 6397 // any nodes in the DAG representing it. Return a special value to 6398 // indicate that a tail call has been emitted and no more Instructions 6399 // should be processed in the current block. 6400 if (isTailCall) { 6401 DAG.setRoot(Chain); 6402 return std::make_pair(SDValue(), SDValue()); 6403 } 6404 6405 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6406 assert(InVals[i].getNode() && 6407 "LowerCall emitted a null value!"); 6408 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6409 "LowerCall emitted a value with the wrong type!"); 6410 }); 6411 6412 // Collect the legal value parts into potentially illegal values 6413 // that correspond to the original function's return values. 6414 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6415 if (RetSExt) 6416 AssertOp = ISD::AssertSext; 6417 else if (RetZExt) 6418 AssertOp = ISD::AssertZext; 6419 SmallVector<SDValue, 4> ReturnValues; 6420 unsigned CurReg = 0; 6421 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6422 EVT VT = RetTys[I]; 6423 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6424 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6425 6426 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6427 NumRegs, RegisterVT, VT, 6428 AssertOp)); 6429 CurReg += NumRegs; 6430 } 6431 6432 // For a function returning void, there is no return value. We can't create 6433 // such a node, so we just return a null return value in that case. In 6434 // that case, nothing will actually look at the value. 6435 if (ReturnValues.empty()) 6436 return std::make_pair(SDValue(), Chain); 6437 6438 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6439 DAG.getVTList(&RetTys[0], RetTys.size()), 6440 &ReturnValues[0], ReturnValues.size()); 6441 return std::make_pair(Res, Chain); 6442} 6443 6444void TargetLowering::LowerOperationWrapper(SDNode *N, 6445 SmallVectorImpl<SDValue> &Results, 6446 SelectionDAG &DAG) const { 6447 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6448 if (Res.getNode()) 6449 Results.push_back(Res); 6450} 6451 6452SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6453 llvm_unreachable("LowerOperation not implemented for this target!"); 6454 return SDValue(); 6455} 6456 6457void 6458SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6459 SDValue Op = getNonRegisterValue(V); 6460 assert((Op.getOpcode() != ISD::CopyFromReg || 6461 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6462 "Copy from a reg to the same reg!"); 6463 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6464 6465 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6466 SDValue Chain = DAG.getEntryNode(); 6467 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6468 PendingExports.push_back(Chain); 6469} 6470 6471#include "llvm/CodeGen/SelectionDAGISel.h" 6472 6473/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6474/// entry block, return true. This includes arguments used by switches, since 6475/// the switch may expand into multiple basic blocks. 6476static bool isOnlyUsedInEntryBlock(const Argument *A) { 6477 // With FastISel active, we may be splitting blocks, so force creation 6478 // of virtual registers for all non-dead arguments. 6479 if (EnableFastISel) 6480 return A->use_empty(); 6481 6482 const BasicBlock *Entry = A->getParent()->begin(); 6483 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6484 UI != E; ++UI) { 6485 const User *U = *UI; 6486 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6487 return false; // Use not in entry block. 6488 } 6489 return true; 6490} 6491 6492void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6493 // If this is the entry block, emit arguments. 6494 const Function &F = *LLVMBB->getParent(); 6495 SelectionDAG &DAG = SDB->DAG; 6496 DebugLoc dl = SDB->getCurDebugLoc(); 6497 const TargetData *TD = TLI.getTargetData(); 6498 SmallVector<ISD::InputArg, 16> Ins; 6499 6500 // Check whether the function can return without sret-demotion. 6501 SmallVector<ISD::OutputArg, 4> Outs; 6502 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6503 Outs, TLI); 6504 6505 if (!FuncInfo->CanLowerReturn) { 6506 // Put in an sret pointer parameter before all the other parameters. 6507 SmallVector<EVT, 1> ValueVTs; 6508 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6509 6510 // NOTE: Assuming that a pointer will never break down to more than one VT 6511 // or one register. 6512 ISD::ArgFlagsTy Flags; 6513 Flags.setSRet(); 6514 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6515 ISD::InputArg RetArg(Flags, RegisterVT, true); 6516 Ins.push_back(RetArg); 6517 } 6518 6519 // Set up the incoming argument description vector. 6520 unsigned Idx = 1; 6521 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6522 I != E; ++I, ++Idx) { 6523 SmallVector<EVT, 4> ValueVTs; 6524 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6525 bool isArgValueUsed = !I->use_empty(); 6526 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6527 Value != NumValues; ++Value) { 6528 EVT VT = ValueVTs[Value]; 6529 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6530 ISD::ArgFlagsTy Flags; 6531 unsigned OriginalAlignment = 6532 TD->getABITypeAlignment(ArgTy); 6533 6534 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6535 Flags.setZExt(); 6536 if (F.paramHasAttr(Idx, Attribute::SExt)) 6537 Flags.setSExt(); 6538 if (F.paramHasAttr(Idx, Attribute::InReg)) 6539 Flags.setInReg(); 6540 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6541 Flags.setSRet(); 6542 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6543 Flags.setByVal(); 6544 PointerType *Ty = cast<PointerType>(I->getType()); 6545 Type *ElementTy = Ty->getElementType(); 6546 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6547 // For ByVal, alignment should be passed from FE. BE will guess if 6548 // this info is not there but there are cases it cannot get right. 6549 unsigned FrameAlign; 6550 if (F.getParamAlignment(Idx)) 6551 FrameAlign = F.getParamAlignment(Idx); 6552 else 6553 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6554 Flags.setByValAlign(FrameAlign); 6555 } 6556 if (F.paramHasAttr(Idx, Attribute::Nest)) 6557 Flags.setNest(); 6558 Flags.setOrigAlign(OriginalAlignment); 6559 6560 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6561 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6562 for (unsigned i = 0; i != NumRegs; ++i) { 6563 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6564 if (NumRegs > 1 && i == 0) 6565 MyFlags.Flags.setSplit(); 6566 // if it isn't first piece, alignment must be 1 6567 else if (i > 0) 6568 MyFlags.Flags.setOrigAlign(1); 6569 Ins.push_back(MyFlags); 6570 } 6571 } 6572 } 6573 6574 // Call the target to set up the argument values. 6575 SmallVector<SDValue, 8> InVals; 6576 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6577 F.isVarArg(), Ins, 6578 dl, DAG, InVals); 6579 6580 // Verify that the target's LowerFormalArguments behaved as expected. 6581 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6582 "LowerFormalArguments didn't return a valid chain!"); 6583 assert(InVals.size() == Ins.size() && 6584 "LowerFormalArguments didn't emit the correct number of values!"); 6585 DEBUG({ 6586 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6587 assert(InVals[i].getNode() && 6588 "LowerFormalArguments emitted a null value!"); 6589 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6590 "LowerFormalArguments emitted a value with the wrong type!"); 6591 } 6592 }); 6593 6594 // Update the DAG with the new chain value resulting from argument lowering. 6595 DAG.setRoot(NewRoot); 6596 6597 // Set up the argument values. 6598 unsigned i = 0; 6599 Idx = 1; 6600 if (!FuncInfo->CanLowerReturn) { 6601 // Create a virtual register for the sret pointer, and put in a copy 6602 // from the sret argument into it. 6603 SmallVector<EVT, 1> ValueVTs; 6604 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6605 EVT VT = ValueVTs[0]; 6606 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6607 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6608 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6609 RegVT, VT, AssertOp); 6610 6611 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6612 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6613 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6614 FuncInfo->DemoteRegister = SRetReg; 6615 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6616 SRetReg, ArgValue); 6617 DAG.setRoot(NewRoot); 6618 6619 // i indexes lowered arguments. Bump it past the hidden sret argument. 6620 // Idx indexes LLVM arguments. Don't touch it. 6621 ++i; 6622 } 6623 6624 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6625 ++I, ++Idx) { 6626 SmallVector<SDValue, 4> ArgValues; 6627 SmallVector<EVT, 4> ValueVTs; 6628 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6629 unsigned NumValues = ValueVTs.size(); 6630 6631 // If this argument is unused then remember its value. It is used to generate 6632 // debugging information. 6633 if (I->use_empty() && NumValues) 6634 SDB->setUnusedArgValue(I, InVals[i]); 6635 6636 for (unsigned Val = 0; Val != NumValues; ++Val) { 6637 EVT VT = ValueVTs[Val]; 6638 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6639 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6640 6641 if (!I->use_empty()) { 6642 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6643 if (F.paramHasAttr(Idx, Attribute::SExt)) 6644 AssertOp = ISD::AssertSext; 6645 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6646 AssertOp = ISD::AssertZext; 6647 6648 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6649 NumParts, PartVT, VT, 6650 AssertOp)); 6651 } 6652 6653 i += NumParts; 6654 } 6655 6656 // We don't need to do anything else for unused arguments. 6657 if (ArgValues.empty()) 6658 continue; 6659 6660 // Note down frame index for byval arguments. 6661 if (I->hasByValAttr()) 6662 if (FrameIndexSDNode *FI = 6663 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6664 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6665 6666 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6667 SDB->getCurDebugLoc()); 6668 SDB->setValue(I, Res); 6669 6670 // If this argument is live outside of the entry block, insert a copy from 6671 // wherever we got it to the vreg that other BB's will reference it as. 6672 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6673 // If we can, though, try to skip creating an unnecessary vreg. 6674 // FIXME: This isn't very clean... it would be nice to make this more 6675 // general. It's also subtly incompatible with the hacks FastISel 6676 // uses with vregs. 6677 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6678 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6679 FuncInfo->ValueMap[I] = Reg; 6680 continue; 6681 } 6682 } 6683 if (!isOnlyUsedInEntryBlock(I)) { 6684 FuncInfo->InitializeRegForValue(I); 6685 SDB->CopyToExportRegsIfNeeded(I); 6686 } 6687 } 6688 6689 assert(i == InVals.size() && "Argument register count mismatch!"); 6690 6691 // Finally, if the target has anything special to do, allow it to do so. 6692 // FIXME: this should insert code into the DAG! 6693 EmitFunctionEntryCode(); 6694} 6695 6696/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6697/// ensure constants are generated when needed. Remember the virtual registers 6698/// that need to be added to the Machine PHI nodes as input. We cannot just 6699/// directly add them, because expansion might result in multiple MBB's for one 6700/// BB. As such, the start of the BB might correspond to a different MBB than 6701/// the end. 6702/// 6703void 6704SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6705 const TerminatorInst *TI = LLVMBB->getTerminator(); 6706 6707 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6708 6709 // Check successor nodes' PHI nodes that expect a constant to be available 6710 // from this block. 6711 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6712 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6713 if (!isa<PHINode>(SuccBB->begin())) continue; 6714 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6715 6716 // If this terminator has multiple identical successors (common for 6717 // switches), only handle each succ once. 6718 if (!SuccsHandled.insert(SuccMBB)) continue; 6719 6720 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6721 6722 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6723 // nodes and Machine PHI nodes, but the incoming operands have not been 6724 // emitted yet. 6725 for (BasicBlock::const_iterator I = SuccBB->begin(); 6726 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6727 // Ignore dead phi's. 6728 if (PN->use_empty()) continue; 6729 6730 // Skip empty types 6731 if (PN->getType()->isEmptyTy()) 6732 continue; 6733 6734 unsigned Reg; 6735 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6736 6737 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6738 unsigned &RegOut = ConstantsOut[C]; 6739 if (RegOut == 0) { 6740 RegOut = FuncInfo.CreateRegs(C->getType()); 6741 CopyValueToVirtualRegister(C, RegOut); 6742 } 6743 Reg = RegOut; 6744 } else { 6745 DenseMap<const Value *, unsigned>::iterator I = 6746 FuncInfo.ValueMap.find(PHIOp); 6747 if (I != FuncInfo.ValueMap.end()) 6748 Reg = I->second; 6749 else { 6750 assert(isa<AllocaInst>(PHIOp) && 6751 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6752 "Didn't codegen value into a register!??"); 6753 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6754 CopyValueToVirtualRegister(PHIOp, Reg); 6755 } 6756 } 6757 6758 // Remember that this register needs to added to the machine PHI node as 6759 // the input for this MBB. 6760 SmallVector<EVT, 4> ValueVTs; 6761 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6762 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6763 EVT VT = ValueVTs[vti]; 6764 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6765 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6766 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6767 Reg += NumRegisters; 6768 } 6769 } 6770 } 6771 ConstantsOut.clear(); 6772} 6773