SelectionDAGBuilder.cpp revision 5c8110883afbf3b4ec5031dc5bfe0f5627f2ca0e
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "FunctionLoweringInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73namespace { 74 /// RegsForValue - This struct represents the registers (physical or virtual) 75 /// that a particular set of values is assigned, and the type information 76 /// about the value. The most common situation is to represent one value at a 77 /// time, but struct or array values are handled element-wise as multiple 78 /// values. The splitting of aggregates is performed recursively, so that we 79 /// never have aggregate-typed registers. The values at this point do not 80 /// necessarily have legal types, so each value may require one or more 81 /// registers of some legal type. 82 /// 83 struct RegsForValue { 84 /// TLI - The TargetLowering object. 85 /// 86 const TargetLowering *TLI; 87 88 /// ValueVTs - The value types of the values, which may not be legal, and 89 /// may need be promoted or synthesized from one or more registers. 90 /// 91 SmallVector<EVT, 4> ValueVTs; 92 93 /// RegVTs - The value types of the registers. This is the same size as 94 /// ValueVTs and it records, for each value, what the type of the assigned 95 /// register or registers are. (Individual values are never synthesized 96 /// from more than one type of register.) 97 /// 98 /// With virtual registers, the contents of RegVTs is redundant with TLI's 99 /// getRegisterType member function, however when with physical registers 100 /// it is necessary to have a separate record of the types. 101 /// 102 SmallVector<EVT, 4> RegVTs; 103 104 /// Regs - This list holds the registers assigned to the values. 105 /// Each legal or promoted value requires one register, and each 106 /// expanded value requires multiple registers. 107 /// 108 SmallVector<unsigned, 4> Regs; 109 110 RegsForValue() : TLI(0) {} 111 112 RegsForValue(const TargetLowering &tli, 113 const SmallVector<unsigned, 4> ®s, 114 EVT regvt, EVT valuevt) 115 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 116 RegsForValue(const TargetLowering &tli, 117 const SmallVector<unsigned, 4> ®s, 118 const SmallVector<EVT, 4> ®vts, 119 const SmallVector<EVT, 4> &valuevts) 120 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} 121 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 122 unsigned Reg, const Type *Ty) : TLI(&tli) { 123 ComputeValueVTs(tli, Ty, ValueVTs); 124 125 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 126 EVT ValueVT = ValueVTs[Value]; 127 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT); 128 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT); 129 for (unsigned i = 0; i != NumRegs; ++i) 130 Regs.push_back(Reg + i); 131 RegVTs.push_back(RegisterVT); 132 Reg += NumRegs; 133 } 134 } 135 136 /// areValueTypesLegal - Return true if types of all the values are legal. 137 bool areValueTypesLegal() { 138 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 139 EVT RegisterVT = RegVTs[Value]; 140 if (!TLI->isTypeLegal(RegisterVT)) 141 return false; 142 } 143 return true; 144 } 145 146 147 /// append - Add the specified values to this one. 148 void append(const RegsForValue &RHS) { 149 TLI = RHS.TLI; 150 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 151 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 152 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 153 } 154 155 156 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 157 /// this value and returns the result as a ValueVTs value. This uses 158 /// Chain/Flag as the input and updates them for the output Chain/Flag. 159 /// If the Flag pointer is NULL, no flag is used. 160 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 161 SDValue &Chain, SDValue *Flag) const; 162 163 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 164 /// specified value into the registers specified by this object. This uses 165 /// Chain/Flag as the input and updates them for the output Chain/Flag. 166 /// If the Flag pointer is NULL, no flag is used. 167 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 168 SDValue &Chain, SDValue *Flag) const; 169 170 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 171 /// operand list. This adds the code marker, matching input operand index 172 /// (if applicable), and includes the number of values added into it. 173 void AddInlineAsmOperands(unsigned Kind, 174 bool HasMatching, unsigned MatchingIdx, 175 SelectionDAG &DAG, 176 std::vector<SDValue> &Ops) const; 177 }; 178} 179 180/// getCopyFromParts - Create a value that contains the specified legal parts 181/// combined into the value they represent. If the parts combine to a type 182/// larger then ValueVT then AssertOp can be used to specify whether the extra 183/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 184/// (ISD::AssertSext). 185static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, 186 const SDValue *Parts, 187 unsigned NumParts, EVT PartVT, EVT ValueVT, 188 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 189 assert(NumParts > 0 && "No parts to assemble!"); 190 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 191 SDValue Val = Parts[0]; 192 193 if (NumParts > 1) { 194 // Assemble the value from multiple parts. 195 if (!ValueVT.isVector() && ValueVT.isInteger()) { 196 unsigned PartBits = PartVT.getSizeInBits(); 197 unsigned ValueBits = ValueVT.getSizeInBits(); 198 199 // Assemble the power of 2 part. 200 unsigned RoundParts = NumParts & (NumParts - 1) ? 201 1 << Log2_32(NumParts) : NumParts; 202 unsigned RoundBits = PartBits * RoundParts; 203 EVT RoundVT = RoundBits == ValueBits ? 204 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 205 SDValue Lo, Hi; 206 207 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 208 209 if (RoundParts > 2) { 210 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2, 211 PartVT, HalfVT); 212 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2, 213 RoundParts / 2, PartVT, HalfVT); 214 } else { 215 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); 216 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); 217 } 218 219 if (TLI.isBigEndian()) 220 std::swap(Lo, Hi); 221 222 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); 223 224 if (RoundParts < NumParts) { 225 // Assemble the trailing non-power-of-2 part. 226 unsigned OddParts = NumParts - RoundParts; 227 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 228 Hi = getCopyFromParts(DAG, dl, 229 Parts + RoundParts, OddParts, PartVT, OddVT); 230 231 // Combine the round and odd parts. 232 Lo = Val; 233 if (TLI.isBigEndian()) 234 std::swap(Lo, Hi); 235 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 236 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); 237 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, 238 DAG.getConstant(Lo.getValueType().getSizeInBits(), 239 TLI.getPointerTy())); 240 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); 241 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); 242 } 243 } else if (ValueVT.isVector()) { 244 // Handle a multi-element vector. 245 EVT IntermediateVT, RegisterVT; 246 unsigned NumIntermediates; 247 unsigned NumRegs = 248 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 249 NumIntermediates, RegisterVT); 250 assert(NumRegs == NumParts 251 && "Part count doesn't match vector breakdown!"); 252 NumParts = NumRegs; // Silence a compiler warning. 253 assert(RegisterVT == PartVT 254 && "Part type doesn't match vector breakdown!"); 255 assert(RegisterVT == Parts[0].getValueType() && 256 "Part type doesn't match part!"); 257 258 // Assemble the parts into intermediate operands. 259 SmallVector<SDValue, 8> Ops(NumIntermediates); 260 if (NumIntermediates == NumParts) { 261 // If the register was not expanded, truncate or copy the value, 262 // as appropriate. 263 for (unsigned i = 0; i != NumParts; ++i) 264 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, 265 PartVT, IntermediateVT); 266 } else if (NumParts > 0) { 267 // If the intermediate type was expanded, build the intermediate 268 // operands from the parts. 269 assert(NumParts % NumIntermediates == 0 && 270 "Must expand into a divisible number of parts!"); 271 unsigned Factor = NumParts / NumIntermediates; 272 for (unsigned i = 0; i != NumIntermediates; ++i) 273 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, 274 PartVT, IntermediateVT); 275 } 276 277 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 278 // intermediate operands. 279 Val = DAG.getNode(IntermediateVT.isVector() ? 280 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, 281 ValueVT, &Ops[0], NumIntermediates); 282 } else if (PartVT.isFloatingPoint()) { 283 // FP split into multiple FP parts (for ppcf128) 284 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 285 "Unexpected split"); 286 SDValue Lo, Hi; 287 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]); 288 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]); 289 if (TLI.isBigEndian()) 290 std::swap(Lo, Hi); 291 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi); 292 } else { 293 // FP split into integer parts (soft fp) 294 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 295 !PartVT.isVector() && "Unexpected split"); 296 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 297 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT); 298 } 299 } 300 301 // There is now one part, held in Val. Correct it to match ValueVT. 302 PartVT = Val.getValueType(); 303 304 if (PartVT == ValueVT) 305 return Val; 306 307 if (PartVT.isVector()) { 308 assert(ValueVT.isVector() && "Unknown vector conversion!"); 309 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 310 } 311 312 if (ValueVT.isVector()) { 313 assert(ValueVT.getVectorElementType() == PartVT && 314 ValueVT.getVectorNumElements() == 1 && 315 "Only trivial scalar-to-vector conversions should get here!"); 316 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); 317 } 318 319 if (PartVT.isInteger() && 320 ValueVT.isInteger()) { 321 if (ValueVT.bitsLT(PartVT)) { 322 // For a truncate, see if we have any information to 323 // indicate whether the truncated bits will always be 324 // zero or sign-extension. 325 if (AssertOp != ISD::DELETED_NODE) 326 Val = DAG.getNode(AssertOp, dl, PartVT, Val, 327 DAG.getValueType(ValueVT)); 328 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 329 } else { 330 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); 331 } 332 } 333 334 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 335 if (ValueVT.bitsLT(Val.getValueType())) { 336 // FP_ROUND's are always exact here. 337 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, 338 DAG.getIntPtrConstant(1)); 339 } 340 341 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); 342 } 343 344 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 345 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); 346 347 llvm_unreachable("Unknown mismatch!"); 348 return SDValue(); 349} 350 351/// getCopyToParts - Create a series of nodes that contain the specified value 352/// split into legal parts. If the parts contain more bits than Val, then, for 353/// integers, ExtendKind can be used to specify how to generate the extra bits. 354static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, 355 SDValue Val, SDValue *Parts, unsigned NumParts, 356 EVT PartVT, 357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 358 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 359 EVT PtrVT = TLI.getPointerTy(); 360 EVT ValueVT = Val.getValueType(); 361 unsigned PartBits = PartVT.getSizeInBits(); 362 unsigned OrigNumParts = NumParts; 363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 364 365 if (!NumParts) 366 return; 367 368 if (!ValueVT.isVector()) { 369 if (PartVT == ValueVT) { 370 assert(NumParts == 1 && "No-op copy with multiple parts!"); 371 Parts[0] = Val; 372 return; 373 } 374 375 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 376 // If the parts cover more bits than the value has, promote the value. 377 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 378 assert(NumParts == 1 && "Do not know what to promote to!"); 379 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); 380 } else if (PartVT.isInteger() && ValueVT.isInteger()) { 381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 382 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); 383 } else { 384 llvm_unreachable("Unknown mismatch!"); 385 } 386 } else if (PartBits == ValueVT.getSizeInBits()) { 387 // Different types of the same size. 388 assert(NumParts == 1 && PartVT != ValueVT); 389 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 390 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 391 // If the parts cover less bits than value has, truncate the value. 392 if (PartVT.isInteger() && ValueVT.isInteger()) { 393 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 394 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 395 } else { 396 llvm_unreachable("Unknown mismatch!"); 397 } 398 } 399 400 // The value may have changed - recompute ValueVT. 401 ValueVT = Val.getValueType(); 402 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 403 "Failed to tile the value with PartVT!"); 404 405 if (NumParts == 1) { 406 assert(PartVT == ValueVT && "Type conversion failed!"); 407 Parts[0] = Val; 408 return; 409 } 410 411 // Expand the value into multiple parts. 412 if (NumParts & (NumParts - 1)) { 413 // The number of parts is not a power of 2. Split off and copy the tail. 414 assert(PartVT.isInteger() && ValueVT.isInteger() && 415 "Do not know what to expand to!"); 416 unsigned RoundParts = 1 << Log2_32(NumParts); 417 unsigned RoundBits = RoundParts * PartBits; 418 unsigned OddParts = NumParts - RoundParts; 419 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, 420 DAG.getConstant(RoundBits, 421 TLI.getPointerTy())); 422 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, 423 OddParts, PartVT); 424 425 if (TLI.isBigEndian()) 426 // The odd parts were reversed by getCopyToParts - unreverse them. 427 std::reverse(Parts + RoundParts, Parts + NumParts); 428 429 NumParts = RoundParts; 430 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 431 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); 432 } 433 434 // The number of parts is a power of 2. Repeatedly bisect the value using 435 // EXTRACT_ELEMENT. 436 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, 437 EVT::getIntegerVT(*DAG.getContext(), 438 ValueVT.getSizeInBits()), 439 Val); 440 441 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 442 for (unsigned i = 0; i < NumParts; i += StepSize) { 443 unsigned ThisBits = StepSize * PartBits / 2; 444 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 445 SDValue &Part0 = Parts[i]; 446 SDValue &Part1 = Parts[i+StepSize/2]; 447 448 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 449 ThisVT, Part0, 450 DAG.getConstant(1, PtrVT)); 451 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 452 ThisVT, Part0, 453 DAG.getConstant(0, PtrVT)); 454 455 if (ThisBits == PartBits && ThisVT != PartVT) { 456 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, 457 PartVT, Part0); 458 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, 459 PartVT, Part1); 460 } 461 } 462 } 463 464 if (TLI.isBigEndian()) 465 std::reverse(Parts, Parts + OrigNumParts); 466 467 return; 468 } 469 470 // Vector ValueVT. 471 if (NumParts == 1) { 472 if (PartVT != ValueVT) { 473 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 474 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); 475 } else { 476 assert(ValueVT.getVectorElementType() == PartVT && 477 ValueVT.getVectorNumElements() == 1 && 478 "Only trivial vector-to-scalar conversions should get here!"); 479 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 480 PartVT, Val, 481 DAG.getConstant(0, PtrVT)); 482 } 483 } 484 485 Parts[0] = Val; 486 return; 487 } 488 489 // Handle a multi-element vector. 490 EVT IntermediateVT, RegisterVT; 491 unsigned NumIntermediates; 492 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 493 IntermediateVT, NumIntermediates, RegisterVT); 494 unsigned NumElements = ValueVT.getVectorNumElements(); 495 496 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 497 NumParts = NumRegs; // Silence a compiler warning. 498 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 499 500 // Split the vector into intermediate operands. 501 SmallVector<SDValue, 8> Ops(NumIntermediates); 502 for (unsigned i = 0; i != NumIntermediates; ++i) { 503 if (IntermediateVT.isVector()) 504 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, 505 IntermediateVT, Val, 506 DAG.getConstant(i * (NumElements / NumIntermediates), 507 PtrVT)); 508 else 509 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 510 IntermediateVT, Val, 511 DAG.getConstant(i, PtrVT)); 512 } 513 514 // Split the intermediate operands into legal parts. 515 if (NumParts == NumIntermediates) { 516 // If the register was not expanded, promote or copy the value, 517 // as appropriate. 518 for (unsigned i = 0; i != NumParts; ++i) 519 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); 520 } else if (NumParts > 0) { 521 // If the intermediate type was expanded, split each the value into 522 // legal parts. 523 assert(NumParts % NumIntermediates == 0 && 524 "Must expand into a divisible number of parts!"); 525 unsigned Factor = NumParts / NumIntermediates; 526 for (unsigned i = 0; i != NumIntermediates; ++i) 527 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT); 528 } 529} 530 531 532void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 533 AA = &aa; 534 GFI = gfi; 535 TD = DAG.getTarget().getTargetData(); 536} 537 538/// clear - Clear out the current SelectionDAG and the associated 539/// state and prepare this SelectionDAGBuilder object to be used 540/// for a new block. This doesn't clear out information about 541/// additional blocks that are needed to complete switch lowering 542/// or PHI node updating; that information is cleared out as it is 543/// consumed. 544void SelectionDAGBuilder::clear() { 545 NodeMap.clear(); 546 PendingLoads.clear(); 547 PendingExports.clear(); 548 EdgeMapping.clear(); 549 DAG.clear(); 550 CurDebugLoc = DebugLoc(); 551 HasTailCall = false; 552} 553 554/// getRoot - Return the current virtual root of the Selection DAG, 555/// flushing any PendingLoad items. This must be done before emitting 556/// a store or any other node that may need to be ordered after any 557/// prior load instructions. 558/// 559SDValue SelectionDAGBuilder::getRoot() { 560 if (PendingLoads.empty()) 561 return DAG.getRoot(); 562 563 if (PendingLoads.size() == 1) { 564 SDValue Root = PendingLoads[0]; 565 DAG.setRoot(Root); 566 PendingLoads.clear(); 567 return Root; 568 } 569 570 // Otherwise, we have to make a token factor node. 571 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 572 &PendingLoads[0], PendingLoads.size()); 573 PendingLoads.clear(); 574 DAG.setRoot(Root); 575 return Root; 576} 577 578/// getControlRoot - Similar to getRoot, but instead of flushing all the 579/// PendingLoad items, flush all the PendingExports items. It is necessary 580/// to do this before emitting a terminator instruction. 581/// 582SDValue SelectionDAGBuilder::getControlRoot() { 583 SDValue Root = DAG.getRoot(); 584 585 if (PendingExports.empty()) 586 return Root; 587 588 // Turn all of the CopyToReg chains into one factored node. 589 if (Root.getOpcode() != ISD::EntryToken) { 590 unsigned i = 0, e = PendingExports.size(); 591 for (; i != e; ++i) { 592 assert(PendingExports[i].getNode()->getNumOperands() > 1); 593 if (PendingExports[i].getNode()->getOperand(0) == Root) 594 break; // Don't add the root if we already indirectly depend on it. 595 } 596 597 if (i == e) 598 PendingExports.push_back(Root); 599 } 600 601 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 602 &PendingExports[0], 603 PendingExports.size()); 604 PendingExports.clear(); 605 DAG.setRoot(Root); 606 return Root; 607} 608 609void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 610 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 611 DAG.AssignOrdering(Node, SDNodeOrder); 612 613 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 614 AssignOrderingToNode(Node->getOperand(I).getNode()); 615} 616 617void SelectionDAGBuilder::visit(const Instruction &I) { 618 // Set up outgoing PHI node register values before emitting the terminator. 619 if (isa<TerminatorInst>(&I)) 620 HandlePHINodesInSuccessorBlocks(I.getParent()); 621 622 CurDebugLoc = I.getDebugLoc(); 623 624 visit(I.getOpcode(), I); 625 626 if (!isa<TerminatorInst>(&I) && !HasTailCall) 627 CopyToExportRegsIfNeeded(&I); 628 629 CurDebugLoc = DebugLoc(); 630} 631 632void SelectionDAGBuilder::visitPHI(const PHINode &) { 633 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 634} 635 636void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 637 // Note: this doesn't use InstVisitor, because it has to work with 638 // ConstantExpr's in addition to instructions. 639 switch (Opcode) { 640 default: llvm_unreachable("Unknown instruction type encountered!"); 641 // Build the switch statement using the Instruction.def file. 642#define HANDLE_INST(NUM, OPCODE, CLASS) \ 643 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 644#include "llvm/Instruction.def" 645 } 646 647 // Assign the ordering to the freshly created DAG nodes. 648 if (NodeMap.count(&I)) { 649 ++SDNodeOrder; 650 AssignOrderingToNode(getValue(&I).getNode()); 651 } 652} 653 654SDValue SelectionDAGBuilder::getValue(const Value *V) { 655 SDValue &N = NodeMap[V]; 656 if (N.getNode()) return N; 657 658 if (const Constant *C = dyn_cast<Constant>(V)) { 659 EVT VT = TLI.getValueType(V->getType(), true); 660 661 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 662 return N = DAG.getConstant(*CI, VT); 663 664 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 665 return N = DAG.getGlobalAddress(GV, VT); 666 667 if (isa<ConstantPointerNull>(C)) 668 return N = DAG.getConstant(0, TLI.getPointerTy()); 669 670 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 671 return N = DAG.getConstantFP(*CFP, VT); 672 673 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 674 return N = DAG.getUNDEF(VT); 675 676 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 677 visit(CE->getOpcode(), *CE); 678 SDValue N1 = NodeMap[V]; 679 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 680 return N1; 681 } 682 683 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 684 SmallVector<SDValue, 4> Constants; 685 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 686 OI != OE; ++OI) { 687 SDNode *Val = getValue(*OI).getNode(); 688 // If the operand is an empty aggregate, there are no values. 689 if (!Val) continue; 690 // Add each leaf value from the operand to the Constants list 691 // to form a flattened list of all the values. 692 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 693 Constants.push_back(SDValue(Val, i)); 694 } 695 696 return DAG.getMergeValues(&Constants[0], Constants.size(), 697 getCurDebugLoc()); 698 } 699 700 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 701 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 702 "Unknown struct or array constant!"); 703 704 SmallVector<EVT, 4> ValueVTs; 705 ComputeValueVTs(TLI, C->getType(), ValueVTs); 706 unsigned NumElts = ValueVTs.size(); 707 if (NumElts == 0) 708 return SDValue(); // empty struct 709 SmallVector<SDValue, 4> Constants(NumElts); 710 for (unsigned i = 0; i != NumElts; ++i) { 711 EVT EltVT = ValueVTs[i]; 712 if (isa<UndefValue>(C)) 713 Constants[i] = DAG.getUNDEF(EltVT); 714 else if (EltVT.isFloatingPoint()) 715 Constants[i] = DAG.getConstantFP(0, EltVT); 716 else 717 Constants[i] = DAG.getConstant(0, EltVT); 718 } 719 720 return DAG.getMergeValues(&Constants[0], NumElts, 721 getCurDebugLoc()); 722 } 723 724 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 725 return DAG.getBlockAddress(BA, VT); 726 727 const VectorType *VecTy = cast<VectorType>(V->getType()); 728 unsigned NumElements = VecTy->getNumElements(); 729 730 // Now that we know the number and type of the elements, get that number of 731 // elements into the Ops array based on what kind of constant it is. 732 SmallVector<SDValue, 16> Ops; 733 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 734 for (unsigned i = 0; i != NumElements; ++i) 735 Ops.push_back(getValue(CP->getOperand(i))); 736 } else { 737 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 738 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 739 740 SDValue Op; 741 if (EltVT.isFloatingPoint()) 742 Op = DAG.getConstantFP(0, EltVT); 743 else 744 Op = DAG.getConstant(0, EltVT); 745 Ops.assign(NumElements, Op); 746 } 747 748 // Create a BUILD_VECTOR node. 749 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 750 VT, &Ops[0], Ops.size()); 751 } 752 753 // If this is a static alloca, generate it as the frameindex instead of 754 // computation. 755 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 756 DenseMap<const AllocaInst*, int>::iterator SI = 757 FuncInfo.StaticAllocaMap.find(AI); 758 if (SI != FuncInfo.StaticAllocaMap.end()) 759 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 760 } 761 762 unsigned InReg = FuncInfo.ValueMap[V]; 763 assert(InReg && "Value not in map!"); 764 765 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 766 SDValue Chain = DAG.getEntryNode(); 767 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); 768} 769 770/// Get the EVTs and ArgFlags collections that represent the legalized return 771/// type of the given function. This does not require a DAG or a return value, 772/// and is suitable for use before any DAGs for the function are constructed. 773static void getReturnInfo(const Type* ReturnType, 774 Attributes attr, SmallVectorImpl<EVT> &OutVTs, 775 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags, 776 const TargetLowering &TLI, 777 SmallVectorImpl<uint64_t> *Offsets = 0) { 778 SmallVector<EVT, 4> ValueVTs; 779 ComputeValueVTs(TLI, ReturnType, ValueVTs); 780 unsigned NumValues = ValueVTs.size(); 781 if (NumValues == 0) return; 782 unsigned Offset = 0; 783 784 for (unsigned j = 0, f = NumValues; j != f; ++j) { 785 EVT VT = ValueVTs[j]; 786 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 787 788 if (attr & Attribute::SExt) 789 ExtendKind = ISD::SIGN_EXTEND; 790 else if (attr & Attribute::ZExt) 791 ExtendKind = ISD::ZERO_EXTEND; 792 793 // FIXME: C calling convention requires the return type to be promoted to 794 // at least 32-bit. But this is not necessary for non-C calling 795 // conventions. The frontend should mark functions whose return values 796 // require promoting with signext or zeroext attributes. 797 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 798 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 799 if (VT.bitsLT(MinVT)) 800 VT = MinVT; 801 } 802 803 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 804 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 805 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 806 PartVT.getTypeForEVT(ReturnType->getContext())); 807 808 // 'inreg' on function refers to return value 809 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 810 if (attr & Attribute::InReg) 811 Flags.setInReg(); 812 813 // Propagate extension type if any 814 if (attr & Attribute::SExt) 815 Flags.setSExt(); 816 else if (attr & Attribute::ZExt) 817 Flags.setZExt(); 818 819 for (unsigned i = 0; i < NumParts; ++i) { 820 OutVTs.push_back(PartVT); 821 OutFlags.push_back(Flags); 822 if (Offsets) 823 { 824 Offsets->push_back(Offset); 825 Offset += PartSize; 826 } 827 } 828 } 829} 830 831void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 832 SDValue Chain = getControlRoot(); 833 SmallVector<ISD::OutputArg, 8> Outs; 834 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 835 836 if (!FLI.CanLowerReturn) { 837 unsigned DemoteReg = FLI.DemoteRegister; 838 const Function *F = I.getParent()->getParent(); 839 840 // Emit a store of the return value through the virtual register. 841 // Leave Outs empty so that LowerReturn won't try to load return 842 // registers the usual way. 843 SmallVector<EVT, 1> PtrValueVTs; 844 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 845 PtrValueVTs); 846 847 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 848 SDValue RetOp = getValue(I.getOperand(0)); 849 850 SmallVector<EVT, 4> ValueVTs; 851 SmallVector<uint64_t, 4> Offsets; 852 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 853 unsigned NumValues = ValueVTs.size(); 854 855 SmallVector<SDValue, 4> Chains(NumValues); 856 EVT PtrVT = PtrValueVTs[0]; 857 for (unsigned i = 0; i != NumValues; ++i) { 858 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr, 859 DAG.getConstant(Offsets[i], PtrVT)); 860 Chains[i] = 861 DAG.getStore(Chain, getCurDebugLoc(), 862 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 863 Add, NULL, Offsets[i], false, false, 0); 864 } 865 866 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 867 MVT::Other, &Chains[0], NumValues); 868 } else if (I.getNumOperands() != 0) { 869 SmallVector<EVT, 4> ValueVTs; 870 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 871 unsigned NumValues = ValueVTs.size(); 872 if (NumValues) { 873 SDValue RetOp = getValue(I.getOperand(0)); 874 for (unsigned j = 0, f = NumValues; j != f; ++j) { 875 EVT VT = ValueVTs[j]; 876 877 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 878 879 const Function *F = I.getParent()->getParent(); 880 if (F->paramHasAttr(0, Attribute::SExt)) 881 ExtendKind = ISD::SIGN_EXTEND; 882 else if (F->paramHasAttr(0, Attribute::ZExt)) 883 ExtendKind = ISD::ZERO_EXTEND; 884 885 // FIXME: C calling convention requires the return type to be promoted 886 // to at least 32-bit. But this is not necessary for non-C calling 887 // conventions. The frontend should mark functions whose return values 888 // require promoting with signext or zeroext attributes. 889 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 890 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 891 if (VT.bitsLT(MinVT)) 892 VT = MinVT; 893 } 894 895 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 896 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 897 SmallVector<SDValue, 4> Parts(NumParts); 898 getCopyToParts(DAG, getCurDebugLoc(), 899 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 900 &Parts[0], NumParts, PartVT, ExtendKind); 901 902 // 'inreg' on function refers to return value 903 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 904 if (F->paramHasAttr(0, Attribute::InReg)) 905 Flags.setInReg(); 906 907 // Propagate extension type if any 908 if (F->paramHasAttr(0, Attribute::SExt)) 909 Flags.setSExt(); 910 else if (F->paramHasAttr(0, Attribute::ZExt)) 911 Flags.setZExt(); 912 913 for (unsigned i = 0; i < NumParts; ++i) 914 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true)); 915 } 916 } 917 } 918 919 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 920 CallingConv::ID CallConv = 921 DAG.getMachineFunction().getFunction()->getCallingConv(); 922 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 923 Outs, getCurDebugLoc(), DAG); 924 925 // Verify that the target's LowerReturn behaved as expected. 926 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 927 "LowerReturn didn't return a valid chain!"); 928 929 // Update the DAG with the new chain value resulting from return lowering. 930 DAG.setRoot(Chain); 931} 932 933/// CopyToExportRegsIfNeeded - If the given value has virtual registers 934/// created for it, emit nodes to copy the value into the virtual 935/// registers. 936void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 937 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 938 if (VMI != FuncInfo.ValueMap.end()) { 939 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 940 CopyValueToVirtualRegister(V, VMI->second); 941 } 942} 943 944/// ExportFromCurrentBlock - If this condition isn't known to be exported from 945/// the current basic block, add it to ValueMap now so that we'll get a 946/// CopyTo/FromReg. 947void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 948 // No need to export constants. 949 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 950 951 // Already exported? 952 if (FuncInfo.isExportedInst(V)) return; 953 954 unsigned Reg = FuncInfo.InitializeRegForValue(V); 955 CopyValueToVirtualRegister(V, Reg); 956} 957 958bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 959 const BasicBlock *FromBB) { 960 // The operands of the setcc have to be in this block. We don't know 961 // how to export them from some other block. 962 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 963 // Can export from current BB. 964 if (VI->getParent() == FromBB) 965 return true; 966 967 // Is already exported, noop. 968 return FuncInfo.isExportedInst(V); 969 } 970 971 // If this is an argument, we can export it if the BB is the entry block or 972 // if it is already exported. 973 if (isa<Argument>(V)) { 974 if (FromBB == &FromBB->getParent()->getEntryBlock()) 975 return true; 976 977 // Otherwise, can only export this if it is already exported. 978 return FuncInfo.isExportedInst(V); 979 } 980 981 // Otherwise, constants can always be exported. 982 return true; 983} 984 985static bool InBlock(const Value *V, const BasicBlock *BB) { 986 if (const Instruction *I = dyn_cast<Instruction>(V)) 987 return I->getParent() == BB; 988 return true; 989} 990 991/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 992/// This function emits a branch and is used at the leaves of an OR or an 993/// AND operator tree. 994/// 995void 996SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 997 MachineBasicBlock *TBB, 998 MachineBasicBlock *FBB, 999 MachineBasicBlock *CurBB, 1000 MachineBasicBlock *SwitchBB) { 1001 const BasicBlock *BB = CurBB->getBasicBlock(); 1002 1003 // If the leaf of the tree is a comparison, merge the condition into 1004 // the caseblock. 1005 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1006 // The operands of the cmp have to be in this block. We don't know 1007 // how to export them from some other block. If this is the first block 1008 // of the sequence, no exporting is needed. 1009 if (CurBB == SwitchBB || 1010 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1011 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1012 ISD::CondCode Condition; 1013 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1014 Condition = getICmpCondCode(IC->getPredicate()); 1015 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1016 Condition = getFCmpCondCode(FC->getPredicate()); 1017 } else { 1018 Condition = ISD::SETEQ; // silence warning. 1019 llvm_unreachable("Unknown compare instruction"); 1020 } 1021 1022 CaseBlock CB(Condition, BOp->getOperand(0), 1023 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1024 SwitchCases.push_back(CB); 1025 return; 1026 } 1027 } 1028 1029 // Create a CaseBlock record representing this branch. 1030 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1031 NULL, TBB, FBB, CurBB); 1032 SwitchCases.push_back(CB); 1033} 1034 1035/// FindMergedConditions - If Cond is an expression like 1036void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1037 MachineBasicBlock *TBB, 1038 MachineBasicBlock *FBB, 1039 MachineBasicBlock *CurBB, 1040 MachineBasicBlock *SwitchBB, 1041 unsigned Opc) { 1042 // If this node is not part of the or/and tree, emit it as a branch. 1043 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1044 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1045 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1046 BOp->getParent() != CurBB->getBasicBlock() || 1047 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1048 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1049 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1050 return; 1051 } 1052 1053 // Create TmpBB after CurBB. 1054 MachineFunction::iterator BBI = CurBB; 1055 MachineFunction &MF = DAG.getMachineFunction(); 1056 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1057 CurBB->getParent()->insert(++BBI, TmpBB); 1058 1059 if (Opc == Instruction::Or) { 1060 // Codegen X | Y as: 1061 // jmp_if_X TBB 1062 // jmp TmpBB 1063 // TmpBB: 1064 // jmp_if_Y TBB 1065 // jmp FBB 1066 // 1067 1068 // Emit the LHS condition. 1069 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1070 1071 // Emit the RHS condition into TmpBB. 1072 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1073 } else { 1074 assert(Opc == Instruction::And && "Unknown merge op!"); 1075 // Codegen X & Y as: 1076 // jmp_if_X TmpBB 1077 // jmp FBB 1078 // TmpBB: 1079 // jmp_if_Y TBB 1080 // jmp FBB 1081 // 1082 // This requires creation of TmpBB after CurBB. 1083 1084 // Emit the LHS condition. 1085 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1086 1087 // Emit the RHS condition into TmpBB. 1088 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1089 } 1090} 1091 1092/// If the set of cases should be emitted as a series of branches, return true. 1093/// If we should emit this as a bunch of and/or'd together conditions, return 1094/// false. 1095bool 1096SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1097 if (Cases.size() != 2) return true; 1098 1099 // If this is two comparisons of the same values or'd or and'd together, they 1100 // will get folded into a single comparison, so don't emit two blocks. 1101 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1102 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1103 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1104 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1105 return false; 1106 } 1107 1108 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1109 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1110 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1111 Cases[0].CC == Cases[1].CC && 1112 isa<Constant>(Cases[0].CmpRHS) && 1113 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1114 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1115 return false; 1116 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1117 return false; 1118 } 1119 1120 return true; 1121} 1122 1123void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1124 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()]; 1125 1126 // Update machine-CFG edges. 1127 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1128 1129 // Figure out which block is immediately after the current one. 1130 MachineBasicBlock *NextBlock = 0; 1131 MachineFunction::iterator BBI = BrMBB; 1132 if (++BBI != FuncInfo.MF->end()) 1133 NextBlock = BBI; 1134 1135 if (I.isUnconditional()) { 1136 // Update machine-CFG edges. 1137 BrMBB->addSuccessor(Succ0MBB); 1138 1139 // If this is not a fall-through branch, emit the branch. 1140 if (Succ0MBB != NextBlock) 1141 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1142 MVT::Other, getControlRoot(), 1143 DAG.getBasicBlock(Succ0MBB))); 1144 1145 return; 1146 } 1147 1148 // If this condition is one of the special cases we handle, do special stuff 1149 // now. 1150 const Value *CondVal = I.getCondition(); 1151 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1152 1153 // If this is a series of conditions that are or'd or and'd together, emit 1154 // this as a sequence of branches instead of setcc's with and/or operations. 1155 // For example, instead of something like: 1156 // cmp A, B 1157 // C = seteq 1158 // cmp D, E 1159 // F = setle 1160 // or C, F 1161 // jnz foo 1162 // Emit: 1163 // cmp A, B 1164 // je foo 1165 // cmp D, E 1166 // jle foo 1167 // 1168 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1169 if (BOp->hasOneUse() && 1170 (BOp->getOpcode() == Instruction::And || 1171 BOp->getOpcode() == Instruction::Or)) { 1172 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1173 BOp->getOpcode()); 1174 // If the compares in later blocks need to use values not currently 1175 // exported from this block, export them now. This block should always 1176 // be the first entry. 1177 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1178 1179 // Allow some cases to be rejected. 1180 if (ShouldEmitAsBranches(SwitchCases)) { 1181 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1182 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1183 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1184 } 1185 1186 // Emit the branch for this block. 1187 visitSwitchCase(SwitchCases[0], BrMBB); 1188 SwitchCases.erase(SwitchCases.begin()); 1189 return; 1190 } 1191 1192 // Okay, we decided not to do this, remove any inserted MBB's and clear 1193 // SwitchCases. 1194 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1195 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1196 1197 SwitchCases.clear(); 1198 } 1199 } 1200 1201 // Create a CaseBlock record representing this branch. 1202 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1203 NULL, Succ0MBB, Succ1MBB, BrMBB); 1204 1205 // Use visitSwitchCase to actually insert the fast branch sequence for this 1206 // cond branch. 1207 visitSwitchCase(CB, BrMBB); 1208} 1209 1210/// visitSwitchCase - Emits the necessary code to represent a single node in 1211/// the binary search tree resulting from lowering a switch instruction. 1212void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1213 MachineBasicBlock *SwitchBB) { 1214 SDValue Cond; 1215 SDValue CondLHS = getValue(CB.CmpLHS); 1216 DebugLoc dl = getCurDebugLoc(); 1217 1218 // Build the setcc now. 1219 if (CB.CmpMHS == NULL) { 1220 // Fold "(X == true)" to X and "(X == false)" to !X to 1221 // handle common cases produced by branch lowering. 1222 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1223 CB.CC == ISD::SETEQ) 1224 Cond = CondLHS; 1225 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1226 CB.CC == ISD::SETEQ) { 1227 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1228 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1229 } else 1230 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1231 } else { 1232 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1233 1234 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1235 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1236 1237 SDValue CmpOp = getValue(CB.CmpMHS); 1238 EVT VT = CmpOp.getValueType(); 1239 1240 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1241 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1242 ISD::SETLE); 1243 } else { 1244 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1245 VT, CmpOp, DAG.getConstant(Low, VT)); 1246 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1247 DAG.getConstant(High-Low, VT), ISD::SETULE); 1248 } 1249 } 1250 1251 // Update successor info 1252 SwitchBB->addSuccessor(CB.TrueBB); 1253 SwitchBB->addSuccessor(CB.FalseBB); 1254 1255 // Set NextBlock to be the MBB immediately after the current one, if any. 1256 // This is used to avoid emitting unnecessary branches to the next block. 1257 MachineBasicBlock *NextBlock = 0; 1258 MachineFunction::iterator BBI = SwitchBB; 1259 if (++BBI != FuncInfo.MF->end()) 1260 NextBlock = BBI; 1261 1262 // If the lhs block is the next block, invert the condition so that we can 1263 // fall through to the lhs instead of the rhs block. 1264 if (CB.TrueBB == NextBlock) { 1265 std::swap(CB.TrueBB, CB.FalseBB); 1266 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1267 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1268 } 1269 1270 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1271 MVT::Other, getControlRoot(), Cond, 1272 DAG.getBasicBlock(CB.TrueBB)); 1273 1274 // If the branch was constant folded, fix up the CFG. 1275 if (BrCond.getOpcode() == ISD::BR) { 1276 SwitchBB->removeSuccessor(CB.FalseBB); 1277 } else { 1278 // Otherwise, go ahead and insert the false branch. 1279 if (BrCond == getControlRoot()) 1280 SwitchBB->removeSuccessor(CB.TrueBB); 1281 1282 if (CB.FalseBB != NextBlock) 1283 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1284 DAG.getBasicBlock(CB.FalseBB)); 1285 } 1286 1287 DAG.setRoot(BrCond); 1288} 1289 1290/// visitJumpTable - Emit JumpTable node in the current MBB 1291void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1292 // Emit the code for the jump table 1293 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1294 EVT PTy = TLI.getPointerTy(); 1295 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1296 JT.Reg, PTy); 1297 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1298 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1299 MVT::Other, Index.getValue(1), 1300 Table, Index); 1301 DAG.setRoot(BrJumpTable); 1302} 1303 1304/// visitJumpTableHeader - This function emits necessary code to produce index 1305/// in the JumpTable from switch case. 1306void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1307 JumpTableHeader &JTH, 1308 MachineBasicBlock *SwitchBB) { 1309 // Subtract the lowest switch case value from the value being switched on and 1310 // conditional branch to default mbb if the result is greater than the 1311 // difference between smallest and largest cases. 1312 SDValue SwitchOp = getValue(JTH.SValue); 1313 EVT VT = SwitchOp.getValueType(); 1314 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1315 DAG.getConstant(JTH.First, VT)); 1316 1317 // The SDNode we just created, which holds the value being switched on minus 1318 // the smallest case value, needs to be copied to a virtual register so it 1319 // can be used as an index into the jump table in a subsequent basic block. 1320 // This value may be smaller or larger than the target's pointer type, and 1321 // therefore require extension or truncating. 1322 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1323 1324 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); 1325 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1326 JumpTableReg, SwitchOp); 1327 JT.Reg = JumpTableReg; 1328 1329 // Emit the range check for the jump table, and branch to the default block 1330 // for the switch statement if the value being switched on exceeds the largest 1331 // case in the switch. 1332 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1333 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1334 DAG.getConstant(JTH.Last-JTH.First,VT), 1335 ISD::SETUGT); 1336 1337 // Set NextBlock to be the MBB immediately after the current one, if any. 1338 // This is used to avoid emitting unnecessary branches to the next block. 1339 MachineBasicBlock *NextBlock = 0; 1340 MachineFunction::iterator BBI = SwitchBB; 1341 1342 if (++BBI != FuncInfo.MF->end()) 1343 NextBlock = BBI; 1344 1345 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1346 MVT::Other, CopyTo, CMP, 1347 DAG.getBasicBlock(JT.Default)); 1348 1349 if (JT.MBB != NextBlock) 1350 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1351 DAG.getBasicBlock(JT.MBB)); 1352 1353 DAG.setRoot(BrCond); 1354} 1355 1356/// visitBitTestHeader - This function emits necessary code to produce value 1357/// suitable for "bit tests" 1358void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1359 MachineBasicBlock *SwitchBB) { 1360 // Subtract the minimum value 1361 SDValue SwitchOp = getValue(B.SValue); 1362 EVT VT = SwitchOp.getValueType(); 1363 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1364 DAG.getConstant(B.First, VT)); 1365 1366 // Check range 1367 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1368 TLI.getSetCCResultType(Sub.getValueType()), 1369 Sub, DAG.getConstant(B.Range, VT), 1370 ISD::SETUGT); 1371 1372 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1373 TLI.getPointerTy()); 1374 1375 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); 1376 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1377 B.Reg, ShiftOp); 1378 1379 // Set NextBlock to be the MBB immediately after the current one, if any. 1380 // This is used to avoid emitting unnecessary branches to the next block. 1381 MachineBasicBlock *NextBlock = 0; 1382 MachineFunction::iterator BBI = SwitchBB; 1383 if (++BBI != FuncInfo.MF->end()) 1384 NextBlock = BBI; 1385 1386 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1387 1388 SwitchBB->addSuccessor(B.Default); 1389 SwitchBB->addSuccessor(MBB); 1390 1391 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1392 MVT::Other, CopyTo, RangeCmp, 1393 DAG.getBasicBlock(B.Default)); 1394 1395 if (MBB != NextBlock) 1396 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1397 DAG.getBasicBlock(MBB)); 1398 1399 DAG.setRoot(BrRange); 1400} 1401 1402/// visitBitTestCase - this function produces one "bit test" 1403void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1404 unsigned Reg, 1405 BitTestCase &B, 1406 MachineBasicBlock *SwitchBB) { 1407 // Make desired shift 1408 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1409 TLI.getPointerTy()); 1410 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1411 TLI.getPointerTy(), 1412 DAG.getConstant(1, TLI.getPointerTy()), 1413 ShiftOp); 1414 1415 // Emit bit tests and jumps 1416 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1417 TLI.getPointerTy(), SwitchVal, 1418 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1419 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), 1420 TLI.getSetCCResultType(AndOp.getValueType()), 1421 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1422 ISD::SETNE); 1423 1424 SwitchBB->addSuccessor(B.TargetBB); 1425 SwitchBB->addSuccessor(NextMBB); 1426 1427 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1428 MVT::Other, getControlRoot(), 1429 AndCmp, DAG.getBasicBlock(B.TargetBB)); 1430 1431 // Set NextBlock to be the MBB immediately after the current one, if any. 1432 // This is used to avoid emitting unnecessary branches to the next block. 1433 MachineBasicBlock *NextBlock = 0; 1434 MachineFunction::iterator BBI = SwitchBB; 1435 if (++BBI != FuncInfo.MF->end()) 1436 NextBlock = BBI; 1437 1438 if (NextMBB != NextBlock) 1439 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1440 DAG.getBasicBlock(NextMBB)); 1441 1442 DAG.setRoot(BrAnd); 1443} 1444 1445void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1446 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()]; 1447 1448 // Retrieve successors. 1449 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1450 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1451 1452 const Value *Callee(I.getCalledValue()); 1453 if (isa<InlineAsm>(Callee)) 1454 visitInlineAsm(&I); 1455 else 1456 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1457 1458 // If the value of the invoke is used outside of its defining block, make it 1459 // available as a virtual register. 1460 CopyToExportRegsIfNeeded(&I); 1461 1462 // Update successor info 1463 InvokeMBB->addSuccessor(Return); 1464 InvokeMBB->addSuccessor(LandingPad); 1465 1466 // Drop into normal successor. 1467 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1468 MVT::Other, getControlRoot(), 1469 DAG.getBasicBlock(Return))); 1470} 1471 1472void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1473} 1474 1475/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1476/// small case ranges). 1477bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1478 CaseRecVector& WorkList, 1479 const Value* SV, 1480 MachineBasicBlock *Default, 1481 MachineBasicBlock *SwitchBB) { 1482 Case& BackCase = *(CR.Range.second-1); 1483 1484 // Size is the number of Cases represented by this range. 1485 size_t Size = CR.Range.second - CR.Range.first; 1486 if (Size > 3) 1487 return false; 1488 1489 // Get the MachineFunction which holds the current MBB. This is used when 1490 // inserting any additional MBBs necessary to represent the switch. 1491 MachineFunction *CurMF = FuncInfo.MF; 1492 1493 // Figure out which block is immediately after the current one. 1494 MachineBasicBlock *NextBlock = 0; 1495 MachineFunction::iterator BBI = CR.CaseBB; 1496 1497 if (++BBI != FuncInfo.MF->end()) 1498 NextBlock = BBI; 1499 1500 // TODO: If any two of the cases has the same destination, and if one value 1501 // is the same as the other, but has one bit unset that the other has set, 1502 // use bit manipulation to do two compares at once. For example: 1503 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1504 1505 // Rearrange the case blocks so that the last one falls through if possible. 1506 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1507 // The last case block won't fall through into 'NextBlock' if we emit the 1508 // branches in this order. See if rearranging a case value would help. 1509 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1510 if (I->BB == NextBlock) { 1511 std::swap(*I, BackCase); 1512 break; 1513 } 1514 } 1515 } 1516 1517 // Create a CaseBlock record representing a conditional branch to 1518 // the Case's target mbb if the value being switched on SV is equal 1519 // to C. 1520 MachineBasicBlock *CurBlock = CR.CaseBB; 1521 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1522 MachineBasicBlock *FallThrough; 1523 if (I != E-1) { 1524 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1525 CurMF->insert(BBI, FallThrough); 1526 1527 // Put SV in a virtual register to make it available from the new blocks. 1528 ExportFromCurrentBlock(SV); 1529 } else { 1530 // If the last case doesn't match, go to the default block. 1531 FallThrough = Default; 1532 } 1533 1534 const Value *RHS, *LHS, *MHS; 1535 ISD::CondCode CC; 1536 if (I->High == I->Low) { 1537 // This is just small small case range :) containing exactly 1 case 1538 CC = ISD::SETEQ; 1539 LHS = SV; RHS = I->High; MHS = NULL; 1540 } else { 1541 CC = ISD::SETLE; 1542 LHS = I->Low; MHS = SV; RHS = I->High; 1543 } 1544 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1545 1546 // If emitting the first comparison, just call visitSwitchCase to emit the 1547 // code into the current block. Otherwise, push the CaseBlock onto the 1548 // vector to be later processed by SDISel, and insert the node's MBB 1549 // before the next MBB. 1550 if (CurBlock == SwitchBB) 1551 visitSwitchCase(CB, SwitchBB); 1552 else 1553 SwitchCases.push_back(CB); 1554 1555 CurBlock = FallThrough; 1556 } 1557 1558 return true; 1559} 1560 1561static inline bool areJTsAllowed(const TargetLowering &TLI) { 1562 return !DisableJumpTables && 1563 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1564 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1565} 1566 1567static APInt ComputeRange(const APInt &First, const APInt &Last) { 1568 APInt LastExt(Last), FirstExt(First); 1569 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1570 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1571 return (LastExt - FirstExt + 1ULL); 1572} 1573 1574/// handleJTSwitchCase - Emit jumptable for current switch case range 1575bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1576 CaseRecVector& WorkList, 1577 const Value* SV, 1578 MachineBasicBlock* Default, 1579 MachineBasicBlock *SwitchBB) { 1580 Case& FrontCase = *CR.Range.first; 1581 Case& BackCase = *(CR.Range.second-1); 1582 1583 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1584 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1585 1586 APInt TSize(First.getBitWidth(), 0); 1587 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1588 I!=E; ++I) 1589 TSize += I->size(); 1590 1591 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1592 return false; 1593 1594 APInt Range = ComputeRange(First, Last); 1595 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1596 if (Density < 0.4) 1597 return false; 1598 1599 DEBUG(dbgs() << "Lowering jump table\n" 1600 << "First entry: " << First << ". Last entry: " << Last << '\n' 1601 << "Range: " << Range 1602 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1603 1604 // Get the MachineFunction which holds the current MBB. This is used when 1605 // inserting any additional MBBs necessary to represent the switch. 1606 MachineFunction *CurMF = FuncInfo.MF; 1607 1608 // Figure out which block is immediately after the current one. 1609 MachineFunction::iterator BBI = CR.CaseBB; 1610 ++BBI; 1611 1612 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1613 1614 // Create a new basic block to hold the code for loading the address 1615 // of the jump table, and jumping to it. Update successor information; 1616 // we will either branch to the default case for the switch, or the jump 1617 // table. 1618 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1619 CurMF->insert(BBI, JumpTableBB); 1620 CR.CaseBB->addSuccessor(Default); 1621 CR.CaseBB->addSuccessor(JumpTableBB); 1622 1623 // Build a vector of destination BBs, corresponding to each target 1624 // of the jump table. If the value of the jump table slot corresponds to 1625 // a case statement, push the case's BB onto the vector, otherwise, push 1626 // the default BB. 1627 std::vector<MachineBasicBlock*> DestBBs; 1628 APInt TEI = First; 1629 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1630 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1631 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1632 1633 if (Low.sle(TEI) && TEI.sle(High)) { 1634 DestBBs.push_back(I->BB); 1635 if (TEI==High) 1636 ++I; 1637 } else { 1638 DestBBs.push_back(Default); 1639 } 1640 } 1641 1642 // Update successor info. Add one edge to each unique successor. 1643 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1644 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1645 E = DestBBs.end(); I != E; ++I) { 1646 if (!SuccsHandled[(*I)->getNumber()]) { 1647 SuccsHandled[(*I)->getNumber()] = true; 1648 JumpTableBB->addSuccessor(*I); 1649 } 1650 } 1651 1652 // Create a jump table index for this jump table. 1653 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1654 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1655 ->createJumpTableIndex(DestBBs); 1656 1657 // Set the jump table information so that we can codegen it as a second 1658 // MachineBasicBlock 1659 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1660 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1661 if (CR.CaseBB == SwitchBB) 1662 visitJumpTableHeader(JT, JTH, SwitchBB); 1663 1664 JTCases.push_back(JumpTableBlock(JTH, JT)); 1665 1666 return true; 1667} 1668 1669/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1670/// 2 subtrees. 1671bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1672 CaseRecVector& WorkList, 1673 const Value* SV, 1674 MachineBasicBlock *Default, 1675 MachineBasicBlock *SwitchBB) { 1676 // Get the MachineFunction which holds the current MBB. This is used when 1677 // inserting any additional MBBs necessary to represent the switch. 1678 MachineFunction *CurMF = FuncInfo.MF; 1679 1680 // Figure out which block is immediately after the current one. 1681 MachineFunction::iterator BBI = CR.CaseBB; 1682 ++BBI; 1683 1684 Case& FrontCase = *CR.Range.first; 1685 Case& BackCase = *(CR.Range.second-1); 1686 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1687 1688 // Size is the number of Cases represented by this range. 1689 unsigned Size = CR.Range.second - CR.Range.first; 1690 1691 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1692 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1693 double FMetric = 0; 1694 CaseItr Pivot = CR.Range.first + Size/2; 1695 1696 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1697 // (heuristically) allow us to emit JumpTable's later. 1698 APInt TSize(First.getBitWidth(), 0); 1699 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1700 I!=E; ++I) 1701 TSize += I->size(); 1702 1703 APInt LSize = FrontCase.size(); 1704 APInt RSize = TSize-LSize; 1705 DEBUG(dbgs() << "Selecting best pivot: \n" 1706 << "First: " << First << ", Last: " << Last <<'\n' 1707 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1708 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1709 J!=E; ++I, ++J) { 1710 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1711 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1712 APInt Range = ComputeRange(LEnd, RBegin); 1713 assert((Range - 2ULL).isNonNegative() && 1714 "Invalid case distance"); 1715 double LDensity = (double)LSize.roundToDouble() / 1716 (LEnd - First + 1ULL).roundToDouble(); 1717 double RDensity = (double)RSize.roundToDouble() / 1718 (Last - RBegin + 1ULL).roundToDouble(); 1719 double Metric = Range.logBase2()*(LDensity+RDensity); 1720 // Should always split in some non-trivial place 1721 DEBUG(dbgs() <<"=>Step\n" 1722 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1723 << "LDensity: " << LDensity 1724 << ", RDensity: " << RDensity << '\n' 1725 << "Metric: " << Metric << '\n'); 1726 if (FMetric < Metric) { 1727 Pivot = J; 1728 FMetric = Metric; 1729 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1730 } 1731 1732 LSize += J->size(); 1733 RSize -= J->size(); 1734 } 1735 if (areJTsAllowed(TLI)) { 1736 // If our case is dense we *really* should handle it earlier! 1737 assert((FMetric > 0) && "Should handle dense range earlier!"); 1738 } else { 1739 Pivot = CR.Range.first + Size/2; 1740 } 1741 1742 CaseRange LHSR(CR.Range.first, Pivot); 1743 CaseRange RHSR(Pivot, CR.Range.second); 1744 Constant *C = Pivot->Low; 1745 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1746 1747 // We know that we branch to the LHS if the Value being switched on is 1748 // less than the Pivot value, C. We use this to optimize our binary 1749 // tree a bit, by recognizing that if SV is greater than or equal to the 1750 // LHS's Case Value, and that Case Value is exactly one less than the 1751 // Pivot's Value, then we can branch directly to the LHS's Target, 1752 // rather than creating a leaf node for it. 1753 if ((LHSR.second - LHSR.first) == 1 && 1754 LHSR.first->High == CR.GE && 1755 cast<ConstantInt>(C)->getValue() == 1756 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1757 TrueBB = LHSR.first->BB; 1758 } else { 1759 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1760 CurMF->insert(BBI, TrueBB); 1761 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1762 1763 // Put SV in a virtual register to make it available from the new blocks. 1764 ExportFromCurrentBlock(SV); 1765 } 1766 1767 // Similar to the optimization above, if the Value being switched on is 1768 // known to be less than the Constant CR.LT, and the current Case Value 1769 // is CR.LT - 1, then we can branch directly to the target block for 1770 // the current Case Value, rather than emitting a RHS leaf node for it. 1771 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 1772 cast<ConstantInt>(RHSR.first->Low)->getValue() == 1773 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 1774 FalseBB = RHSR.first->BB; 1775 } else { 1776 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1777 CurMF->insert(BBI, FalseBB); 1778 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 1779 1780 // Put SV in a virtual register to make it available from the new blocks. 1781 ExportFromCurrentBlock(SV); 1782 } 1783 1784 // Create a CaseBlock record representing a conditional branch to 1785 // the LHS node if the value being switched on SV is less than C. 1786 // Otherwise, branch to LHS. 1787 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 1788 1789 if (CR.CaseBB == SwitchBB) 1790 visitSwitchCase(CB, SwitchBB); 1791 else 1792 SwitchCases.push_back(CB); 1793 1794 return true; 1795} 1796 1797/// handleBitTestsSwitchCase - if current case range has few destination and 1798/// range span less, than machine word bitwidth, encode case range into series 1799/// of masks and emit bit tests with these masks. 1800bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 1801 CaseRecVector& WorkList, 1802 const Value* SV, 1803 MachineBasicBlock* Default, 1804 MachineBasicBlock *SwitchBB){ 1805 EVT PTy = TLI.getPointerTy(); 1806 unsigned IntPtrBits = PTy.getSizeInBits(); 1807 1808 Case& FrontCase = *CR.Range.first; 1809 Case& BackCase = *(CR.Range.second-1); 1810 1811 // Get the MachineFunction which holds the current MBB. This is used when 1812 // inserting any additional MBBs necessary to represent the switch. 1813 MachineFunction *CurMF = FuncInfo.MF; 1814 1815 // If target does not have legal shift left, do not emit bit tests at all. 1816 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 1817 return false; 1818 1819 size_t numCmps = 0; 1820 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1821 I!=E; ++I) { 1822 // Single case counts one, case range - two. 1823 numCmps += (I->Low == I->High ? 1 : 2); 1824 } 1825 1826 // Count unique destinations 1827 SmallSet<MachineBasicBlock*, 4> Dests; 1828 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1829 Dests.insert(I->BB); 1830 if (Dests.size() > 3) 1831 // Don't bother the code below, if there are too much unique destinations 1832 return false; 1833 } 1834 DEBUG(dbgs() << "Total number of unique destinations: " 1835 << Dests.size() << '\n' 1836 << "Total number of comparisons: " << numCmps << '\n'); 1837 1838 // Compute span of values. 1839 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 1840 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 1841 APInt cmpRange = maxValue - minValue; 1842 1843 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 1844 << "Low bound: " << minValue << '\n' 1845 << "High bound: " << maxValue << '\n'); 1846 1847 if (cmpRange.uge(IntPtrBits) || 1848 (!(Dests.size() == 1 && numCmps >= 3) && 1849 !(Dests.size() == 2 && numCmps >= 5) && 1850 !(Dests.size() >= 3 && numCmps >= 6))) 1851 return false; 1852 1853 DEBUG(dbgs() << "Emitting bit tests\n"); 1854 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 1855 1856 // Optimize the case where all the case values fit in a 1857 // word without having to subtract minValue. In this case, 1858 // we can optimize away the subtraction. 1859 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 1860 cmpRange = maxValue; 1861 } else { 1862 lowBound = minValue; 1863 } 1864 1865 CaseBitsVector CasesBits; 1866 unsigned i, count = 0; 1867 1868 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 1869 MachineBasicBlock* Dest = I->BB; 1870 for (i = 0; i < count; ++i) 1871 if (Dest == CasesBits[i].BB) 1872 break; 1873 1874 if (i == count) { 1875 assert((count < 3) && "Too much destinations to test!"); 1876 CasesBits.push_back(CaseBits(0, Dest, 0)); 1877 count++; 1878 } 1879 1880 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 1881 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 1882 1883 uint64_t lo = (lowValue - lowBound).getZExtValue(); 1884 uint64_t hi = (highValue - lowBound).getZExtValue(); 1885 1886 for (uint64_t j = lo; j <= hi; j++) { 1887 CasesBits[i].Mask |= 1ULL << j; 1888 CasesBits[i].Bits++; 1889 } 1890 1891 } 1892 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 1893 1894 BitTestInfo BTC; 1895 1896 // Figure out which block is immediately after the current one. 1897 MachineFunction::iterator BBI = CR.CaseBB; 1898 ++BBI; 1899 1900 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1901 1902 DEBUG(dbgs() << "Cases:\n"); 1903 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 1904 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 1905 << ", Bits: " << CasesBits[i].Bits 1906 << ", BB: " << CasesBits[i].BB << '\n'); 1907 1908 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1909 CurMF->insert(BBI, CaseBB); 1910 BTC.push_back(BitTestCase(CasesBits[i].Mask, 1911 CaseBB, 1912 CasesBits[i].BB)); 1913 1914 // Put SV in a virtual register to make it available from the new blocks. 1915 ExportFromCurrentBlock(SV); 1916 } 1917 1918 BitTestBlock BTB(lowBound, cmpRange, SV, 1919 -1U, (CR.CaseBB == SwitchBB), 1920 CR.CaseBB, Default, BTC); 1921 1922 if (CR.CaseBB == SwitchBB) 1923 visitBitTestHeader(BTB, SwitchBB); 1924 1925 BitTestCases.push_back(BTB); 1926 1927 return true; 1928} 1929 1930/// Clusterify - Transform simple list of Cases into list of CaseRange's 1931size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 1932 const SwitchInst& SI) { 1933 size_t numCmps = 0; 1934 1935 // Start with "simple" cases 1936 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 1937 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 1938 Cases.push_back(Case(SI.getSuccessorValue(i), 1939 SI.getSuccessorValue(i), 1940 SMBB)); 1941 } 1942 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 1943 1944 // Merge case into clusters 1945 if (Cases.size() >= 2) 1946 // Must recompute end() each iteration because it may be 1947 // invalidated by erase if we hold on to it 1948 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 1949 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 1950 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 1951 MachineBasicBlock* nextBB = J->BB; 1952 MachineBasicBlock* currentBB = I->BB; 1953 1954 // If the two neighboring cases go to the same destination, merge them 1955 // into a single case. 1956 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 1957 I->High = J->High; 1958 J = Cases.erase(J); 1959 } else { 1960 I = J++; 1961 } 1962 } 1963 1964 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 1965 if (I->Low != I->High) 1966 // A range counts double, since it requires two compares. 1967 ++numCmps; 1968 } 1969 1970 return numCmps; 1971} 1972 1973void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 1974 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()]; 1975 1976 // Figure out which block is immediately after the current one. 1977 MachineBasicBlock *NextBlock = 0; 1978 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 1979 1980 // If there is only the default destination, branch to it if it is not the 1981 // next basic block. Otherwise, just fall through. 1982 if (SI.getNumOperands() == 2) { 1983 // Update machine-CFG edges. 1984 1985 // If this is not a fall-through branch, emit the branch. 1986 SwitchMBB->addSuccessor(Default); 1987 if (Default != NextBlock) 1988 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1989 MVT::Other, getControlRoot(), 1990 DAG.getBasicBlock(Default))); 1991 1992 return; 1993 } 1994 1995 // If there are any non-default case statements, create a vector of Cases 1996 // representing each one, and sort the vector so that we can efficiently 1997 // create a binary search tree from them. 1998 CaseVector Cases; 1999 size_t numCmps = Clusterify(Cases, SI); 2000 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2001 << ". Total compares: " << numCmps << '\n'); 2002 numCmps = 0; 2003 2004 // Get the Value to be switched on and default basic blocks, which will be 2005 // inserted into CaseBlock records, representing basic blocks in the binary 2006 // search tree. 2007 const Value *SV = SI.getOperand(0); 2008 2009 // Push the initial CaseRec onto the worklist 2010 CaseRecVector WorkList; 2011 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2012 CaseRange(Cases.begin(),Cases.end()))); 2013 2014 while (!WorkList.empty()) { 2015 // Grab a record representing a case range to process off the worklist 2016 CaseRec CR = WorkList.back(); 2017 WorkList.pop_back(); 2018 2019 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2020 continue; 2021 2022 // If the range has few cases (two or less) emit a series of specific 2023 // tests. 2024 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2025 continue; 2026 2027 // If the switch has more than 5 blocks, and at least 40% dense, and the 2028 // target supports indirect branches, then emit a jump table rather than 2029 // lowering the switch to a binary tree of conditional branches. 2030 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2031 continue; 2032 2033 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2034 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2035 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2036 } 2037} 2038 2039void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2040 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()]; 2041 2042 // Update machine-CFG edges with unique successors. 2043 SmallVector<BasicBlock*, 32> succs; 2044 succs.reserve(I.getNumSuccessors()); 2045 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2046 succs.push_back(I.getSuccessor(i)); 2047 array_pod_sort(succs.begin(), succs.end()); 2048 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2049 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2050 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2051 2052 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2053 MVT::Other, getControlRoot(), 2054 getValue(I.getAddress()))); 2055} 2056 2057void SelectionDAGBuilder::visitFSub(const User &I) { 2058 // -0.0 - X --> fneg 2059 const Type *Ty = I.getType(); 2060 if (Ty->isVectorTy()) { 2061 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2062 const VectorType *DestTy = cast<VectorType>(I.getType()); 2063 const Type *ElTy = DestTy->getElementType(); 2064 unsigned VL = DestTy->getNumElements(); 2065 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2066 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2067 if (CV == CNZ) { 2068 SDValue Op2 = getValue(I.getOperand(1)); 2069 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2070 Op2.getValueType(), Op2)); 2071 return; 2072 } 2073 } 2074 } 2075 2076 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2077 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2078 SDValue Op2 = getValue(I.getOperand(1)); 2079 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2080 Op2.getValueType(), Op2)); 2081 return; 2082 } 2083 2084 visitBinary(I, ISD::FSUB); 2085} 2086 2087void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2088 SDValue Op1 = getValue(I.getOperand(0)); 2089 SDValue Op2 = getValue(I.getOperand(1)); 2090 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2091 Op1.getValueType(), Op1, Op2)); 2092} 2093 2094void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2095 SDValue Op1 = getValue(I.getOperand(0)); 2096 SDValue Op2 = getValue(I.getOperand(1)); 2097 if (!I.getType()->isVectorTy() && 2098 Op2.getValueType() != TLI.getShiftAmountTy()) { 2099 // If the operand is smaller than the shift count type, promote it. 2100 EVT PTy = TLI.getPointerTy(); 2101 EVT STy = TLI.getShiftAmountTy(); 2102 if (STy.bitsGT(Op2.getValueType())) 2103 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2104 TLI.getShiftAmountTy(), Op2); 2105 // If the operand is larger than the shift count type but the shift 2106 // count type has enough bits to represent any shift value, truncate 2107 // it now. This is a common case and it exposes the truncate to 2108 // optimization early. 2109 else if (STy.getSizeInBits() >= 2110 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2111 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2112 TLI.getShiftAmountTy(), Op2); 2113 // Otherwise we'll need to temporarily settle for some other 2114 // convenient type; type legalization will make adjustments as 2115 // needed. 2116 else if (PTy.bitsLT(Op2.getValueType())) 2117 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2118 TLI.getPointerTy(), Op2); 2119 else if (PTy.bitsGT(Op2.getValueType())) 2120 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2121 TLI.getPointerTy(), Op2); 2122 } 2123 2124 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2125 Op1.getValueType(), Op1, Op2)); 2126} 2127 2128void SelectionDAGBuilder::visitICmp(const User &I) { 2129 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2130 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2131 predicate = IC->getPredicate(); 2132 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2133 predicate = ICmpInst::Predicate(IC->getPredicate()); 2134 SDValue Op1 = getValue(I.getOperand(0)); 2135 SDValue Op2 = getValue(I.getOperand(1)); 2136 ISD::CondCode Opcode = getICmpCondCode(predicate); 2137 2138 EVT DestVT = TLI.getValueType(I.getType()); 2139 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2140} 2141 2142void SelectionDAGBuilder::visitFCmp(const User &I) { 2143 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2144 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2145 predicate = FC->getPredicate(); 2146 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2147 predicate = FCmpInst::Predicate(FC->getPredicate()); 2148 SDValue Op1 = getValue(I.getOperand(0)); 2149 SDValue Op2 = getValue(I.getOperand(1)); 2150 ISD::CondCode Condition = getFCmpCondCode(predicate); 2151 EVT DestVT = TLI.getValueType(I.getType()); 2152 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2153} 2154 2155void SelectionDAGBuilder::visitSelect(const User &I) { 2156 SmallVector<EVT, 4> ValueVTs; 2157 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2158 unsigned NumValues = ValueVTs.size(); 2159 if (NumValues == 0) return; 2160 2161 SmallVector<SDValue, 4> Values(NumValues); 2162 SDValue Cond = getValue(I.getOperand(0)); 2163 SDValue TrueVal = getValue(I.getOperand(1)); 2164 SDValue FalseVal = getValue(I.getOperand(2)); 2165 2166 for (unsigned i = 0; i != NumValues; ++i) 2167 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2168 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2169 Cond, 2170 SDValue(TrueVal.getNode(), 2171 TrueVal.getResNo() + i), 2172 SDValue(FalseVal.getNode(), 2173 FalseVal.getResNo() + i)); 2174 2175 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2176 DAG.getVTList(&ValueVTs[0], NumValues), 2177 &Values[0], NumValues)); 2178} 2179 2180void SelectionDAGBuilder::visitTrunc(const User &I) { 2181 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2182 SDValue N = getValue(I.getOperand(0)); 2183 EVT DestVT = TLI.getValueType(I.getType()); 2184 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2185} 2186 2187void SelectionDAGBuilder::visitZExt(const User &I) { 2188 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2189 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2190 SDValue N = getValue(I.getOperand(0)); 2191 EVT DestVT = TLI.getValueType(I.getType()); 2192 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2193} 2194 2195void SelectionDAGBuilder::visitSExt(const User &I) { 2196 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2197 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2198 SDValue N = getValue(I.getOperand(0)); 2199 EVT DestVT = TLI.getValueType(I.getType()); 2200 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2201} 2202 2203void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2204 // FPTrunc is never a no-op cast, no need to check 2205 SDValue N = getValue(I.getOperand(0)); 2206 EVT DestVT = TLI.getValueType(I.getType()); 2207 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2208 DestVT, N, DAG.getIntPtrConstant(0))); 2209} 2210 2211void SelectionDAGBuilder::visitFPExt(const User &I){ 2212 // FPTrunc is never a no-op cast, no need to check 2213 SDValue N = getValue(I.getOperand(0)); 2214 EVT DestVT = TLI.getValueType(I.getType()); 2215 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2216} 2217 2218void SelectionDAGBuilder::visitFPToUI(const User &I) { 2219 // FPToUI is never a no-op cast, no need to check 2220 SDValue N = getValue(I.getOperand(0)); 2221 EVT DestVT = TLI.getValueType(I.getType()); 2222 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2223} 2224 2225void SelectionDAGBuilder::visitFPToSI(const User &I) { 2226 // FPToSI is never a no-op cast, no need to check 2227 SDValue N = getValue(I.getOperand(0)); 2228 EVT DestVT = TLI.getValueType(I.getType()); 2229 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2230} 2231 2232void SelectionDAGBuilder::visitUIToFP(const User &I) { 2233 // UIToFP is never a no-op cast, no need to check 2234 SDValue N = getValue(I.getOperand(0)); 2235 EVT DestVT = TLI.getValueType(I.getType()); 2236 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2237} 2238 2239void SelectionDAGBuilder::visitSIToFP(const User &I){ 2240 // SIToFP is never a no-op cast, no need to check 2241 SDValue N = getValue(I.getOperand(0)); 2242 EVT DestVT = TLI.getValueType(I.getType()); 2243 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2244} 2245 2246void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2247 // What to do depends on the size of the integer and the size of the pointer. 2248 // We can either truncate, zero extend, or no-op, accordingly. 2249 SDValue N = getValue(I.getOperand(0)); 2250 EVT SrcVT = N.getValueType(); 2251 EVT DestVT = TLI.getValueType(I.getType()); 2252 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2253} 2254 2255void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2256 // What to do depends on the size of the integer and the size of the pointer. 2257 // We can either truncate, zero extend, or no-op, accordingly. 2258 SDValue N = getValue(I.getOperand(0)); 2259 EVT SrcVT = N.getValueType(); 2260 EVT DestVT = TLI.getValueType(I.getType()); 2261 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2262} 2263 2264void SelectionDAGBuilder::visitBitCast(const User &I) { 2265 SDValue N = getValue(I.getOperand(0)); 2266 EVT DestVT = TLI.getValueType(I.getType()); 2267 2268 // BitCast assures us that source and destination are the same size so this is 2269 // either a BIT_CONVERT or a no-op. 2270 if (DestVT != N.getValueType()) 2271 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2272 DestVT, N)); // convert types. 2273 else 2274 setValue(&I, N); // noop cast. 2275} 2276 2277void SelectionDAGBuilder::visitInsertElement(const User &I) { 2278 SDValue InVec = getValue(I.getOperand(0)); 2279 SDValue InVal = getValue(I.getOperand(1)); 2280 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2281 TLI.getPointerTy(), 2282 getValue(I.getOperand(2))); 2283 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2284 TLI.getValueType(I.getType()), 2285 InVec, InVal, InIdx)); 2286} 2287 2288void SelectionDAGBuilder::visitExtractElement(const User &I) { 2289 SDValue InVec = getValue(I.getOperand(0)); 2290 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2291 TLI.getPointerTy(), 2292 getValue(I.getOperand(1))); 2293 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2294 TLI.getValueType(I.getType()), InVec, InIdx)); 2295} 2296 2297// Utility for visitShuffleVector - Returns true if the mask is mask starting 2298// from SIndx and increasing to the element length (undefs are allowed). 2299static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2300 unsigned MaskNumElts = Mask.size(); 2301 for (unsigned i = 0; i != MaskNumElts; ++i) 2302 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2303 return false; 2304 return true; 2305} 2306 2307void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2308 SmallVector<int, 8> Mask; 2309 SDValue Src1 = getValue(I.getOperand(0)); 2310 SDValue Src2 = getValue(I.getOperand(1)); 2311 2312 // Convert the ConstantVector mask operand into an array of ints, with -1 2313 // representing undef values. 2314 SmallVector<Constant*, 8> MaskElts; 2315 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2316 unsigned MaskNumElts = MaskElts.size(); 2317 for (unsigned i = 0; i != MaskNumElts; ++i) { 2318 if (isa<UndefValue>(MaskElts[i])) 2319 Mask.push_back(-1); 2320 else 2321 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2322 } 2323 2324 EVT VT = TLI.getValueType(I.getType()); 2325 EVT SrcVT = Src1.getValueType(); 2326 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2327 2328 if (SrcNumElts == MaskNumElts) { 2329 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2330 &Mask[0])); 2331 return; 2332 } 2333 2334 // Normalize the shuffle vector since mask and vector length don't match. 2335 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2336 // Mask is longer than the source vectors and is a multiple of the source 2337 // vectors. We can use concatenate vector to make the mask and vectors 2338 // lengths match. 2339 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2340 // The shuffle is concatenating two vectors together. 2341 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2342 VT, Src1, Src2)); 2343 return; 2344 } 2345 2346 // Pad both vectors with undefs to make them the same length as the mask. 2347 unsigned NumConcat = MaskNumElts / SrcNumElts; 2348 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2349 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2350 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2351 2352 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2353 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2354 MOps1[0] = Src1; 2355 MOps2[0] = Src2; 2356 2357 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2358 getCurDebugLoc(), VT, 2359 &MOps1[0], NumConcat); 2360 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2361 getCurDebugLoc(), VT, 2362 &MOps2[0], NumConcat); 2363 2364 // Readjust mask for new input vector length. 2365 SmallVector<int, 8> MappedOps; 2366 for (unsigned i = 0; i != MaskNumElts; ++i) { 2367 int Idx = Mask[i]; 2368 if (Idx < (int)SrcNumElts) 2369 MappedOps.push_back(Idx); 2370 else 2371 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2372 } 2373 2374 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2375 &MappedOps[0])); 2376 return; 2377 } 2378 2379 if (SrcNumElts > MaskNumElts) { 2380 // Analyze the access pattern of the vector to see if we can extract 2381 // two subvectors and do the shuffle. The analysis is done by calculating 2382 // the range of elements the mask access on both vectors. 2383 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2384 int MaxRange[2] = {-1, -1}; 2385 2386 for (unsigned i = 0; i != MaskNumElts; ++i) { 2387 int Idx = Mask[i]; 2388 int Input = 0; 2389 if (Idx < 0) 2390 continue; 2391 2392 if (Idx >= (int)SrcNumElts) { 2393 Input = 1; 2394 Idx -= SrcNumElts; 2395 } 2396 if (Idx > MaxRange[Input]) 2397 MaxRange[Input] = Idx; 2398 if (Idx < MinRange[Input]) 2399 MinRange[Input] = Idx; 2400 } 2401 2402 // Check if the access is smaller than the vector size and can we find 2403 // a reasonable extract index. 2404 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2405 // Extract. 2406 int StartIdx[2]; // StartIdx to extract from 2407 for (int Input=0; Input < 2; ++Input) { 2408 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2409 RangeUse[Input] = 0; // Unused 2410 StartIdx[Input] = 0; 2411 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2412 // Fits within range but we should see if we can find a good 2413 // start index that is a multiple of the mask length. 2414 if (MaxRange[Input] < (int)MaskNumElts) { 2415 RangeUse[Input] = 1; // Extract from beginning of the vector 2416 StartIdx[Input] = 0; 2417 } else { 2418 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2419 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2420 StartIdx[Input] + MaskNumElts < SrcNumElts) 2421 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2422 } 2423 } 2424 } 2425 2426 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2427 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2428 return; 2429 } 2430 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2431 // Extract appropriate subvector and generate a vector shuffle 2432 for (int Input=0; Input < 2; ++Input) { 2433 SDValue &Src = Input == 0 ? Src1 : Src2; 2434 if (RangeUse[Input] == 0) 2435 Src = DAG.getUNDEF(VT); 2436 else 2437 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2438 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2439 } 2440 2441 // Calculate new mask. 2442 SmallVector<int, 8> MappedOps; 2443 for (unsigned i = 0; i != MaskNumElts; ++i) { 2444 int Idx = Mask[i]; 2445 if (Idx < 0) 2446 MappedOps.push_back(Idx); 2447 else if (Idx < (int)SrcNumElts) 2448 MappedOps.push_back(Idx - StartIdx[0]); 2449 else 2450 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2451 } 2452 2453 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2454 &MappedOps[0])); 2455 return; 2456 } 2457 } 2458 2459 // We can't use either concat vectors or extract subvectors so fall back to 2460 // replacing the shuffle with extract and build vector. 2461 // to insert and build vector. 2462 EVT EltVT = VT.getVectorElementType(); 2463 EVT PtrVT = TLI.getPointerTy(); 2464 SmallVector<SDValue,8> Ops; 2465 for (unsigned i = 0; i != MaskNumElts; ++i) { 2466 if (Mask[i] < 0) { 2467 Ops.push_back(DAG.getUNDEF(EltVT)); 2468 } else { 2469 int Idx = Mask[i]; 2470 SDValue Res; 2471 2472 if (Idx < (int)SrcNumElts) 2473 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2474 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2475 else 2476 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2477 EltVT, Src2, 2478 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2479 2480 Ops.push_back(Res); 2481 } 2482 } 2483 2484 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2485 VT, &Ops[0], Ops.size())); 2486} 2487 2488void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2489 const Value *Op0 = I.getOperand(0); 2490 const Value *Op1 = I.getOperand(1); 2491 const Type *AggTy = I.getType(); 2492 const Type *ValTy = Op1->getType(); 2493 bool IntoUndef = isa<UndefValue>(Op0); 2494 bool FromUndef = isa<UndefValue>(Op1); 2495 2496 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2497 I.idx_begin(), I.idx_end()); 2498 2499 SmallVector<EVT, 4> AggValueVTs; 2500 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2501 SmallVector<EVT, 4> ValValueVTs; 2502 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2503 2504 unsigned NumAggValues = AggValueVTs.size(); 2505 unsigned NumValValues = ValValueVTs.size(); 2506 SmallVector<SDValue, 4> Values(NumAggValues); 2507 2508 SDValue Agg = getValue(Op0); 2509 SDValue Val = getValue(Op1); 2510 unsigned i = 0; 2511 // Copy the beginning value(s) from the original aggregate. 2512 for (; i != LinearIndex; ++i) 2513 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2514 SDValue(Agg.getNode(), Agg.getResNo() + i); 2515 // Copy values from the inserted value(s). 2516 for (; i != LinearIndex + NumValValues; ++i) 2517 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2518 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2519 // Copy remaining value(s) from the original aggregate. 2520 for (; i != NumAggValues; ++i) 2521 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2522 SDValue(Agg.getNode(), Agg.getResNo() + i); 2523 2524 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2525 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2526 &Values[0], NumAggValues)); 2527} 2528 2529void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2530 const Value *Op0 = I.getOperand(0); 2531 const Type *AggTy = Op0->getType(); 2532 const Type *ValTy = I.getType(); 2533 bool OutOfUndef = isa<UndefValue>(Op0); 2534 2535 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2536 I.idx_begin(), I.idx_end()); 2537 2538 SmallVector<EVT, 4> ValValueVTs; 2539 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2540 2541 unsigned NumValValues = ValValueVTs.size(); 2542 SmallVector<SDValue, 4> Values(NumValValues); 2543 2544 SDValue Agg = getValue(Op0); 2545 // Copy out the selected value(s). 2546 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2547 Values[i - LinearIndex] = 2548 OutOfUndef ? 2549 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2550 SDValue(Agg.getNode(), Agg.getResNo() + i); 2551 2552 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2553 DAG.getVTList(&ValValueVTs[0], NumValValues), 2554 &Values[0], NumValValues)); 2555} 2556 2557void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2558 SDValue N = getValue(I.getOperand(0)); 2559 const Type *Ty = I.getOperand(0)->getType(); 2560 2561 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2562 OI != E; ++OI) { 2563 const Value *Idx = *OI; 2564 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2565 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2566 if (Field) { 2567 // N = N + Offset 2568 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2569 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2570 DAG.getIntPtrConstant(Offset)); 2571 } 2572 2573 Ty = StTy->getElementType(Field); 2574 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) { 2575 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2576 2577 // Offset canonically 0 for unions, but type changes 2578 Ty = UnTy->getElementType(Field); 2579 } else { 2580 Ty = cast<SequentialType>(Ty)->getElementType(); 2581 2582 // If this is a constant subscript, handle it quickly. 2583 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2584 if (CI->getZExtValue() == 0) continue; 2585 uint64_t Offs = 2586 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2587 SDValue OffsVal; 2588 EVT PTy = TLI.getPointerTy(); 2589 unsigned PtrBits = PTy.getSizeInBits(); 2590 if (PtrBits < 64) 2591 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2592 TLI.getPointerTy(), 2593 DAG.getConstant(Offs, MVT::i64)); 2594 else 2595 OffsVal = DAG.getIntPtrConstant(Offs); 2596 2597 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2598 OffsVal); 2599 continue; 2600 } 2601 2602 // N = N + Idx * ElementSize; 2603 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2604 TD->getTypeAllocSize(Ty)); 2605 SDValue IdxN = getValue(Idx); 2606 2607 // If the index is smaller or larger than intptr_t, truncate or extend 2608 // it. 2609 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2610 2611 // If this is a multiply by a power of two, turn it into a shl 2612 // immediately. This is a very common case. 2613 if (ElementSize != 1) { 2614 if (ElementSize.isPowerOf2()) { 2615 unsigned Amt = ElementSize.logBase2(); 2616 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2617 N.getValueType(), IdxN, 2618 DAG.getConstant(Amt, TLI.getPointerTy())); 2619 } else { 2620 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2621 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2622 N.getValueType(), IdxN, Scale); 2623 } 2624 } 2625 2626 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2627 N.getValueType(), N, IdxN); 2628 } 2629 } 2630 2631 setValue(&I, N); 2632} 2633 2634void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2635 // If this is a fixed sized alloca in the entry block of the function, 2636 // allocate it statically on the stack. 2637 if (FuncInfo.StaticAllocaMap.count(&I)) 2638 return; // getValue will auto-populate this. 2639 2640 const Type *Ty = I.getAllocatedType(); 2641 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2642 unsigned Align = 2643 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2644 I.getAlignment()); 2645 2646 SDValue AllocSize = getValue(I.getArraySize()); 2647 2648 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(), 2649 AllocSize, 2650 DAG.getConstant(TySize, AllocSize.getValueType())); 2651 2652 EVT IntPtr = TLI.getPointerTy(); 2653 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2654 2655 // Handle alignment. If the requested alignment is less than or equal to 2656 // the stack alignment, ignore it. If the size is greater than or equal to 2657 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2658 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2659 if (Align <= StackAlign) 2660 Align = 0; 2661 2662 // Round the size of the allocation up to the stack alignment size 2663 // by add SA-1 to the size. 2664 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2665 AllocSize.getValueType(), AllocSize, 2666 DAG.getIntPtrConstant(StackAlign-1)); 2667 2668 // Mask out the low bits for alignment purposes. 2669 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2670 AllocSize.getValueType(), AllocSize, 2671 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2672 2673 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2674 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2675 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2676 VTs, Ops, 3); 2677 setValue(&I, DSA); 2678 DAG.setRoot(DSA.getValue(1)); 2679 2680 // Inform the Frame Information that we have just allocated a variable-sized 2681 // object. 2682 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); 2683} 2684 2685void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2686 const Value *SV = I.getOperand(0); 2687 SDValue Ptr = getValue(SV); 2688 2689 const Type *Ty = I.getType(); 2690 2691 bool isVolatile = I.isVolatile(); 2692 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2693 unsigned Alignment = I.getAlignment(); 2694 2695 SmallVector<EVT, 4> ValueVTs; 2696 SmallVector<uint64_t, 4> Offsets; 2697 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2698 unsigned NumValues = ValueVTs.size(); 2699 if (NumValues == 0) 2700 return; 2701 2702 SDValue Root; 2703 bool ConstantMemory = false; 2704 if (I.isVolatile()) 2705 // Serialize volatile loads with other side effects. 2706 Root = getRoot(); 2707 else if (AA->pointsToConstantMemory(SV)) { 2708 // Do not serialize (non-volatile) loads of constant memory with anything. 2709 Root = DAG.getEntryNode(); 2710 ConstantMemory = true; 2711 } else { 2712 // Do not serialize non-volatile loads against each other. 2713 Root = DAG.getRoot(); 2714 } 2715 2716 SmallVector<SDValue, 4> Values(NumValues); 2717 SmallVector<SDValue, 4> Chains(NumValues); 2718 EVT PtrVT = Ptr.getValueType(); 2719 for (unsigned i = 0; i != NumValues; ++i) { 2720 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2721 PtrVT, Ptr, 2722 DAG.getConstant(Offsets[i], PtrVT)); 2723 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2724 A, SV, Offsets[i], isVolatile, 2725 isNonTemporal, Alignment); 2726 2727 Values[i] = L; 2728 Chains[i] = L.getValue(1); 2729 } 2730 2731 if (!ConstantMemory) { 2732 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2733 MVT::Other, &Chains[0], NumValues); 2734 if (isVolatile) 2735 DAG.setRoot(Chain); 2736 else 2737 PendingLoads.push_back(Chain); 2738 } 2739 2740 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2741 DAG.getVTList(&ValueVTs[0], NumValues), 2742 &Values[0], NumValues)); 2743} 2744 2745void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2746 const Value *SrcV = I.getOperand(0); 2747 const Value *PtrV = I.getOperand(1); 2748 2749 SmallVector<EVT, 4> ValueVTs; 2750 SmallVector<uint64_t, 4> Offsets; 2751 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2752 unsigned NumValues = ValueVTs.size(); 2753 if (NumValues == 0) 2754 return; 2755 2756 // Get the lowered operands. Note that we do this after 2757 // checking if NumResults is zero, because with zero results 2758 // the operands won't have values in the map. 2759 SDValue Src = getValue(SrcV); 2760 SDValue Ptr = getValue(PtrV); 2761 2762 SDValue Root = getRoot(); 2763 SmallVector<SDValue, 4> Chains(NumValues); 2764 EVT PtrVT = Ptr.getValueType(); 2765 bool isVolatile = I.isVolatile(); 2766 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2767 unsigned Alignment = I.getAlignment(); 2768 2769 for (unsigned i = 0; i != NumValues; ++i) { 2770 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 2771 DAG.getConstant(Offsets[i], PtrVT)); 2772 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 2773 SDValue(Src.getNode(), Src.getResNo() + i), 2774 Add, PtrV, Offsets[i], isVolatile, 2775 isNonTemporal, Alignment); 2776 } 2777 2778 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2779 MVT::Other, &Chains[0], NumValues)); 2780} 2781 2782/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 2783/// node. 2784void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 2785 unsigned Intrinsic) { 2786 bool HasChain = !I.doesNotAccessMemory(); 2787 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 2788 2789 // Build the operand list. 2790 SmallVector<SDValue, 8> Ops; 2791 if (HasChain) { // If this intrinsic has side-effects, chainify it. 2792 if (OnlyLoad) { 2793 // We don't need to serialize loads against other loads. 2794 Ops.push_back(DAG.getRoot()); 2795 } else { 2796 Ops.push_back(getRoot()); 2797 } 2798 } 2799 2800 // Info is set by getTgtMemInstrinsic 2801 TargetLowering::IntrinsicInfo Info; 2802 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 2803 2804 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 2805 if (!IsTgtIntrinsic) 2806 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 2807 2808 // Add all operands of the call to the operand list. 2809 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) { 2810 SDValue Op = getValue(I.getOperand(i)); 2811 assert(TLI.isTypeLegal(Op.getValueType()) && 2812 "Intrinsic uses a non-legal type?"); 2813 Ops.push_back(Op); 2814 } 2815 2816 SmallVector<EVT, 4> ValueVTs; 2817 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2818#ifndef NDEBUG 2819 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 2820 assert(TLI.isTypeLegal(ValueVTs[Val]) && 2821 "Intrinsic uses a non-legal type?"); 2822 } 2823#endif // NDEBUG 2824 2825 if (HasChain) 2826 ValueVTs.push_back(MVT::Other); 2827 2828 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 2829 2830 // Create the node. 2831 SDValue Result; 2832 if (IsTgtIntrinsic) { 2833 // This is target intrinsic that touches memory 2834 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 2835 VTs, &Ops[0], Ops.size(), 2836 Info.memVT, Info.ptrVal, Info.offset, 2837 Info.align, Info.vol, 2838 Info.readMem, Info.writeMem); 2839 } else if (!HasChain) { 2840 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 2841 VTs, &Ops[0], Ops.size()); 2842 } else if (!I.getType()->isVoidTy()) { 2843 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 2844 VTs, &Ops[0], Ops.size()); 2845 } else { 2846 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 2847 VTs, &Ops[0], Ops.size()); 2848 } 2849 2850 if (HasChain) { 2851 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 2852 if (OnlyLoad) 2853 PendingLoads.push_back(Chain); 2854 else 2855 DAG.setRoot(Chain); 2856 } 2857 2858 if (!I.getType()->isVoidTy()) { 2859 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 2860 EVT VT = TLI.getValueType(PTy); 2861 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 2862 } 2863 2864 setValue(&I, Result); 2865 } 2866} 2867 2868/// GetSignificand - Get the significand and build it into a floating-point 2869/// number with exponent of 1: 2870/// 2871/// Op = (Op & 0x007fffff) | 0x3f800000; 2872/// 2873/// where Op is the hexidecimal representation of floating point value. 2874static SDValue 2875GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 2876 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2877 DAG.getConstant(0x007fffff, MVT::i32)); 2878 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 2879 DAG.getConstant(0x3f800000, MVT::i32)); 2880 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 2881} 2882 2883/// GetExponent - Get the exponent: 2884/// 2885/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 2886/// 2887/// where Op is the hexidecimal representation of floating point value. 2888static SDValue 2889GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 2890 DebugLoc dl) { 2891 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 2892 DAG.getConstant(0x7f800000, MVT::i32)); 2893 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 2894 DAG.getConstant(23, TLI.getPointerTy())); 2895 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 2896 DAG.getConstant(127, MVT::i32)); 2897 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 2898} 2899 2900/// getF32Constant - Get 32-bit floating point constant. 2901static SDValue 2902getF32Constant(SelectionDAG &DAG, unsigned Flt) { 2903 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 2904} 2905 2906/// Inlined utility function to implement binary input atomic intrinsics for 2907/// visitIntrinsicCall: I is a call instruction 2908/// Op is the associated NodeType for I 2909const char * 2910SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 2911 ISD::NodeType Op) { 2912 SDValue Root = getRoot(); 2913 SDValue L = 2914 DAG.getAtomic(Op, getCurDebugLoc(), 2915 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 2916 Root, 2917 getValue(I.getOperand(1)), 2918 getValue(I.getOperand(2)), 2919 I.getOperand(1)); 2920 setValue(&I, L); 2921 DAG.setRoot(L.getValue(1)); 2922 return 0; 2923} 2924 2925// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 2926const char * 2927SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 2928 SDValue Op1 = getValue(I.getOperand(1)); 2929 SDValue Op2 = getValue(I.getOperand(2)); 2930 2931 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 2932 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 2933 return 0; 2934} 2935 2936/// visitExp - Lower an exp intrinsic. Handles the special sequences for 2937/// limited-precision mode. 2938void 2939SelectionDAGBuilder::visitExp(const CallInst &I) { 2940 SDValue result; 2941 DebugLoc dl = getCurDebugLoc(); 2942 2943 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 2944 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 2945 SDValue Op = getValue(I.getOperand(1)); 2946 2947 // Put the exponent in the right bit position for later addition to the 2948 // final result: 2949 // 2950 // #define LOG2OFe 1.4426950f 2951 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 2952 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 2953 getF32Constant(DAG, 0x3fb8aa3b)); 2954 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 2955 2956 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 2957 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 2958 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 2959 2960 // IntegerPartOfX <<= 23; 2961 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 2962 DAG.getConstant(23, TLI.getPointerTy())); 2963 2964 if (LimitFloatPrecision <= 6) { 2965 // For floating-point precision of 6: 2966 // 2967 // TwoToFractionalPartOfX = 2968 // 0.997535578f + 2969 // (0.735607626f + 0.252464424f * x) * x; 2970 // 2971 // error 0.0144103317, which is 6 bits 2972 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 2973 getF32Constant(DAG, 0x3e814304)); 2974 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 2975 getF32Constant(DAG, 0x3f3c50c8)); 2976 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 2977 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 2978 getF32Constant(DAG, 0x3f7f5e7e)); 2979 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 2980 2981 // Add the exponent into the result in integer domain. 2982 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 2983 TwoToFracPartOfX, IntegerPartOfX); 2984 2985 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 2986 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 2987 // For floating-point precision of 12: 2988 // 2989 // TwoToFractionalPartOfX = 2990 // 0.999892986f + 2991 // (0.696457318f + 2992 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 2993 // 2994 // 0.000107046256 error, which is 13 to 14 bits 2995 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 2996 getF32Constant(DAG, 0x3da235e3)); 2997 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 2998 getF32Constant(DAG, 0x3e65b8f3)); 2999 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3000 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3001 getF32Constant(DAG, 0x3f324b07)); 3002 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3003 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3004 getF32Constant(DAG, 0x3f7ff8fd)); 3005 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3006 3007 // Add the exponent into the result in integer domain. 3008 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3009 TwoToFracPartOfX, IntegerPartOfX); 3010 3011 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3012 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3013 // For floating-point precision of 18: 3014 // 3015 // TwoToFractionalPartOfX = 3016 // 0.999999982f + 3017 // (0.693148872f + 3018 // (0.240227044f + 3019 // (0.554906021e-1f + 3020 // (0.961591928e-2f + 3021 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3022 // 3023 // error 2.47208000*10^(-7), which is better than 18 bits 3024 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3025 getF32Constant(DAG, 0x3924b03e)); 3026 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3027 getF32Constant(DAG, 0x3ab24b87)); 3028 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3029 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3030 getF32Constant(DAG, 0x3c1d8c17)); 3031 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3032 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3033 getF32Constant(DAG, 0x3d634a1d)); 3034 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3035 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3036 getF32Constant(DAG, 0x3e75fe14)); 3037 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3038 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3039 getF32Constant(DAG, 0x3f317234)); 3040 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3041 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3042 getF32Constant(DAG, 0x3f800000)); 3043 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3044 MVT::i32, t13); 3045 3046 // Add the exponent into the result in integer domain. 3047 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3048 TwoToFracPartOfX, IntegerPartOfX); 3049 3050 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3051 } 3052 } else { 3053 // No special expansion. 3054 result = DAG.getNode(ISD::FEXP, dl, 3055 getValue(I.getOperand(1)).getValueType(), 3056 getValue(I.getOperand(1))); 3057 } 3058 3059 setValue(&I, result); 3060} 3061 3062/// visitLog - Lower a log intrinsic. Handles the special sequences for 3063/// limited-precision mode. 3064void 3065SelectionDAGBuilder::visitLog(const CallInst &I) { 3066 SDValue result; 3067 DebugLoc dl = getCurDebugLoc(); 3068 3069 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3070 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3071 SDValue Op = getValue(I.getOperand(1)); 3072 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3073 3074 // Scale the exponent by log(2) [0.69314718f]. 3075 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3076 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3077 getF32Constant(DAG, 0x3f317218)); 3078 3079 // Get the significand and build it into a floating-point number with 3080 // exponent of 1. 3081 SDValue X = GetSignificand(DAG, Op1, dl); 3082 3083 if (LimitFloatPrecision <= 6) { 3084 // For floating-point precision of 6: 3085 // 3086 // LogofMantissa = 3087 // -1.1609546f + 3088 // (1.4034025f - 0.23903021f * x) * x; 3089 // 3090 // error 0.0034276066, which is better than 8 bits 3091 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3092 getF32Constant(DAG, 0xbe74c456)); 3093 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3094 getF32Constant(DAG, 0x3fb3a2b1)); 3095 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3096 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3097 getF32Constant(DAG, 0x3f949a29)); 3098 3099 result = DAG.getNode(ISD::FADD, dl, 3100 MVT::f32, LogOfExponent, LogOfMantissa); 3101 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3102 // For floating-point precision of 12: 3103 // 3104 // LogOfMantissa = 3105 // -1.7417939f + 3106 // (2.8212026f + 3107 // (-1.4699568f + 3108 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3109 // 3110 // error 0.000061011436, which is 14 bits 3111 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3112 getF32Constant(DAG, 0xbd67b6d6)); 3113 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3114 getF32Constant(DAG, 0x3ee4f4b8)); 3115 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3116 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3117 getF32Constant(DAG, 0x3fbc278b)); 3118 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3119 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3120 getF32Constant(DAG, 0x40348e95)); 3121 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3122 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3123 getF32Constant(DAG, 0x3fdef31a)); 3124 3125 result = DAG.getNode(ISD::FADD, dl, 3126 MVT::f32, LogOfExponent, LogOfMantissa); 3127 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3128 // For floating-point precision of 18: 3129 // 3130 // LogOfMantissa = 3131 // -2.1072184f + 3132 // (4.2372794f + 3133 // (-3.7029485f + 3134 // (2.2781945f + 3135 // (-0.87823314f + 3136 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3137 // 3138 // error 0.0000023660568, which is better than 18 bits 3139 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3140 getF32Constant(DAG, 0xbc91e5ac)); 3141 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3142 getF32Constant(DAG, 0x3e4350aa)); 3143 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3144 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3145 getF32Constant(DAG, 0x3f60d3e3)); 3146 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3147 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3148 getF32Constant(DAG, 0x4011cdf0)); 3149 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3150 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3151 getF32Constant(DAG, 0x406cfd1c)); 3152 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3153 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3154 getF32Constant(DAG, 0x408797cb)); 3155 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3156 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3157 getF32Constant(DAG, 0x4006dcab)); 3158 3159 result = DAG.getNode(ISD::FADD, dl, 3160 MVT::f32, LogOfExponent, LogOfMantissa); 3161 } 3162 } else { 3163 // No special expansion. 3164 result = DAG.getNode(ISD::FLOG, dl, 3165 getValue(I.getOperand(1)).getValueType(), 3166 getValue(I.getOperand(1))); 3167 } 3168 3169 setValue(&I, result); 3170} 3171 3172/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3173/// limited-precision mode. 3174void 3175SelectionDAGBuilder::visitLog2(const CallInst &I) { 3176 SDValue result; 3177 DebugLoc dl = getCurDebugLoc(); 3178 3179 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3180 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3181 SDValue Op = getValue(I.getOperand(1)); 3182 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3183 3184 // Get the exponent. 3185 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3186 3187 // Get the significand and build it into a floating-point number with 3188 // exponent of 1. 3189 SDValue X = GetSignificand(DAG, Op1, dl); 3190 3191 // Different possible minimax approximations of significand in 3192 // floating-point for various degrees of accuracy over [1,2]. 3193 if (LimitFloatPrecision <= 6) { 3194 // For floating-point precision of 6: 3195 // 3196 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3197 // 3198 // error 0.0049451742, which is more than 7 bits 3199 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3200 getF32Constant(DAG, 0xbeb08fe0)); 3201 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3202 getF32Constant(DAG, 0x40019463)); 3203 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3204 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3205 getF32Constant(DAG, 0x3fd6633d)); 3206 3207 result = DAG.getNode(ISD::FADD, dl, 3208 MVT::f32, LogOfExponent, Log2ofMantissa); 3209 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3210 // For floating-point precision of 12: 3211 // 3212 // Log2ofMantissa = 3213 // -2.51285454f + 3214 // (4.07009056f + 3215 // (-2.12067489f + 3216 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3217 // 3218 // error 0.0000876136000, which is better than 13 bits 3219 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3220 getF32Constant(DAG, 0xbda7262e)); 3221 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3222 getF32Constant(DAG, 0x3f25280b)); 3223 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3224 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3225 getF32Constant(DAG, 0x4007b923)); 3226 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3227 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3228 getF32Constant(DAG, 0x40823e2f)); 3229 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3230 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3231 getF32Constant(DAG, 0x4020d29c)); 3232 3233 result = DAG.getNode(ISD::FADD, dl, 3234 MVT::f32, LogOfExponent, Log2ofMantissa); 3235 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3236 // For floating-point precision of 18: 3237 // 3238 // Log2ofMantissa = 3239 // -3.0400495f + 3240 // (6.1129976f + 3241 // (-5.3420409f + 3242 // (3.2865683f + 3243 // (-1.2669343f + 3244 // (0.27515199f - 3245 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3246 // 3247 // error 0.0000018516, which is better than 18 bits 3248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3249 getF32Constant(DAG, 0xbcd2769e)); 3250 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3251 getF32Constant(DAG, 0x3e8ce0b9)); 3252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3253 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3254 getF32Constant(DAG, 0x3fa22ae7)); 3255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3257 getF32Constant(DAG, 0x40525723)); 3258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3259 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3260 getF32Constant(DAG, 0x40aaf200)); 3261 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3262 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3263 getF32Constant(DAG, 0x40c39dad)); 3264 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3265 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3266 getF32Constant(DAG, 0x4042902c)); 3267 3268 result = DAG.getNode(ISD::FADD, dl, 3269 MVT::f32, LogOfExponent, Log2ofMantissa); 3270 } 3271 } else { 3272 // No special expansion. 3273 result = DAG.getNode(ISD::FLOG2, dl, 3274 getValue(I.getOperand(1)).getValueType(), 3275 getValue(I.getOperand(1))); 3276 } 3277 3278 setValue(&I, result); 3279} 3280 3281/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3282/// limited-precision mode. 3283void 3284SelectionDAGBuilder::visitLog10(const CallInst &I) { 3285 SDValue result; 3286 DebugLoc dl = getCurDebugLoc(); 3287 3288 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3289 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3290 SDValue Op = getValue(I.getOperand(1)); 3291 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3292 3293 // Scale the exponent by log10(2) [0.30102999f]. 3294 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3295 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3296 getF32Constant(DAG, 0x3e9a209a)); 3297 3298 // Get the significand and build it into a floating-point number with 3299 // exponent of 1. 3300 SDValue X = GetSignificand(DAG, Op1, dl); 3301 3302 if (LimitFloatPrecision <= 6) { 3303 // For floating-point precision of 6: 3304 // 3305 // Log10ofMantissa = 3306 // -0.50419619f + 3307 // (0.60948995f - 0.10380950f * x) * x; 3308 // 3309 // error 0.0014886165, which is 6 bits 3310 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3311 getF32Constant(DAG, 0xbdd49a13)); 3312 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3313 getF32Constant(DAG, 0x3f1c0789)); 3314 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3315 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3316 getF32Constant(DAG, 0x3f011300)); 3317 3318 result = DAG.getNode(ISD::FADD, dl, 3319 MVT::f32, LogOfExponent, Log10ofMantissa); 3320 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3321 // For floating-point precision of 12: 3322 // 3323 // Log10ofMantissa = 3324 // -0.64831180f + 3325 // (0.91751397f + 3326 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3327 // 3328 // error 0.00019228036, which is better than 12 bits 3329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3330 getF32Constant(DAG, 0x3d431f31)); 3331 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3332 getF32Constant(DAG, 0x3ea21fb2)); 3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3334 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3335 getF32Constant(DAG, 0x3f6ae232)); 3336 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3337 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3338 getF32Constant(DAG, 0x3f25f7c3)); 3339 3340 result = DAG.getNode(ISD::FADD, dl, 3341 MVT::f32, LogOfExponent, Log10ofMantissa); 3342 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3343 // For floating-point precision of 18: 3344 // 3345 // Log10ofMantissa = 3346 // -0.84299375f + 3347 // (1.5327582f + 3348 // (-1.0688956f + 3349 // (0.49102474f + 3350 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3351 // 3352 // error 0.0000037995730, which is better than 18 bits 3353 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3354 getF32Constant(DAG, 0x3c5d51ce)); 3355 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3356 getF32Constant(DAG, 0x3e00685a)); 3357 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3358 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3359 getF32Constant(DAG, 0x3efb6798)); 3360 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3361 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3362 getF32Constant(DAG, 0x3f88d192)); 3363 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3364 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3365 getF32Constant(DAG, 0x3fc4316c)); 3366 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3367 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3368 getF32Constant(DAG, 0x3f57ce70)); 3369 3370 result = DAG.getNode(ISD::FADD, dl, 3371 MVT::f32, LogOfExponent, Log10ofMantissa); 3372 } 3373 } else { 3374 // No special expansion. 3375 result = DAG.getNode(ISD::FLOG10, dl, 3376 getValue(I.getOperand(1)).getValueType(), 3377 getValue(I.getOperand(1))); 3378 } 3379 3380 setValue(&I, result); 3381} 3382 3383/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3384/// limited-precision mode. 3385void 3386SelectionDAGBuilder::visitExp2(const CallInst &I) { 3387 SDValue result; 3388 DebugLoc dl = getCurDebugLoc(); 3389 3390 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && 3391 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3392 SDValue Op = getValue(I.getOperand(1)); 3393 3394 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3395 3396 // FractionalPartOfX = x - (float)IntegerPartOfX; 3397 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3398 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3399 3400 // IntegerPartOfX <<= 23; 3401 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3402 DAG.getConstant(23, TLI.getPointerTy())); 3403 3404 if (LimitFloatPrecision <= 6) { 3405 // For floating-point precision of 6: 3406 // 3407 // TwoToFractionalPartOfX = 3408 // 0.997535578f + 3409 // (0.735607626f + 0.252464424f * x) * x; 3410 // 3411 // error 0.0144103317, which is 6 bits 3412 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3413 getF32Constant(DAG, 0x3e814304)); 3414 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3415 getF32Constant(DAG, 0x3f3c50c8)); 3416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3418 getF32Constant(DAG, 0x3f7f5e7e)); 3419 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3420 SDValue TwoToFractionalPartOfX = 3421 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3422 3423 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3424 MVT::f32, TwoToFractionalPartOfX); 3425 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3426 // For floating-point precision of 12: 3427 // 3428 // TwoToFractionalPartOfX = 3429 // 0.999892986f + 3430 // (0.696457318f + 3431 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3432 // 3433 // error 0.000107046256, which is 13 to 14 bits 3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3435 getF32Constant(DAG, 0x3da235e3)); 3436 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3437 getF32Constant(DAG, 0x3e65b8f3)); 3438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3439 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3440 getF32Constant(DAG, 0x3f324b07)); 3441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3442 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3443 getF32Constant(DAG, 0x3f7ff8fd)); 3444 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3445 SDValue TwoToFractionalPartOfX = 3446 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3447 3448 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3449 MVT::f32, TwoToFractionalPartOfX); 3450 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3451 // For floating-point precision of 18: 3452 // 3453 // TwoToFractionalPartOfX = 3454 // 0.999999982f + 3455 // (0.693148872f + 3456 // (0.240227044f + 3457 // (0.554906021e-1f + 3458 // (0.961591928e-2f + 3459 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3460 // error 2.47208000*10^(-7), which is better than 18 bits 3461 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3462 getF32Constant(DAG, 0x3924b03e)); 3463 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3464 getF32Constant(DAG, 0x3ab24b87)); 3465 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3466 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3467 getF32Constant(DAG, 0x3c1d8c17)); 3468 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3469 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3470 getF32Constant(DAG, 0x3d634a1d)); 3471 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3472 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3473 getF32Constant(DAG, 0x3e75fe14)); 3474 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3475 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3476 getF32Constant(DAG, 0x3f317234)); 3477 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3478 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3479 getF32Constant(DAG, 0x3f800000)); 3480 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3481 SDValue TwoToFractionalPartOfX = 3482 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3483 3484 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3485 MVT::f32, TwoToFractionalPartOfX); 3486 } 3487 } else { 3488 // No special expansion. 3489 result = DAG.getNode(ISD::FEXP2, dl, 3490 getValue(I.getOperand(1)).getValueType(), 3491 getValue(I.getOperand(1))); 3492 } 3493 3494 setValue(&I, result); 3495} 3496 3497/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3498/// limited-precision mode with x == 10.0f. 3499void 3500SelectionDAGBuilder::visitPow(const CallInst &I) { 3501 SDValue result; 3502 const Value *Val = I.getOperand(1); 3503 DebugLoc dl = getCurDebugLoc(); 3504 bool IsExp10 = false; 3505 3506 if (getValue(Val).getValueType() == MVT::f32 && 3507 getValue(I.getOperand(2)).getValueType() == MVT::f32 && 3508 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3509 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3510 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3511 APFloat Ten(10.0f); 3512 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3513 } 3514 } 3515 } 3516 3517 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3518 SDValue Op = getValue(I.getOperand(2)); 3519 3520 // Put the exponent in the right bit position for later addition to the 3521 // final result: 3522 // 3523 // #define LOG2OF10 3.3219281f 3524 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3525 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3526 getF32Constant(DAG, 0x40549a78)); 3527 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3528 3529 // FractionalPartOfX = x - (float)IntegerPartOfX; 3530 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3531 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3532 3533 // IntegerPartOfX <<= 23; 3534 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3535 DAG.getConstant(23, TLI.getPointerTy())); 3536 3537 if (LimitFloatPrecision <= 6) { 3538 // For floating-point precision of 6: 3539 // 3540 // twoToFractionalPartOfX = 3541 // 0.997535578f + 3542 // (0.735607626f + 0.252464424f * x) * x; 3543 // 3544 // error 0.0144103317, which is 6 bits 3545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3546 getF32Constant(DAG, 0x3e814304)); 3547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3548 getF32Constant(DAG, 0x3f3c50c8)); 3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3550 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3551 getF32Constant(DAG, 0x3f7f5e7e)); 3552 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3553 SDValue TwoToFractionalPartOfX = 3554 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3555 3556 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3557 MVT::f32, TwoToFractionalPartOfX); 3558 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3559 // For floating-point precision of 12: 3560 // 3561 // TwoToFractionalPartOfX = 3562 // 0.999892986f + 3563 // (0.696457318f + 3564 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3565 // 3566 // error 0.000107046256, which is 13 to 14 bits 3567 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3568 getF32Constant(DAG, 0x3da235e3)); 3569 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3570 getF32Constant(DAG, 0x3e65b8f3)); 3571 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3572 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3573 getF32Constant(DAG, 0x3f324b07)); 3574 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3575 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3576 getF32Constant(DAG, 0x3f7ff8fd)); 3577 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3578 SDValue TwoToFractionalPartOfX = 3579 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3580 3581 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3582 MVT::f32, TwoToFractionalPartOfX); 3583 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3584 // For floating-point precision of 18: 3585 // 3586 // TwoToFractionalPartOfX = 3587 // 0.999999982f + 3588 // (0.693148872f + 3589 // (0.240227044f + 3590 // (0.554906021e-1f + 3591 // (0.961591928e-2f + 3592 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3593 // error 2.47208000*10^(-7), which is better than 18 bits 3594 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3595 getF32Constant(DAG, 0x3924b03e)); 3596 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3597 getF32Constant(DAG, 0x3ab24b87)); 3598 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3599 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3600 getF32Constant(DAG, 0x3c1d8c17)); 3601 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3602 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3603 getF32Constant(DAG, 0x3d634a1d)); 3604 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3605 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3606 getF32Constant(DAG, 0x3e75fe14)); 3607 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3608 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3609 getF32Constant(DAG, 0x3f317234)); 3610 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3611 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3612 getF32Constant(DAG, 0x3f800000)); 3613 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3614 SDValue TwoToFractionalPartOfX = 3615 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3616 3617 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3618 MVT::f32, TwoToFractionalPartOfX); 3619 } 3620 } else { 3621 // No special expansion. 3622 result = DAG.getNode(ISD::FPOW, dl, 3623 getValue(I.getOperand(1)).getValueType(), 3624 getValue(I.getOperand(1)), 3625 getValue(I.getOperand(2))); 3626 } 3627 3628 setValue(&I, result); 3629} 3630 3631 3632/// ExpandPowI - Expand a llvm.powi intrinsic. 3633static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3634 SelectionDAG &DAG) { 3635 // If RHS is a constant, we can expand this out to a multiplication tree, 3636 // otherwise we end up lowering to a call to __powidf2 (for example). When 3637 // optimizing for size, we only want to do this if the expansion would produce 3638 // a small number of multiplies, otherwise we do the full expansion. 3639 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3640 // Get the exponent as a positive value. 3641 unsigned Val = RHSC->getSExtValue(); 3642 if ((int)Val < 0) Val = -Val; 3643 3644 // powi(x, 0) -> 1.0 3645 if (Val == 0) 3646 return DAG.getConstantFP(1.0, LHS.getValueType()); 3647 3648 const Function *F = DAG.getMachineFunction().getFunction(); 3649 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3650 // If optimizing for size, don't insert too many multiplies. This 3651 // inserts up to 5 multiplies. 3652 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3653 // We use the simple binary decomposition method to generate the multiply 3654 // sequence. There are more optimal ways to do this (for example, 3655 // powi(x,15) generates one more multiply than it should), but this has 3656 // the benefit of being both really simple and much better than a libcall. 3657 SDValue Res; // Logically starts equal to 1.0 3658 SDValue CurSquare = LHS; 3659 while (Val) { 3660 if (Val & 1) { 3661 if (Res.getNode()) 3662 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3663 else 3664 Res = CurSquare; // 1.0*CurSquare. 3665 } 3666 3667 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3668 CurSquare, CurSquare); 3669 Val >>= 1; 3670 } 3671 3672 // If the original was negative, invert the result, producing 1/(x*x*x). 3673 if (RHSC->getSExtValue() < 0) 3674 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3675 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3676 return Res; 3677 } 3678 } 3679 3680 // Otherwise, expand to a libcall. 3681 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3682} 3683 3684/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3685/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3686/// At the end of instruction selection, they will be inserted to the entry BB. 3687void 3688SelectionDAGBuilder::EmitFuncArgumentDbgValue(const DbgValueInst &DI, 3689 const Value *V, MDNode *Variable, 3690 uint64_t Offset, SDValue &N) { 3691 if (!isa<Argument>(V)) 3692 return; 3693 3694 MachineFunction &MF = DAG.getMachineFunction(); 3695 MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()]; 3696 if (MBB != &MF.front()) 3697 return; 3698 3699 unsigned Reg = 0; 3700 if (N.getOpcode() == ISD::CopyFromReg) { 3701 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3702 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3703 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3704 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3705 if (PR) 3706 Reg = PR; 3707 } 3708 } 3709 3710 if (!Reg) 3711 Reg = FuncInfo.ValueMap[V]; 3712 3713 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3714 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3715 TII->get(TargetOpcode::DBG_VALUE)) 3716 .addReg(Reg).addImm(Offset).addMetadata(Variable); 3717 FuncInfo.ArgDbgValues.push_back(&*MIB); 3718} 3719 3720/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3721/// we want to emit this as a call to a named external function, return the name 3722/// otherwise lower it and return null. 3723const char * 3724SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3725 DebugLoc dl = getCurDebugLoc(); 3726 SDValue Res; 3727 3728 switch (Intrinsic) { 3729 default: 3730 // By default, turn this into a target intrinsic node. 3731 visitTargetIntrinsic(I, Intrinsic); 3732 return 0; 3733 case Intrinsic::vastart: visitVAStart(I); return 0; 3734 case Intrinsic::vaend: visitVAEnd(I); return 0; 3735 case Intrinsic::vacopy: visitVACopy(I); return 0; 3736 case Intrinsic::returnaddress: 3737 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3738 getValue(I.getOperand(1)))); 3739 return 0; 3740 case Intrinsic::frameaddress: 3741 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3742 getValue(I.getOperand(1)))); 3743 return 0; 3744 case Intrinsic::setjmp: 3745 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 3746 case Intrinsic::longjmp: 3747 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 3748 case Intrinsic::memcpy: { 3749 // Assert for address < 256 since we support only user defined address 3750 // spaces. 3751 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3752 < 256 && 3753 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace() 3754 < 256 && 3755 "Unknown address space"); 3756 SDValue Op1 = getValue(I.getOperand(1)); 3757 SDValue Op2 = getValue(I.getOperand(2)); 3758 SDValue Op3 = getValue(I.getOperand(3)); 3759 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3760 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3761 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 3762 I.getOperand(1), 0, I.getOperand(2), 0)); 3763 return 0; 3764 } 3765 case Intrinsic::memset: { 3766 // Assert for address < 256 since we support only user defined address 3767 // spaces. 3768 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3769 < 256 && 3770 "Unknown address space"); 3771 SDValue Op1 = getValue(I.getOperand(1)); 3772 SDValue Op2 = getValue(I.getOperand(2)); 3773 SDValue Op3 = getValue(I.getOperand(3)); 3774 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3775 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3776 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3777 I.getOperand(1), 0)); 3778 return 0; 3779 } 3780 case Intrinsic::memmove: { 3781 // Assert for address < 256 since we support only user defined address 3782 // spaces. 3783 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace() 3784 < 256 && 3785 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace() 3786 < 256 && 3787 "Unknown address space"); 3788 SDValue Op1 = getValue(I.getOperand(1)); 3789 SDValue Op2 = getValue(I.getOperand(2)); 3790 SDValue Op3 = getValue(I.getOperand(3)); 3791 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue(); 3792 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue(); 3793 3794 // If the source and destination are known to not be aliases, we can 3795 // lower memmove as memcpy. 3796 uint64_t Size = -1ULL; 3797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 3798 Size = C->getZExtValue(); 3799 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == 3800 AliasAnalysis::NoAlias) { 3801 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3802 false, I.getOperand(1), 0, I.getOperand(2), 0)); 3803 return 0; 3804 } 3805 3806 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 3807 I.getOperand(1), 0, I.getOperand(2), 0)); 3808 return 0; 3809 } 3810 case Intrinsic::dbg_declare: { 3811 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 3812 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3813 return 0; 3814 3815 MDNode *Variable = DI.getVariable(); 3816 // Parameters are handled specially. 3817 bool isParameter = false; 3818 ConstantInt *CI = dyn_cast_or_null<ConstantInt>(Variable->getOperand(0)); 3819 if (CI) { 3820 unsigned Val = CI->getZExtValue(); 3821 unsigned Tag = Val & ~LLVMDebugVersionMask; 3822 if (Tag == dwarf::DW_TAG_arg_variable) 3823 isParameter = true; 3824 } 3825 const Value *Address = DI.getAddress(); 3826 if (!Address) 3827 return 0; 3828 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 3829 Address = BCI->getOperand(0); 3830 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 3831 if (AI) { 3832 // Don't handle byval arguments or VLAs, for example. 3833 // Non-byval arguments are handled here (they refer to the stack temporary 3834 // alloca at this point). 3835 DenseMap<const AllocaInst*, int>::iterator SI = 3836 FuncInfo.StaticAllocaMap.find(AI); 3837 if (SI == FuncInfo.StaticAllocaMap.end()) 3838 return 0; // VLAs. 3839 int FI = SI->second; 3840 3841 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 3842 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 3843 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 3844 } 3845 3846 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 3847 // but do not always have a corresponding SDNode built. The SDNodeOrder 3848 // absolute, but not relative, values are different depending on whether 3849 // debug info exists. 3850 ++SDNodeOrder; 3851 SDValue &N = NodeMap[Address]; 3852 SDDbgValue *SDV; 3853 if (N.getNode()) { 3854 if (isParameter && !AI) { 3855 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 3856 if (FINode) 3857 // Byval parameter. We have a frame index at this point. 3858 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 3859 0, dl, SDNodeOrder); 3860 else 3861 // Can't do anything with other non-AI cases yet. This might be a 3862 // parameter of a callee function that got inlined, for example. 3863 return 0; 3864 } else if (AI) 3865 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 3866 0, dl, SDNodeOrder); 3867 else 3868 // Can't do anything with other non-AI cases yet. 3869 return 0; 3870 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 3871 } else { 3872 // This isn't useful, but it shows what we're missing. 3873 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 3874 0, dl, SDNodeOrder); 3875 DAG.AddDbgValue(SDV, 0, isParameter); 3876 } 3877 return 0; 3878 } 3879 case Intrinsic::dbg_value: { 3880 const DbgValueInst &DI = cast<DbgValueInst>(I); 3881 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None)) 3882 return 0; 3883 3884 MDNode *Variable = DI.getVariable(); 3885 uint64_t Offset = DI.getOffset(); 3886 const Value *V = DI.getValue(); 3887 if (!V) 3888 return 0; 3889 3890 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 3891 // but do not always have a corresponding SDNode built. The SDNodeOrder 3892 // absolute, but not relative, values are different depending on whether 3893 // debug info exists. 3894 ++SDNodeOrder; 3895 SDDbgValue *SDV; 3896 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 3897 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 3898 DAG.AddDbgValue(SDV, 0, false); 3899 } else { 3900 SDValue &N = NodeMap[V]; 3901 if (N.getNode()) { 3902 EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N); 3903 SDV = DAG.getDbgValue(Variable, N.getNode(), 3904 N.getResNo(), Offset, dl, SDNodeOrder); 3905 DAG.AddDbgValue(SDV, N.getNode(), false); 3906 } else { 3907 // We may expand this to cover more cases. One case where we have no 3908 // data available is an unreferenced parameter; we need this fallback. 3909 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 3910 Offset, dl, SDNodeOrder); 3911 DAG.AddDbgValue(SDV, 0, false); 3912 } 3913 } 3914 3915 // Build a debug info table entry. 3916 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 3917 V = BCI->getOperand(0); 3918 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 3919 // Don't handle byval struct arguments or VLAs, for example. 3920 if (!AI) 3921 return 0; 3922 DenseMap<const AllocaInst*, int>::iterator SI = 3923 FuncInfo.StaticAllocaMap.find(AI); 3924 if (SI == FuncInfo.StaticAllocaMap.end()) 3925 return 0; // VLAs. 3926 int FI = SI->second; 3927 3928 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 3929 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 3930 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 3931 return 0; 3932 } 3933 case Intrinsic::eh_exception: { 3934 // Insert the EXCEPTIONADDR instruction. 3935 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() && 3936 "Call to eh.exception not in landing pad!"); 3937 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3938 SDValue Ops[1]; 3939 Ops[0] = DAG.getRoot(); 3940 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 3941 setValue(&I, Op); 3942 DAG.setRoot(Op.getValue(1)); 3943 return 0; 3944 } 3945 3946 case Intrinsic::eh_selector: { 3947 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()]; 3948 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 3949 if (CallMBB->isLandingPad()) 3950 AddCatchInfo(I, &MMI, CallMBB); 3951 else { 3952#ifndef NDEBUG 3953 FuncInfo.CatchInfoLost.insert(&I); 3954#endif 3955 // FIXME: Mark exception selector register as live in. Hack for PR1508. 3956 unsigned Reg = TLI.getExceptionSelectorRegister(); 3957 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg); 3958 } 3959 3960 // Insert the EHSELECTION instruction. 3961 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 3962 SDValue Ops[2]; 3963 Ops[0] = getValue(I.getOperand(1)); 3964 Ops[1] = getRoot(); 3965 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 3966 DAG.setRoot(Op.getValue(1)); 3967 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 3968 return 0; 3969 } 3970 3971 case Intrinsic::eh_typeid_for: { 3972 // Find the type id for the given typeinfo. 3973 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); 3974 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 3975 Res = DAG.getConstant(TypeID, MVT::i32); 3976 setValue(&I, Res); 3977 return 0; 3978 } 3979 3980 case Intrinsic::eh_return_i32: 3981 case Intrinsic::eh_return_i64: 3982 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 3983 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 3984 MVT::Other, 3985 getControlRoot(), 3986 getValue(I.getOperand(1)), 3987 getValue(I.getOperand(2)))); 3988 return 0; 3989 case Intrinsic::eh_unwind_init: 3990 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 3991 return 0; 3992 case Intrinsic::eh_dwarf_cfa: { 3993 EVT VT = getValue(I.getOperand(1)).getValueType(); 3994 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl, 3995 TLI.getPointerTy()); 3996 SDValue Offset = DAG.getNode(ISD::ADD, dl, 3997 TLI.getPointerTy(), 3998 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 3999 TLI.getPointerTy()), 4000 CfaArg); 4001 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4002 TLI.getPointerTy(), 4003 DAG.getConstant(0, TLI.getPointerTy())); 4004 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4005 FA, Offset)); 4006 return 0; 4007 } 4008 case Intrinsic::eh_sjlj_callsite: { 4009 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4010 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1)); 4011 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4012 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4013 4014 MMI.setCurrentCallSite(CI->getZExtValue()); 4015 return 0; 4016 } 4017 4018 case Intrinsic::convertff: 4019 case Intrinsic::convertfsi: 4020 case Intrinsic::convertfui: 4021 case Intrinsic::convertsif: 4022 case Intrinsic::convertuif: 4023 case Intrinsic::convertss: 4024 case Intrinsic::convertsu: 4025 case Intrinsic::convertus: 4026 case Intrinsic::convertuu: { 4027 ISD::CvtCode Code = ISD::CVT_INVALID; 4028 switch (Intrinsic) { 4029 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4030 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4031 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4032 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4033 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4034 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4035 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4036 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4037 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4038 } 4039 EVT DestVT = TLI.getValueType(I.getType()); 4040 const Value *Op1 = I.getOperand(1); 4041 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4042 DAG.getValueType(DestVT), 4043 DAG.getValueType(getValue(Op1).getValueType()), 4044 getValue(I.getOperand(2)), 4045 getValue(I.getOperand(3)), 4046 Code); 4047 setValue(&I, Res); 4048 return 0; 4049 } 4050 case Intrinsic::sqrt: 4051 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4052 getValue(I.getOperand(1)).getValueType(), 4053 getValue(I.getOperand(1)))); 4054 return 0; 4055 case Intrinsic::powi: 4056 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)), 4057 getValue(I.getOperand(2)), DAG)); 4058 return 0; 4059 case Intrinsic::sin: 4060 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4061 getValue(I.getOperand(1)).getValueType(), 4062 getValue(I.getOperand(1)))); 4063 return 0; 4064 case Intrinsic::cos: 4065 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4066 getValue(I.getOperand(1)).getValueType(), 4067 getValue(I.getOperand(1)))); 4068 return 0; 4069 case Intrinsic::log: 4070 visitLog(I); 4071 return 0; 4072 case Intrinsic::log2: 4073 visitLog2(I); 4074 return 0; 4075 case Intrinsic::log10: 4076 visitLog10(I); 4077 return 0; 4078 case Intrinsic::exp: 4079 visitExp(I); 4080 return 0; 4081 case Intrinsic::exp2: 4082 visitExp2(I); 4083 return 0; 4084 case Intrinsic::pow: 4085 visitPow(I); 4086 return 0; 4087 case Intrinsic::convert_to_fp16: 4088 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4089 MVT::i16, getValue(I.getOperand(1)))); 4090 return 0; 4091 case Intrinsic::convert_from_fp16: 4092 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4093 MVT::f32, getValue(I.getOperand(1)))); 4094 return 0; 4095 case Intrinsic::pcmarker: { 4096 SDValue Tmp = getValue(I.getOperand(1)); 4097 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4098 return 0; 4099 } 4100 case Intrinsic::readcyclecounter: { 4101 SDValue Op = getRoot(); 4102 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4103 DAG.getVTList(MVT::i64, MVT::Other), 4104 &Op, 1); 4105 setValue(&I, Res); 4106 DAG.setRoot(Res.getValue(1)); 4107 return 0; 4108 } 4109 case Intrinsic::bswap: 4110 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4111 getValue(I.getOperand(1)).getValueType(), 4112 getValue(I.getOperand(1)))); 4113 return 0; 4114 case Intrinsic::cttz: { 4115 SDValue Arg = getValue(I.getOperand(1)); 4116 EVT Ty = Arg.getValueType(); 4117 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4118 return 0; 4119 } 4120 case Intrinsic::ctlz: { 4121 SDValue Arg = getValue(I.getOperand(1)); 4122 EVT Ty = Arg.getValueType(); 4123 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4124 return 0; 4125 } 4126 case Intrinsic::ctpop: { 4127 SDValue Arg = getValue(I.getOperand(1)); 4128 EVT Ty = Arg.getValueType(); 4129 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4130 return 0; 4131 } 4132 case Intrinsic::stacksave: { 4133 SDValue Op = getRoot(); 4134 Res = DAG.getNode(ISD::STACKSAVE, dl, 4135 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4136 setValue(&I, Res); 4137 DAG.setRoot(Res.getValue(1)); 4138 return 0; 4139 } 4140 case Intrinsic::stackrestore: { 4141 Res = getValue(I.getOperand(1)); 4142 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4143 return 0; 4144 } 4145 case Intrinsic::stackprotector: { 4146 // Emit code into the DAG to store the stack guard onto the stack. 4147 MachineFunction &MF = DAG.getMachineFunction(); 4148 MachineFrameInfo *MFI = MF.getFrameInfo(); 4149 EVT PtrTy = TLI.getPointerTy(); 4150 4151 SDValue Src = getValue(I.getOperand(1)); // The guard's value. 4152 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 4153 4154 int FI = FuncInfo.StaticAllocaMap[Slot]; 4155 MFI->setStackProtectorIndex(FI); 4156 4157 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4158 4159 // Store the stack protector onto the stack. 4160 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4161 PseudoSourceValue::getFixedStack(FI), 4162 0, true, false, 0); 4163 setValue(&I, Res); 4164 DAG.setRoot(Res); 4165 return 0; 4166 } 4167 case Intrinsic::objectsize: { 4168 // If we don't know by now, we're never going to know. 4169 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 4170 4171 assert(CI && "Non-constant type in __builtin_object_size?"); 4172 4173 SDValue Arg = getValue(I.getOperand(0)); 4174 EVT Ty = Arg.getValueType(); 4175 4176 if (CI->getZExtValue() == 0) 4177 Res = DAG.getConstant(-1ULL, Ty); 4178 else 4179 Res = DAG.getConstant(0, Ty); 4180 4181 setValue(&I, Res); 4182 return 0; 4183 } 4184 case Intrinsic::var_annotation: 4185 // Discard annotate attributes 4186 return 0; 4187 4188 case Intrinsic::init_trampoline: { 4189 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts()); 4190 4191 SDValue Ops[6]; 4192 Ops[0] = getRoot(); 4193 Ops[1] = getValue(I.getOperand(1)); 4194 Ops[2] = getValue(I.getOperand(2)); 4195 Ops[3] = getValue(I.getOperand(3)); 4196 Ops[4] = DAG.getSrcValue(I.getOperand(1)); 4197 Ops[5] = DAG.getSrcValue(F); 4198 4199 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4200 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4201 Ops, 6); 4202 4203 setValue(&I, Res); 4204 DAG.setRoot(Res.getValue(1)); 4205 return 0; 4206 } 4207 case Intrinsic::gcroot: 4208 if (GFI) { 4209 const Value *Alloca = I.getOperand(1); 4210 const Constant *TypeMap = cast<Constant>(I.getOperand(2)); 4211 4212 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4213 GFI->addStackRoot(FI->getIndex(), TypeMap); 4214 } 4215 return 0; 4216 case Intrinsic::gcread: 4217 case Intrinsic::gcwrite: 4218 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4219 return 0; 4220 case Intrinsic::flt_rounds: 4221 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4222 return 0; 4223 case Intrinsic::trap: 4224 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4225 return 0; 4226 case Intrinsic::uadd_with_overflow: 4227 return implVisitAluOverflow(I, ISD::UADDO); 4228 case Intrinsic::sadd_with_overflow: 4229 return implVisitAluOverflow(I, ISD::SADDO); 4230 case Intrinsic::usub_with_overflow: 4231 return implVisitAluOverflow(I, ISD::USUBO); 4232 case Intrinsic::ssub_with_overflow: 4233 return implVisitAluOverflow(I, ISD::SSUBO); 4234 case Intrinsic::umul_with_overflow: 4235 return implVisitAluOverflow(I, ISD::UMULO); 4236 case Intrinsic::smul_with_overflow: 4237 return implVisitAluOverflow(I, ISD::SMULO); 4238 4239 case Intrinsic::prefetch: { 4240 SDValue Ops[4]; 4241 Ops[0] = getRoot(); 4242 Ops[1] = getValue(I.getOperand(1)); 4243 Ops[2] = getValue(I.getOperand(2)); 4244 Ops[3] = getValue(I.getOperand(3)); 4245 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4246 return 0; 4247 } 4248 4249 case Intrinsic::memory_barrier: { 4250 SDValue Ops[6]; 4251 Ops[0] = getRoot(); 4252 for (int x = 1; x < 6; ++x) 4253 Ops[x] = getValue(I.getOperand(x)); 4254 4255 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4256 return 0; 4257 } 4258 case Intrinsic::atomic_cmp_swap: { 4259 SDValue Root = getRoot(); 4260 SDValue L = 4261 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4262 getValue(I.getOperand(2)).getValueType().getSimpleVT(), 4263 Root, 4264 getValue(I.getOperand(1)), 4265 getValue(I.getOperand(2)), 4266 getValue(I.getOperand(3)), 4267 I.getOperand(1)); 4268 setValue(&I, L); 4269 DAG.setRoot(L.getValue(1)); 4270 return 0; 4271 } 4272 case Intrinsic::atomic_load_add: 4273 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4274 case Intrinsic::atomic_load_sub: 4275 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4276 case Intrinsic::atomic_load_or: 4277 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4278 case Intrinsic::atomic_load_xor: 4279 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4280 case Intrinsic::atomic_load_and: 4281 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4282 case Intrinsic::atomic_load_nand: 4283 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4284 case Intrinsic::atomic_load_max: 4285 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4286 case Intrinsic::atomic_load_min: 4287 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4288 case Intrinsic::atomic_load_umin: 4289 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4290 case Intrinsic::atomic_load_umax: 4291 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4292 case Intrinsic::atomic_swap: 4293 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4294 4295 case Intrinsic::invariant_start: 4296 case Intrinsic::lifetime_start: 4297 // Discard region information. 4298 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4299 return 0; 4300 case Intrinsic::invariant_end: 4301 case Intrinsic::lifetime_end: 4302 // Discard region information. 4303 return 0; 4304 } 4305} 4306 4307void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4308 bool isTailCall, 4309 MachineBasicBlock *LandingPad) { 4310 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4311 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4312 const Type *RetTy = FTy->getReturnType(); 4313 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4314 MCSymbol *BeginLabel = 0; 4315 4316 TargetLowering::ArgListTy Args; 4317 TargetLowering::ArgListEntry Entry; 4318 Args.reserve(CS.arg_size()); 4319 4320 // Check whether the function can return without sret-demotion. 4321 SmallVector<EVT, 4> OutVTs; 4322 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 4323 SmallVector<uint64_t, 4> Offsets; 4324 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4325 OutVTs, OutsFlags, TLI, &Offsets); 4326 4327 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4328 FTy->isVarArg(), OutVTs, OutsFlags, DAG); 4329 4330 SDValue DemoteStackSlot; 4331 4332 if (!CanLowerReturn) { 4333 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4334 FTy->getReturnType()); 4335 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4336 FTy->getReturnType()); 4337 MachineFunction &MF = DAG.getMachineFunction(); 4338 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4339 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4340 4341 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4342 Entry.Node = DemoteStackSlot; 4343 Entry.Ty = StackSlotPtrType; 4344 Entry.isSExt = false; 4345 Entry.isZExt = false; 4346 Entry.isInReg = false; 4347 Entry.isSRet = true; 4348 Entry.isNest = false; 4349 Entry.isByVal = false; 4350 Entry.Alignment = Align; 4351 Args.push_back(Entry); 4352 RetTy = Type::getVoidTy(FTy->getContext()); 4353 } 4354 4355 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4356 i != e; ++i) { 4357 SDValue ArgNode = getValue(*i); 4358 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4359 4360 unsigned attrInd = i - CS.arg_begin() + 1; 4361 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4362 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4363 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4364 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4365 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4366 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4367 Entry.Alignment = CS.getParamAlignment(attrInd); 4368 Args.push_back(Entry); 4369 } 4370 4371 if (LandingPad) { 4372 // Insert a label before the invoke call to mark the try range. This can be 4373 // used to detect deletion of the invoke via the MachineModuleInfo. 4374 BeginLabel = MMI.getContext().CreateTempSymbol(); 4375 4376 // For SjLj, keep track of which landing pads go with which invokes 4377 // so as to maintain the ordering of pads in the LSDA. 4378 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4379 if (CallSiteIndex) { 4380 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4381 // Now that the call site is handled, stop tracking it. 4382 MMI.setCurrentCallSite(0); 4383 } 4384 4385 // Both PendingLoads and PendingExports must be flushed here; 4386 // this call might not return. 4387 (void)getRoot(); 4388 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4389 } 4390 4391 // Check if target-independent constraints permit a tail call here. 4392 // Target-dependent constraints are checked within TLI.LowerCallTo. 4393 if (isTailCall && 4394 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4395 isTailCall = false; 4396 4397 std::pair<SDValue,SDValue> Result = 4398 TLI.LowerCallTo(getRoot(), RetTy, 4399 CS.paramHasAttr(0, Attribute::SExt), 4400 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4401 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4402 CS.getCallingConv(), 4403 isTailCall, 4404 !CS.getInstruction()->use_empty(), 4405 Callee, Args, DAG, getCurDebugLoc()); 4406 assert((isTailCall || Result.second.getNode()) && 4407 "Non-null chain expected with non-tail call!"); 4408 assert((Result.second.getNode() || !Result.first.getNode()) && 4409 "Null value expected with tail call!"); 4410 if (Result.first.getNode()) { 4411 setValue(CS.getInstruction(), Result.first); 4412 } else if (!CanLowerReturn && Result.second.getNode()) { 4413 // The instruction result is the result of loading from the 4414 // hidden sret parameter. 4415 SmallVector<EVT, 1> PVTs; 4416 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4417 4418 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4419 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4420 EVT PtrVT = PVTs[0]; 4421 unsigned NumValues = OutVTs.size(); 4422 SmallVector<SDValue, 4> Values(NumValues); 4423 SmallVector<SDValue, 4> Chains(NumValues); 4424 4425 for (unsigned i = 0; i < NumValues; ++i) { 4426 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4427 DemoteStackSlot, 4428 DAG.getConstant(Offsets[i], PtrVT)); 4429 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second, 4430 Add, NULL, Offsets[i], false, false, 1); 4431 Values[i] = L; 4432 Chains[i] = L.getValue(1); 4433 } 4434 4435 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4436 MVT::Other, &Chains[0], NumValues); 4437 PendingLoads.push_back(Chain); 4438 4439 // Collect the legal value parts into potentially illegal values 4440 // that correspond to the original function's return values. 4441 SmallVector<EVT, 4> RetTys; 4442 RetTy = FTy->getReturnType(); 4443 ComputeValueVTs(TLI, RetTy, RetTys); 4444 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4445 SmallVector<SDValue, 4> ReturnValues; 4446 unsigned CurReg = 0; 4447 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4448 EVT VT = RetTys[I]; 4449 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4450 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4451 4452 SDValue ReturnValue = 4453 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4454 RegisterVT, VT, AssertOp); 4455 ReturnValues.push_back(ReturnValue); 4456 CurReg += NumRegs; 4457 } 4458 4459 setValue(CS.getInstruction(), 4460 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4461 DAG.getVTList(&RetTys[0], RetTys.size()), 4462 &ReturnValues[0], ReturnValues.size())); 4463 4464 } 4465 4466 // As a special case, a null chain means that a tail call has been emitted and 4467 // the DAG root is already updated. 4468 if (Result.second.getNode()) 4469 DAG.setRoot(Result.second); 4470 else 4471 HasTailCall = true; 4472 4473 if (LandingPad) { 4474 // Insert a label at the end of the invoke call to mark the try range. This 4475 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4476 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4477 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4478 4479 // Inform MachineModuleInfo of range. 4480 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4481 } 4482} 4483 4484/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4485/// value is equal or not-equal to zero. 4486static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4487 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4488 UI != E; ++UI) { 4489 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4490 if (IC->isEquality()) 4491 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4492 if (C->isNullValue()) 4493 continue; 4494 // Unknown instruction. 4495 return false; 4496 } 4497 return true; 4498} 4499 4500static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4501 const Type *LoadTy, 4502 SelectionDAGBuilder &Builder) { 4503 4504 // Check to see if this load can be trivially constant folded, e.g. if the 4505 // input is from a string literal. 4506 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4507 // Cast pointer to the type we really want to load. 4508 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4509 PointerType::getUnqual(LoadTy)); 4510 4511 if (const Constant *LoadCst = 4512 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4513 Builder.TD)) 4514 return Builder.getValue(LoadCst); 4515 } 4516 4517 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4518 // still constant memory, the input chain can be the entry node. 4519 SDValue Root; 4520 bool ConstantMemory = false; 4521 4522 // Do not serialize (non-volatile) loads of constant memory with anything. 4523 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4524 Root = Builder.DAG.getEntryNode(); 4525 ConstantMemory = true; 4526 } else { 4527 // Do not serialize non-volatile loads against each other. 4528 Root = Builder.DAG.getRoot(); 4529 } 4530 4531 SDValue Ptr = Builder.getValue(PtrVal); 4532 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4533 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/, 4534 false /*volatile*/, 4535 false /*nontemporal*/, 1 /* align=1 */); 4536 4537 if (!ConstantMemory) 4538 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4539 return LoadVal; 4540} 4541 4542 4543/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4544/// If so, return true and lower it, otherwise return false and it will be 4545/// lowered like a normal call. 4546bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4547 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4548 if (I.getNumOperands() != 4) 4549 return false; 4550 4551 const Value *LHS = I.getOperand(1), *RHS = I.getOperand(2); 4552 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4553 !I.getOperand(3)->getType()->isIntegerTy() || 4554 !I.getType()->isIntegerTy()) 4555 return false; 4556 4557 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3)); 4558 4559 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4560 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4561 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4562 bool ActuallyDoIt = true; 4563 MVT LoadVT; 4564 const Type *LoadTy; 4565 switch (Size->getZExtValue()) { 4566 default: 4567 LoadVT = MVT::Other; 4568 LoadTy = 0; 4569 ActuallyDoIt = false; 4570 break; 4571 case 2: 4572 LoadVT = MVT::i16; 4573 LoadTy = Type::getInt16Ty(Size->getContext()); 4574 break; 4575 case 4: 4576 LoadVT = MVT::i32; 4577 LoadTy = Type::getInt32Ty(Size->getContext()); 4578 break; 4579 case 8: 4580 LoadVT = MVT::i64; 4581 LoadTy = Type::getInt64Ty(Size->getContext()); 4582 break; 4583 /* 4584 case 16: 4585 LoadVT = MVT::v4i32; 4586 LoadTy = Type::getInt32Ty(Size->getContext()); 4587 LoadTy = VectorType::get(LoadTy, 4); 4588 break; 4589 */ 4590 } 4591 4592 // This turns into unaligned loads. We only do this if the target natively 4593 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4594 // we'll only produce a small number of byte loads. 4595 4596 // Require that we can find a legal MVT, and only do this if the target 4597 // supports unaligned loads of that type. Expanding into byte loads would 4598 // bloat the code. 4599 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4600 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4601 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4602 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4603 ActuallyDoIt = false; 4604 } 4605 4606 if (ActuallyDoIt) { 4607 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4608 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4609 4610 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4611 ISD::SETNE); 4612 EVT CallVT = TLI.getValueType(I.getType(), true); 4613 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4614 return true; 4615 } 4616 } 4617 4618 4619 return false; 4620} 4621 4622 4623void SelectionDAGBuilder::visitCall(const CallInst &I) { 4624 const char *RenameFn = 0; 4625 if (Function *F = I.getCalledFunction()) { 4626 if (F->isDeclaration()) { 4627 const TargetIntrinsicInfo *II = TM.getIntrinsicInfo(); 4628 if (II) { 4629 if (unsigned IID = II->getIntrinsicID(F)) { 4630 RenameFn = visitIntrinsicCall(I, IID); 4631 if (!RenameFn) 4632 return; 4633 } 4634 } 4635 if (unsigned IID = F->getIntrinsicID()) { 4636 RenameFn = visitIntrinsicCall(I, IID); 4637 if (!RenameFn) 4638 return; 4639 } 4640 } 4641 4642 // Check for well-known libc/libm calls. If the function is internal, it 4643 // can't be a library call. 4644 if (!F->hasLocalLinkage() && F->hasName()) { 4645 StringRef Name = F->getName(); 4646 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4647 if (I.getNumOperands() == 3 && // Basic sanity checks. 4648 I.getOperand(1)->getType()->isFloatingPointTy() && 4649 I.getType() == I.getOperand(1)->getType() && 4650 I.getType() == I.getOperand(2)->getType()) { 4651 SDValue LHS = getValue(I.getOperand(1)); 4652 SDValue RHS = getValue(I.getOperand(2)); 4653 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4654 LHS.getValueType(), LHS, RHS)); 4655 return; 4656 } 4657 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4658 if (I.getNumOperands() == 2 && // Basic sanity checks. 4659 I.getOperand(1)->getType()->isFloatingPointTy() && 4660 I.getType() == I.getOperand(1)->getType()) { 4661 SDValue Tmp = getValue(I.getOperand(1)); 4662 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4663 Tmp.getValueType(), Tmp)); 4664 return; 4665 } 4666 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4667 if (I.getNumOperands() == 2 && // Basic sanity checks. 4668 I.getOperand(1)->getType()->isFloatingPointTy() && 4669 I.getType() == I.getOperand(1)->getType() && 4670 I.onlyReadsMemory()) { 4671 SDValue Tmp = getValue(I.getOperand(1)); 4672 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4673 Tmp.getValueType(), Tmp)); 4674 return; 4675 } 4676 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4677 if (I.getNumOperands() == 2 && // Basic sanity checks. 4678 I.getOperand(1)->getType()->isFloatingPointTy() && 4679 I.getType() == I.getOperand(1)->getType() && 4680 I.onlyReadsMemory()) { 4681 SDValue Tmp = getValue(I.getOperand(1)); 4682 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4683 Tmp.getValueType(), Tmp)); 4684 return; 4685 } 4686 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4687 if (I.getNumOperands() == 2 && // Basic sanity checks. 4688 I.getOperand(1)->getType()->isFloatingPointTy() && 4689 I.getType() == I.getOperand(1)->getType() && 4690 I.onlyReadsMemory()) { 4691 SDValue Tmp = getValue(I.getOperand(1)); 4692 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4693 Tmp.getValueType(), Tmp)); 4694 return; 4695 } 4696 } else if (Name == "memcmp") { 4697 if (visitMemCmpCall(I)) 4698 return; 4699 } 4700 } 4701 } else if (isa<InlineAsm>(I.getOperand(0))) { 4702 visitInlineAsm(&I); 4703 return; 4704 } 4705 4706 SDValue Callee; 4707 if (!RenameFn) 4708 Callee = getValue(I.getOperand(0)); 4709 else 4710 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 4711 4712 // Check if we can potentially perform a tail call. More detailed checking is 4713 // be done within LowerCallTo, after more information about the call is known. 4714 LowerCallTo(&I, Callee, I.isTailCall()); 4715} 4716 4717/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 4718/// this value and returns the result as a ValueVT value. This uses 4719/// Chain/Flag as the input and updates them for the output Chain/Flag. 4720/// If the Flag pointer is NULL, no flag is used. 4721SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, 4722 SDValue &Chain, SDValue *Flag) const { 4723 // Assemble the legal parts into the final values. 4724 SmallVector<SDValue, 4> Values(ValueVTs.size()); 4725 SmallVector<SDValue, 8> Parts; 4726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4727 // Copy the legal parts from the registers. 4728 EVT ValueVT = ValueVTs[Value]; 4729 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4730 EVT RegisterVT = RegVTs[Value]; 4731 4732 Parts.resize(NumRegs); 4733 for (unsigned i = 0; i != NumRegs; ++i) { 4734 SDValue P; 4735 if (Flag == 0) { 4736 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 4737 } else { 4738 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 4739 *Flag = P.getValue(2); 4740 } 4741 4742 Chain = P.getValue(1); 4743 4744 // If the source register was virtual and if we know something about it, 4745 // add an assert node. 4746 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 4747 RegisterVT.isInteger() && !RegisterVT.isVector()) { 4748 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 4749 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 4750 if (FLI.LiveOutRegInfo.size() > SlotNo) { 4751 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; 4752 4753 unsigned RegSize = RegisterVT.getSizeInBits(); 4754 unsigned NumSignBits = LOI.NumSignBits; 4755 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 4756 4757 // FIXME: We capture more information than the dag can represent. For 4758 // now, just use the tightest assertzext/assertsext possible. 4759 bool isSExt = true; 4760 EVT FromVT(MVT::Other); 4761 if (NumSignBits == RegSize) 4762 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 4763 else if (NumZeroBits >= RegSize-1) 4764 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 4765 else if (NumSignBits > RegSize-8) 4766 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 4767 else if (NumZeroBits >= RegSize-8) 4768 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 4769 else if (NumSignBits > RegSize-16) 4770 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 4771 else if (NumZeroBits >= RegSize-16) 4772 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 4773 else if (NumSignBits > RegSize-32) 4774 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 4775 else if (NumZeroBits >= RegSize-32) 4776 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 4777 4778 if (FromVT != MVT::Other) 4779 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 4780 RegisterVT, P, DAG.getValueType(FromVT)); 4781 } 4782 } 4783 4784 Parts[i] = P; 4785 } 4786 4787 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 4788 NumRegs, RegisterVT, ValueVT); 4789 Part += NumRegs; 4790 Parts.clear(); 4791 } 4792 4793 return DAG.getNode(ISD::MERGE_VALUES, dl, 4794 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 4795 &Values[0], ValueVTs.size()); 4796} 4797 4798/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 4799/// specified value into the registers specified by this object. This uses 4800/// Chain/Flag as the input and updates them for the output Chain/Flag. 4801/// If the Flag pointer is NULL, no flag is used. 4802void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 4803 SDValue &Chain, SDValue *Flag) const { 4804 // Get the list of the values's legal parts. 4805 unsigned NumRegs = Regs.size(); 4806 SmallVector<SDValue, 8> Parts(NumRegs); 4807 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 4808 EVT ValueVT = ValueVTs[Value]; 4809 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT); 4810 EVT RegisterVT = RegVTs[Value]; 4811 4812 getCopyToParts(DAG, dl, 4813 Val.getValue(Val.getResNo() + Value), 4814 &Parts[Part], NumParts, RegisterVT); 4815 Part += NumParts; 4816 } 4817 4818 // Copy the parts into the registers. 4819 SmallVector<SDValue, 8> Chains(NumRegs); 4820 for (unsigned i = 0; i != NumRegs; ++i) { 4821 SDValue Part; 4822 if (Flag == 0) { 4823 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 4824 } else { 4825 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 4826 *Flag = Part.getValue(1); 4827 } 4828 4829 Chains[i] = Part.getValue(0); 4830 } 4831 4832 if (NumRegs == 1 || Flag) 4833 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 4834 // flagged to it. That is the CopyToReg nodes and the user are considered 4835 // a single scheduling unit. If we create a TokenFactor and return it as 4836 // chain, then the TokenFactor is both a predecessor (operand) of the 4837 // user as well as a successor (the TF operands are flagged to the user). 4838 // c1, f1 = CopyToReg 4839 // c2, f2 = CopyToReg 4840 // c3 = TokenFactor c1, c2 4841 // ... 4842 // = op c3, ..., f2 4843 Chain = Chains[NumRegs-1]; 4844 else 4845 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 4846} 4847 4848/// AddInlineAsmOperands - Add this value to the specified inlineasm node 4849/// operand list. This adds the code marker and includes the number of 4850/// values added into it. 4851void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 4852 unsigned MatchingIdx, 4853 SelectionDAG &DAG, 4854 std::vector<SDValue> &Ops) const { 4855 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 4856 if (HasMatching) 4857 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 4858 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 4859 Ops.push_back(Res); 4860 4861 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 4862 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 4863 EVT RegisterVT = RegVTs[Value]; 4864 for (unsigned i = 0; i != NumRegs; ++i) { 4865 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 4866 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 4867 } 4868 } 4869} 4870 4871/// isAllocatableRegister - If the specified register is safe to allocate, 4872/// i.e. it isn't a stack pointer or some other special register, return the 4873/// register class for the register. Otherwise, return null. 4874static const TargetRegisterClass * 4875isAllocatableRegister(unsigned Reg, MachineFunction &MF, 4876 const TargetLowering &TLI, 4877 const TargetRegisterInfo *TRI) { 4878 EVT FoundVT = MVT::Other; 4879 const TargetRegisterClass *FoundRC = 0; 4880 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 4881 E = TRI->regclass_end(); RCI != E; ++RCI) { 4882 EVT ThisVT = MVT::Other; 4883 4884 const TargetRegisterClass *RC = *RCI; 4885 // If none of the value types for this register class are valid, we 4886 // can't use it. For example, 64-bit reg classes on 32-bit targets. 4887 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 4888 I != E; ++I) { 4889 if (TLI.isTypeLegal(*I)) { 4890 // If we have already found this register in a different register class, 4891 // choose the one with the largest VT specified. For example, on 4892 // PowerPC, we favor f64 register classes over f32. 4893 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 4894 ThisVT = *I; 4895 break; 4896 } 4897 } 4898 } 4899 4900 if (ThisVT == MVT::Other) continue; 4901 4902 // NOTE: This isn't ideal. In particular, this might allocate the 4903 // frame pointer in functions that need it (due to them not being taken 4904 // out of allocation, because a variable sized allocation hasn't been seen 4905 // yet). This is a slight code pessimization, but should still work. 4906 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 4907 E = RC->allocation_order_end(MF); I != E; ++I) 4908 if (*I == Reg) { 4909 // We found a matching register class. Keep looking at others in case 4910 // we find one with larger registers that this physreg is also in. 4911 FoundRC = RC; 4912 FoundVT = ThisVT; 4913 break; 4914 } 4915 } 4916 return FoundRC; 4917} 4918 4919 4920namespace llvm { 4921/// AsmOperandInfo - This contains information for each constraint that we are 4922/// lowering. 4923class VISIBILITY_HIDDEN SDISelAsmOperandInfo : 4924 public TargetLowering::AsmOperandInfo { 4925public: 4926 /// CallOperand - If this is the result output operand or a clobber 4927 /// this is null, otherwise it is the incoming operand to the CallInst. 4928 /// This gets modified as the asm is processed. 4929 SDValue CallOperand; 4930 4931 /// AssignedRegs - If this is a register or register class operand, this 4932 /// contains the set of register corresponding to the operand. 4933 RegsForValue AssignedRegs; 4934 4935 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) 4936 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 4937 } 4938 4939 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 4940 /// busy in OutputRegs/InputRegs. 4941 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 4942 std::set<unsigned> &OutputRegs, 4943 std::set<unsigned> &InputRegs, 4944 const TargetRegisterInfo &TRI) const { 4945 if (isOutReg) { 4946 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4947 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 4948 } 4949 if (isInReg) { 4950 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 4951 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 4952 } 4953 } 4954 4955 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 4956 /// corresponds to. If there is no Value* for this operand, it returns 4957 /// MVT::Other. 4958 EVT getCallOperandValEVT(LLVMContext &Context, 4959 const TargetLowering &TLI, 4960 const TargetData *TD) const { 4961 if (CallOperandVal == 0) return MVT::Other; 4962 4963 if (isa<BasicBlock>(CallOperandVal)) 4964 return TLI.getPointerTy(); 4965 4966 const llvm::Type *OpTy = CallOperandVal->getType(); 4967 4968 // If this is an indirect operand, the operand is a pointer to the 4969 // accessed type. 4970 if (isIndirect) { 4971 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 4972 if (!PtrTy) 4973 report_fatal_error("Indirect operand for inline asm not a pointer!"); 4974 OpTy = PtrTy->getElementType(); 4975 } 4976 4977 // If OpTy is not a single value, it may be a struct/union that we 4978 // can tile with integers. 4979 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 4980 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 4981 switch (BitSize) { 4982 default: break; 4983 case 1: 4984 case 8: 4985 case 16: 4986 case 32: 4987 case 64: 4988 case 128: 4989 OpTy = IntegerType::get(Context, BitSize); 4990 break; 4991 } 4992 } 4993 4994 return TLI.getValueType(OpTy, true); 4995 } 4996 4997private: 4998 /// MarkRegAndAliases - Mark the specified register and all aliases in the 4999 /// specified set. 5000 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5001 const TargetRegisterInfo &TRI) { 5002 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5003 Regs.insert(Reg); 5004 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5005 for (; *Aliases; ++Aliases) 5006 Regs.insert(*Aliases); 5007 } 5008}; 5009} // end llvm namespace. 5010 5011 5012/// GetRegistersForValue - Assign registers (virtual or physical) for the 5013/// specified operand. We prefer to assign virtual registers, to allow the 5014/// register allocator to handle the assignment process. However, if the asm 5015/// uses features that we can't model on machineinstrs, we have SDISel do the 5016/// allocation. This produces generally horrible, but correct, code. 5017/// 5018/// OpInfo describes the operand. 5019/// Input and OutputRegs are the set of already allocated physical registers. 5020/// 5021void SelectionDAGBuilder:: 5022GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5023 std::set<unsigned> &OutputRegs, 5024 std::set<unsigned> &InputRegs) { 5025 LLVMContext &Context = FuncInfo.Fn->getContext(); 5026 5027 // Compute whether this value requires an input register, an output register, 5028 // or both. 5029 bool isOutReg = false; 5030 bool isInReg = false; 5031 switch (OpInfo.Type) { 5032 case InlineAsm::isOutput: 5033 isOutReg = true; 5034 5035 // If there is an input constraint that matches this, we need to reserve 5036 // the input register so no other inputs allocate to it. 5037 isInReg = OpInfo.hasMatchingInput(); 5038 break; 5039 case InlineAsm::isInput: 5040 isInReg = true; 5041 isOutReg = false; 5042 break; 5043 case InlineAsm::isClobber: 5044 isOutReg = true; 5045 isInReg = true; 5046 break; 5047 } 5048 5049 5050 MachineFunction &MF = DAG.getMachineFunction(); 5051 SmallVector<unsigned, 4> Regs; 5052 5053 // If this is a constraint for a single physreg, or a constraint for a 5054 // register class, find it. 5055 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5056 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5057 OpInfo.ConstraintVT); 5058 5059 unsigned NumRegs = 1; 5060 if (OpInfo.ConstraintVT != MVT::Other) { 5061 // If this is a FP input in an integer register (or visa versa) insert a bit 5062 // cast of the input value. More generally, handle any case where the input 5063 // value disagrees with the register class we plan to stick this in. 5064 if (OpInfo.Type == InlineAsm::isInput && 5065 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5066 // Try to convert to the first EVT that the reg class contains. If the 5067 // types are identical size, use a bitcast to convert (e.g. two differing 5068 // vector types). 5069 EVT RegVT = *PhysReg.second->vt_begin(); 5070 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5071 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5072 RegVT, OpInfo.CallOperand); 5073 OpInfo.ConstraintVT = RegVT; 5074 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5075 // If the input is a FP value and we want it in FP registers, do a 5076 // bitcast to the corresponding integer type. This turns an f64 value 5077 // into i64, which can be passed with two i32 values on a 32-bit 5078 // machine. 5079 RegVT = EVT::getIntegerVT(Context, 5080 OpInfo.ConstraintVT.getSizeInBits()); 5081 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5082 RegVT, OpInfo.CallOperand); 5083 OpInfo.ConstraintVT = RegVT; 5084 } 5085 } 5086 5087 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5088 } 5089 5090 EVT RegVT; 5091 EVT ValueVT = OpInfo.ConstraintVT; 5092 5093 // If this is a constraint for a specific physical register, like {r17}, 5094 // assign it now. 5095 if (unsigned AssignedReg = PhysReg.first) { 5096 const TargetRegisterClass *RC = PhysReg.second; 5097 if (OpInfo.ConstraintVT == MVT::Other) 5098 ValueVT = *RC->vt_begin(); 5099 5100 // Get the actual register value type. This is important, because the user 5101 // may have asked for (e.g.) the AX register in i32 type. We need to 5102 // remember that AX is actually i16 to get the right extension. 5103 RegVT = *RC->vt_begin(); 5104 5105 // This is a explicit reference to a physical register. 5106 Regs.push_back(AssignedReg); 5107 5108 // If this is an expanded reference, add the rest of the regs to Regs. 5109 if (NumRegs != 1) { 5110 TargetRegisterClass::iterator I = RC->begin(); 5111 for (; *I != AssignedReg; ++I) 5112 assert(I != RC->end() && "Didn't find reg!"); 5113 5114 // Already added the first reg. 5115 --NumRegs; ++I; 5116 for (; NumRegs; --NumRegs, ++I) { 5117 assert(I != RC->end() && "Ran out of registers to allocate!"); 5118 Regs.push_back(*I); 5119 } 5120 } 5121 5122 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5123 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5124 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5125 return; 5126 } 5127 5128 // Otherwise, if this was a reference to an LLVM register class, create vregs 5129 // for this reference. 5130 if (const TargetRegisterClass *RC = PhysReg.second) { 5131 RegVT = *RC->vt_begin(); 5132 if (OpInfo.ConstraintVT == MVT::Other) 5133 ValueVT = RegVT; 5134 5135 // Create the appropriate number of virtual registers. 5136 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5137 for (; NumRegs; --NumRegs) 5138 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5139 5140 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); 5141 return; 5142 } 5143 5144 // This is a reference to a register class that doesn't directly correspond 5145 // to an LLVM register class. Allocate NumRegs consecutive, available, 5146 // registers from the class. 5147 std::vector<unsigned> RegClassRegs 5148 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5149 OpInfo.ConstraintVT); 5150 5151 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5152 unsigned NumAllocated = 0; 5153 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5154 unsigned Reg = RegClassRegs[i]; 5155 // See if this register is available. 5156 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5157 (isInReg && InputRegs.count(Reg))) { // Already used. 5158 // Make sure we find consecutive registers. 5159 NumAllocated = 0; 5160 continue; 5161 } 5162 5163 // Check to see if this register is allocatable (i.e. don't give out the 5164 // stack pointer). 5165 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5166 if (!RC) { // Couldn't allocate this register. 5167 // Reset NumAllocated to make sure we return consecutive registers. 5168 NumAllocated = 0; 5169 continue; 5170 } 5171 5172 // Okay, this register is good, we can use it. 5173 ++NumAllocated; 5174 5175 // If we allocated enough consecutive registers, succeed. 5176 if (NumAllocated == NumRegs) { 5177 unsigned RegStart = (i-NumAllocated)+1; 5178 unsigned RegEnd = i+1; 5179 // Mark all of the allocated registers used. 5180 for (unsigned i = RegStart; i != RegEnd; ++i) 5181 Regs.push_back(RegClassRegs[i]); 5182 5183 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), 5184 OpInfo.ConstraintVT); 5185 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5186 return; 5187 } 5188 } 5189 5190 // Otherwise, we couldn't allocate enough registers for this. 5191} 5192 5193/// visitInlineAsm - Handle a call to an InlineAsm object. 5194/// 5195void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5196 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5197 5198 /// ConstraintOperands - Information about all of the constraints. 5199 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5200 5201 std::set<unsigned> OutputRegs, InputRegs; 5202 5203 // Do a prepass over the constraints, canonicalizing them, and building up the 5204 // ConstraintOperands list. 5205 std::vector<InlineAsm::ConstraintInfo> 5206 ConstraintInfos = IA->ParseConstraints(); 5207 5208 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); 5209 5210 SDValue Chain, Flag; 5211 5212 // We won't need to flush pending loads if this asm doesn't touch 5213 // memory and is nonvolatile. 5214 if (hasMemory || IA->hasSideEffects()) 5215 Chain = getRoot(); 5216 else 5217 Chain = DAG.getRoot(); 5218 5219 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5220 unsigned ResNo = 0; // ResNo - The result number of the next output. 5221 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5222 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); 5223 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5224 5225 EVT OpVT = MVT::Other; 5226 5227 // Compute the value type for each operand. 5228 switch (OpInfo.Type) { 5229 case InlineAsm::isOutput: 5230 // Indirect outputs just consume an argument. 5231 if (OpInfo.isIndirect) { 5232 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5233 break; 5234 } 5235 5236 // The return value of the call is this value. As such, there is no 5237 // corresponding argument. 5238 assert(!CS.getType()->isVoidTy() && 5239 "Bad inline asm!"); 5240 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5241 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5242 } else { 5243 assert(ResNo == 0 && "Asm only has one result!"); 5244 OpVT = TLI.getValueType(CS.getType()); 5245 } 5246 ++ResNo; 5247 break; 5248 case InlineAsm::isInput: 5249 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5250 break; 5251 case InlineAsm::isClobber: 5252 // Nothing to do. 5253 break; 5254 } 5255 5256 // If this is an input or an indirect output, process the call argument. 5257 // BasicBlocks are labels, currently appearing only in asm's. 5258 if (OpInfo.CallOperandVal) { 5259 // Strip bitcasts, if any. This mostly comes up for functions. 5260 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5261 5262 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5263 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5264 } else { 5265 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5266 } 5267 5268 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5269 } 5270 5271 OpInfo.ConstraintVT = OpVT; 5272 } 5273 5274 // Second pass over the constraints: compute which constraint option to use 5275 // and assign registers to constraints that want a specific physreg. 5276 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 5277 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5278 5279 // If this is an output operand with a matching input operand, look up the 5280 // matching input. If their types mismatch, e.g. one is an integer, the 5281 // other is floating point, or their sizes are different, flag it as an 5282 // error. 5283 if (OpInfo.hasMatchingInput()) { 5284 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5285 5286 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5287 if ((OpInfo.ConstraintVT.isInteger() != 5288 Input.ConstraintVT.isInteger()) || 5289 (OpInfo.ConstraintVT.getSizeInBits() != 5290 Input.ConstraintVT.getSizeInBits())) { 5291 report_fatal_error("Unsupported asm: input constraint" 5292 " with a matching output constraint of" 5293 " incompatible type!"); 5294 } 5295 Input.ConstraintVT = OpInfo.ConstraintVT; 5296 } 5297 } 5298 5299 // Compute the constraint code and ConstraintType to use. 5300 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG); 5301 5302 // If this is a memory input, and if the operand is not indirect, do what we 5303 // need to to provide an address for the memory input. 5304 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5305 !OpInfo.isIndirect) { 5306 assert(OpInfo.Type == InlineAsm::isInput && 5307 "Can only indirectify direct input operands!"); 5308 5309 // Memory operands really want the address of the value. If we don't have 5310 // an indirect input, put it in the constpool if we can, otherwise spill 5311 // it to a stack slot. 5312 5313 // If the operand is a float, integer, or vector constant, spill to a 5314 // constant pool entry to get its address. 5315 const Value *OpVal = OpInfo.CallOperandVal; 5316 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5317 isa<ConstantVector>(OpVal)) { 5318 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5319 TLI.getPointerTy()); 5320 } else { 5321 // Otherwise, create a stack slot and emit a store to it before the 5322 // asm. 5323 const Type *Ty = OpVal->getType(); 5324 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5325 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5326 MachineFunction &MF = DAG.getMachineFunction(); 5327 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5328 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5329 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5330 OpInfo.CallOperand, StackSlot, NULL, 0, 5331 false, false, 0); 5332 OpInfo.CallOperand = StackSlot; 5333 } 5334 5335 // There is no longer a Value* corresponding to this operand. 5336 OpInfo.CallOperandVal = 0; 5337 5338 // It is now an indirect operand. 5339 OpInfo.isIndirect = true; 5340 } 5341 5342 // If this constraint is for a specific register, allocate it before 5343 // anything else. 5344 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5345 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5346 } 5347 5348 ConstraintInfos.clear(); 5349 5350 // Second pass - Loop over all of the operands, assigning virtual or physregs 5351 // to register class operands. 5352 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5353 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5354 5355 // C_Register operands have already been allocated, Other/Memory don't need 5356 // to be. 5357 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5358 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5359 } 5360 5361 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5362 std::vector<SDValue> AsmNodeOperands; 5363 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5364 AsmNodeOperands.push_back( 5365 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5366 TLI.getPointerTy())); 5367 5368 // If we have a !srcloc metadata node associated with it, we want to attach 5369 // this to the ultimately generated inline asm machineinstr. To do this, we 5370 // pass in the third operand as this (potentially null) inline asm MDNode. 5371 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5372 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5373 5374 // Loop over all of the inputs, copying the operand values into the 5375 // appropriate registers and processing the output regs. 5376 RegsForValue RetValRegs; 5377 5378 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5379 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5380 5381 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5382 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5383 5384 switch (OpInfo.Type) { 5385 case InlineAsm::isOutput: { 5386 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5387 OpInfo.ConstraintType != TargetLowering::C_Register) { 5388 // Memory output, or 'other' output (e.g. 'X' constraint). 5389 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5390 5391 // Add information to the INLINEASM node to know about this output. 5392 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5393 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5394 TLI.getPointerTy())); 5395 AsmNodeOperands.push_back(OpInfo.CallOperand); 5396 break; 5397 } 5398 5399 // Otherwise, this is a register or register class output. 5400 5401 // Copy the output from the appropriate register. Find a register that 5402 // we can use. 5403 if (OpInfo.AssignedRegs.Regs.empty()) 5404 report_fatal_error("Couldn't allocate output reg for constraint '" + 5405 Twine(OpInfo.ConstraintCode) + "'!"); 5406 5407 // If this is an indirect operand, store through the pointer after the 5408 // asm. 5409 if (OpInfo.isIndirect) { 5410 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5411 OpInfo.CallOperandVal)); 5412 } else { 5413 // This is the result value of the call. 5414 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5415 // Concatenate this output onto the outputs list. 5416 RetValRegs.append(OpInfo.AssignedRegs); 5417 } 5418 5419 // Add information to the INLINEASM node to know that this register is 5420 // set. 5421 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5422 InlineAsm::Kind_RegDefEarlyClobber : 5423 InlineAsm::Kind_RegDef, 5424 false, 5425 0, 5426 DAG, 5427 AsmNodeOperands); 5428 break; 5429 } 5430 case InlineAsm::isInput: { 5431 SDValue InOperandVal = OpInfo.CallOperand; 5432 5433 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5434 // If this is required to match an output register we have already set, 5435 // just use its register. 5436 unsigned OperandNo = OpInfo.getMatchedOperand(); 5437 5438 // Scan until we find the definition we already emitted of this operand. 5439 // When we find it, create a RegsForValue operand. 5440 unsigned CurOp = InlineAsm::Op_FirstOperand; 5441 for (; OperandNo; --OperandNo) { 5442 // Advance to the next operand. 5443 unsigned OpFlag = 5444 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5445 assert((InlineAsm::isRegDefKind(OpFlag) || 5446 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5447 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5448 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5449 } 5450 5451 unsigned OpFlag = 5452 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5453 if (InlineAsm::isRegDefKind(OpFlag) || 5454 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5455 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5456 if (OpInfo.isIndirect) { 5457 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5458 LLVMContext &Ctx = *DAG.getContext(); 5459 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5460 " don't know how to handle tied " 5461 "indirect register inputs"); 5462 } 5463 5464 RegsForValue MatchedRegs; 5465 MatchedRegs.TLI = &TLI; 5466 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5467 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5468 MatchedRegs.RegVTs.push_back(RegVT); 5469 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5470 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5471 i != e; ++i) 5472 MatchedRegs.Regs.push_back 5473 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5474 5475 // Use the produced MatchedRegs object to 5476 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5477 Chain, &Flag); 5478 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5479 true, OpInfo.getMatchedOperand(), 5480 DAG, AsmNodeOperands); 5481 break; 5482 } 5483 5484 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5485 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5486 "Unexpected number of operands"); 5487 // Add information to the INLINEASM node to know about this input. 5488 // See InlineAsm.h isUseOperandTiedToDef. 5489 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5490 OpInfo.getMatchedOperand()); 5491 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5492 TLI.getPointerTy())); 5493 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5494 break; 5495 } 5496 5497 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5498 assert(!OpInfo.isIndirect && 5499 "Don't know how to handle indirect other inputs yet!"); 5500 5501 std::vector<SDValue> Ops; 5502 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5503 hasMemory, Ops, DAG); 5504 if (Ops.empty()) 5505 report_fatal_error("Invalid operand for inline asm constraint '" + 5506 Twine(OpInfo.ConstraintCode) + "'!"); 5507 5508 // Add information to the INLINEASM node to know about this input. 5509 unsigned ResOpType = 5510 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5511 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5512 TLI.getPointerTy())); 5513 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5514 break; 5515 } 5516 5517 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5518 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5519 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5520 "Memory operands expect pointer values"); 5521 5522 // Add information to the INLINEASM node to know about this input. 5523 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5524 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5525 TLI.getPointerTy())); 5526 AsmNodeOperands.push_back(InOperandVal); 5527 break; 5528 } 5529 5530 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5531 OpInfo.ConstraintType == TargetLowering::C_Register) && 5532 "Unknown constraint type!"); 5533 assert(!OpInfo.isIndirect && 5534 "Don't know how to handle indirect register inputs yet!"); 5535 5536 // Copy the input into the appropriate registers. 5537 if (OpInfo.AssignedRegs.Regs.empty() || 5538 !OpInfo.AssignedRegs.areValueTypesLegal()) 5539 report_fatal_error("Couldn't allocate input reg for constraint '" + 5540 Twine(OpInfo.ConstraintCode) + "'!"); 5541 5542 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5543 Chain, &Flag); 5544 5545 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5546 DAG, AsmNodeOperands); 5547 break; 5548 } 5549 case InlineAsm::isClobber: { 5550 // Add the clobbered value to the operand list, so that the register 5551 // allocator is aware that the physreg got clobbered. 5552 if (!OpInfo.AssignedRegs.Regs.empty()) 5553 OpInfo.AssignedRegs.AddInlineAsmOperands( 5554 InlineAsm::Kind_RegDefEarlyClobber, 5555 false, 0, DAG, 5556 AsmNodeOperands); 5557 break; 5558 } 5559 } 5560 } 5561 5562 // Finish up input operands. Set the input chain and add the flag last. 5563 AsmNodeOperands[0] = Chain; 5564 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5565 5566 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5567 DAG.getVTList(MVT::Other, MVT::Flag), 5568 &AsmNodeOperands[0], AsmNodeOperands.size()); 5569 Flag = Chain.getValue(1); 5570 5571 // If this asm returns a register value, copy the result from that register 5572 // and set it as the value of the call. 5573 if (!RetValRegs.Regs.empty()) { 5574 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5575 Chain, &Flag); 5576 5577 // FIXME: Why don't we do this for inline asms with MRVs? 5578 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5579 EVT ResultType = TLI.getValueType(CS.getType()); 5580 5581 // If any of the results of the inline asm is a vector, it may have the 5582 // wrong width/num elts. This can happen for register classes that can 5583 // contain multiple different value types. The preg or vreg allocated may 5584 // not have the same VT as was expected. Convert it to the right type 5585 // with bit_convert. 5586 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5587 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5588 ResultType, Val); 5589 5590 } else if (ResultType != Val.getValueType() && 5591 ResultType.isInteger() && Val.getValueType().isInteger()) { 5592 // If a result value was tied to an input value, the computed result may 5593 // have a wider width than the expected result. Extract the relevant 5594 // portion. 5595 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5596 } 5597 5598 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5599 } 5600 5601 setValue(CS.getInstruction(), Val); 5602 // Don't need to use this as a chain in this case. 5603 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5604 return; 5605 } 5606 5607 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5608 5609 // Process indirect outputs, first output all of the flagged copies out of 5610 // physregs. 5611 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5612 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5613 const Value *Ptr = IndirectStoresToEmit[i].second; 5614 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), 5615 Chain, &Flag); 5616 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5617 } 5618 5619 // Emit the non-flagged stores from the physregs. 5620 SmallVector<SDValue, 8> OutChains; 5621 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5622 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5623 StoresToEmit[i].first, 5624 getValue(StoresToEmit[i].second), 5625 StoresToEmit[i].second, 0, 5626 false, false, 0); 5627 OutChains.push_back(Val); 5628 } 5629 5630 if (!OutChains.empty()) 5631 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5632 &OutChains[0], OutChains.size()); 5633 5634 DAG.setRoot(Chain); 5635} 5636 5637void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5638 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5639 MVT::Other, getRoot(), 5640 getValue(I.getOperand(1)), 5641 DAG.getSrcValue(I.getOperand(1)))); 5642} 5643 5644void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5645 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5646 getRoot(), getValue(I.getOperand(0)), 5647 DAG.getSrcValue(I.getOperand(0))); 5648 setValue(&I, V); 5649 DAG.setRoot(V.getValue(1)); 5650} 5651 5652void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5653 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5654 MVT::Other, getRoot(), 5655 getValue(I.getOperand(1)), 5656 DAG.getSrcValue(I.getOperand(1)))); 5657} 5658 5659void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5660 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5661 MVT::Other, getRoot(), 5662 getValue(I.getOperand(1)), 5663 getValue(I.getOperand(2)), 5664 DAG.getSrcValue(I.getOperand(1)), 5665 DAG.getSrcValue(I.getOperand(2)))); 5666} 5667 5668/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5669/// implementation, which just calls LowerCall. 5670/// FIXME: When all targets are 5671/// migrated to using LowerCall, this hook should be integrated into SDISel. 5672std::pair<SDValue, SDValue> 5673TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5674 bool RetSExt, bool RetZExt, bool isVarArg, 5675 bool isInreg, unsigned NumFixedArgs, 5676 CallingConv::ID CallConv, bool isTailCall, 5677 bool isReturnValueUsed, 5678 SDValue Callee, 5679 ArgListTy &Args, SelectionDAG &DAG, 5680 DebugLoc dl) const { 5681 // Handle all of the outgoing arguments. 5682 SmallVector<ISD::OutputArg, 32> Outs; 5683 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5684 SmallVector<EVT, 4> ValueVTs; 5685 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5686 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5687 Value != NumValues; ++Value) { 5688 EVT VT = ValueVTs[Value]; 5689 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5690 SDValue Op = SDValue(Args[i].Node.getNode(), 5691 Args[i].Node.getResNo() + Value); 5692 ISD::ArgFlagsTy Flags; 5693 unsigned OriginalAlignment = 5694 getTargetData()->getABITypeAlignment(ArgTy); 5695 5696 if (Args[i].isZExt) 5697 Flags.setZExt(); 5698 if (Args[i].isSExt) 5699 Flags.setSExt(); 5700 if (Args[i].isInReg) 5701 Flags.setInReg(); 5702 if (Args[i].isSRet) 5703 Flags.setSRet(); 5704 if (Args[i].isByVal) { 5705 Flags.setByVal(); 5706 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5707 const Type *ElementTy = Ty->getElementType(); 5708 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5709 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5710 // For ByVal, alignment should come from FE. BE will guess if this 5711 // info is not there but there are cases it cannot get right. 5712 if (Args[i].Alignment) 5713 FrameAlign = Args[i].Alignment; 5714 Flags.setByValAlign(FrameAlign); 5715 Flags.setByValSize(FrameSize); 5716 } 5717 if (Args[i].isNest) 5718 Flags.setNest(); 5719 Flags.setOrigAlign(OriginalAlignment); 5720 5721 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5722 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5723 SmallVector<SDValue, 4> Parts(NumParts); 5724 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5725 5726 if (Args[i].isSExt) 5727 ExtendKind = ISD::SIGN_EXTEND; 5728 else if (Args[i].isZExt) 5729 ExtendKind = ISD::ZERO_EXTEND; 5730 5731 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5732 PartVT, ExtendKind); 5733 5734 for (unsigned j = 0; j != NumParts; ++j) { 5735 // if it isn't first piece, alignment must be 1 5736 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs); 5737 if (NumParts > 1 && j == 0) 5738 MyFlags.Flags.setSplit(); 5739 else if (j != 0) 5740 MyFlags.Flags.setOrigAlign(1); 5741 5742 Outs.push_back(MyFlags); 5743 } 5744 } 5745 } 5746 5747 // Handle the incoming return values from the call. 5748 SmallVector<ISD::InputArg, 32> Ins; 5749 SmallVector<EVT, 4> RetTys; 5750 ComputeValueVTs(*this, RetTy, RetTys); 5751 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5752 EVT VT = RetTys[I]; 5753 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5754 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5755 for (unsigned i = 0; i != NumRegs; ++i) { 5756 ISD::InputArg MyFlags; 5757 MyFlags.VT = RegisterVT; 5758 MyFlags.Used = isReturnValueUsed; 5759 if (RetSExt) 5760 MyFlags.Flags.setSExt(); 5761 if (RetZExt) 5762 MyFlags.Flags.setZExt(); 5763 if (isInreg) 5764 MyFlags.Flags.setInReg(); 5765 Ins.push_back(MyFlags); 5766 } 5767 } 5768 5769 SmallVector<SDValue, 4> InVals; 5770 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5771 Outs, Ins, dl, DAG, InVals); 5772 5773 // Verify that the target's LowerCall behaved as expected. 5774 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5775 "LowerCall didn't return a valid chain!"); 5776 assert((!isTailCall || InVals.empty()) && 5777 "LowerCall emitted a return value for a tail call!"); 5778 assert((isTailCall || InVals.size() == Ins.size()) && 5779 "LowerCall didn't emit the correct number of values!"); 5780 5781 // For a tail call, the return value is merely live-out and there aren't 5782 // any nodes in the DAG representing it. Return a special value to 5783 // indicate that a tail call has been emitted and no more Instructions 5784 // should be processed in the current block. 5785 if (isTailCall) { 5786 DAG.setRoot(Chain); 5787 return std::make_pair(SDValue(), SDValue()); 5788 } 5789 5790 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5791 assert(InVals[i].getNode() && 5792 "LowerCall emitted a null value!"); 5793 assert(Ins[i].VT == InVals[i].getValueType() && 5794 "LowerCall emitted a value with the wrong type!"); 5795 }); 5796 5797 // Collect the legal value parts into potentially illegal values 5798 // that correspond to the original function's return values. 5799 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5800 if (RetSExt) 5801 AssertOp = ISD::AssertSext; 5802 else if (RetZExt) 5803 AssertOp = ISD::AssertZext; 5804 SmallVector<SDValue, 4> ReturnValues; 5805 unsigned CurReg = 0; 5806 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5807 EVT VT = RetTys[I]; 5808 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5809 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5810 5811 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5812 NumRegs, RegisterVT, VT, 5813 AssertOp)); 5814 CurReg += NumRegs; 5815 } 5816 5817 // For a function returning void, there is no return value. We can't create 5818 // such a node, so we just return a null return value in that case. In 5819 // that case, nothing will actualy look at the value. 5820 if (ReturnValues.empty()) 5821 return std::make_pair(SDValue(), Chain); 5822 5823 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5824 DAG.getVTList(&RetTys[0], RetTys.size()), 5825 &ReturnValues[0], ReturnValues.size()); 5826 return std::make_pair(Res, Chain); 5827} 5828 5829void TargetLowering::LowerOperationWrapper(SDNode *N, 5830 SmallVectorImpl<SDValue> &Results, 5831 SelectionDAG &DAG) const { 5832 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5833 if (Res.getNode()) 5834 Results.push_back(Res); 5835} 5836 5837SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5838 llvm_unreachable("LowerOperation not implemented for this target!"); 5839 return SDValue(); 5840} 5841 5842void 5843SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 5844 SDValue Op = getValue(V); 5845 assert((Op.getOpcode() != ISD::CopyFromReg || 5846 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5847 "Copy from a reg to the same reg!"); 5848 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5849 5850 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5851 SDValue Chain = DAG.getEntryNode(); 5852 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5853 PendingExports.push_back(Chain); 5854} 5855 5856#include "llvm/CodeGen/SelectionDAGISel.h" 5857 5858void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 5859 // If this is the entry block, emit arguments. 5860 const Function &F = *LLVMBB->getParent(); 5861 SelectionDAG &DAG = SDB->DAG; 5862 SDValue OldRoot = DAG.getRoot(); 5863 DebugLoc dl = SDB->getCurDebugLoc(); 5864 const TargetData *TD = TLI.getTargetData(); 5865 SmallVector<ISD::InputArg, 16> Ins; 5866 5867 // Check whether the function can return without sret-demotion. 5868 SmallVector<EVT, 4> OutVTs; 5869 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; 5870 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 5871 OutVTs, OutsFlags, TLI); 5872 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); 5873 5874 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), 5875 OutVTs, OutsFlags, DAG); 5876 if (!FLI.CanLowerReturn) { 5877 // Put in an sret pointer parameter before all the other parameters. 5878 SmallVector<EVT, 1> ValueVTs; 5879 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5880 5881 // NOTE: Assuming that a pointer will never break down to more than one VT 5882 // or one register. 5883 ISD::ArgFlagsTy Flags; 5884 Flags.setSRet(); 5885 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 5886 ISD::InputArg RetArg(Flags, RegisterVT, true); 5887 Ins.push_back(RetArg); 5888 } 5889 5890 // Set up the incoming argument description vector. 5891 unsigned Idx = 1; 5892 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 5893 I != E; ++I, ++Idx) { 5894 SmallVector<EVT, 4> ValueVTs; 5895 ComputeValueVTs(TLI, I->getType(), ValueVTs); 5896 bool isArgValueUsed = !I->use_empty(); 5897 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5898 Value != NumValues; ++Value) { 5899 EVT VT = ValueVTs[Value]; 5900 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 5901 ISD::ArgFlagsTy Flags; 5902 unsigned OriginalAlignment = 5903 TD->getABITypeAlignment(ArgTy); 5904 5905 if (F.paramHasAttr(Idx, Attribute::ZExt)) 5906 Flags.setZExt(); 5907 if (F.paramHasAttr(Idx, Attribute::SExt)) 5908 Flags.setSExt(); 5909 if (F.paramHasAttr(Idx, Attribute::InReg)) 5910 Flags.setInReg(); 5911 if (F.paramHasAttr(Idx, Attribute::StructRet)) 5912 Flags.setSRet(); 5913 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 5914 Flags.setByVal(); 5915 const PointerType *Ty = cast<PointerType>(I->getType()); 5916 const Type *ElementTy = Ty->getElementType(); 5917 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 5918 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 5919 // For ByVal, alignment should be passed from FE. BE will guess if 5920 // this info is not there but there are cases it cannot get right. 5921 if (F.getParamAlignment(Idx)) 5922 FrameAlign = F.getParamAlignment(Idx); 5923 Flags.setByValAlign(FrameAlign); 5924 Flags.setByValSize(FrameSize); 5925 } 5926 if (F.paramHasAttr(Idx, Attribute::Nest)) 5927 Flags.setNest(); 5928 Flags.setOrigAlign(OriginalAlignment); 5929 5930 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5931 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 5932 for (unsigned i = 0; i != NumRegs; ++i) { 5933 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 5934 if (NumRegs > 1 && i == 0) 5935 MyFlags.Flags.setSplit(); 5936 // if it isn't first piece, alignment must be 1 5937 else if (i > 0) 5938 MyFlags.Flags.setOrigAlign(1); 5939 Ins.push_back(MyFlags); 5940 } 5941 } 5942 } 5943 5944 // Call the target to set up the argument values. 5945 SmallVector<SDValue, 8> InVals; 5946 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 5947 F.isVarArg(), Ins, 5948 dl, DAG, InVals); 5949 5950 // Verify that the target's LowerFormalArguments behaved as expected. 5951 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 5952 "LowerFormalArguments didn't return a valid chain!"); 5953 assert(InVals.size() == Ins.size() && 5954 "LowerFormalArguments didn't emit the correct number of values!"); 5955 DEBUG({ 5956 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5957 assert(InVals[i].getNode() && 5958 "LowerFormalArguments emitted a null value!"); 5959 assert(Ins[i].VT == InVals[i].getValueType() && 5960 "LowerFormalArguments emitted a value with the wrong type!"); 5961 } 5962 }); 5963 5964 // Update the DAG with the new chain value resulting from argument lowering. 5965 DAG.setRoot(NewRoot); 5966 5967 // Set up the argument values. 5968 unsigned i = 0; 5969 Idx = 1; 5970 if (!FLI.CanLowerReturn) { 5971 // Create a virtual register for the sret pointer, and put in a copy 5972 // from the sret argument into it. 5973 SmallVector<EVT, 1> ValueVTs; 5974 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 5975 EVT VT = ValueVTs[0]; 5976 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 5977 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5978 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 5979 RegVT, VT, AssertOp); 5980 5981 MachineFunction& MF = SDB->DAG.getMachineFunction(); 5982 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 5983 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 5984 FLI.DemoteRegister = SRetReg; 5985 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 5986 SRetReg, ArgValue); 5987 DAG.setRoot(NewRoot); 5988 5989 // i indexes lowered arguments. Bump it past the hidden sret argument. 5990 // Idx indexes LLVM arguments. Don't touch it. 5991 ++i; 5992 } 5993 5994 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 5995 ++I, ++Idx) { 5996 SmallVector<SDValue, 4> ArgValues; 5997 SmallVector<EVT, 4> ValueVTs; 5998 ComputeValueVTs(TLI, I->getType(), ValueVTs); 5999 unsigned NumValues = ValueVTs.size(); 6000 for (unsigned Value = 0; Value != NumValues; ++Value) { 6001 EVT VT = ValueVTs[Value]; 6002 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6003 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6004 6005 if (!I->use_empty()) { 6006 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6007 if (F.paramHasAttr(Idx, Attribute::SExt)) 6008 AssertOp = ISD::AssertSext; 6009 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6010 AssertOp = ISD::AssertZext; 6011 6012 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6013 NumParts, PartVT, VT, 6014 AssertOp)); 6015 } 6016 6017 i += NumParts; 6018 } 6019 6020 if (!I->use_empty()) { 6021 SDValue Res; 6022 if (!ArgValues.empty()) 6023 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6024 SDB->getCurDebugLoc()); 6025 SDB->setValue(I, Res); 6026 6027 // If this argument is live outside of the entry block, insert a copy from 6028 // whereever we got it to the vreg that other BB's will reference it as. 6029 SDB->CopyToExportRegsIfNeeded(I); 6030 } 6031 } 6032 6033 assert(i == InVals.size() && "Argument register count mismatch!"); 6034 6035 // Finally, if the target has anything special to do, allow it to do so. 6036 // FIXME: this should insert code into the DAG! 6037 EmitFunctionEntryCode(); 6038} 6039 6040/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6041/// ensure constants are generated when needed. Remember the virtual registers 6042/// that need to be added to the Machine PHI nodes as input. We cannot just 6043/// directly add them, because expansion might result in multiple MBB's for one 6044/// BB. As such, the start of the BB might correspond to a different MBB than 6045/// the end. 6046/// 6047void 6048SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6049 const TerminatorInst *TI = LLVMBB->getTerminator(); 6050 6051 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6052 6053 // Check successor nodes' PHI nodes that expect a constant to be available 6054 // from this block. 6055 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6056 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6057 if (!isa<PHINode>(SuccBB->begin())) continue; 6058 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6059 6060 // If this terminator has multiple identical successors (common for 6061 // switches), only handle each succ once. 6062 if (!SuccsHandled.insert(SuccMBB)) continue; 6063 6064 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6065 6066 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6067 // nodes and Machine PHI nodes, but the incoming operands have not been 6068 // emitted yet. 6069 for (BasicBlock::const_iterator I = SuccBB->begin(); 6070 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6071 // Ignore dead phi's. 6072 if (PN->use_empty()) continue; 6073 6074 unsigned Reg; 6075 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6076 6077 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6078 unsigned &RegOut = ConstantsOut[C]; 6079 if (RegOut == 0) { 6080 RegOut = FuncInfo.CreateRegForValue(C); 6081 CopyValueToVirtualRegister(C, RegOut); 6082 } 6083 Reg = RegOut; 6084 } else { 6085 Reg = FuncInfo.ValueMap[PHIOp]; 6086 if (Reg == 0) { 6087 assert(isa<AllocaInst>(PHIOp) && 6088 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6089 "Didn't codegen value into a register!??"); 6090 Reg = FuncInfo.CreateRegForValue(PHIOp); 6091 CopyValueToVirtualRegister(PHIOp, Reg); 6092 } 6093 } 6094 6095 // Remember that this register needs to added to the machine PHI node as 6096 // the input for this MBB. 6097 SmallVector<EVT, 4> ValueVTs; 6098 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6099 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6100 EVT VT = ValueVTs[vti]; 6101 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6102 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6103 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6104 Reg += NumRegisters; 6105 } 6106 } 6107 } 6108 ConstantsOut.clear(); 6109} 6110