SelectionDAGBuilder.cpp revision 65ffec49f73d1f8856211b107712c58cc9636b78
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/SmallSet.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Analysis/ConstantFolding.h" 21#include "llvm/Constants.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/IntrinsicInst.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/Module.h" 32#include "llvm/CodeGen/Analysis.h" 33#include "llvm/CodeGen/FastISel.h" 34#include "llvm/CodeGen/FunctionLoweringInfo.h" 35#include "llvm/CodeGen/GCStrategy.h" 36#include "llvm/CodeGen/GCMetadata.h" 37#include "llvm/CodeGen/MachineFunction.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineInstrBuilder.h" 40#include "llvm/CodeGen/MachineJumpTableInfo.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetRegisterInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameInfo.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/Compiler.h" 54#include "llvm/Support/CommandLine.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 74 const SDValue *Parts, unsigned NumParts, 75 EVT PartVT, EVT ValueVT); 76 77/// getCopyFromParts - Create a value that contains the specified legal parts 78/// combined into the value they represent. If the parts combine to a type 79/// larger then ValueVT then AssertOp can be used to specify whether the extra 80/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 81/// (ISD::AssertSext). 82static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 83 const SDValue *Parts, 84 unsigned NumParts, EVT PartVT, EVT ValueVT, 85 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 86 if (ValueVT.isVector()) 87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 88 89 assert(NumParts > 0 && "No parts to assemble!"); 90 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 91 SDValue Val = Parts[0]; 92 93 if (NumParts > 1) { 94 // Assemble the value from multiple parts. 95 if (ValueVT.isInteger()) { 96 unsigned PartBits = PartVT.getSizeInBits(); 97 unsigned ValueBits = ValueVT.getSizeInBits(); 98 99 // Assemble the power of 2 part. 100 unsigned RoundParts = NumParts & (NumParts - 1) ? 101 1 << Log2_32(NumParts) : NumParts; 102 unsigned RoundBits = PartBits * RoundParts; 103 EVT RoundVT = RoundBits == ValueBits ? 104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 105 SDValue Lo, Hi; 106 107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 108 109 if (RoundParts > 2) { 110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 111 PartVT, HalfVT); 112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 113 RoundParts / 2, PartVT, HalfVT); 114 } else { 115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]); 116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]); 117 } 118 119 if (TLI.isBigEndian()) 120 std::swap(Lo, Hi); 121 122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 123 124 if (RoundParts < NumParts) { 125 // Assemble the trailing non-power-of-2 part. 126 unsigned OddParts = NumParts - RoundParts; 127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 128 Hi = getCopyFromParts(DAG, DL, 129 Parts + RoundParts, OddParts, PartVT, OddVT); 130 131 // Combine the round and odd parts. 132 Lo = Val; 133 if (TLI.isBigEndian()) 134 std::swap(Lo, Hi); 135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 138 DAG.getConstant(Lo.getValueType().getSizeInBits(), 139 TLI.getPointerTy())); 140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 142 } 143 } else if (PartVT.isFloatingPoint()) { 144 // FP split into multiple FP parts (for ppcf128) 145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 146 "Unexpected split"); 147 SDValue Lo, Hi; 148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]); 149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]); 150 if (TLI.isBigEndian()) 151 std::swap(Lo, Hi); 152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 153 } else { 154 // FP split into integer parts (soft fp) 155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 156 !PartVT.isVector() && "Unexpected split"); 157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 159 } 160 } 161 162 // There is now one part, held in Val. Correct it to match ValueVT. 163 PartVT = Val.getValueType(); 164 165 if (PartVT == ValueVT) 166 return Val; 167 168 if (PartVT.isInteger() && ValueVT.isInteger()) { 169 if (ValueVT.bitsLT(PartVT)) { 170 // For a truncate, see if we have any information to 171 // indicate whether the truncated bits will always be 172 // zero or sign-extension. 173 if (AssertOp != ISD::DELETED_NODE) 174 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 175 DAG.getValueType(ValueVT)); 176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 177 } 178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 179 } 180 181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 182 // FP_ROUND's are always exact here. 183 if (ValueVT.bitsLT(Val.getValueType())) 184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 185 DAG.getIntPtrConstant(1)); 186 187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 188 } 189 190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 192 193 llvm_unreachable("Unknown mismatch!"); 194 return SDValue(); 195} 196 197/// getCopyFromParts - Create a value that contains the specified legal parts 198/// combined into the value they represent. If the parts combine to a type 199/// larger then ValueVT then AssertOp can be used to specify whether the extra 200/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 201/// (ISD::AssertSext). 202static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 203 const SDValue *Parts, unsigned NumParts, 204 EVT PartVT, EVT ValueVT) { 205 assert(ValueVT.isVector() && "Not a vector value"); 206 assert(NumParts > 0 && "No parts to assemble!"); 207 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 208 SDValue Val = Parts[0]; 209 210 // Handle a multi-element vector. 211 if (NumParts > 1) { 212 EVT IntermediateVT, RegisterVT; 213 unsigned NumIntermediates; 214 unsigned NumRegs = 215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 216 NumIntermediates, RegisterVT); 217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 218 NumParts = NumRegs; // Silence a compiler warning. 219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 220 assert(RegisterVT == Parts[0].getValueType() && 221 "Part type doesn't match part!"); 222 223 // Assemble the parts into intermediate operands. 224 SmallVector<SDValue, 8> Ops(NumIntermediates); 225 if (NumIntermediates == NumParts) { 226 // If the register was not expanded, truncate or copy the value, 227 // as appropriate. 228 for (unsigned i = 0; i != NumParts; ++i) 229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 230 PartVT, IntermediateVT); 231 } else if (NumParts > 0) { 232 // If the intermediate type was expanded, build the intermediate 233 // operands from the parts. 234 assert(NumParts % NumIntermediates == 0 && 235 "Must expand into a divisible number of parts!"); 236 unsigned Factor = NumParts / NumIntermediates; 237 for (unsigned i = 0; i != NumIntermediates; ++i) 238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 239 PartVT, IntermediateVT); 240 } 241 242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 243 // intermediate operands. 244 Val = DAG.getNode(IntermediateVT.isVector() ? 245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 246 ValueVT, &Ops[0], NumIntermediates); 247 } 248 249 // There is now one part, held in Val. Correct it to match ValueVT. 250 PartVT = Val.getValueType(); 251 252 if (PartVT == ValueVT) 253 return Val; 254 255 if (PartVT.isVector()) { 256 // If the element type of the source/dest vectors are the same, but the 257 // parts vector has more elements than the value vector, then we have a 258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 259 // elements we want. 260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 262 "Cannot narrow, it would be a lossy transformation"); 263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 264 DAG.getIntPtrConstant(0)); 265 } 266 267 // Vector/Vector bitcast. 268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val); 269 } 270 271 assert(ValueVT.getVectorElementType() == PartVT && 272 ValueVT.getVectorNumElements() == 1 && 273 "Only trivial scalar-to-vector conversions should get here!"); 274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 275} 276 277 278 279 280static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 281 SDValue Val, SDValue *Parts, unsigned NumParts, 282 EVT PartVT); 283 284/// getCopyToParts - Create a series of nodes that contain the specified value 285/// split into legal parts. If the parts contain more bits than Val, then, for 286/// integers, ExtendKind can be used to specify how to generate the extra bits. 287static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 288 SDValue Val, SDValue *Parts, unsigned NumParts, 289 EVT PartVT, 290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 291 EVT ValueVT = Val.getValueType(); 292 293 // Handle the vector case separately. 294 if (ValueVT.isVector()) 295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 296 297 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 298 unsigned PartBits = PartVT.getSizeInBits(); 299 unsigned OrigNumParts = NumParts; 300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 301 302 if (NumParts == 0) 303 return; 304 305 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 306 if (PartVT == ValueVT) { 307 assert(NumParts == 1 && "No-op copy with multiple parts!"); 308 Parts[0] = Val; 309 return; 310 } 311 312 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 313 // If the parts cover more bits than the value has, promote the value. 314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 315 assert(NumParts == 1 && "Do not know what to promote to!"); 316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 317 } else { 318 assert(PartVT.isInteger() && ValueVT.isInteger() && 319 "Unknown mismatch!"); 320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 322 } 323 } else if (PartBits == ValueVT.getSizeInBits()) { 324 // Different types of the same size. 325 assert(NumParts == 1 && PartVT != ValueVT); 326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 328 // If the parts cover less bits than value has, truncate the value. 329 assert(PartVT.isInteger() && ValueVT.isInteger() && 330 "Unknown mismatch!"); 331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 333 } 334 335 // The value may have changed - recompute ValueVT. 336 ValueVT = Val.getValueType(); 337 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 338 "Failed to tile the value with PartVT!"); 339 340 if (NumParts == 1) { 341 assert(PartVT == ValueVT && "Type conversion failed!"); 342 Parts[0] = Val; 343 return; 344 } 345 346 // Expand the value into multiple parts. 347 if (NumParts & (NumParts - 1)) { 348 // The number of parts is not a power of 2. Split off and copy the tail. 349 assert(PartVT.isInteger() && ValueVT.isInteger() && 350 "Do not know what to expand to!"); 351 unsigned RoundParts = 1 << Log2_32(NumParts); 352 unsigned RoundBits = RoundParts * PartBits; 353 unsigned OddParts = NumParts - RoundParts; 354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 355 DAG.getIntPtrConstant(RoundBits)); 356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 357 358 if (TLI.isBigEndian()) 359 // The odd parts were reversed by getCopyToParts - unreverse them. 360 std::reverse(Parts + RoundParts, Parts + NumParts); 361 362 NumParts = RoundParts; 363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 365 } 366 367 // The number of parts is a power of 2. Repeatedly bisect the value using 368 // EXTRACT_ELEMENT. 369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL, 370 EVT::getIntegerVT(*DAG.getContext(), 371 ValueVT.getSizeInBits()), 372 Val); 373 374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 375 for (unsigned i = 0; i < NumParts; i += StepSize) { 376 unsigned ThisBits = StepSize * PartBits / 2; 377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 378 SDValue &Part0 = Parts[i]; 379 SDValue &Part1 = Parts[i+StepSize/2]; 380 381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 382 ThisVT, Part0, DAG.getIntPtrConstant(1)); 383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 384 ThisVT, Part0, DAG.getIntPtrConstant(0)); 385 386 if (ThisBits == PartBits && ThisVT != PartVT) { 387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0); 388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1); 389 } 390 } 391 } 392 393 if (TLI.isBigEndian()) 394 std::reverse(Parts, Parts + OrigNumParts); 395} 396 397 398/// getCopyToPartsVector - Create a series of nodes that contain the specified 399/// value split into legal parts. 400static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 401 SDValue Val, SDValue *Parts, unsigned NumParts, 402 EVT PartVT) { 403 EVT ValueVT = Val.getValueType(); 404 assert(ValueVT.isVector() && "Not a vector"); 405 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 406 407 if (NumParts == 1) { 408 if (PartVT == ValueVT) { 409 // Nothing to do. 410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 411 // Bitconvert vector->vector case. 412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val); 413 } else if (PartVT.isVector() && 414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 416 EVT ElementVT = PartVT.getVectorElementType(); 417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 418 // undef elements. 419 SmallVector<SDValue, 16> Ops; 420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 422 ElementVT, Val, DAG.getIntPtrConstant(i))); 423 424 for (unsigned i = ValueVT.getVectorNumElements(), 425 e = PartVT.getVectorNumElements(); i != e; ++i) 426 Ops.push_back(DAG.getUNDEF(ElementVT)); 427 428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 429 430 // FIXME: Use CONCAT for 2x -> 4x. 431 432 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 434 } else { 435 // Vector -> scalar conversion. 436 assert(ValueVT.getVectorElementType() == PartVT && 437 ValueVT.getVectorNumElements() == 1 && 438 "Only trivial vector-to-scalar conversions should get here!"); 439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 440 PartVT, Val, DAG.getIntPtrConstant(0)); 441 } 442 443 Parts[0] = Val; 444 return; 445 } 446 447 // Handle a multi-element vector. 448 EVT IntermediateVT, RegisterVT; 449 unsigned NumIntermediates; 450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 451 IntermediateVT, 452 NumIntermediates, RegisterVT); 453 unsigned NumElements = ValueVT.getVectorNumElements(); 454 455 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 456 NumParts = NumRegs; // Silence a compiler warning. 457 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 458 459 // Split the vector into intermediate operands. 460 SmallVector<SDValue, 8> Ops(NumIntermediates); 461 for (unsigned i = 0; i != NumIntermediates; ++i) { 462 if (IntermediateVT.isVector()) 463 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 464 IntermediateVT, Val, 465 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 466 else 467 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 468 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 469 } 470 471 // Split the intermediate operands into legal parts. 472 if (NumParts == NumIntermediates) { 473 // If the register was not expanded, promote or copy the value, 474 // as appropriate. 475 for (unsigned i = 0; i != NumParts; ++i) 476 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 477 } else if (NumParts > 0) { 478 // If the intermediate type was expanded, split each the value into 479 // legal parts. 480 assert(NumParts % NumIntermediates == 0 && 481 "Must expand into a divisible number of parts!"); 482 unsigned Factor = NumParts / NumIntermediates; 483 for (unsigned i = 0; i != NumIntermediates; ++i) 484 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 485 } 486} 487 488 489 490 491namespace { 492 /// RegsForValue - This struct represents the registers (physical or virtual) 493 /// that a particular set of values is assigned, and the type information 494 /// about the value. The most common situation is to represent one value at a 495 /// time, but struct or array values are handled element-wise as multiple 496 /// values. The splitting of aggregates is performed recursively, so that we 497 /// never have aggregate-typed registers. The values at this point do not 498 /// necessarily have legal types, so each value may require one or more 499 /// registers of some legal type. 500 /// 501 struct RegsForValue { 502 /// ValueVTs - The value types of the values, which may not be legal, and 503 /// may need be promoted or synthesized from one or more registers. 504 /// 505 SmallVector<EVT, 4> ValueVTs; 506 507 /// RegVTs - The value types of the registers. This is the same size as 508 /// ValueVTs and it records, for each value, what the type of the assigned 509 /// register or registers are. (Individual values are never synthesized 510 /// from more than one type of register.) 511 /// 512 /// With virtual registers, the contents of RegVTs is redundant with TLI's 513 /// getRegisterType member function, however when with physical registers 514 /// it is necessary to have a separate record of the types. 515 /// 516 SmallVector<EVT, 4> RegVTs; 517 518 /// Regs - This list holds the registers assigned to the values. 519 /// Each legal or promoted value requires one register, and each 520 /// expanded value requires multiple registers. 521 /// 522 SmallVector<unsigned, 4> Regs; 523 524 RegsForValue() {} 525 526 RegsForValue(const SmallVector<unsigned, 4> ®s, 527 EVT regvt, EVT valuevt) 528 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 529 530 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 531 unsigned Reg, const Type *Ty) { 532 ComputeValueVTs(tli, Ty, ValueVTs); 533 534 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 535 EVT ValueVT = ValueVTs[Value]; 536 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 537 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 538 for (unsigned i = 0; i != NumRegs; ++i) 539 Regs.push_back(Reg + i); 540 RegVTs.push_back(RegisterVT); 541 Reg += NumRegs; 542 } 543 } 544 545 /// areValueTypesLegal - Return true if types of all the values are legal. 546 bool areValueTypesLegal(const TargetLowering &TLI) { 547 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 548 EVT RegisterVT = RegVTs[Value]; 549 if (!TLI.isTypeLegal(RegisterVT)) 550 return false; 551 } 552 return true; 553 } 554 555 /// append - Add the specified values to this one. 556 void append(const RegsForValue &RHS) { 557 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 558 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 559 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 560 } 561 562 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 563 /// this value and returns the result as a ValueVTs value. This uses 564 /// Chain/Flag as the input and updates them for the output Chain/Flag. 565 /// If the Flag pointer is NULL, no flag is used. 566 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 567 DebugLoc dl, 568 SDValue &Chain, SDValue *Flag) const; 569 570 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 571 /// specified value into the registers specified by this object. This uses 572 /// Chain/Flag as the input and updates them for the output Chain/Flag. 573 /// If the Flag pointer is NULL, no flag is used. 574 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 575 SDValue &Chain, SDValue *Flag) const; 576 577 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 578 /// operand list. This adds the code marker, matching input operand index 579 /// (if applicable), and includes the number of values added into it. 580 void AddInlineAsmOperands(unsigned Kind, 581 bool HasMatching, unsigned MatchingIdx, 582 SelectionDAG &DAG, 583 std::vector<SDValue> &Ops) const; 584 }; 585} 586 587/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 588/// this value and returns the result as a ValueVT value. This uses 589/// Chain/Flag as the input and updates them for the output Chain/Flag. 590/// If the Flag pointer is NULL, no flag is used. 591SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 592 FunctionLoweringInfo &FuncInfo, 593 DebugLoc dl, 594 SDValue &Chain, SDValue *Flag) const { 595 // A Value with type {} or [0 x %t] needs no registers. 596 if (ValueVTs.empty()) 597 return SDValue(); 598 599 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 600 601 // Assemble the legal parts into the final values. 602 SmallVector<SDValue, 4> Values(ValueVTs.size()); 603 SmallVector<SDValue, 8> Parts; 604 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 605 // Copy the legal parts from the registers. 606 EVT ValueVT = ValueVTs[Value]; 607 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 608 EVT RegisterVT = RegVTs[Value]; 609 610 Parts.resize(NumRegs); 611 for (unsigned i = 0; i != NumRegs; ++i) { 612 SDValue P; 613 if (Flag == 0) { 614 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 615 } else { 616 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 617 *Flag = P.getValue(2); 618 } 619 620 Chain = P.getValue(1); 621 622 // If the source register was virtual and if we know something about it, 623 // add an assert node. 624 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && 625 RegisterVT.isInteger() && !RegisterVT.isVector()) { 626 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 627 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) { 628 const FunctionLoweringInfo::LiveOutInfo &LOI = 629 FuncInfo.LiveOutRegInfo[SlotNo]; 630 631 unsigned RegSize = RegisterVT.getSizeInBits(); 632 unsigned NumSignBits = LOI.NumSignBits; 633 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 634 635 // FIXME: We capture more information than the dag can represent. For 636 // now, just use the tightest assertzext/assertsext possible. 637 bool isSExt = true; 638 EVT FromVT(MVT::Other); 639 if (NumSignBits == RegSize) 640 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 641 else if (NumZeroBits >= RegSize-1) 642 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 643 else if (NumSignBits > RegSize-8) 644 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 645 else if (NumZeroBits >= RegSize-8) 646 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 647 else if (NumSignBits > RegSize-16) 648 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 649 else if (NumZeroBits >= RegSize-16) 650 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 651 else if (NumSignBits > RegSize-32) 652 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 653 else if (NumZeroBits >= RegSize-32) 654 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 655 656 if (FromVT != MVT::Other) 657 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 658 RegisterVT, P, DAG.getValueType(FromVT)); 659 } 660 } 661 662 Parts[i] = P; 663 } 664 665 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 666 NumRegs, RegisterVT, ValueVT); 667 Part += NumRegs; 668 Parts.clear(); 669 } 670 671 return DAG.getNode(ISD::MERGE_VALUES, dl, 672 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 673 &Values[0], ValueVTs.size()); 674} 675 676/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 677/// specified value into the registers specified by this object. This uses 678/// Chain/Flag as the input and updates them for the output Chain/Flag. 679/// If the Flag pointer is NULL, no flag is used. 680void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 681 SDValue &Chain, SDValue *Flag) const { 682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 683 684 // Get the list of the values's legal parts. 685 unsigned NumRegs = Regs.size(); 686 SmallVector<SDValue, 8> Parts(NumRegs); 687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 EVT RegisterVT = RegVTs[Value]; 691 692 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 693 &Parts[Part], NumParts, RegisterVT); 694 Part += NumParts; 695 } 696 697 // Copy the parts into the registers. 698 SmallVector<SDValue, 8> Chains(NumRegs); 699 for (unsigned i = 0; i != NumRegs; ++i) { 700 SDValue Part; 701 if (Flag == 0) { 702 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 703 } else { 704 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 705 *Flag = Part.getValue(1); 706 } 707 708 Chains[i] = Part.getValue(0); 709 } 710 711 if (NumRegs == 1 || Flag) 712 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 713 // flagged to it. That is the CopyToReg nodes and the user are considered 714 // a single scheduling unit. If we create a TokenFactor and return it as 715 // chain, then the TokenFactor is both a predecessor (operand) of the 716 // user as well as a successor (the TF operands are flagged to the user). 717 // c1, f1 = CopyToReg 718 // c2, f2 = CopyToReg 719 // c3 = TokenFactor c1, c2 720 // ... 721 // = op c3, ..., f2 722 Chain = Chains[NumRegs-1]; 723 else 724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 725} 726 727/// AddInlineAsmOperands - Add this value to the specified inlineasm node 728/// operand list. This adds the code marker and includes the number of 729/// values added into it. 730void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 731 unsigned MatchingIdx, 732 SelectionDAG &DAG, 733 std::vector<SDValue> &Ops) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 737 if (HasMatching) 738 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 739 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 740 Ops.push_back(Res); 741 742 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 743 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 744 EVT RegisterVT = RegVTs[Value]; 745 for (unsigned i = 0; i != NumRegs; ++i) { 746 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 747 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 748 } 749 } 750} 751 752void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 753 AA = &aa; 754 GFI = gfi; 755 TD = DAG.getTarget().getTargetData(); 756} 757 758/// clear - Clear out the current SelectionDAG and the associated 759/// state and prepare this SelectionDAGBuilder object to be used 760/// for a new block. This doesn't clear out information about 761/// additional blocks that are needed to complete switch lowering 762/// or PHI node updating; that information is cleared out as it is 763/// consumed. 764void SelectionDAGBuilder::clear() { 765 NodeMap.clear(); 766 UnusedArgNodeMap.clear(); 767 PendingLoads.clear(); 768 PendingExports.clear(); 769 DanglingDebugInfoMap.clear(); 770 CurDebugLoc = DebugLoc(); 771 HasTailCall = false; 772} 773 774/// getRoot - Return the current virtual root of the Selection DAG, 775/// flushing any PendingLoad items. This must be done before emitting 776/// a store or any other node that may need to be ordered after any 777/// prior load instructions. 778/// 779SDValue SelectionDAGBuilder::getRoot() { 780 if (PendingLoads.empty()) 781 return DAG.getRoot(); 782 783 if (PendingLoads.size() == 1) { 784 SDValue Root = PendingLoads[0]; 785 DAG.setRoot(Root); 786 PendingLoads.clear(); 787 return Root; 788 } 789 790 // Otherwise, we have to make a token factor node. 791 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 792 &PendingLoads[0], PendingLoads.size()); 793 PendingLoads.clear(); 794 DAG.setRoot(Root); 795 return Root; 796} 797 798/// getControlRoot - Similar to getRoot, but instead of flushing all the 799/// PendingLoad items, flush all the PendingExports items. It is necessary 800/// to do this before emitting a terminator instruction. 801/// 802SDValue SelectionDAGBuilder::getControlRoot() { 803 SDValue Root = DAG.getRoot(); 804 805 if (PendingExports.empty()) 806 return Root; 807 808 // Turn all of the CopyToReg chains into one factored node. 809 if (Root.getOpcode() != ISD::EntryToken) { 810 unsigned i = 0, e = PendingExports.size(); 811 for (; i != e; ++i) { 812 assert(PendingExports[i].getNode()->getNumOperands() > 1); 813 if (PendingExports[i].getNode()->getOperand(0) == Root) 814 break; // Don't add the root if we already indirectly depend on it. 815 } 816 817 if (i == e) 818 PendingExports.push_back(Root); 819 } 820 821 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 822 &PendingExports[0], 823 PendingExports.size()); 824 PendingExports.clear(); 825 DAG.setRoot(Root); 826 return Root; 827} 828 829void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 830 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 831 DAG.AssignOrdering(Node, SDNodeOrder); 832 833 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 834 AssignOrderingToNode(Node->getOperand(I).getNode()); 835} 836 837void SelectionDAGBuilder::visit(const Instruction &I) { 838 // Set up outgoing PHI node register values before emitting the terminator. 839 if (isa<TerminatorInst>(&I)) 840 HandlePHINodesInSuccessorBlocks(I.getParent()); 841 842 CurDebugLoc = I.getDebugLoc(); 843 844 visit(I.getOpcode(), I); 845 846 if (!isa<TerminatorInst>(&I) && !HasTailCall) 847 CopyToExportRegsIfNeeded(&I); 848 849 CurDebugLoc = DebugLoc(); 850} 851 852void SelectionDAGBuilder::visitPHI(const PHINode &) { 853 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 854} 855 856void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 857 // Note: this doesn't use InstVisitor, because it has to work with 858 // ConstantExpr's in addition to instructions. 859 switch (Opcode) { 860 default: llvm_unreachable("Unknown instruction type encountered!"); 861 // Build the switch statement using the Instruction.def file. 862#define HANDLE_INST(NUM, OPCODE, CLASS) \ 863 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 864#include "llvm/Instruction.def" 865 } 866 867 // Assign the ordering to the freshly created DAG nodes. 868 if (NodeMap.count(&I)) { 869 ++SDNodeOrder; 870 AssignOrderingToNode(getValue(&I).getNode()); 871 } 872} 873 874// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 875// generate the debug data structures now that we've seen its definition. 876void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 877 SDValue Val) { 878 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 879 if (DDI.getDI()) { 880 const DbgValueInst *DI = DDI.getDI(); 881 DebugLoc dl = DDI.getdl(); 882 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 883 MDNode *Variable = DI->getVariable(); 884 uint64_t Offset = DI->getOffset(); 885 SDDbgValue *SDV; 886 if (Val.getNode()) { 887 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 888 SDV = DAG.getDbgValue(Variable, Val.getNode(), 889 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 890 DAG.AddDbgValue(SDV, Val.getNode(), false); 891 } 892 } else { 893 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 894 Offset, dl, SDNodeOrder); 895 DAG.AddDbgValue(SDV, 0, false); 896 } 897 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 898 } 899} 900 901// getValue - Return an SDValue for the given Value. 902SDValue SelectionDAGBuilder::getValue(const Value *V) { 903 // If we already have an SDValue for this value, use it. It's important 904 // to do this first, so that we don't create a CopyFromReg if we already 905 // have a regular SDValue. 906 SDValue &N = NodeMap[V]; 907 if (N.getNode()) return N; 908 909 // If there's a virtual register allocated and initialized for this 910 // value, use it. 911 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 912 if (It != FuncInfo.ValueMap.end()) { 913 unsigned InReg = It->second; 914 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 915 SDValue Chain = DAG.getEntryNode(); 916 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 917 } 918 919 // Otherwise create a new SDValue and remember it. 920 SDValue Val = getValueImpl(V); 921 NodeMap[V] = Val; 922 resolveDanglingDebugInfo(V, Val); 923 return Val; 924} 925 926/// getNonRegisterValue - Return an SDValue for the given Value, but 927/// don't look in FuncInfo.ValueMap for a virtual register. 928SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 929 // If we already have an SDValue for this value, use it. 930 SDValue &N = NodeMap[V]; 931 if (N.getNode()) return N; 932 933 // Otherwise create a new SDValue and remember it. 934 SDValue Val = getValueImpl(V); 935 NodeMap[V] = Val; 936 resolveDanglingDebugInfo(V, Val); 937 return Val; 938} 939 940/// getValueImpl - Helper function for getValue and getNonRegisterValue. 941/// Create an SDValue for the given value. 942SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 943 if (const Constant *C = dyn_cast<Constant>(V)) { 944 EVT VT = TLI.getValueType(V->getType(), true); 945 946 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 947 return DAG.getConstant(*CI, VT); 948 949 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 950 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 951 952 if (isa<ConstantPointerNull>(C)) 953 return DAG.getConstant(0, TLI.getPointerTy()); 954 955 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 956 return DAG.getConstantFP(*CFP, VT); 957 958 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 959 return DAG.getUNDEF(VT); 960 961 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 962 visit(CE->getOpcode(), *CE); 963 SDValue N1 = NodeMap[V]; 964 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 965 return N1; 966 } 967 968 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 969 SmallVector<SDValue, 4> Constants; 970 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 971 OI != OE; ++OI) { 972 SDNode *Val = getValue(*OI).getNode(); 973 // If the operand is an empty aggregate, there are no values. 974 if (!Val) continue; 975 // Add each leaf value from the operand to the Constants list 976 // to form a flattened list of all the values. 977 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 978 Constants.push_back(SDValue(Val, i)); 979 } 980 981 return DAG.getMergeValues(&Constants[0], Constants.size(), 982 getCurDebugLoc()); 983 } 984 985 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 986 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 987 "Unknown struct or array constant!"); 988 989 SmallVector<EVT, 4> ValueVTs; 990 ComputeValueVTs(TLI, C->getType(), ValueVTs); 991 unsigned NumElts = ValueVTs.size(); 992 if (NumElts == 0) 993 return SDValue(); // empty struct 994 SmallVector<SDValue, 4> Constants(NumElts); 995 for (unsigned i = 0; i != NumElts; ++i) { 996 EVT EltVT = ValueVTs[i]; 997 if (isa<UndefValue>(C)) 998 Constants[i] = DAG.getUNDEF(EltVT); 999 else if (EltVT.isFloatingPoint()) 1000 Constants[i] = DAG.getConstantFP(0, EltVT); 1001 else 1002 Constants[i] = DAG.getConstant(0, EltVT); 1003 } 1004 1005 return DAG.getMergeValues(&Constants[0], NumElts, 1006 getCurDebugLoc()); 1007 } 1008 1009 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1010 return DAG.getBlockAddress(BA, VT); 1011 1012 const VectorType *VecTy = cast<VectorType>(V->getType()); 1013 unsigned NumElements = VecTy->getNumElements(); 1014 1015 // Now that we know the number and type of the elements, get that number of 1016 // elements into the Ops array based on what kind of constant it is. 1017 SmallVector<SDValue, 16> Ops; 1018 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1019 for (unsigned i = 0; i != NumElements; ++i) 1020 Ops.push_back(getValue(CP->getOperand(i))); 1021 } else { 1022 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1023 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1024 1025 SDValue Op; 1026 if (EltVT.isFloatingPoint()) 1027 Op = DAG.getConstantFP(0, EltVT); 1028 else 1029 Op = DAG.getConstant(0, EltVT); 1030 Ops.assign(NumElements, Op); 1031 } 1032 1033 // Create a BUILD_VECTOR node. 1034 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1035 VT, &Ops[0], Ops.size()); 1036 } 1037 1038 // If this is a static alloca, generate it as the frameindex instead of 1039 // computation. 1040 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1041 DenseMap<const AllocaInst*, int>::iterator SI = 1042 FuncInfo.StaticAllocaMap.find(AI); 1043 if (SI != FuncInfo.StaticAllocaMap.end()) 1044 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1045 } 1046 1047 // If this is an instruction which fast-isel has deferred, select it now. 1048 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1049 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1050 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1051 SDValue Chain = DAG.getEntryNode(); 1052 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1053 } 1054 1055 llvm_unreachable("Can't get register for value!"); 1056 return SDValue(); 1057} 1058 1059void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1060 SDValue Chain = getControlRoot(); 1061 SmallVector<ISD::OutputArg, 8> Outs; 1062 SmallVector<SDValue, 8> OutVals; 1063 1064 if (!FuncInfo.CanLowerReturn) { 1065 unsigned DemoteReg = FuncInfo.DemoteRegister; 1066 const Function *F = I.getParent()->getParent(); 1067 1068 // Emit a store of the return value through the virtual register. 1069 // Leave Outs empty so that LowerReturn won't try to load return 1070 // registers the usual way. 1071 SmallVector<EVT, 1> PtrValueVTs; 1072 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1073 PtrValueVTs); 1074 1075 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1076 SDValue RetOp = getValue(I.getOperand(0)); 1077 1078 SmallVector<EVT, 4> ValueVTs; 1079 SmallVector<uint64_t, 4> Offsets; 1080 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1081 unsigned NumValues = ValueVTs.size(); 1082 1083 SmallVector<SDValue, 4> Chains(NumValues); 1084 for (unsigned i = 0; i != NumValues; ++i) { 1085 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1086 RetPtr.getValueType(), RetPtr, 1087 DAG.getIntPtrConstant(Offsets[i])); 1088 Chains[i] = 1089 DAG.getStore(Chain, getCurDebugLoc(), 1090 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1091 Add, NULL, Offsets[i], false, false, 0); 1092 } 1093 1094 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1095 MVT::Other, &Chains[0], NumValues); 1096 } else if (I.getNumOperands() != 0) { 1097 SmallVector<EVT, 4> ValueVTs; 1098 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1099 unsigned NumValues = ValueVTs.size(); 1100 if (NumValues) { 1101 SDValue RetOp = getValue(I.getOperand(0)); 1102 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1103 EVT VT = ValueVTs[j]; 1104 1105 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1106 1107 const Function *F = I.getParent()->getParent(); 1108 if (F->paramHasAttr(0, Attribute::SExt)) 1109 ExtendKind = ISD::SIGN_EXTEND; 1110 else if (F->paramHasAttr(0, Attribute::ZExt)) 1111 ExtendKind = ISD::ZERO_EXTEND; 1112 1113 // FIXME: C calling convention requires the return type to be promoted 1114 // to at least 32-bit. But this is not necessary for non-C calling 1115 // conventions. The frontend should mark functions whose return values 1116 // require promoting with signext or zeroext attributes. 1117 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1118 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1119 if (VT.bitsLT(MinVT)) 1120 VT = MinVT; 1121 } 1122 1123 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1124 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1125 SmallVector<SDValue, 4> Parts(NumParts); 1126 getCopyToParts(DAG, getCurDebugLoc(), 1127 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1128 &Parts[0], NumParts, PartVT, ExtendKind); 1129 1130 // 'inreg' on function refers to return value 1131 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1132 if (F->paramHasAttr(0, Attribute::InReg)) 1133 Flags.setInReg(); 1134 1135 // Propagate extension type if any 1136 if (F->paramHasAttr(0, Attribute::SExt)) 1137 Flags.setSExt(); 1138 else if (F->paramHasAttr(0, Attribute::ZExt)) 1139 Flags.setZExt(); 1140 1141 for (unsigned i = 0; i < NumParts; ++i) { 1142 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1143 /*isfixed=*/true)); 1144 OutVals.push_back(Parts[i]); 1145 } 1146 } 1147 } 1148 } 1149 1150 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1151 CallingConv::ID CallConv = 1152 DAG.getMachineFunction().getFunction()->getCallingConv(); 1153 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1154 Outs, OutVals, getCurDebugLoc(), DAG); 1155 1156 // Verify that the target's LowerReturn behaved as expected. 1157 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1158 "LowerReturn didn't return a valid chain!"); 1159 1160 // Update the DAG with the new chain value resulting from return lowering. 1161 DAG.setRoot(Chain); 1162} 1163 1164/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1165/// created for it, emit nodes to copy the value into the virtual 1166/// registers. 1167void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1168 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1169 if (VMI != FuncInfo.ValueMap.end()) { 1170 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1171 CopyValueToVirtualRegister(V, VMI->second); 1172 } 1173} 1174 1175/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1176/// the current basic block, add it to ValueMap now so that we'll get a 1177/// CopyTo/FromReg. 1178void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1179 // No need to export constants. 1180 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1181 1182 // Already exported? 1183 if (FuncInfo.isExportedInst(V)) return; 1184 1185 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1186 CopyValueToVirtualRegister(V, Reg); 1187} 1188 1189bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1190 const BasicBlock *FromBB) { 1191 // The operands of the setcc have to be in this block. We don't know 1192 // how to export them from some other block. 1193 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1194 // Can export from current BB. 1195 if (VI->getParent() == FromBB) 1196 return true; 1197 1198 // Is already exported, noop. 1199 return FuncInfo.isExportedInst(V); 1200 } 1201 1202 // If this is an argument, we can export it if the BB is the entry block or 1203 // if it is already exported. 1204 if (isa<Argument>(V)) { 1205 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1206 return true; 1207 1208 // Otherwise, can only export this if it is already exported. 1209 return FuncInfo.isExportedInst(V); 1210 } 1211 1212 // Otherwise, constants can always be exported. 1213 return true; 1214} 1215 1216static bool InBlock(const Value *V, const BasicBlock *BB) { 1217 if (const Instruction *I = dyn_cast<Instruction>(V)) 1218 return I->getParent() == BB; 1219 return true; 1220} 1221 1222/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1223/// This function emits a branch and is used at the leaves of an OR or an 1224/// AND operator tree. 1225/// 1226void 1227SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1228 MachineBasicBlock *TBB, 1229 MachineBasicBlock *FBB, 1230 MachineBasicBlock *CurBB, 1231 MachineBasicBlock *SwitchBB) { 1232 const BasicBlock *BB = CurBB->getBasicBlock(); 1233 1234 // If the leaf of the tree is a comparison, merge the condition into 1235 // the caseblock. 1236 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1237 // The operands of the cmp have to be in this block. We don't know 1238 // how to export them from some other block. If this is the first block 1239 // of the sequence, no exporting is needed. 1240 if (CurBB == SwitchBB || 1241 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1242 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1243 ISD::CondCode Condition; 1244 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1245 Condition = getICmpCondCode(IC->getPredicate()); 1246 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1247 Condition = getFCmpCondCode(FC->getPredicate()); 1248 } else { 1249 Condition = ISD::SETEQ; // silence warning. 1250 llvm_unreachable("Unknown compare instruction"); 1251 } 1252 1253 CaseBlock CB(Condition, BOp->getOperand(0), 1254 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1255 SwitchCases.push_back(CB); 1256 return; 1257 } 1258 } 1259 1260 // Create a CaseBlock record representing this branch. 1261 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1262 NULL, TBB, FBB, CurBB); 1263 SwitchCases.push_back(CB); 1264} 1265 1266/// FindMergedConditions - If Cond is an expression like 1267void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1268 MachineBasicBlock *TBB, 1269 MachineBasicBlock *FBB, 1270 MachineBasicBlock *CurBB, 1271 MachineBasicBlock *SwitchBB, 1272 unsigned Opc) { 1273 // If this node is not part of the or/and tree, emit it as a branch. 1274 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1275 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1276 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1277 BOp->getParent() != CurBB->getBasicBlock() || 1278 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1279 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1280 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1281 return; 1282 } 1283 1284 // Create TmpBB after CurBB. 1285 MachineFunction::iterator BBI = CurBB; 1286 MachineFunction &MF = DAG.getMachineFunction(); 1287 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1288 CurBB->getParent()->insert(++BBI, TmpBB); 1289 1290 if (Opc == Instruction::Or) { 1291 // Codegen X | Y as: 1292 // jmp_if_X TBB 1293 // jmp TmpBB 1294 // TmpBB: 1295 // jmp_if_Y TBB 1296 // jmp FBB 1297 // 1298 1299 // Emit the LHS condition. 1300 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1301 1302 // Emit the RHS condition into TmpBB. 1303 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1304 } else { 1305 assert(Opc == Instruction::And && "Unknown merge op!"); 1306 // Codegen X & Y as: 1307 // jmp_if_X TmpBB 1308 // jmp FBB 1309 // TmpBB: 1310 // jmp_if_Y TBB 1311 // jmp FBB 1312 // 1313 // This requires creation of TmpBB after CurBB. 1314 1315 // Emit the LHS condition. 1316 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1317 1318 // Emit the RHS condition into TmpBB. 1319 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1320 } 1321} 1322 1323/// If the set of cases should be emitted as a series of branches, return true. 1324/// If we should emit this as a bunch of and/or'd together conditions, return 1325/// false. 1326bool 1327SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1328 if (Cases.size() != 2) return true; 1329 1330 // If this is two comparisons of the same values or'd or and'd together, they 1331 // will get folded into a single comparison, so don't emit two blocks. 1332 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1333 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1334 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1335 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1336 return false; 1337 } 1338 1339 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1340 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1341 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1342 Cases[0].CC == Cases[1].CC && 1343 isa<Constant>(Cases[0].CmpRHS) && 1344 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1345 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1346 return false; 1347 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1348 return false; 1349 } 1350 1351 return true; 1352} 1353 1354void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1355 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1356 1357 // Update machine-CFG edges. 1358 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1359 1360 // Figure out which block is immediately after the current one. 1361 MachineBasicBlock *NextBlock = 0; 1362 MachineFunction::iterator BBI = BrMBB; 1363 if (++BBI != FuncInfo.MF->end()) 1364 NextBlock = BBI; 1365 1366 if (I.isUnconditional()) { 1367 // Update machine-CFG edges. 1368 BrMBB->addSuccessor(Succ0MBB); 1369 1370 // If this is not a fall-through branch, emit the branch. 1371 if (Succ0MBB != NextBlock) 1372 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1373 MVT::Other, getControlRoot(), 1374 DAG.getBasicBlock(Succ0MBB))); 1375 1376 return; 1377 } 1378 1379 // If this condition is one of the special cases we handle, do special stuff 1380 // now. 1381 const Value *CondVal = I.getCondition(); 1382 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1383 1384 // If this is a series of conditions that are or'd or and'd together, emit 1385 // this as a sequence of branches instead of setcc's with and/or operations. 1386 // For example, instead of something like: 1387 // cmp A, B 1388 // C = seteq 1389 // cmp D, E 1390 // F = setle 1391 // or C, F 1392 // jnz foo 1393 // Emit: 1394 // cmp A, B 1395 // je foo 1396 // cmp D, E 1397 // jle foo 1398 // 1399 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1400 if (BOp->hasOneUse() && 1401 (BOp->getOpcode() == Instruction::And || 1402 BOp->getOpcode() == Instruction::Or)) { 1403 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1404 BOp->getOpcode()); 1405 // If the compares in later blocks need to use values not currently 1406 // exported from this block, export them now. This block should always 1407 // be the first entry. 1408 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1409 1410 // Allow some cases to be rejected. 1411 if (ShouldEmitAsBranches(SwitchCases)) { 1412 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1413 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1414 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1415 } 1416 1417 // Emit the branch for this block. 1418 visitSwitchCase(SwitchCases[0], BrMBB); 1419 SwitchCases.erase(SwitchCases.begin()); 1420 return; 1421 } 1422 1423 // Okay, we decided not to do this, remove any inserted MBB's and clear 1424 // SwitchCases. 1425 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1426 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1427 1428 SwitchCases.clear(); 1429 } 1430 } 1431 1432 // Create a CaseBlock record representing this branch. 1433 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1434 NULL, Succ0MBB, Succ1MBB, BrMBB); 1435 1436 // Use visitSwitchCase to actually insert the fast branch sequence for this 1437 // cond branch. 1438 visitSwitchCase(CB, BrMBB); 1439} 1440 1441/// visitSwitchCase - Emits the necessary code to represent a single node in 1442/// the binary search tree resulting from lowering a switch instruction. 1443void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1444 MachineBasicBlock *SwitchBB) { 1445 SDValue Cond; 1446 SDValue CondLHS = getValue(CB.CmpLHS); 1447 DebugLoc dl = getCurDebugLoc(); 1448 1449 // Build the setcc now. 1450 if (CB.CmpMHS == NULL) { 1451 // Fold "(X == true)" to X and "(X == false)" to !X to 1452 // handle common cases produced by branch lowering. 1453 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1454 CB.CC == ISD::SETEQ) 1455 Cond = CondLHS; 1456 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1457 CB.CC == ISD::SETEQ) { 1458 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1459 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1460 } else 1461 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1462 } else { 1463 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1464 1465 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1466 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1467 1468 SDValue CmpOp = getValue(CB.CmpMHS); 1469 EVT VT = CmpOp.getValueType(); 1470 1471 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1472 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1473 ISD::SETLE); 1474 } else { 1475 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1476 VT, CmpOp, DAG.getConstant(Low, VT)); 1477 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1478 DAG.getConstant(High-Low, VT), ISD::SETULE); 1479 } 1480 } 1481 1482 // Update successor info 1483 SwitchBB->addSuccessor(CB.TrueBB); 1484 SwitchBB->addSuccessor(CB.FalseBB); 1485 1486 // Set NextBlock to be the MBB immediately after the current one, if any. 1487 // This is used to avoid emitting unnecessary branches to the next block. 1488 MachineBasicBlock *NextBlock = 0; 1489 MachineFunction::iterator BBI = SwitchBB; 1490 if (++BBI != FuncInfo.MF->end()) 1491 NextBlock = BBI; 1492 1493 // If the lhs block is the next block, invert the condition so that we can 1494 // fall through to the lhs instead of the rhs block. 1495 if (CB.TrueBB == NextBlock) { 1496 std::swap(CB.TrueBB, CB.FalseBB); 1497 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1498 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1499 } 1500 1501 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1502 MVT::Other, getControlRoot(), Cond, 1503 DAG.getBasicBlock(CB.TrueBB)); 1504 1505 // Insert the false branch. 1506 if (CB.FalseBB != NextBlock) 1507 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1508 DAG.getBasicBlock(CB.FalseBB)); 1509 1510 DAG.setRoot(BrCond); 1511} 1512 1513/// visitJumpTable - Emit JumpTable node in the current MBB 1514void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1515 // Emit the code for the jump table 1516 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1517 EVT PTy = TLI.getPointerTy(); 1518 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1519 JT.Reg, PTy); 1520 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1521 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1522 MVT::Other, Index.getValue(1), 1523 Table, Index); 1524 DAG.setRoot(BrJumpTable); 1525} 1526 1527/// visitJumpTableHeader - This function emits necessary code to produce index 1528/// in the JumpTable from switch case. 1529void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1530 JumpTableHeader &JTH, 1531 MachineBasicBlock *SwitchBB) { 1532 // Subtract the lowest switch case value from the value being switched on and 1533 // conditional branch to default mbb if the result is greater than the 1534 // difference between smallest and largest cases. 1535 SDValue SwitchOp = getValue(JTH.SValue); 1536 EVT VT = SwitchOp.getValueType(); 1537 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1538 DAG.getConstant(JTH.First, VT)); 1539 1540 // The SDNode we just created, which holds the value being switched on minus 1541 // the smallest case value, needs to be copied to a virtual register so it 1542 // can be used as an index into the jump table in a subsequent basic block. 1543 // This value may be smaller or larger than the target's pointer type, and 1544 // therefore require extension or truncating. 1545 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1546 1547 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1548 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1549 JumpTableReg, SwitchOp); 1550 JT.Reg = JumpTableReg; 1551 1552 // Emit the range check for the jump table, and branch to the default block 1553 // for the switch statement if the value being switched on exceeds the largest 1554 // case in the switch. 1555 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1556 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1557 DAG.getConstant(JTH.Last-JTH.First,VT), 1558 ISD::SETUGT); 1559 1560 // Set NextBlock to be the MBB immediately after the current one, if any. 1561 // This is used to avoid emitting unnecessary branches to the next block. 1562 MachineBasicBlock *NextBlock = 0; 1563 MachineFunction::iterator BBI = SwitchBB; 1564 1565 if (++BBI != FuncInfo.MF->end()) 1566 NextBlock = BBI; 1567 1568 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1569 MVT::Other, CopyTo, CMP, 1570 DAG.getBasicBlock(JT.Default)); 1571 1572 if (JT.MBB != NextBlock) 1573 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1574 DAG.getBasicBlock(JT.MBB)); 1575 1576 DAG.setRoot(BrCond); 1577} 1578 1579/// visitBitTestHeader - This function emits necessary code to produce value 1580/// suitable for "bit tests" 1581void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1582 MachineBasicBlock *SwitchBB) { 1583 // Subtract the minimum value 1584 SDValue SwitchOp = getValue(B.SValue); 1585 EVT VT = SwitchOp.getValueType(); 1586 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1587 DAG.getConstant(B.First, VT)); 1588 1589 // Check range 1590 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1591 TLI.getSetCCResultType(Sub.getValueType()), 1592 Sub, DAG.getConstant(B.Range, VT), 1593 ISD::SETUGT); 1594 1595 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1596 TLI.getPointerTy()); 1597 1598 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1599 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1600 B.Reg, ShiftOp); 1601 1602 // Set NextBlock to be the MBB immediately after the current one, if any. 1603 // This is used to avoid emitting unnecessary branches to the next block. 1604 MachineBasicBlock *NextBlock = 0; 1605 MachineFunction::iterator BBI = SwitchBB; 1606 if (++BBI != FuncInfo.MF->end()) 1607 NextBlock = BBI; 1608 1609 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1610 1611 SwitchBB->addSuccessor(B.Default); 1612 SwitchBB->addSuccessor(MBB); 1613 1614 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1615 MVT::Other, CopyTo, RangeCmp, 1616 DAG.getBasicBlock(B.Default)); 1617 1618 if (MBB != NextBlock) 1619 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1620 DAG.getBasicBlock(MBB)); 1621 1622 DAG.setRoot(BrRange); 1623} 1624 1625/// visitBitTestCase - this function produces one "bit test" 1626void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1627 unsigned Reg, 1628 BitTestCase &B, 1629 MachineBasicBlock *SwitchBB) { 1630 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1631 TLI.getPointerTy()); 1632 SDValue Cmp; 1633 if (CountPopulation_64(B.Mask) == 1) { 1634 // Testing for a single bit; just compare the shift count with what it 1635 // would need to be to shift a 1 bit in that position. 1636 Cmp = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(ShiftOp.getValueType()), 1638 ShiftOp, 1639 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1640 TLI.getPointerTy()), 1641 ISD::SETEQ); 1642 } else { 1643 // Make desired shift 1644 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1645 TLI.getPointerTy(), 1646 DAG.getConstant(1, TLI.getPointerTy()), 1647 ShiftOp); 1648 1649 // Emit bit tests and jumps 1650 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1651 TLI.getPointerTy(), SwitchVal, 1652 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1653 Cmp = DAG.getSetCC(getCurDebugLoc(), 1654 TLI.getSetCCResultType(AndOp.getValueType()), 1655 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1656 ISD::SETNE); 1657 } 1658 1659 SwitchBB->addSuccessor(B.TargetBB); 1660 SwitchBB->addSuccessor(NextMBB); 1661 1662 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1663 MVT::Other, getControlRoot(), 1664 Cmp, DAG.getBasicBlock(B.TargetBB)); 1665 1666 // Set NextBlock to be the MBB immediately after the current one, if any. 1667 // This is used to avoid emitting unnecessary branches to the next block. 1668 MachineBasicBlock *NextBlock = 0; 1669 MachineFunction::iterator BBI = SwitchBB; 1670 if (++BBI != FuncInfo.MF->end()) 1671 NextBlock = BBI; 1672 1673 if (NextMBB != NextBlock) 1674 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1675 DAG.getBasicBlock(NextMBB)); 1676 1677 DAG.setRoot(BrAnd); 1678} 1679 1680void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1681 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1682 1683 // Retrieve successors. 1684 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1685 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1686 1687 const Value *Callee(I.getCalledValue()); 1688 if (isa<InlineAsm>(Callee)) 1689 visitInlineAsm(&I); 1690 else 1691 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1692 1693 // If the value of the invoke is used outside of its defining block, make it 1694 // available as a virtual register. 1695 CopyToExportRegsIfNeeded(&I); 1696 1697 // Update successor info 1698 InvokeMBB->addSuccessor(Return); 1699 InvokeMBB->addSuccessor(LandingPad); 1700 1701 // Drop into normal successor. 1702 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1703 MVT::Other, getControlRoot(), 1704 DAG.getBasicBlock(Return))); 1705} 1706 1707void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1708} 1709 1710/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1711/// small case ranges). 1712bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1713 CaseRecVector& WorkList, 1714 const Value* SV, 1715 MachineBasicBlock *Default, 1716 MachineBasicBlock *SwitchBB) { 1717 Case& BackCase = *(CR.Range.second-1); 1718 1719 // Size is the number of Cases represented by this range. 1720 size_t Size = CR.Range.second - CR.Range.first; 1721 if (Size > 3) 1722 return false; 1723 1724 // Get the MachineFunction which holds the current MBB. This is used when 1725 // inserting any additional MBBs necessary to represent the switch. 1726 MachineFunction *CurMF = FuncInfo.MF; 1727 1728 // Figure out which block is immediately after the current one. 1729 MachineBasicBlock *NextBlock = 0; 1730 MachineFunction::iterator BBI = CR.CaseBB; 1731 1732 if (++BBI != FuncInfo.MF->end()) 1733 NextBlock = BBI; 1734 1735 // TODO: If any two of the cases has the same destination, and if one value 1736 // is the same as the other, but has one bit unset that the other has set, 1737 // use bit manipulation to do two compares at once. For example: 1738 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1739 1740 // Rearrange the case blocks so that the last one falls through if possible. 1741 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1742 // The last case block won't fall through into 'NextBlock' if we emit the 1743 // branches in this order. See if rearranging a case value would help. 1744 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1745 if (I->BB == NextBlock) { 1746 std::swap(*I, BackCase); 1747 break; 1748 } 1749 } 1750 } 1751 1752 // Create a CaseBlock record representing a conditional branch to 1753 // the Case's target mbb if the value being switched on SV is equal 1754 // to C. 1755 MachineBasicBlock *CurBlock = CR.CaseBB; 1756 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1757 MachineBasicBlock *FallThrough; 1758 if (I != E-1) { 1759 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1760 CurMF->insert(BBI, FallThrough); 1761 1762 // Put SV in a virtual register to make it available from the new blocks. 1763 ExportFromCurrentBlock(SV); 1764 } else { 1765 // If the last case doesn't match, go to the default block. 1766 FallThrough = Default; 1767 } 1768 1769 const Value *RHS, *LHS, *MHS; 1770 ISD::CondCode CC; 1771 if (I->High == I->Low) { 1772 // This is just small small case range :) containing exactly 1 case 1773 CC = ISD::SETEQ; 1774 LHS = SV; RHS = I->High; MHS = NULL; 1775 } else { 1776 CC = ISD::SETLE; 1777 LHS = I->Low; MHS = SV; RHS = I->High; 1778 } 1779 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1780 1781 // If emitting the first comparison, just call visitSwitchCase to emit the 1782 // code into the current block. Otherwise, push the CaseBlock onto the 1783 // vector to be later processed by SDISel, and insert the node's MBB 1784 // before the next MBB. 1785 if (CurBlock == SwitchBB) 1786 visitSwitchCase(CB, SwitchBB); 1787 else 1788 SwitchCases.push_back(CB); 1789 1790 CurBlock = FallThrough; 1791 } 1792 1793 return true; 1794} 1795 1796static inline bool areJTsAllowed(const TargetLowering &TLI) { 1797 return !DisableJumpTables && 1798 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1799 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1800} 1801 1802static APInt ComputeRange(const APInt &First, const APInt &Last) { 1803 APInt LastExt(Last), FirstExt(First); 1804 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1805 LastExt.sext(BitWidth); FirstExt.sext(BitWidth); 1806 return (LastExt - FirstExt + 1ULL); 1807} 1808 1809/// handleJTSwitchCase - Emit jumptable for current switch case range 1810bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1811 CaseRecVector& WorkList, 1812 const Value* SV, 1813 MachineBasicBlock* Default, 1814 MachineBasicBlock *SwitchBB) { 1815 Case& FrontCase = *CR.Range.first; 1816 Case& BackCase = *(CR.Range.second-1); 1817 1818 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1819 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1820 1821 APInt TSize(First.getBitWidth(), 0); 1822 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1823 I!=E; ++I) 1824 TSize += I->size(); 1825 1826 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1827 return false; 1828 1829 APInt Range = ComputeRange(First, Last); 1830 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1831 if (Density < 0.4) 1832 return false; 1833 1834 DEBUG(dbgs() << "Lowering jump table\n" 1835 << "First entry: " << First << ". Last entry: " << Last << '\n' 1836 << "Range: " << Range 1837 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1838 1839 // Get the MachineFunction which holds the current MBB. This is used when 1840 // inserting any additional MBBs necessary to represent the switch. 1841 MachineFunction *CurMF = FuncInfo.MF; 1842 1843 // Figure out which block is immediately after the current one. 1844 MachineFunction::iterator BBI = CR.CaseBB; 1845 ++BBI; 1846 1847 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1848 1849 // Create a new basic block to hold the code for loading the address 1850 // of the jump table, and jumping to it. Update successor information; 1851 // we will either branch to the default case for the switch, or the jump 1852 // table. 1853 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1854 CurMF->insert(BBI, JumpTableBB); 1855 CR.CaseBB->addSuccessor(Default); 1856 CR.CaseBB->addSuccessor(JumpTableBB); 1857 1858 // Build a vector of destination BBs, corresponding to each target 1859 // of the jump table. If the value of the jump table slot corresponds to 1860 // a case statement, push the case's BB onto the vector, otherwise, push 1861 // the default BB. 1862 std::vector<MachineBasicBlock*> DestBBs; 1863 APInt TEI = First; 1864 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1865 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1866 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1867 1868 if (Low.sle(TEI) && TEI.sle(High)) { 1869 DestBBs.push_back(I->BB); 1870 if (TEI==High) 1871 ++I; 1872 } else { 1873 DestBBs.push_back(Default); 1874 } 1875 } 1876 1877 // Update successor info. Add one edge to each unique successor. 1878 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1879 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1880 E = DestBBs.end(); I != E; ++I) { 1881 if (!SuccsHandled[(*I)->getNumber()]) { 1882 SuccsHandled[(*I)->getNumber()] = true; 1883 JumpTableBB->addSuccessor(*I); 1884 } 1885 } 1886 1887 // Create a jump table index for this jump table. 1888 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1889 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1890 ->createJumpTableIndex(DestBBs); 1891 1892 // Set the jump table information so that we can codegen it as a second 1893 // MachineBasicBlock 1894 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1895 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1896 if (CR.CaseBB == SwitchBB) 1897 visitJumpTableHeader(JT, JTH, SwitchBB); 1898 1899 JTCases.push_back(JumpTableBlock(JTH, JT)); 1900 1901 return true; 1902} 1903 1904/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1905/// 2 subtrees. 1906bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1907 CaseRecVector& WorkList, 1908 const Value* SV, 1909 MachineBasicBlock *Default, 1910 MachineBasicBlock *SwitchBB) { 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineFunction::iterator BBI = CR.CaseBB; 1917 ++BBI; 1918 1919 Case& FrontCase = *CR.Range.first; 1920 Case& BackCase = *(CR.Range.second-1); 1921 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1922 1923 // Size is the number of Cases represented by this range. 1924 unsigned Size = CR.Range.second - CR.Range.first; 1925 1926 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1927 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1928 double FMetric = 0; 1929 CaseItr Pivot = CR.Range.first + Size/2; 1930 1931 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 1932 // (heuristically) allow us to emit JumpTable's later. 1933 APInt TSize(First.getBitWidth(), 0); 1934 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1935 I!=E; ++I) 1936 TSize += I->size(); 1937 1938 APInt LSize = FrontCase.size(); 1939 APInt RSize = TSize-LSize; 1940 DEBUG(dbgs() << "Selecting best pivot: \n" 1941 << "First: " << First << ", Last: " << Last <<'\n' 1942 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 1943 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 1944 J!=E; ++I, ++J) { 1945 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 1946 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 1947 APInt Range = ComputeRange(LEnd, RBegin); 1948 assert((Range - 2ULL).isNonNegative() && 1949 "Invalid case distance"); 1950 double LDensity = (double)LSize.roundToDouble() / 1951 (LEnd - First + 1ULL).roundToDouble(); 1952 double RDensity = (double)RSize.roundToDouble() / 1953 (Last - RBegin + 1ULL).roundToDouble(); 1954 double Metric = Range.logBase2()*(LDensity+RDensity); 1955 // Should always split in some non-trivial place 1956 DEBUG(dbgs() <<"=>Step\n" 1957 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 1958 << "LDensity: " << LDensity 1959 << ", RDensity: " << RDensity << '\n' 1960 << "Metric: " << Metric << '\n'); 1961 if (FMetric < Metric) { 1962 Pivot = J; 1963 FMetric = Metric; 1964 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 1965 } 1966 1967 LSize += J->size(); 1968 RSize -= J->size(); 1969 } 1970 if (areJTsAllowed(TLI)) { 1971 // If our case is dense we *really* should handle it earlier! 1972 assert((FMetric > 0) && "Should handle dense range earlier!"); 1973 } else { 1974 Pivot = CR.Range.first + Size/2; 1975 } 1976 1977 CaseRange LHSR(CR.Range.first, Pivot); 1978 CaseRange RHSR(Pivot, CR.Range.second); 1979 Constant *C = Pivot->Low; 1980 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 1981 1982 // We know that we branch to the LHS if the Value being switched on is 1983 // less than the Pivot value, C. We use this to optimize our binary 1984 // tree a bit, by recognizing that if SV is greater than or equal to the 1985 // LHS's Case Value, and that Case Value is exactly one less than the 1986 // Pivot's Value, then we can branch directly to the LHS's Target, 1987 // rather than creating a leaf node for it. 1988 if ((LHSR.second - LHSR.first) == 1 && 1989 LHSR.first->High == CR.GE && 1990 cast<ConstantInt>(C)->getValue() == 1991 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 1992 TrueBB = LHSR.first->BB; 1993 } else { 1994 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1995 CurMF->insert(BBI, TrueBB); 1996 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 1997 1998 // Put SV in a virtual register to make it available from the new blocks. 1999 ExportFromCurrentBlock(SV); 2000 } 2001 2002 // Similar to the optimization above, if the Value being switched on is 2003 // known to be less than the Constant CR.LT, and the current Case Value 2004 // is CR.LT - 1, then we can branch directly to the target block for 2005 // the current Case Value, rather than emitting a RHS leaf node for it. 2006 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2007 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2008 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2009 FalseBB = RHSR.first->BB; 2010 } else { 2011 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2012 CurMF->insert(BBI, FalseBB); 2013 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2014 2015 // Put SV in a virtual register to make it available from the new blocks. 2016 ExportFromCurrentBlock(SV); 2017 } 2018 2019 // Create a CaseBlock record representing a conditional branch to 2020 // the LHS node if the value being switched on SV is less than C. 2021 // Otherwise, branch to LHS. 2022 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2023 2024 if (CR.CaseBB == SwitchBB) 2025 visitSwitchCase(CB, SwitchBB); 2026 else 2027 SwitchCases.push_back(CB); 2028 2029 return true; 2030} 2031 2032/// handleBitTestsSwitchCase - if current case range has few destination and 2033/// range span less, than machine word bitwidth, encode case range into series 2034/// of masks and emit bit tests with these masks. 2035bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2036 CaseRecVector& WorkList, 2037 const Value* SV, 2038 MachineBasicBlock* Default, 2039 MachineBasicBlock *SwitchBB){ 2040 EVT PTy = TLI.getPointerTy(); 2041 unsigned IntPtrBits = PTy.getSizeInBits(); 2042 2043 Case& FrontCase = *CR.Range.first; 2044 Case& BackCase = *(CR.Range.second-1); 2045 2046 // Get the MachineFunction which holds the current MBB. This is used when 2047 // inserting any additional MBBs necessary to represent the switch. 2048 MachineFunction *CurMF = FuncInfo.MF; 2049 2050 // If target does not have legal shift left, do not emit bit tests at all. 2051 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2052 return false; 2053 2054 size_t numCmps = 0; 2055 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2056 I!=E; ++I) { 2057 // Single case counts one, case range - two. 2058 numCmps += (I->Low == I->High ? 1 : 2); 2059 } 2060 2061 // Count unique destinations 2062 SmallSet<MachineBasicBlock*, 4> Dests; 2063 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2064 Dests.insert(I->BB); 2065 if (Dests.size() > 3) 2066 // Don't bother the code below, if there are too much unique destinations 2067 return false; 2068 } 2069 DEBUG(dbgs() << "Total number of unique destinations: " 2070 << Dests.size() << '\n' 2071 << "Total number of comparisons: " << numCmps << '\n'); 2072 2073 // Compute span of values. 2074 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2075 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2076 APInt cmpRange = maxValue - minValue; 2077 2078 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2079 << "Low bound: " << minValue << '\n' 2080 << "High bound: " << maxValue << '\n'); 2081 2082 if (cmpRange.uge(IntPtrBits) || 2083 (!(Dests.size() == 1 && numCmps >= 3) && 2084 !(Dests.size() == 2 && numCmps >= 5) && 2085 !(Dests.size() >= 3 && numCmps >= 6))) 2086 return false; 2087 2088 DEBUG(dbgs() << "Emitting bit tests\n"); 2089 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2090 2091 // Optimize the case where all the case values fit in a 2092 // word without having to subtract minValue. In this case, 2093 // we can optimize away the subtraction. 2094 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2095 cmpRange = maxValue; 2096 } else { 2097 lowBound = minValue; 2098 } 2099 2100 CaseBitsVector CasesBits; 2101 unsigned i, count = 0; 2102 2103 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2104 MachineBasicBlock* Dest = I->BB; 2105 for (i = 0; i < count; ++i) 2106 if (Dest == CasesBits[i].BB) 2107 break; 2108 2109 if (i == count) { 2110 assert((count < 3) && "Too much destinations to test!"); 2111 CasesBits.push_back(CaseBits(0, Dest, 0)); 2112 count++; 2113 } 2114 2115 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2116 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2117 2118 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2119 uint64_t hi = (highValue - lowBound).getZExtValue(); 2120 2121 for (uint64_t j = lo; j <= hi; j++) { 2122 CasesBits[i].Mask |= 1ULL << j; 2123 CasesBits[i].Bits++; 2124 } 2125 2126 } 2127 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2128 2129 BitTestInfo BTC; 2130 2131 // Figure out which block is immediately after the current one. 2132 MachineFunction::iterator BBI = CR.CaseBB; 2133 ++BBI; 2134 2135 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2136 2137 DEBUG(dbgs() << "Cases:\n"); 2138 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2139 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2140 << ", Bits: " << CasesBits[i].Bits 2141 << ", BB: " << CasesBits[i].BB << '\n'); 2142 2143 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2144 CurMF->insert(BBI, CaseBB); 2145 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2146 CaseBB, 2147 CasesBits[i].BB)); 2148 2149 // Put SV in a virtual register to make it available from the new blocks. 2150 ExportFromCurrentBlock(SV); 2151 } 2152 2153 BitTestBlock BTB(lowBound, cmpRange, SV, 2154 -1U, (CR.CaseBB == SwitchBB), 2155 CR.CaseBB, Default, BTC); 2156 2157 if (CR.CaseBB == SwitchBB) 2158 visitBitTestHeader(BTB, SwitchBB); 2159 2160 BitTestCases.push_back(BTB); 2161 2162 return true; 2163} 2164 2165/// Clusterify - Transform simple list of Cases into list of CaseRange's 2166size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2167 const SwitchInst& SI) { 2168 size_t numCmps = 0; 2169 2170 // Start with "simple" cases 2171 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2172 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2173 Cases.push_back(Case(SI.getSuccessorValue(i), 2174 SI.getSuccessorValue(i), 2175 SMBB)); 2176 } 2177 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2178 2179 // Merge case into clusters 2180 if (Cases.size() >= 2) 2181 // Must recompute end() each iteration because it may be 2182 // invalidated by erase if we hold on to it 2183 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2184 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2185 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2186 MachineBasicBlock* nextBB = J->BB; 2187 MachineBasicBlock* currentBB = I->BB; 2188 2189 // If the two neighboring cases go to the same destination, merge them 2190 // into a single case. 2191 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2192 I->High = J->High; 2193 J = Cases.erase(J); 2194 } else { 2195 I = J++; 2196 } 2197 } 2198 2199 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2200 if (I->Low != I->High) 2201 // A range counts double, since it requires two compares. 2202 ++numCmps; 2203 } 2204 2205 return numCmps; 2206} 2207 2208void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2209 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2210 2211 // Figure out which block is immediately after the current one. 2212 MachineBasicBlock *NextBlock = 0; 2213 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2214 2215 // If there is only the default destination, branch to it if it is not the 2216 // next basic block. Otherwise, just fall through. 2217 if (SI.getNumOperands() == 2) { 2218 // Update machine-CFG edges. 2219 2220 // If this is not a fall-through branch, emit the branch. 2221 SwitchMBB->addSuccessor(Default); 2222 if (Default != NextBlock) 2223 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2224 MVT::Other, getControlRoot(), 2225 DAG.getBasicBlock(Default))); 2226 2227 return; 2228 } 2229 2230 // If there are any non-default case statements, create a vector of Cases 2231 // representing each one, and sort the vector so that we can efficiently 2232 // create a binary search tree from them. 2233 CaseVector Cases; 2234 size_t numCmps = Clusterify(Cases, SI); 2235 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2236 << ". Total compares: " << numCmps << '\n'); 2237 numCmps = 0; 2238 2239 // Get the Value to be switched on and default basic blocks, which will be 2240 // inserted into CaseBlock records, representing basic blocks in the binary 2241 // search tree. 2242 const Value *SV = SI.getOperand(0); 2243 2244 // Push the initial CaseRec onto the worklist 2245 CaseRecVector WorkList; 2246 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2247 CaseRange(Cases.begin(),Cases.end()))); 2248 2249 while (!WorkList.empty()) { 2250 // Grab a record representing a case range to process off the worklist 2251 CaseRec CR = WorkList.back(); 2252 WorkList.pop_back(); 2253 2254 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2255 continue; 2256 2257 // If the range has few cases (two or less) emit a series of specific 2258 // tests. 2259 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2260 continue; 2261 2262 // If the switch has more than 5 blocks, and at least 40% dense, and the 2263 // target supports indirect branches, then emit a jump table rather than 2264 // lowering the switch to a binary tree of conditional branches. 2265 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2266 continue; 2267 2268 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2269 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2270 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2271 } 2272} 2273 2274void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2275 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2276 2277 // Update machine-CFG edges with unique successors. 2278 SmallVector<BasicBlock*, 32> succs; 2279 succs.reserve(I.getNumSuccessors()); 2280 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2281 succs.push_back(I.getSuccessor(i)); 2282 array_pod_sort(succs.begin(), succs.end()); 2283 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2284 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2285 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2286 2287 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2288 MVT::Other, getControlRoot(), 2289 getValue(I.getAddress()))); 2290} 2291 2292void SelectionDAGBuilder::visitFSub(const User &I) { 2293 // -0.0 - X --> fneg 2294 const Type *Ty = I.getType(); 2295 if (Ty->isVectorTy()) { 2296 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2297 const VectorType *DestTy = cast<VectorType>(I.getType()); 2298 const Type *ElTy = DestTy->getElementType(); 2299 unsigned VL = DestTy->getNumElements(); 2300 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2301 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2302 if (CV == CNZ) { 2303 SDValue Op2 = getValue(I.getOperand(1)); 2304 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2305 Op2.getValueType(), Op2)); 2306 return; 2307 } 2308 } 2309 } 2310 2311 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2312 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2313 SDValue Op2 = getValue(I.getOperand(1)); 2314 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2315 Op2.getValueType(), Op2)); 2316 return; 2317 } 2318 2319 visitBinary(I, ISD::FSUB); 2320} 2321 2322void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2323 SDValue Op1 = getValue(I.getOperand(0)); 2324 SDValue Op2 = getValue(I.getOperand(1)); 2325 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2326 Op1.getValueType(), Op1, Op2)); 2327} 2328 2329void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2330 SDValue Op1 = getValue(I.getOperand(0)); 2331 SDValue Op2 = getValue(I.getOperand(1)); 2332 if (!I.getType()->isVectorTy() && 2333 Op2.getValueType() != TLI.getShiftAmountTy()) { 2334 // If the operand is smaller than the shift count type, promote it. 2335 EVT PTy = TLI.getPointerTy(); 2336 EVT STy = TLI.getShiftAmountTy(); 2337 if (STy.bitsGT(Op2.getValueType())) 2338 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2339 TLI.getShiftAmountTy(), Op2); 2340 // If the operand is larger than the shift count type but the shift 2341 // count type has enough bits to represent any shift value, truncate 2342 // it now. This is a common case and it exposes the truncate to 2343 // optimization early. 2344 else if (STy.getSizeInBits() >= 2345 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2346 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2347 TLI.getShiftAmountTy(), Op2); 2348 // Otherwise we'll need to temporarily settle for some other 2349 // convenient type; type legalization will make adjustments as 2350 // needed. 2351 else if (PTy.bitsLT(Op2.getValueType())) 2352 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2353 TLI.getPointerTy(), Op2); 2354 else if (PTy.bitsGT(Op2.getValueType())) 2355 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2356 TLI.getPointerTy(), Op2); 2357 } 2358 2359 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2360 Op1.getValueType(), Op1, Op2)); 2361} 2362 2363void SelectionDAGBuilder::visitICmp(const User &I) { 2364 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2365 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2366 predicate = IC->getPredicate(); 2367 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2368 predicate = ICmpInst::Predicate(IC->getPredicate()); 2369 SDValue Op1 = getValue(I.getOperand(0)); 2370 SDValue Op2 = getValue(I.getOperand(1)); 2371 ISD::CondCode Opcode = getICmpCondCode(predicate); 2372 2373 EVT DestVT = TLI.getValueType(I.getType()); 2374 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2375} 2376 2377void SelectionDAGBuilder::visitFCmp(const User &I) { 2378 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2379 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2380 predicate = FC->getPredicate(); 2381 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2382 predicate = FCmpInst::Predicate(FC->getPredicate()); 2383 SDValue Op1 = getValue(I.getOperand(0)); 2384 SDValue Op2 = getValue(I.getOperand(1)); 2385 ISD::CondCode Condition = getFCmpCondCode(predicate); 2386 EVT DestVT = TLI.getValueType(I.getType()); 2387 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2388} 2389 2390void SelectionDAGBuilder::visitSelect(const User &I) { 2391 SmallVector<EVT, 4> ValueVTs; 2392 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2393 unsigned NumValues = ValueVTs.size(); 2394 if (NumValues == 0) return; 2395 2396 SmallVector<SDValue, 4> Values(NumValues); 2397 SDValue Cond = getValue(I.getOperand(0)); 2398 SDValue TrueVal = getValue(I.getOperand(1)); 2399 SDValue FalseVal = getValue(I.getOperand(2)); 2400 2401 for (unsigned i = 0; i != NumValues; ++i) 2402 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2403 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2404 Cond, 2405 SDValue(TrueVal.getNode(), 2406 TrueVal.getResNo() + i), 2407 SDValue(FalseVal.getNode(), 2408 FalseVal.getResNo() + i)); 2409 2410 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2411 DAG.getVTList(&ValueVTs[0], NumValues), 2412 &Values[0], NumValues)); 2413} 2414 2415void SelectionDAGBuilder::visitTrunc(const User &I) { 2416 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2417 SDValue N = getValue(I.getOperand(0)); 2418 EVT DestVT = TLI.getValueType(I.getType()); 2419 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2420} 2421 2422void SelectionDAGBuilder::visitZExt(const User &I) { 2423 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2424 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2425 SDValue N = getValue(I.getOperand(0)); 2426 EVT DestVT = TLI.getValueType(I.getType()); 2427 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2428} 2429 2430void SelectionDAGBuilder::visitSExt(const User &I) { 2431 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2432 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2433 SDValue N = getValue(I.getOperand(0)); 2434 EVT DestVT = TLI.getValueType(I.getType()); 2435 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2436} 2437 2438void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2439 // FPTrunc is never a no-op cast, no need to check 2440 SDValue N = getValue(I.getOperand(0)); 2441 EVT DestVT = TLI.getValueType(I.getType()); 2442 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2443 DestVT, N, DAG.getIntPtrConstant(0))); 2444} 2445 2446void SelectionDAGBuilder::visitFPExt(const User &I){ 2447 // FPTrunc is never a no-op cast, no need to check 2448 SDValue N = getValue(I.getOperand(0)); 2449 EVT DestVT = TLI.getValueType(I.getType()); 2450 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2451} 2452 2453void SelectionDAGBuilder::visitFPToUI(const User &I) { 2454 // FPToUI is never a no-op cast, no need to check 2455 SDValue N = getValue(I.getOperand(0)); 2456 EVT DestVT = TLI.getValueType(I.getType()); 2457 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2458} 2459 2460void SelectionDAGBuilder::visitFPToSI(const User &I) { 2461 // FPToSI is never a no-op cast, no need to check 2462 SDValue N = getValue(I.getOperand(0)); 2463 EVT DestVT = TLI.getValueType(I.getType()); 2464 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2465} 2466 2467void SelectionDAGBuilder::visitUIToFP(const User &I) { 2468 // UIToFP is never a no-op cast, no need to check 2469 SDValue N = getValue(I.getOperand(0)); 2470 EVT DestVT = TLI.getValueType(I.getType()); 2471 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2472} 2473 2474void SelectionDAGBuilder::visitSIToFP(const User &I){ 2475 // SIToFP is never a no-op cast, no need to check 2476 SDValue N = getValue(I.getOperand(0)); 2477 EVT DestVT = TLI.getValueType(I.getType()); 2478 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2479} 2480 2481void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2482 // What to do depends on the size of the integer and the size of the pointer. 2483 // We can either truncate, zero extend, or no-op, accordingly. 2484 SDValue N = getValue(I.getOperand(0)); 2485 EVT DestVT = TLI.getValueType(I.getType()); 2486 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2487} 2488 2489void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2490 // What to do depends on the size of the integer and the size of the pointer. 2491 // We can either truncate, zero extend, or no-op, accordingly. 2492 SDValue N = getValue(I.getOperand(0)); 2493 EVT DestVT = TLI.getValueType(I.getType()); 2494 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2495} 2496 2497void SelectionDAGBuilder::visitBitCast(const User &I) { 2498 SDValue N = getValue(I.getOperand(0)); 2499 EVT DestVT = TLI.getValueType(I.getType()); 2500 2501 // BitCast assures us that source and destination are the same size so this is 2502 // either a BIT_CONVERT or a no-op. 2503 if (DestVT != N.getValueType()) 2504 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 2505 DestVT, N)); // convert types. 2506 else 2507 setValue(&I, N); // noop cast. 2508} 2509 2510void SelectionDAGBuilder::visitInsertElement(const User &I) { 2511 SDValue InVec = getValue(I.getOperand(0)); 2512 SDValue InVal = getValue(I.getOperand(1)); 2513 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2514 TLI.getPointerTy(), 2515 getValue(I.getOperand(2))); 2516 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2517 TLI.getValueType(I.getType()), 2518 InVec, InVal, InIdx)); 2519} 2520 2521void SelectionDAGBuilder::visitExtractElement(const User &I) { 2522 SDValue InVec = getValue(I.getOperand(0)); 2523 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2524 TLI.getPointerTy(), 2525 getValue(I.getOperand(1))); 2526 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2527 TLI.getValueType(I.getType()), InVec, InIdx)); 2528} 2529 2530// Utility for visitShuffleVector - Returns true if the mask is mask starting 2531// from SIndx and increasing to the element length (undefs are allowed). 2532static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2533 unsigned MaskNumElts = Mask.size(); 2534 for (unsigned i = 0; i != MaskNumElts; ++i) 2535 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2536 return false; 2537 return true; 2538} 2539 2540void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2541 SmallVector<int, 8> Mask; 2542 SDValue Src1 = getValue(I.getOperand(0)); 2543 SDValue Src2 = getValue(I.getOperand(1)); 2544 2545 // Convert the ConstantVector mask operand into an array of ints, with -1 2546 // representing undef values. 2547 SmallVector<Constant*, 8> MaskElts; 2548 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2549 unsigned MaskNumElts = MaskElts.size(); 2550 for (unsigned i = 0; i != MaskNumElts; ++i) { 2551 if (isa<UndefValue>(MaskElts[i])) 2552 Mask.push_back(-1); 2553 else 2554 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2555 } 2556 2557 EVT VT = TLI.getValueType(I.getType()); 2558 EVT SrcVT = Src1.getValueType(); 2559 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2560 2561 if (SrcNumElts == MaskNumElts) { 2562 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2563 &Mask[0])); 2564 return; 2565 } 2566 2567 // Normalize the shuffle vector since mask and vector length don't match. 2568 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2569 // Mask is longer than the source vectors and is a multiple of the source 2570 // vectors. We can use concatenate vector to make the mask and vectors 2571 // lengths match. 2572 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2573 // The shuffle is concatenating two vectors together. 2574 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2575 VT, Src1, Src2)); 2576 return; 2577 } 2578 2579 // Pad both vectors with undefs to make them the same length as the mask. 2580 unsigned NumConcat = MaskNumElts / SrcNumElts; 2581 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2582 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2583 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2584 2585 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2586 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2587 MOps1[0] = Src1; 2588 MOps2[0] = Src2; 2589 2590 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2591 getCurDebugLoc(), VT, 2592 &MOps1[0], NumConcat); 2593 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2594 getCurDebugLoc(), VT, 2595 &MOps2[0], NumConcat); 2596 2597 // Readjust mask for new input vector length. 2598 SmallVector<int, 8> MappedOps; 2599 for (unsigned i = 0; i != MaskNumElts; ++i) { 2600 int Idx = Mask[i]; 2601 if (Idx < (int)SrcNumElts) 2602 MappedOps.push_back(Idx); 2603 else 2604 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2605 } 2606 2607 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2608 &MappedOps[0])); 2609 return; 2610 } 2611 2612 if (SrcNumElts > MaskNumElts) { 2613 // Analyze the access pattern of the vector to see if we can extract 2614 // two subvectors and do the shuffle. The analysis is done by calculating 2615 // the range of elements the mask access on both vectors. 2616 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2617 int MaxRange[2] = {-1, -1}; 2618 2619 for (unsigned i = 0; i != MaskNumElts; ++i) { 2620 int Idx = Mask[i]; 2621 int Input = 0; 2622 if (Idx < 0) 2623 continue; 2624 2625 if (Idx >= (int)SrcNumElts) { 2626 Input = 1; 2627 Idx -= SrcNumElts; 2628 } 2629 if (Idx > MaxRange[Input]) 2630 MaxRange[Input] = Idx; 2631 if (Idx < MinRange[Input]) 2632 MinRange[Input] = Idx; 2633 } 2634 2635 // Check if the access is smaller than the vector size and can we find 2636 // a reasonable extract index. 2637 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2638 // Extract. 2639 int StartIdx[2]; // StartIdx to extract from 2640 for (int Input=0; Input < 2; ++Input) { 2641 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2642 RangeUse[Input] = 0; // Unused 2643 StartIdx[Input] = 0; 2644 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2645 // Fits within range but we should see if we can find a good 2646 // start index that is a multiple of the mask length. 2647 if (MaxRange[Input] < (int)MaskNumElts) { 2648 RangeUse[Input] = 1; // Extract from beginning of the vector 2649 StartIdx[Input] = 0; 2650 } else { 2651 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2652 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2653 StartIdx[Input] + MaskNumElts < SrcNumElts) 2654 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2655 } 2656 } 2657 } 2658 2659 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2660 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2661 return; 2662 } 2663 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2664 // Extract appropriate subvector and generate a vector shuffle 2665 for (int Input=0; Input < 2; ++Input) { 2666 SDValue &Src = Input == 0 ? Src1 : Src2; 2667 if (RangeUse[Input] == 0) 2668 Src = DAG.getUNDEF(VT); 2669 else 2670 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2671 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2672 } 2673 2674 // Calculate new mask. 2675 SmallVector<int, 8> MappedOps; 2676 for (unsigned i = 0; i != MaskNumElts; ++i) { 2677 int Idx = Mask[i]; 2678 if (Idx < 0) 2679 MappedOps.push_back(Idx); 2680 else if (Idx < (int)SrcNumElts) 2681 MappedOps.push_back(Idx - StartIdx[0]); 2682 else 2683 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2684 } 2685 2686 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2687 &MappedOps[0])); 2688 return; 2689 } 2690 } 2691 2692 // We can't use either concat vectors or extract subvectors so fall back to 2693 // replacing the shuffle with extract and build vector. 2694 // to insert and build vector. 2695 EVT EltVT = VT.getVectorElementType(); 2696 EVT PtrVT = TLI.getPointerTy(); 2697 SmallVector<SDValue,8> Ops; 2698 for (unsigned i = 0; i != MaskNumElts; ++i) { 2699 if (Mask[i] < 0) { 2700 Ops.push_back(DAG.getUNDEF(EltVT)); 2701 } else { 2702 int Idx = Mask[i]; 2703 SDValue Res; 2704 2705 if (Idx < (int)SrcNumElts) 2706 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2707 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2708 else 2709 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2710 EltVT, Src2, 2711 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2712 2713 Ops.push_back(Res); 2714 } 2715 } 2716 2717 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2718 VT, &Ops[0], Ops.size())); 2719} 2720 2721void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2722 const Value *Op0 = I.getOperand(0); 2723 const Value *Op1 = I.getOperand(1); 2724 const Type *AggTy = I.getType(); 2725 const Type *ValTy = Op1->getType(); 2726 bool IntoUndef = isa<UndefValue>(Op0); 2727 bool FromUndef = isa<UndefValue>(Op1); 2728 2729 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2730 I.idx_begin(), I.idx_end()); 2731 2732 SmallVector<EVT, 4> AggValueVTs; 2733 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2734 SmallVector<EVT, 4> ValValueVTs; 2735 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2736 2737 unsigned NumAggValues = AggValueVTs.size(); 2738 unsigned NumValValues = ValValueVTs.size(); 2739 SmallVector<SDValue, 4> Values(NumAggValues); 2740 2741 SDValue Agg = getValue(Op0); 2742 SDValue Val = getValue(Op1); 2743 unsigned i = 0; 2744 // Copy the beginning value(s) from the original aggregate. 2745 for (; i != LinearIndex; ++i) 2746 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2747 SDValue(Agg.getNode(), Agg.getResNo() + i); 2748 // Copy values from the inserted value(s). 2749 for (; i != LinearIndex + NumValValues; ++i) 2750 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2751 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2752 // Copy remaining value(s) from the original aggregate. 2753 for (; i != NumAggValues; ++i) 2754 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2755 SDValue(Agg.getNode(), Agg.getResNo() + i); 2756 2757 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2758 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2759 &Values[0], NumAggValues)); 2760} 2761 2762void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2763 const Value *Op0 = I.getOperand(0); 2764 const Type *AggTy = Op0->getType(); 2765 const Type *ValTy = I.getType(); 2766 bool OutOfUndef = isa<UndefValue>(Op0); 2767 2768 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, 2769 I.idx_begin(), I.idx_end()); 2770 2771 SmallVector<EVT, 4> ValValueVTs; 2772 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2773 2774 unsigned NumValValues = ValValueVTs.size(); 2775 SmallVector<SDValue, 4> Values(NumValValues); 2776 2777 SDValue Agg = getValue(Op0); 2778 // Copy out the selected value(s). 2779 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2780 Values[i - LinearIndex] = 2781 OutOfUndef ? 2782 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2783 SDValue(Agg.getNode(), Agg.getResNo() + i); 2784 2785 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2786 DAG.getVTList(&ValValueVTs[0], NumValValues), 2787 &Values[0], NumValValues)); 2788} 2789 2790void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2791 SDValue N = getValue(I.getOperand(0)); 2792 const Type *Ty = I.getOperand(0)->getType(); 2793 2794 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2795 OI != E; ++OI) { 2796 const Value *Idx = *OI; 2797 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2798 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2799 if (Field) { 2800 // N = N + Offset 2801 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2802 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2803 DAG.getIntPtrConstant(Offset)); 2804 } 2805 2806 Ty = StTy->getElementType(Field); 2807 } else { 2808 Ty = cast<SequentialType>(Ty)->getElementType(); 2809 2810 // If this is a constant subscript, handle it quickly. 2811 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2812 if (CI->isZero()) continue; 2813 uint64_t Offs = 2814 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2815 SDValue OffsVal; 2816 EVT PTy = TLI.getPointerTy(); 2817 unsigned PtrBits = PTy.getSizeInBits(); 2818 if (PtrBits < 64) 2819 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2820 TLI.getPointerTy(), 2821 DAG.getConstant(Offs, MVT::i64)); 2822 else 2823 OffsVal = DAG.getIntPtrConstant(Offs); 2824 2825 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2826 OffsVal); 2827 continue; 2828 } 2829 2830 // N = N + Idx * ElementSize; 2831 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2832 TD->getTypeAllocSize(Ty)); 2833 SDValue IdxN = getValue(Idx); 2834 2835 // If the index is smaller or larger than intptr_t, truncate or extend 2836 // it. 2837 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2838 2839 // If this is a multiply by a power of two, turn it into a shl 2840 // immediately. This is a very common case. 2841 if (ElementSize != 1) { 2842 if (ElementSize.isPowerOf2()) { 2843 unsigned Amt = ElementSize.logBase2(); 2844 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2845 N.getValueType(), IdxN, 2846 DAG.getConstant(Amt, TLI.getPointerTy())); 2847 } else { 2848 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2849 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2850 N.getValueType(), IdxN, Scale); 2851 } 2852 } 2853 2854 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2855 N.getValueType(), N, IdxN); 2856 } 2857 } 2858 2859 setValue(&I, N); 2860} 2861 2862void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2863 // If this is a fixed sized alloca in the entry block of the function, 2864 // allocate it statically on the stack. 2865 if (FuncInfo.StaticAllocaMap.count(&I)) 2866 return; // getValue will auto-populate this. 2867 2868 const Type *Ty = I.getAllocatedType(); 2869 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2870 unsigned Align = 2871 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2872 I.getAlignment()); 2873 2874 SDValue AllocSize = getValue(I.getArraySize()); 2875 2876 EVT IntPtr = TLI.getPointerTy(); 2877 if (AllocSize.getValueType() != IntPtr) 2878 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2879 2880 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2881 AllocSize, 2882 DAG.getConstant(TySize, IntPtr)); 2883 2884 // Handle alignment. If the requested alignment is less than or equal to 2885 // the stack alignment, ignore it. If the size is greater than or equal to 2886 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2887 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2888 if (Align <= StackAlign) 2889 Align = 0; 2890 2891 // Round the size of the allocation up to the stack alignment size 2892 // by add SA-1 to the size. 2893 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2894 AllocSize.getValueType(), AllocSize, 2895 DAG.getIntPtrConstant(StackAlign-1)); 2896 2897 // Mask out the low bits for alignment purposes. 2898 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2899 AllocSize.getValueType(), AllocSize, 2900 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2901 2902 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2903 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2904 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2905 VTs, Ops, 3); 2906 setValue(&I, DSA); 2907 DAG.setRoot(DSA.getValue(1)); 2908 2909 // Inform the Frame Information that we have just allocated a variable-sized 2910 // object. 2911 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2912} 2913 2914void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2915 const Value *SV = I.getOperand(0); 2916 SDValue Ptr = getValue(SV); 2917 2918 const Type *Ty = I.getType(); 2919 2920 bool isVolatile = I.isVolatile(); 2921 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2922 unsigned Alignment = I.getAlignment(); 2923 2924 SmallVector<EVT, 4> ValueVTs; 2925 SmallVector<uint64_t, 4> Offsets; 2926 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 2927 unsigned NumValues = ValueVTs.size(); 2928 if (NumValues == 0) 2929 return; 2930 2931 SDValue Root; 2932 bool ConstantMemory = false; 2933 if (I.isVolatile()) 2934 // Serialize volatile loads with other side effects. 2935 Root = getRoot(); 2936 else if (AA->pointsToConstantMemory(SV)) { 2937 // Do not serialize (non-volatile) loads of constant memory with anything. 2938 Root = DAG.getEntryNode(); 2939 ConstantMemory = true; 2940 } else { 2941 // Do not serialize non-volatile loads against each other. 2942 Root = DAG.getRoot(); 2943 } 2944 2945 SmallVector<SDValue, 4> Values(NumValues); 2946 SmallVector<SDValue, 4> Chains(NumValues); 2947 EVT PtrVT = Ptr.getValueType(); 2948 for (unsigned i = 0; i != NumValues; ++i) { 2949 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2950 PtrVT, Ptr, 2951 DAG.getConstant(Offsets[i], PtrVT)); 2952 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 2953 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 2954 isNonTemporal, Alignment); 2955 2956 Values[i] = L; 2957 Chains[i] = L.getValue(1); 2958 } 2959 2960 if (!ConstantMemory) { 2961 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 2962 MVT::Other, &Chains[0], NumValues); 2963 if (isVolatile) 2964 DAG.setRoot(Chain); 2965 else 2966 PendingLoads.push_back(Chain); 2967 } 2968 2969 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2970 DAG.getVTList(&ValueVTs[0], NumValues), 2971 &Values[0], NumValues)); 2972} 2973 2974void SelectionDAGBuilder::visitStore(const StoreInst &I) { 2975 const Value *SrcV = I.getOperand(0); 2976 const Value *PtrV = I.getOperand(1); 2977 2978 SmallVector<EVT, 4> ValueVTs; 2979 SmallVector<uint64_t, 4> Offsets; 2980 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 2981 unsigned NumValues = ValueVTs.size(); 2982 if (NumValues == 0) 2983 return; 2984 2985 // Get the lowered operands. Note that we do this after 2986 // checking if NumResults is zero, because with zero results 2987 // the operands won't have values in the map. 2988 SDValue Src = getValue(SrcV); 2989 SDValue Ptr = getValue(PtrV); 2990 2991 SDValue Root = getRoot(); 2992 SmallVector<SDValue, 4> Chains(NumValues); 2993 EVT PtrVT = Ptr.getValueType(); 2994 bool isVolatile = I.isVolatile(); 2995 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 2996 unsigned Alignment = I.getAlignment(); 2997 2998 for (unsigned i = 0; i != NumValues; ++i) { 2999 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3000 DAG.getConstant(Offsets[i], PtrVT)); 3001 Chains[i] = DAG.getStore(Root, getCurDebugLoc(), 3002 SDValue(Src.getNode(), Src.getResNo() + i), 3003 Add, PtrV, Offsets[i], isVolatile, 3004 isNonTemporal, Alignment); 3005 } 3006 3007 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3008 MVT::Other, &Chains[0], NumValues)); 3009} 3010 3011/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3012/// node. 3013void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3014 unsigned Intrinsic) { 3015 bool HasChain = !I.doesNotAccessMemory(); 3016 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3017 3018 // Build the operand list. 3019 SmallVector<SDValue, 8> Ops; 3020 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3021 if (OnlyLoad) { 3022 // We don't need to serialize loads against other loads. 3023 Ops.push_back(DAG.getRoot()); 3024 } else { 3025 Ops.push_back(getRoot()); 3026 } 3027 } 3028 3029 // Info is set by getTgtMemInstrinsic 3030 TargetLowering::IntrinsicInfo Info; 3031 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3032 3033 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3034 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3035 Info.opc == ISD::INTRINSIC_W_CHAIN) 3036 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3037 3038 // Add all operands of the call to the operand list. 3039 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3040 SDValue Op = getValue(I.getArgOperand(i)); 3041 assert(TLI.isTypeLegal(Op.getValueType()) && 3042 "Intrinsic uses a non-legal type?"); 3043 Ops.push_back(Op); 3044 } 3045 3046 SmallVector<EVT, 4> ValueVTs; 3047 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3048#ifndef NDEBUG 3049 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3050 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3051 "Intrinsic uses a non-legal type?"); 3052 } 3053#endif // NDEBUG 3054 3055 if (HasChain) 3056 ValueVTs.push_back(MVT::Other); 3057 3058 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3059 3060 // Create the node. 3061 SDValue Result; 3062 if (IsTgtIntrinsic) { 3063 // This is target intrinsic that touches memory 3064 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3065 VTs, &Ops[0], Ops.size(), 3066 Info.memVT, 3067 MachinePointerInfo(Info.ptrVal, Info.offset), 3068 Info.align, Info.vol, 3069 Info.readMem, Info.writeMem); 3070 } else if (!HasChain) { 3071 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3072 VTs, &Ops[0], Ops.size()); 3073 } else if (!I.getType()->isVoidTy()) { 3074 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3075 VTs, &Ops[0], Ops.size()); 3076 } else { 3077 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3078 VTs, &Ops[0], Ops.size()); 3079 } 3080 3081 if (HasChain) { 3082 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3083 if (OnlyLoad) 3084 PendingLoads.push_back(Chain); 3085 else 3086 DAG.setRoot(Chain); 3087 } 3088 3089 if (!I.getType()->isVoidTy()) { 3090 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3091 EVT VT = TLI.getValueType(PTy); 3092 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); 3093 } 3094 3095 setValue(&I, Result); 3096 } 3097} 3098 3099/// GetSignificand - Get the significand and build it into a floating-point 3100/// number with exponent of 1: 3101/// 3102/// Op = (Op & 0x007fffff) | 0x3f800000; 3103/// 3104/// where Op is the hexidecimal representation of floating point value. 3105static SDValue 3106GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3107 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3108 DAG.getConstant(0x007fffff, MVT::i32)); 3109 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3110 DAG.getConstant(0x3f800000, MVT::i32)); 3111 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); 3112} 3113 3114/// GetExponent - Get the exponent: 3115/// 3116/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3117/// 3118/// where Op is the hexidecimal representation of floating point value. 3119static SDValue 3120GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3121 DebugLoc dl) { 3122 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3123 DAG.getConstant(0x7f800000, MVT::i32)); 3124 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3125 DAG.getConstant(23, TLI.getPointerTy())); 3126 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3127 DAG.getConstant(127, MVT::i32)); 3128 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3129} 3130 3131/// getF32Constant - Get 32-bit floating point constant. 3132static SDValue 3133getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3134 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3135} 3136 3137/// Inlined utility function to implement binary input atomic intrinsics for 3138/// visitIntrinsicCall: I is a call instruction 3139/// Op is the associated NodeType for I 3140const char * 3141SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3142 ISD::NodeType Op) { 3143 SDValue Root = getRoot(); 3144 SDValue L = 3145 DAG.getAtomic(Op, getCurDebugLoc(), 3146 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3147 Root, 3148 getValue(I.getArgOperand(0)), 3149 getValue(I.getArgOperand(1)), 3150 I.getArgOperand(0)); 3151 setValue(&I, L); 3152 DAG.setRoot(L.getValue(1)); 3153 return 0; 3154} 3155 3156// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3157const char * 3158SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3159 SDValue Op1 = getValue(I.getArgOperand(0)); 3160 SDValue Op2 = getValue(I.getArgOperand(1)); 3161 3162 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3163 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3164 return 0; 3165} 3166 3167/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3168/// limited-precision mode. 3169void 3170SelectionDAGBuilder::visitExp(const CallInst &I) { 3171 SDValue result; 3172 DebugLoc dl = getCurDebugLoc(); 3173 3174 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3175 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3176 SDValue Op = getValue(I.getArgOperand(0)); 3177 3178 // Put the exponent in the right bit position for later addition to the 3179 // final result: 3180 // 3181 // #define LOG2OFe 1.4426950f 3182 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3183 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3184 getF32Constant(DAG, 0x3fb8aa3b)); 3185 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3186 3187 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3188 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3189 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3190 3191 // IntegerPartOfX <<= 23; 3192 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3193 DAG.getConstant(23, TLI.getPointerTy())); 3194 3195 if (LimitFloatPrecision <= 6) { 3196 // For floating-point precision of 6: 3197 // 3198 // TwoToFractionalPartOfX = 3199 // 0.997535578f + 3200 // (0.735607626f + 0.252464424f * x) * x; 3201 // 3202 // error 0.0144103317, which is 6 bits 3203 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3204 getF32Constant(DAG, 0x3e814304)); 3205 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3206 getF32Constant(DAG, 0x3f3c50c8)); 3207 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3208 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3209 getF32Constant(DAG, 0x3f7f5e7e)); 3210 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); 3211 3212 // Add the exponent into the result in integer domain. 3213 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3214 TwoToFracPartOfX, IntegerPartOfX); 3215 3216 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); 3217 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3218 // For floating-point precision of 12: 3219 // 3220 // TwoToFractionalPartOfX = 3221 // 0.999892986f + 3222 // (0.696457318f + 3223 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3224 // 3225 // 0.000107046256 error, which is 13 to 14 bits 3226 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3227 getF32Constant(DAG, 0x3da235e3)); 3228 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3229 getF32Constant(DAG, 0x3e65b8f3)); 3230 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3231 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3232 getF32Constant(DAG, 0x3f324b07)); 3233 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3234 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3235 getF32Constant(DAG, 0x3f7ff8fd)); 3236 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); 3237 3238 // Add the exponent into the result in integer domain. 3239 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3240 TwoToFracPartOfX, IntegerPartOfX); 3241 3242 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); 3243 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3244 // For floating-point precision of 18: 3245 // 3246 // TwoToFractionalPartOfX = 3247 // 0.999999982f + 3248 // (0.693148872f + 3249 // (0.240227044f + 3250 // (0.554906021e-1f + 3251 // (0.961591928e-2f + 3252 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3253 // 3254 // error 2.47208000*10^(-7), which is better than 18 bits 3255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3256 getF32Constant(DAG, 0x3924b03e)); 3257 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3258 getF32Constant(DAG, 0x3ab24b87)); 3259 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3260 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3261 getF32Constant(DAG, 0x3c1d8c17)); 3262 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3263 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3264 getF32Constant(DAG, 0x3d634a1d)); 3265 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3266 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3267 getF32Constant(DAG, 0x3e75fe14)); 3268 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3269 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3270 getF32Constant(DAG, 0x3f317234)); 3271 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3272 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3273 getF32Constant(DAG, 0x3f800000)); 3274 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, 3275 MVT::i32, t13); 3276 3277 // Add the exponent into the result in integer domain. 3278 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3279 TwoToFracPartOfX, IntegerPartOfX); 3280 3281 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); 3282 } 3283 } else { 3284 // No special expansion. 3285 result = DAG.getNode(ISD::FEXP, dl, 3286 getValue(I.getArgOperand(0)).getValueType(), 3287 getValue(I.getArgOperand(0))); 3288 } 3289 3290 setValue(&I, result); 3291} 3292 3293/// visitLog - Lower a log intrinsic. Handles the special sequences for 3294/// limited-precision mode. 3295void 3296SelectionDAGBuilder::visitLog(const CallInst &I) { 3297 SDValue result; 3298 DebugLoc dl = getCurDebugLoc(); 3299 3300 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3301 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3302 SDValue Op = getValue(I.getArgOperand(0)); 3303 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3304 3305 // Scale the exponent by log(2) [0.69314718f]. 3306 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3307 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3308 getF32Constant(DAG, 0x3f317218)); 3309 3310 // Get the significand and build it into a floating-point number with 3311 // exponent of 1. 3312 SDValue X = GetSignificand(DAG, Op1, dl); 3313 3314 if (LimitFloatPrecision <= 6) { 3315 // For floating-point precision of 6: 3316 // 3317 // LogofMantissa = 3318 // -1.1609546f + 3319 // (1.4034025f - 0.23903021f * x) * x; 3320 // 3321 // error 0.0034276066, which is better than 8 bits 3322 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3323 getF32Constant(DAG, 0xbe74c456)); 3324 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3325 getF32Constant(DAG, 0x3fb3a2b1)); 3326 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3327 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3328 getF32Constant(DAG, 0x3f949a29)); 3329 3330 result = DAG.getNode(ISD::FADD, dl, 3331 MVT::f32, LogOfExponent, LogOfMantissa); 3332 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3333 // For floating-point precision of 12: 3334 // 3335 // LogOfMantissa = 3336 // -1.7417939f + 3337 // (2.8212026f + 3338 // (-1.4699568f + 3339 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3340 // 3341 // error 0.000061011436, which is 14 bits 3342 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3343 getF32Constant(DAG, 0xbd67b6d6)); 3344 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3345 getF32Constant(DAG, 0x3ee4f4b8)); 3346 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3347 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3348 getF32Constant(DAG, 0x3fbc278b)); 3349 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3350 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3351 getF32Constant(DAG, 0x40348e95)); 3352 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3353 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3354 getF32Constant(DAG, 0x3fdef31a)); 3355 3356 result = DAG.getNode(ISD::FADD, dl, 3357 MVT::f32, LogOfExponent, LogOfMantissa); 3358 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3359 // For floating-point precision of 18: 3360 // 3361 // LogOfMantissa = 3362 // -2.1072184f + 3363 // (4.2372794f + 3364 // (-3.7029485f + 3365 // (2.2781945f + 3366 // (-0.87823314f + 3367 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3368 // 3369 // error 0.0000023660568, which is better than 18 bits 3370 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3371 getF32Constant(DAG, 0xbc91e5ac)); 3372 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3373 getF32Constant(DAG, 0x3e4350aa)); 3374 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3375 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3376 getF32Constant(DAG, 0x3f60d3e3)); 3377 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3378 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3379 getF32Constant(DAG, 0x4011cdf0)); 3380 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3381 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3382 getF32Constant(DAG, 0x406cfd1c)); 3383 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3384 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3385 getF32Constant(DAG, 0x408797cb)); 3386 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3387 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3388 getF32Constant(DAG, 0x4006dcab)); 3389 3390 result = DAG.getNode(ISD::FADD, dl, 3391 MVT::f32, LogOfExponent, LogOfMantissa); 3392 } 3393 } else { 3394 // No special expansion. 3395 result = DAG.getNode(ISD::FLOG, dl, 3396 getValue(I.getArgOperand(0)).getValueType(), 3397 getValue(I.getArgOperand(0))); 3398 } 3399 3400 setValue(&I, result); 3401} 3402 3403/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3404/// limited-precision mode. 3405void 3406SelectionDAGBuilder::visitLog2(const CallInst &I) { 3407 SDValue result; 3408 DebugLoc dl = getCurDebugLoc(); 3409 3410 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3411 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3412 SDValue Op = getValue(I.getArgOperand(0)); 3413 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3414 3415 // Get the exponent. 3416 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3417 3418 // Get the significand and build it into a floating-point number with 3419 // exponent of 1. 3420 SDValue X = GetSignificand(DAG, Op1, dl); 3421 3422 // Different possible minimax approximations of significand in 3423 // floating-point for various degrees of accuracy over [1,2]. 3424 if (LimitFloatPrecision <= 6) { 3425 // For floating-point precision of 6: 3426 // 3427 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3428 // 3429 // error 0.0049451742, which is more than 7 bits 3430 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3431 getF32Constant(DAG, 0xbeb08fe0)); 3432 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3433 getF32Constant(DAG, 0x40019463)); 3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3435 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3436 getF32Constant(DAG, 0x3fd6633d)); 3437 3438 result = DAG.getNode(ISD::FADD, dl, 3439 MVT::f32, LogOfExponent, Log2ofMantissa); 3440 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3441 // For floating-point precision of 12: 3442 // 3443 // Log2ofMantissa = 3444 // -2.51285454f + 3445 // (4.07009056f + 3446 // (-2.12067489f + 3447 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3448 // 3449 // error 0.0000876136000, which is better than 13 bits 3450 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3451 getF32Constant(DAG, 0xbda7262e)); 3452 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3453 getF32Constant(DAG, 0x3f25280b)); 3454 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3455 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3456 getF32Constant(DAG, 0x4007b923)); 3457 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3458 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3459 getF32Constant(DAG, 0x40823e2f)); 3460 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3461 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3462 getF32Constant(DAG, 0x4020d29c)); 3463 3464 result = DAG.getNode(ISD::FADD, dl, 3465 MVT::f32, LogOfExponent, Log2ofMantissa); 3466 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3467 // For floating-point precision of 18: 3468 // 3469 // Log2ofMantissa = 3470 // -3.0400495f + 3471 // (6.1129976f + 3472 // (-5.3420409f + 3473 // (3.2865683f + 3474 // (-1.2669343f + 3475 // (0.27515199f - 3476 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3477 // 3478 // error 0.0000018516, which is better than 18 bits 3479 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3480 getF32Constant(DAG, 0xbcd2769e)); 3481 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3482 getF32Constant(DAG, 0x3e8ce0b9)); 3483 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3484 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3485 getF32Constant(DAG, 0x3fa22ae7)); 3486 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3487 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3488 getF32Constant(DAG, 0x40525723)); 3489 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3490 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3491 getF32Constant(DAG, 0x40aaf200)); 3492 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3493 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3494 getF32Constant(DAG, 0x40c39dad)); 3495 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3496 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3497 getF32Constant(DAG, 0x4042902c)); 3498 3499 result = DAG.getNode(ISD::FADD, dl, 3500 MVT::f32, LogOfExponent, Log2ofMantissa); 3501 } 3502 } else { 3503 // No special expansion. 3504 result = DAG.getNode(ISD::FLOG2, dl, 3505 getValue(I.getArgOperand(0)).getValueType(), 3506 getValue(I.getArgOperand(0))); 3507 } 3508 3509 setValue(&I, result); 3510} 3511 3512/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3513/// limited-precision mode. 3514void 3515SelectionDAGBuilder::visitLog10(const CallInst &I) { 3516 SDValue result; 3517 DebugLoc dl = getCurDebugLoc(); 3518 3519 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3520 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3521 SDValue Op = getValue(I.getArgOperand(0)); 3522 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 3523 3524 // Scale the exponent by log10(2) [0.30102999f]. 3525 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3526 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3527 getF32Constant(DAG, 0x3e9a209a)); 3528 3529 // Get the significand and build it into a floating-point number with 3530 // exponent of 1. 3531 SDValue X = GetSignificand(DAG, Op1, dl); 3532 3533 if (LimitFloatPrecision <= 6) { 3534 // For floating-point precision of 6: 3535 // 3536 // Log10ofMantissa = 3537 // -0.50419619f + 3538 // (0.60948995f - 0.10380950f * x) * x; 3539 // 3540 // error 0.0014886165, which is 6 bits 3541 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3542 getF32Constant(DAG, 0xbdd49a13)); 3543 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3544 getF32Constant(DAG, 0x3f1c0789)); 3545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3546 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3547 getF32Constant(DAG, 0x3f011300)); 3548 3549 result = DAG.getNode(ISD::FADD, dl, 3550 MVT::f32, LogOfExponent, Log10ofMantissa); 3551 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3552 // For floating-point precision of 12: 3553 // 3554 // Log10ofMantissa = 3555 // -0.64831180f + 3556 // (0.91751397f + 3557 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3558 // 3559 // error 0.00019228036, which is better than 12 bits 3560 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3561 getF32Constant(DAG, 0x3d431f31)); 3562 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3563 getF32Constant(DAG, 0x3ea21fb2)); 3564 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3565 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3566 getF32Constant(DAG, 0x3f6ae232)); 3567 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3568 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3569 getF32Constant(DAG, 0x3f25f7c3)); 3570 3571 result = DAG.getNode(ISD::FADD, dl, 3572 MVT::f32, LogOfExponent, Log10ofMantissa); 3573 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3574 // For floating-point precision of 18: 3575 // 3576 // Log10ofMantissa = 3577 // -0.84299375f + 3578 // (1.5327582f + 3579 // (-1.0688956f + 3580 // (0.49102474f + 3581 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3582 // 3583 // error 0.0000037995730, which is better than 18 bits 3584 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3585 getF32Constant(DAG, 0x3c5d51ce)); 3586 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3587 getF32Constant(DAG, 0x3e00685a)); 3588 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3589 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3590 getF32Constant(DAG, 0x3efb6798)); 3591 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3592 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3593 getF32Constant(DAG, 0x3f88d192)); 3594 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3595 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3596 getF32Constant(DAG, 0x3fc4316c)); 3597 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3598 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3599 getF32Constant(DAG, 0x3f57ce70)); 3600 3601 result = DAG.getNode(ISD::FADD, dl, 3602 MVT::f32, LogOfExponent, Log10ofMantissa); 3603 } 3604 } else { 3605 // No special expansion. 3606 result = DAG.getNode(ISD::FLOG10, dl, 3607 getValue(I.getArgOperand(0)).getValueType(), 3608 getValue(I.getArgOperand(0))); 3609 } 3610 3611 setValue(&I, result); 3612} 3613 3614/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3615/// limited-precision mode. 3616void 3617SelectionDAGBuilder::visitExp2(const CallInst &I) { 3618 SDValue result; 3619 DebugLoc dl = getCurDebugLoc(); 3620 3621 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3622 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3623 SDValue Op = getValue(I.getArgOperand(0)); 3624 3625 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3626 3627 // FractionalPartOfX = x - (float)IntegerPartOfX; 3628 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3629 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3630 3631 // IntegerPartOfX <<= 23; 3632 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3633 DAG.getConstant(23, TLI.getPointerTy())); 3634 3635 if (LimitFloatPrecision <= 6) { 3636 // For floating-point precision of 6: 3637 // 3638 // TwoToFractionalPartOfX = 3639 // 0.997535578f + 3640 // (0.735607626f + 0.252464424f * x) * x; 3641 // 3642 // error 0.0144103317, which is 6 bits 3643 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3644 getF32Constant(DAG, 0x3e814304)); 3645 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3646 getF32Constant(DAG, 0x3f3c50c8)); 3647 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3648 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3649 getF32Constant(DAG, 0x3f7f5e7e)); 3650 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3651 SDValue TwoToFractionalPartOfX = 3652 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3653 3654 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3655 MVT::f32, TwoToFractionalPartOfX); 3656 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3657 // For floating-point precision of 12: 3658 // 3659 // TwoToFractionalPartOfX = 3660 // 0.999892986f + 3661 // (0.696457318f + 3662 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3663 // 3664 // error 0.000107046256, which is 13 to 14 bits 3665 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3666 getF32Constant(DAG, 0x3da235e3)); 3667 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3668 getF32Constant(DAG, 0x3e65b8f3)); 3669 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3670 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3671 getF32Constant(DAG, 0x3f324b07)); 3672 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3673 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3674 getF32Constant(DAG, 0x3f7ff8fd)); 3675 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3676 SDValue TwoToFractionalPartOfX = 3677 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3678 3679 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3680 MVT::f32, TwoToFractionalPartOfX); 3681 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3682 // For floating-point precision of 18: 3683 // 3684 // TwoToFractionalPartOfX = 3685 // 0.999999982f + 3686 // (0.693148872f + 3687 // (0.240227044f + 3688 // (0.554906021e-1f + 3689 // (0.961591928e-2f + 3690 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3691 // error 2.47208000*10^(-7), which is better than 18 bits 3692 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3693 getF32Constant(DAG, 0x3924b03e)); 3694 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3695 getF32Constant(DAG, 0x3ab24b87)); 3696 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3697 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3698 getF32Constant(DAG, 0x3c1d8c17)); 3699 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3700 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3701 getF32Constant(DAG, 0x3d634a1d)); 3702 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3703 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3704 getF32Constant(DAG, 0x3e75fe14)); 3705 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3706 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3707 getF32Constant(DAG, 0x3f317234)); 3708 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3709 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3710 getF32Constant(DAG, 0x3f800000)); 3711 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3712 SDValue TwoToFractionalPartOfX = 3713 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3714 3715 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3716 MVT::f32, TwoToFractionalPartOfX); 3717 } 3718 } else { 3719 // No special expansion. 3720 result = DAG.getNode(ISD::FEXP2, dl, 3721 getValue(I.getArgOperand(0)).getValueType(), 3722 getValue(I.getArgOperand(0))); 3723 } 3724 3725 setValue(&I, result); 3726} 3727 3728/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3729/// limited-precision mode with x == 10.0f. 3730void 3731SelectionDAGBuilder::visitPow(const CallInst &I) { 3732 SDValue result; 3733 const Value *Val = I.getArgOperand(0); 3734 DebugLoc dl = getCurDebugLoc(); 3735 bool IsExp10 = false; 3736 3737 if (getValue(Val).getValueType() == MVT::f32 && 3738 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3739 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3740 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3741 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3742 APFloat Ten(10.0f); 3743 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3744 } 3745 } 3746 } 3747 3748 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3749 SDValue Op = getValue(I.getArgOperand(1)); 3750 3751 // Put the exponent in the right bit position for later addition to the 3752 // final result: 3753 // 3754 // #define LOG2OF10 3.3219281f 3755 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3756 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3757 getF32Constant(DAG, 0x40549a78)); 3758 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3759 3760 // FractionalPartOfX = x - (float)IntegerPartOfX; 3761 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3762 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3763 3764 // IntegerPartOfX <<= 23; 3765 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3766 DAG.getConstant(23, TLI.getPointerTy())); 3767 3768 if (LimitFloatPrecision <= 6) { 3769 // For floating-point precision of 6: 3770 // 3771 // twoToFractionalPartOfX = 3772 // 0.997535578f + 3773 // (0.735607626f + 0.252464424f * x) * x; 3774 // 3775 // error 0.0144103317, which is 6 bits 3776 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3777 getF32Constant(DAG, 0x3e814304)); 3778 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3779 getF32Constant(DAG, 0x3f3c50c8)); 3780 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3781 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3782 getF32Constant(DAG, 0x3f7f5e7e)); 3783 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); 3784 SDValue TwoToFractionalPartOfX = 3785 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3786 3787 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3788 MVT::f32, TwoToFractionalPartOfX); 3789 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3790 // For floating-point precision of 12: 3791 // 3792 // TwoToFractionalPartOfX = 3793 // 0.999892986f + 3794 // (0.696457318f + 3795 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3796 // 3797 // error 0.000107046256, which is 13 to 14 bits 3798 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3799 getF32Constant(DAG, 0x3da235e3)); 3800 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3801 getF32Constant(DAG, 0x3e65b8f3)); 3802 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3803 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3804 getF32Constant(DAG, 0x3f324b07)); 3805 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3806 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3807 getF32Constant(DAG, 0x3f7ff8fd)); 3808 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); 3809 SDValue TwoToFractionalPartOfX = 3810 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3811 3812 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3813 MVT::f32, TwoToFractionalPartOfX); 3814 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3815 // For floating-point precision of 18: 3816 // 3817 // TwoToFractionalPartOfX = 3818 // 0.999999982f + 3819 // (0.693148872f + 3820 // (0.240227044f + 3821 // (0.554906021e-1f + 3822 // (0.961591928e-2f + 3823 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3824 // error 2.47208000*10^(-7), which is better than 18 bits 3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3826 getF32Constant(DAG, 0x3924b03e)); 3827 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3828 getF32Constant(DAG, 0x3ab24b87)); 3829 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3830 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3831 getF32Constant(DAG, 0x3c1d8c17)); 3832 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3833 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3834 getF32Constant(DAG, 0x3d634a1d)); 3835 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3836 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3837 getF32Constant(DAG, 0x3e75fe14)); 3838 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3839 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3840 getF32Constant(DAG, 0x3f317234)); 3841 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3842 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3843 getF32Constant(DAG, 0x3f800000)); 3844 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); 3845 SDValue TwoToFractionalPartOfX = 3846 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3847 3848 result = DAG.getNode(ISD::BIT_CONVERT, dl, 3849 MVT::f32, TwoToFractionalPartOfX); 3850 } 3851 } else { 3852 // No special expansion. 3853 result = DAG.getNode(ISD::FPOW, dl, 3854 getValue(I.getArgOperand(0)).getValueType(), 3855 getValue(I.getArgOperand(0)), 3856 getValue(I.getArgOperand(1))); 3857 } 3858 3859 setValue(&I, result); 3860} 3861 3862 3863/// ExpandPowI - Expand a llvm.powi intrinsic. 3864static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3865 SelectionDAG &DAG) { 3866 // If RHS is a constant, we can expand this out to a multiplication tree, 3867 // otherwise we end up lowering to a call to __powidf2 (for example). When 3868 // optimizing for size, we only want to do this if the expansion would produce 3869 // a small number of multiplies, otherwise we do the full expansion. 3870 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3871 // Get the exponent as a positive value. 3872 unsigned Val = RHSC->getSExtValue(); 3873 if ((int)Val < 0) Val = -Val; 3874 3875 // powi(x, 0) -> 1.0 3876 if (Val == 0) 3877 return DAG.getConstantFP(1.0, LHS.getValueType()); 3878 3879 const Function *F = DAG.getMachineFunction().getFunction(); 3880 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3881 // If optimizing for size, don't insert too many multiplies. This 3882 // inserts up to 5 multiplies. 3883 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3884 // We use the simple binary decomposition method to generate the multiply 3885 // sequence. There are more optimal ways to do this (for example, 3886 // powi(x,15) generates one more multiply than it should), but this has 3887 // the benefit of being both really simple and much better than a libcall. 3888 SDValue Res; // Logically starts equal to 1.0 3889 SDValue CurSquare = LHS; 3890 while (Val) { 3891 if (Val & 1) { 3892 if (Res.getNode()) 3893 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 3894 else 3895 Res = CurSquare; // 1.0*CurSquare. 3896 } 3897 3898 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 3899 CurSquare, CurSquare); 3900 Val >>= 1; 3901 } 3902 3903 // If the original was negative, invert the result, producing 1/(x*x*x). 3904 if (RHSC->getSExtValue() < 0) 3905 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 3906 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 3907 return Res; 3908 } 3909 } 3910 3911 // Otherwise, expand to a libcall. 3912 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 3913} 3914 3915/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 3916/// argument, create the corresponding DBG_VALUE machine instruction for it now. 3917/// At the end of instruction selection, they will be inserted to the entry BB. 3918bool 3919SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 3920 int64_t Offset, 3921 const SDValue &N) { 3922 const Argument *Arg = dyn_cast<Argument>(V); 3923 if (!Arg) 3924 return false; 3925 3926 MachineFunction &MF = DAG.getMachineFunction(); 3927 // Ignore inlined function arguments here. 3928 DIVariable DV(Variable); 3929 if (DV.isInlinedFnArgument(MF.getFunction())) 3930 return false; 3931 3932 MachineBasicBlock *MBB = FuncInfo.MBB; 3933 if (MBB != &MF.front()) 3934 return false; 3935 3936 unsigned Reg = 0; 3937 if (Arg->hasByValAttr()) { 3938 // Byval arguments' frame index is recorded during argument lowering. 3939 // Use this info directly. 3940 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 3941 Reg = TRI->getFrameRegister(MF); 3942 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 3943 } 3944 3945 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 3946 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 3947 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 3948 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3949 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 3950 if (PR) 3951 Reg = PR; 3952 } 3953 } 3954 3955 if (!Reg) { 3956 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 3957 if (VMI == FuncInfo.ValueMap.end()) 3958 return false; 3959 Reg = VMI->second; 3960 } 3961 3962 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 3963 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 3964 TII->get(TargetOpcode::DBG_VALUE)) 3965 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 3966 FuncInfo.ArgDbgValues.push_back(&*MIB); 3967 return true; 3968} 3969 3970// VisualStudio defines setjmp as _setjmp 3971#if defined(_MSC_VER) && defined(setjmp) 3972#define setjmp_undefined_for_visual_studio 3973#undef setjmp 3974#endif 3975 3976/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 3977/// we want to emit this as a call to a named external function, return the name 3978/// otherwise lower it and return null. 3979const char * 3980SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 3981 DebugLoc dl = getCurDebugLoc(); 3982 SDValue Res; 3983 3984 switch (Intrinsic) { 3985 default: 3986 // By default, turn this into a target intrinsic node. 3987 visitTargetIntrinsic(I, Intrinsic); 3988 return 0; 3989 case Intrinsic::vastart: visitVAStart(I); return 0; 3990 case Intrinsic::vaend: visitVAEnd(I); return 0; 3991 case Intrinsic::vacopy: visitVACopy(I); return 0; 3992 case Intrinsic::returnaddress: 3993 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 3994 getValue(I.getArgOperand(0)))); 3995 return 0; 3996 case Intrinsic::frameaddress: 3997 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 3998 getValue(I.getArgOperand(0)))); 3999 return 0; 4000 case Intrinsic::setjmp: 4001 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4002 case Intrinsic::longjmp: 4003 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4004 case Intrinsic::memcpy: { 4005 // Assert for address < 256 since we support only user defined address 4006 // spaces. 4007 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4008 < 256 && 4009 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4010 < 256 && 4011 "Unknown address space"); 4012 SDValue Op1 = getValue(I.getArgOperand(0)); 4013 SDValue Op2 = getValue(I.getArgOperand(1)); 4014 SDValue Op3 = getValue(I.getArgOperand(2)); 4015 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4016 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4017 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4018 MachinePointerInfo(I.getArgOperand(0)), 4019 MachinePointerInfo(I.getArgOperand(1)))); 4020 return 0; 4021 } 4022 case Intrinsic::memset: { 4023 // Assert for address < 256 since we support only user defined address 4024 // spaces. 4025 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4026 < 256 && 4027 "Unknown address space"); 4028 SDValue Op1 = getValue(I.getArgOperand(0)); 4029 SDValue Op2 = getValue(I.getArgOperand(1)); 4030 SDValue Op3 = getValue(I.getArgOperand(2)); 4031 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4032 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4033 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4034 MachinePointerInfo(I.getArgOperand(0)))); 4035 return 0; 4036 } 4037 case Intrinsic::memmove: { 4038 // Assert for address < 256 since we support only user defined address 4039 // spaces. 4040 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4041 < 256 && 4042 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4043 < 256 && 4044 "Unknown address space"); 4045 SDValue Op1 = getValue(I.getArgOperand(0)); 4046 SDValue Op2 = getValue(I.getArgOperand(1)); 4047 SDValue Op3 = getValue(I.getArgOperand(2)); 4048 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4049 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4050 4051 // If the source and destination are known to not be aliases, we can 4052 // lower memmove as memcpy. 4053 uint64_t Size = -1ULL; 4054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3)) 4055 Size = C->getZExtValue(); 4056 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == 4057 AliasAnalysis::NoAlias) { 4058 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4059 false, MachinePointerInfo(I.getArgOperand(0)), 4060 MachinePointerInfo(I.getArgOperand(1)))); 4061 return 0; 4062 } 4063 4064 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4065 MachinePointerInfo(I.getArgOperand(0)), 4066 MachinePointerInfo(I.getArgOperand(1)))); 4067 return 0; 4068 } 4069 case Intrinsic::dbg_declare: { 4070 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4071 MDNode *Variable = DI.getVariable(); 4072 const Value *Address = DI.getAddress(); 4073 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4074 return 0; 4075 4076 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4077 // but do not always have a corresponding SDNode built. The SDNodeOrder 4078 // absolute, but not relative, values are different depending on whether 4079 // debug info exists. 4080 ++SDNodeOrder; 4081 4082 // Check if address has undef value. 4083 if (isa<UndefValue>(Address) || 4084 (Address->use_empty() && !isa<Argument>(Address))) { 4085 SDDbgValue*SDV = 4086 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4087 0, dl, SDNodeOrder); 4088 DAG.AddDbgValue(SDV, 0, false); 4089 return 0; 4090 } 4091 4092 SDValue &N = NodeMap[Address]; 4093 if (!N.getNode() && isa<Argument>(Address)) 4094 // Check unused arguments map. 4095 N = UnusedArgNodeMap[Address]; 4096 SDDbgValue *SDV; 4097 if (N.getNode()) { 4098 // Parameters are handled specially. 4099 bool isParameter = 4100 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4101 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4102 Address = BCI->getOperand(0); 4103 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4104 4105 if (isParameter && !AI) { 4106 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4107 if (FINode) 4108 // Byval parameter. We have a frame index at this point. 4109 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4110 0, dl, SDNodeOrder); 4111 else 4112 // Can't do anything with other non-AI cases yet. This might be a 4113 // parameter of a callee function that got inlined, for example. 4114 return 0; 4115 } else if (AI) 4116 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4117 0, dl, SDNodeOrder); 4118 else 4119 // Can't do anything with other non-AI cases yet. 4120 return 0; 4121 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4122 } else { 4123 // If Address is an arugment then try to emits its dbg value using 4124 // virtual register info from the FuncInfo.ValueMap. 4125 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4126 // If variable is pinned by a alloca in dominating bb then 4127 // use StaticAllocaMap. 4128 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4129 if (AI->getParent() != DI.getParent()) { 4130 DenseMap<const AllocaInst*, int>::iterator SI = 4131 FuncInfo.StaticAllocaMap.find(AI); 4132 if (SI != FuncInfo.StaticAllocaMap.end()) { 4133 SDV = DAG.getDbgValue(Variable, SI->second, 4134 0, dl, SDNodeOrder); 4135 DAG.AddDbgValue(SDV, 0, false); 4136 return 0; 4137 } 4138 } 4139 } 4140 // Otherwise add undef to help track missing debug info. 4141 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 4142 0, dl, SDNodeOrder); 4143 DAG.AddDbgValue(SDV, 0, false); 4144 } 4145 } 4146 return 0; 4147 } 4148 case Intrinsic::dbg_value: { 4149 const DbgValueInst &DI = cast<DbgValueInst>(I); 4150 if (!DIVariable(DI.getVariable()).Verify()) 4151 return 0; 4152 4153 MDNode *Variable = DI.getVariable(); 4154 uint64_t Offset = DI.getOffset(); 4155 const Value *V = DI.getValue(); 4156 if (!V) 4157 return 0; 4158 4159 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4160 // but do not always have a corresponding SDNode built. The SDNodeOrder 4161 // absolute, but not relative, values are different depending on whether 4162 // debug info exists. 4163 ++SDNodeOrder; 4164 SDDbgValue *SDV; 4165 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4166 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4167 DAG.AddDbgValue(SDV, 0, false); 4168 } else { 4169 // Do not use getValue() in here; we don't want to generate code at 4170 // this point if it hasn't been done yet. 4171 SDValue N = NodeMap[V]; 4172 if (!N.getNode() && isa<Argument>(V)) 4173 // Check unused arguments map. 4174 N = UnusedArgNodeMap[V]; 4175 if (N.getNode()) { 4176 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4177 SDV = DAG.getDbgValue(Variable, N.getNode(), 4178 N.getResNo(), Offset, dl, SDNodeOrder); 4179 DAG.AddDbgValue(SDV, N.getNode(), false); 4180 } 4181 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4182 // Do not call getValue(V) yet, as we don't want to generate code. 4183 // Remember it for later. 4184 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4185 DanglingDebugInfoMap[V] = DDI; 4186 } else { 4187 // We may expand this to cover more cases. One case where we have no 4188 // data available is an unreferenced parameter; we need this fallback. 4189 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), 4190 Offset, dl, SDNodeOrder); 4191 DAG.AddDbgValue(SDV, 0, false); 4192 } 4193 } 4194 4195 // Build a debug info table entry. 4196 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4197 V = BCI->getOperand(0); 4198 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4199 // Don't handle byval struct arguments or VLAs, for example. 4200 if (!AI) 4201 return 0; 4202 DenseMap<const AllocaInst*, int>::iterator SI = 4203 FuncInfo.StaticAllocaMap.find(AI); 4204 if (SI == FuncInfo.StaticAllocaMap.end()) 4205 return 0; // VLAs. 4206 int FI = SI->second; 4207 4208 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4209 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4210 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4211 return 0; 4212 } 4213 case Intrinsic::eh_exception: { 4214 // Insert the EXCEPTIONADDR instruction. 4215 assert(FuncInfo.MBB->isLandingPad() && 4216 "Call to eh.exception not in landing pad!"); 4217 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4218 SDValue Ops[1]; 4219 Ops[0] = DAG.getRoot(); 4220 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4221 setValue(&I, Op); 4222 DAG.setRoot(Op.getValue(1)); 4223 return 0; 4224 } 4225 4226 case Intrinsic::eh_selector: { 4227 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4228 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4229 if (CallMBB->isLandingPad()) 4230 AddCatchInfo(I, &MMI, CallMBB); 4231 else { 4232#ifndef NDEBUG 4233 FuncInfo.CatchInfoLost.insert(&I); 4234#endif 4235 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4236 unsigned Reg = TLI.getExceptionSelectorRegister(); 4237 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4238 } 4239 4240 // Insert the EHSELECTION instruction. 4241 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4242 SDValue Ops[2]; 4243 Ops[0] = getValue(I.getArgOperand(0)); 4244 Ops[1] = getRoot(); 4245 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4246 DAG.setRoot(Op.getValue(1)); 4247 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4248 return 0; 4249 } 4250 4251 case Intrinsic::eh_typeid_for: { 4252 // Find the type id for the given typeinfo. 4253 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4254 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4255 Res = DAG.getConstant(TypeID, MVT::i32); 4256 setValue(&I, Res); 4257 return 0; 4258 } 4259 4260 case Intrinsic::eh_return_i32: 4261 case Intrinsic::eh_return_i64: 4262 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4263 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4264 MVT::Other, 4265 getControlRoot(), 4266 getValue(I.getArgOperand(0)), 4267 getValue(I.getArgOperand(1)))); 4268 return 0; 4269 case Intrinsic::eh_unwind_init: 4270 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4271 return 0; 4272 case Intrinsic::eh_dwarf_cfa: { 4273 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4274 TLI.getPointerTy()); 4275 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4276 TLI.getPointerTy(), 4277 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4278 TLI.getPointerTy()), 4279 CfaArg); 4280 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4281 TLI.getPointerTy(), 4282 DAG.getConstant(0, TLI.getPointerTy())); 4283 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4284 FA, Offset)); 4285 return 0; 4286 } 4287 case Intrinsic::eh_sjlj_callsite: { 4288 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4289 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4290 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4291 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4292 4293 MMI.setCurrentCallSite(CI->getZExtValue()); 4294 return 0; 4295 } 4296 case Intrinsic::eh_sjlj_setjmp: { 4297 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4298 getValue(I.getArgOperand(0)))); 4299 return 0; 4300 } 4301 case Intrinsic::eh_sjlj_longjmp: { 4302 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4303 getRoot(), 4304 getValue(I.getArgOperand(0)))); 4305 return 0; 4306 } 4307 4308 case Intrinsic::convertff: 4309 case Intrinsic::convertfsi: 4310 case Intrinsic::convertfui: 4311 case Intrinsic::convertsif: 4312 case Intrinsic::convertuif: 4313 case Intrinsic::convertss: 4314 case Intrinsic::convertsu: 4315 case Intrinsic::convertus: 4316 case Intrinsic::convertuu: { 4317 ISD::CvtCode Code = ISD::CVT_INVALID; 4318 switch (Intrinsic) { 4319 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4320 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4321 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4322 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4323 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4324 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4325 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4326 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4327 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4328 } 4329 EVT DestVT = TLI.getValueType(I.getType()); 4330 const Value *Op1 = I.getArgOperand(0); 4331 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4332 DAG.getValueType(DestVT), 4333 DAG.getValueType(getValue(Op1).getValueType()), 4334 getValue(I.getArgOperand(1)), 4335 getValue(I.getArgOperand(2)), 4336 Code); 4337 setValue(&I, Res); 4338 return 0; 4339 } 4340 case Intrinsic::sqrt: 4341 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4342 getValue(I.getArgOperand(0)).getValueType(), 4343 getValue(I.getArgOperand(0)))); 4344 return 0; 4345 case Intrinsic::powi: 4346 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4347 getValue(I.getArgOperand(1)), DAG)); 4348 return 0; 4349 case Intrinsic::sin: 4350 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4351 getValue(I.getArgOperand(0)).getValueType(), 4352 getValue(I.getArgOperand(0)))); 4353 return 0; 4354 case Intrinsic::cos: 4355 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4356 getValue(I.getArgOperand(0)).getValueType(), 4357 getValue(I.getArgOperand(0)))); 4358 return 0; 4359 case Intrinsic::log: 4360 visitLog(I); 4361 return 0; 4362 case Intrinsic::log2: 4363 visitLog2(I); 4364 return 0; 4365 case Intrinsic::log10: 4366 visitLog10(I); 4367 return 0; 4368 case Intrinsic::exp: 4369 visitExp(I); 4370 return 0; 4371 case Intrinsic::exp2: 4372 visitExp2(I); 4373 return 0; 4374 case Intrinsic::pow: 4375 visitPow(I); 4376 return 0; 4377 case Intrinsic::convert_to_fp16: 4378 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4379 MVT::i16, getValue(I.getArgOperand(0)))); 4380 return 0; 4381 case Intrinsic::convert_from_fp16: 4382 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4383 MVT::f32, getValue(I.getArgOperand(0)))); 4384 return 0; 4385 case Intrinsic::pcmarker: { 4386 SDValue Tmp = getValue(I.getArgOperand(0)); 4387 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4388 return 0; 4389 } 4390 case Intrinsic::readcyclecounter: { 4391 SDValue Op = getRoot(); 4392 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4393 DAG.getVTList(MVT::i64, MVT::Other), 4394 &Op, 1); 4395 setValue(&I, Res); 4396 DAG.setRoot(Res.getValue(1)); 4397 return 0; 4398 } 4399 case Intrinsic::bswap: 4400 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4401 getValue(I.getArgOperand(0)).getValueType(), 4402 getValue(I.getArgOperand(0)))); 4403 return 0; 4404 case Intrinsic::cttz: { 4405 SDValue Arg = getValue(I.getArgOperand(0)); 4406 EVT Ty = Arg.getValueType(); 4407 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4408 return 0; 4409 } 4410 case Intrinsic::ctlz: { 4411 SDValue Arg = getValue(I.getArgOperand(0)); 4412 EVT Ty = Arg.getValueType(); 4413 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4414 return 0; 4415 } 4416 case Intrinsic::ctpop: { 4417 SDValue Arg = getValue(I.getArgOperand(0)); 4418 EVT Ty = Arg.getValueType(); 4419 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4420 return 0; 4421 } 4422 case Intrinsic::stacksave: { 4423 SDValue Op = getRoot(); 4424 Res = DAG.getNode(ISD::STACKSAVE, dl, 4425 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4426 setValue(&I, Res); 4427 DAG.setRoot(Res.getValue(1)); 4428 return 0; 4429 } 4430 case Intrinsic::stackrestore: { 4431 Res = getValue(I.getArgOperand(0)); 4432 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4433 return 0; 4434 } 4435 case Intrinsic::stackprotector: { 4436 // Emit code into the DAG to store the stack guard onto the stack. 4437 MachineFunction &MF = DAG.getMachineFunction(); 4438 MachineFrameInfo *MFI = MF.getFrameInfo(); 4439 EVT PtrTy = TLI.getPointerTy(); 4440 4441 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4442 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4443 4444 int FI = FuncInfo.StaticAllocaMap[Slot]; 4445 MFI->setStackProtectorIndex(FI); 4446 4447 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4448 4449 // Store the stack protector onto the stack. 4450 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4451 PseudoSourceValue::getFixedStack(FI), 4452 0, true, false, 0); 4453 setValue(&I, Res); 4454 DAG.setRoot(Res); 4455 return 0; 4456 } 4457 case Intrinsic::objectsize: { 4458 // If we don't know by now, we're never going to know. 4459 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4460 4461 assert(CI && "Non-constant type in __builtin_object_size?"); 4462 4463 SDValue Arg = getValue(I.getCalledValue()); 4464 EVT Ty = Arg.getValueType(); 4465 4466 if (CI->isZero()) 4467 Res = DAG.getConstant(-1ULL, Ty); 4468 else 4469 Res = DAG.getConstant(0, Ty); 4470 4471 setValue(&I, Res); 4472 return 0; 4473 } 4474 case Intrinsic::var_annotation: 4475 // Discard annotate attributes 4476 return 0; 4477 4478 case Intrinsic::init_trampoline: { 4479 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4480 4481 SDValue Ops[6]; 4482 Ops[0] = getRoot(); 4483 Ops[1] = getValue(I.getArgOperand(0)); 4484 Ops[2] = getValue(I.getArgOperand(1)); 4485 Ops[3] = getValue(I.getArgOperand(2)); 4486 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4487 Ops[5] = DAG.getSrcValue(F); 4488 4489 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4490 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4491 Ops, 6); 4492 4493 setValue(&I, Res); 4494 DAG.setRoot(Res.getValue(1)); 4495 return 0; 4496 } 4497 case Intrinsic::gcroot: 4498 if (GFI) { 4499 const Value *Alloca = I.getArgOperand(0); 4500 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4501 4502 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4503 GFI->addStackRoot(FI->getIndex(), TypeMap); 4504 } 4505 return 0; 4506 case Intrinsic::gcread: 4507 case Intrinsic::gcwrite: 4508 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4509 return 0; 4510 case Intrinsic::flt_rounds: 4511 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4512 return 0; 4513 case Intrinsic::trap: 4514 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4515 return 0; 4516 case Intrinsic::uadd_with_overflow: 4517 return implVisitAluOverflow(I, ISD::UADDO); 4518 case Intrinsic::sadd_with_overflow: 4519 return implVisitAluOverflow(I, ISD::SADDO); 4520 case Intrinsic::usub_with_overflow: 4521 return implVisitAluOverflow(I, ISD::USUBO); 4522 case Intrinsic::ssub_with_overflow: 4523 return implVisitAluOverflow(I, ISD::SSUBO); 4524 case Intrinsic::umul_with_overflow: 4525 return implVisitAluOverflow(I, ISD::UMULO); 4526 case Intrinsic::smul_with_overflow: 4527 return implVisitAluOverflow(I, ISD::SMULO); 4528 4529 case Intrinsic::prefetch: { 4530 SDValue Ops[4]; 4531 Ops[0] = getRoot(); 4532 Ops[1] = getValue(I.getArgOperand(0)); 4533 Ops[2] = getValue(I.getArgOperand(1)); 4534 Ops[3] = getValue(I.getArgOperand(2)); 4535 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); 4536 return 0; 4537 } 4538 4539 case Intrinsic::memory_barrier: { 4540 SDValue Ops[6]; 4541 Ops[0] = getRoot(); 4542 for (int x = 1; x < 6; ++x) 4543 Ops[x] = getValue(I.getArgOperand(x - 1)); 4544 4545 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4546 return 0; 4547 } 4548 case Intrinsic::atomic_cmp_swap: { 4549 SDValue Root = getRoot(); 4550 SDValue L = 4551 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4552 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4553 Root, 4554 getValue(I.getArgOperand(0)), 4555 getValue(I.getArgOperand(1)), 4556 getValue(I.getArgOperand(2)), 4557 MachinePointerInfo(I.getArgOperand(0))); 4558 setValue(&I, L); 4559 DAG.setRoot(L.getValue(1)); 4560 return 0; 4561 } 4562 case Intrinsic::atomic_load_add: 4563 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4564 case Intrinsic::atomic_load_sub: 4565 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4566 case Intrinsic::atomic_load_or: 4567 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4568 case Intrinsic::atomic_load_xor: 4569 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4570 case Intrinsic::atomic_load_and: 4571 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4572 case Intrinsic::atomic_load_nand: 4573 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4574 case Intrinsic::atomic_load_max: 4575 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4576 case Intrinsic::atomic_load_min: 4577 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4578 case Intrinsic::atomic_load_umin: 4579 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4580 case Intrinsic::atomic_load_umax: 4581 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4582 case Intrinsic::atomic_swap: 4583 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4584 4585 case Intrinsic::invariant_start: 4586 case Intrinsic::lifetime_start: 4587 // Discard region information. 4588 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4589 return 0; 4590 case Intrinsic::invariant_end: 4591 case Intrinsic::lifetime_end: 4592 // Discard region information. 4593 return 0; 4594 } 4595} 4596 4597void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4598 bool isTailCall, 4599 MachineBasicBlock *LandingPad) { 4600 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4601 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4602 const Type *RetTy = FTy->getReturnType(); 4603 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4604 MCSymbol *BeginLabel = 0; 4605 4606 TargetLowering::ArgListTy Args; 4607 TargetLowering::ArgListEntry Entry; 4608 Args.reserve(CS.arg_size()); 4609 4610 // Check whether the function can return without sret-demotion. 4611 SmallVector<ISD::OutputArg, 4> Outs; 4612 SmallVector<uint64_t, 4> Offsets; 4613 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4614 Outs, TLI, &Offsets); 4615 4616 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4617 FTy->isVarArg(), Outs, FTy->getContext()); 4618 4619 SDValue DemoteStackSlot; 4620 int DemoteStackIdx = -100; 4621 4622 if (!CanLowerReturn) { 4623 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4624 FTy->getReturnType()); 4625 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4626 FTy->getReturnType()); 4627 MachineFunction &MF = DAG.getMachineFunction(); 4628 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4629 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4630 4631 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4632 Entry.Node = DemoteStackSlot; 4633 Entry.Ty = StackSlotPtrType; 4634 Entry.isSExt = false; 4635 Entry.isZExt = false; 4636 Entry.isInReg = false; 4637 Entry.isSRet = true; 4638 Entry.isNest = false; 4639 Entry.isByVal = false; 4640 Entry.Alignment = Align; 4641 Args.push_back(Entry); 4642 RetTy = Type::getVoidTy(FTy->getContext()); 4643 } 4644 4645 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4646 i != e; ++i) { 4647 SDValue ArgNode = getValue(*i); 4648 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4649 4650 unsigned attrInd = i - CS.arg_begin() + 1; 4651 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4652 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4653 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4654 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4655 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4656 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4657 Entry.Alignment = CS.getParamAlignment(attrInd); 4658 Args.push_back(Entry); 4659 } 4660 4661 if (LandingPad) { 4662 // Insert a label before the invoke call to mark the try range. This can be 4663 // used to detect deletion of the invoke via the MachineModuleInfo. 4664 BeginLabel = MMI.getContext().CreateTempSymbol(); 4665 4666 // For SjLj, keep track of which landing pads go with which invokes 4667 // so as to maintain the ordering of pads in the LSDA. 4668 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4669 if (CallSiteIndex) { 4670 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4671 // Now that the call site is handled, stop tracking it. 4672 MMI.setCurrentCallSite(0); 4673 } 4674 4675 // Both PendingLoads and PendingExports must be flushed here; 4676 // this call might not return. 4677 (void)getRoot(); 4678 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4679 } 4680 4681 // Check if target-independent constraints permit a tail call here. 4682 // Target-dependent constraints are checked within TLI.LowerCallTo. 4683 if (isTailCall && 4684 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4685 isTailCall = false; 4686 4687 // If there's a possibility that fast-isel has already selected some amount 4688 // of the current basic block, don't emit a tail call. 4689 if (isTailCall && EnableFastISel) 4690 isTailCall = false; 4691 4692 std::pair<SDValue,SDValue> Result = 4693 TLI.LowerCallTo(getRoot(), RetTy, 4694 CS.paramHasAttr(0, Attribute::SExt), 4695 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4696 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4697 CS.getCallingConv(), 4698 isTailCall, 4699 !CS.getInstruction()->use_empty(), 4700 Callee, Args, DAG, getCurDebugLoc()); 4701 assert((isTailCall || Result.second.getNode()) && 4702 "Non-null chain expected with non-tail call!"); 4703 assert((Result.second.getNode() || !Result.first.getNode()) && 4704 "Null value expected with tail call!"); 4705 if (Result.first.getNode()) { 4706 setValue(CS.getInstruction(), Result.first); 4707 } else if (!CanLowerReturn && Result.second.getNode()) { 4708 // The instruction result is the result of loading from the 4709 // hidden sret parameter. 4710 SmallVector<EVT, 1> PVTs; 4711 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4712 4713 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4714 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4715 EVT PtrVT = PVTs[0]; 4716 unsigned NumValues = Outs.size(); 4717 SmallVector<SDValue, 4> Values(NumValues); 4718 SmallVector<SDValue, 4> Chains(NumValues); 4719 4720 for (unsigned i = 0; i < NumValues; ++i) { 4721 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4722 DemoteStackSlot, 4723 DAG.getConstant(Offsets[i], PtrVT)); 4724 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4725 Add, 4726 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4727 false, false, 1); 4728 Values[i] = L; 4729 Chains[i] = L.getValue(1); 4730 } 4731 4732 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4733 MVT::Other, &Chains[0], NumValues); 4734 PendingLoads.push_back(Chain); 4735 4736 // Collect the legal value parts into potentially illegal values 4737 // that correspond to the original function's return values. 4738 SmallVector<EVT, 4> RetTys; 4739 RetTy = FTy->getReturnType(); 4740 ComputeValueVTs(TLI, RetTy, RetTys); 4741 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4742 SmallVector<SDValue, 4> ReturnValues; 4743 unsigned CurReg = 0; 4744 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4745 EVT VT = RetTys[I]; 4746 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4747 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4748 4749 SDValue ReturnValue = 4750 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4751 RegisterVT, VT, AssertOp); 4752 ReturnValues.push_back(ReturnValue); 4753 CurReg += NumRegs; 4754 } 4755 4756 setValue(CS.getInstruction(), 4757 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4758 DAG.getVTList(&RetTys[0], RetTys.size()), 4759 &ReturnValues[0], ReturnValues.size())); 4760 4761 } 4762 4763 // As a special case, a null chain means that a tail call has been emitted and 4764 // the DAG root is already updated. 4765 if (Result.second.getNode()) 4766 DAG.setRoot(Result.second); 4767 else 4768 HasTailCall = true; 4769 4770 if (LandingPad) { 4771 // Insert a label at the end of the invoke call to mark the try range. This 4772 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4773 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4774 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4775 4776 // Inform MachineModuleInfo of range. 4777 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4778 } 4779} 4780 4781/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4782/// value is equal or not-equal to zero. 4783static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4784 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4785 UI != E; ++UI) { 4786 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4787 if (IC->isEquality()) 4788 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4789 if (C->isNullValue()) 4790 continue; 4791 // Unknown instruction. 4792 return false; 4793 } 4794 return true; 4795} 4796 4797static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4798 const Type *LoadTy, 4799 SelectionDAGBuilder &Builder) { 4800 4801 // Check to see if this load can be trivially constant folded, e.g. if the 4802 // input is from a string literal. 4803 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4804 // Cast pointer to the type we really want to load. 4805 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4806 PointerType::getUnqual(LoadTy)); 4807 4808 if (const Constant *LoadCst = 4809 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4810 Builder.TD)) 4811 return Builder.getValue(LoadCst); 4812 } 4813 4814 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4815 // still constant memory, the input chain can be the entry node. 4816 SDValue Root; 4817 bool ConstantMemory = false; 4818 4819 // Do not serialize (non-volatile) loads of constant memory with anything. 4820 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 4821 Root = Builder.DAG.getEntryNode(); 4822 ConstantMemory = true; 4823 } else { 4824 // Do not serialize non-volatile loads against each other. 4825 Root = Builder.DAG.getRoot(); 4826 } 4827 4828 SDValue Ptr = Builder.getValue(PtrVal); 4829 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 4830 Ptr, MachinePointerInfo(PtrVal), 4831 false /*volatile*/, 4832 false /*nontemporal*/, 1 /* align=1 */); 4833 4834 if (!ConstantMemory) 4835 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 4836 return LoadVal; 4837} 4838 4839 4840/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 4841/// If so, return true and lower it, otherwise return false and it will be 4842/// lowered like a normal call. 4843bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 4844 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 4845 if (I.getNumArgOperands() != 3) 4846 return false; 4847 4848 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 4849 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 4850 !I.getArgOperand(2)->getType()->isIntegerTy() || 4851 !I.getType()->isIntegerTy()) 4852 return false; 4853 4854 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 4855 4856 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 4857 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 4858 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 4859 bool ActuallyDoIt = true; 4860 MVT LoadVT; 4861 const Type *LoadTy; 4862 switch (Size->getZExtValue()) { 4863 default: 4864 LoadVT = MVT::Other; 4865 LoadTy = 0; 4866 ActuallyDoIt = false; 4867 break; 4868 case 2: 4869 LoadVT = MVT::i16; 4870 LoadTy = Type::getInt16Ty(Size->getContext()); 4871 break; 4872 case 4: 4873 LoadVT = MVT::i32; 4874 LoadTy = Type::getInt32Ty(Size->getContext()); 4875 break; 4876 case 8: 4877 LoadVT = MVT::i64; 4878 LoadTy = Type::getInt64Ty(Size->getContext()); 4879 break; 4880 /* 4881 case 16: 4882 LoadVT = MVT::v4i32; 4883 LoadTy = Type::getInt32Ty(Size->getContext()); 4884 LoadTy = VectorType::get(LoadTy, 4); 4885 break; 4886 */ 4887 } 4888 4889 // This turns into unaligned loads. We only do this if the target natively 4890 // supports the MVT we'll be loading or if it is small enough (<= 4) that 4891 // we'll only produce a small number of byte loads. 4892 4893 // Require that we can find a legal MVT, and only do this if the target 4894 // supports unaligned loads of that type. Expanding into byte loads would 4895 // bloat the code. 4896 if (ActuallyDoIt && Size->getZExtValue() > 4) { 4897 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 4898 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 4899 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 4900 ActuallyDoIt = false; 4901 } 4902 4903 if (ActuallyDoIt) { 4904 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 4905 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 4906 4907 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 4908 ISD::SETNE); 4909 EVT CallVT = TLI.getValueType(I.getType(), true); 4910 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 4911 return true; 4912 } 4913 } 4914 4915 4916 return false; 4917} 4918 4919 4920void SelectionDAGBuilder::visitCall(const CallInst &I) { 4921 // Handle inline assembly differently. 4922 if (isa<InlineAsm>(I.getCalledValue())) { 4923 visitInlineAsm(&I); 4924 return; 4925 } 4926 4927 const char *RenameFn = 0; 4928 if (Function *F = I.getCalledFunction()) { 4929 if (F->isDeclaration()) { 4930 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 4931 if (unsigned IID = II->getIntrinsicID(F)) { 4932 RenameFn = visitIntrinsicCall(I, IID); 4933 if (!RenameFn) 4934 return; 4935 } 4936 } 4937 if (unsigned IID = F->getIntrinsicID()) { 4938 RenameFn = visitIntrinsicCall(I, IID); 4939 if (!RenameFn) 4940 return; 4941 } 4942 } 4943 4944 // Check for well-known libc/libm calls. If the function is internal, it 4945 // can't be a library call. 4946 if (!F->hasLocalLinkage() && F->hasName()) { 4947 StringRef Name = F->getName(); 4948 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 4949 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 4950 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4951 I.getType() == I.getArgOperand(0)->getType() && 4952 I.getType() == I.getArgOperand(1)->getType()) { 4953 SDValue LHS = getValue(I.getArgOperand(0)); 4954 SDValue RHS = getValue(I.getArgOperand(1)); 4955 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 4956 LHS.getValueType(), LHS, RHS)); 4957 return; 4958 } 4959 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 4960 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4961 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4962 I.getType() == I.getArgOperand(0)->getType()) { 4963 SDValue Tmp = getValue(I.getArgOperand(0)); 4964 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 4965 Tmp.getValueType(), Tmp)); 4966 return; 4967 } 4968 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 4969 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4970 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4971 I.getType() == I.getArgOperand(0)->getType() && 4972 I.onlyReadsMemory()) { 4973 SDValue Tmp = getValue(I.getArgOperand(0)); 4974 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 4975 Tmp.getValueType(), Tmp)); 4976 return; 4977 } 4978 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 4979 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4980 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4981 I.getType() == I.getArgOperand(0)->getType() && 4982 I.onlyReadsMemory()) { 4983 SDValue Tmp = getValue(I.getArgOperand(0)); 4984 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 4985 Tmp.getValueType(), Tmp)); 4986 return; 4987 } 4988 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 4989 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 4990 I.getArgOperand(0)->getType()->isFloatingPointTy() && 4991 I.getType() == I.getArgOperand(0)->getType() && 4992 I.onlyReadsMemory()) { 4993 SDValue Tmp = getValue(I.getArgOperand(0)); 4994 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 4995 Tmp.getValueType(), Tmp)); 4996 return; 4997 } 4998 } else if (Name == "memcmp") { 4999 if (visitMemCmpCall(I)) 5000 return; 5001 } 5002 } 5003 } 5004 5005 SDValue Callee; 5006 if (!RenameFn) 5007 Callee = getValue(I.getCalledValue()); 5008 else 5009 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5010 5011 // Check if we can potentially perform a tail call. More detailed checking is 5012 // be done within LowerCallTo, after more information about the call is known. 5013 LowerCallTo(&I, Callee, I.isTailCall()); 5014} 5015 5016namespace llvm { 5017 5018/// AsmOperandInfo - This contains information for each constraint that we are 5019/// lowering. 5020class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5021 public TargetLowering::AsmOperandInfo { 5022public: 5023 /// CallOperand - If this is the result output operand or a clobber 5024 /// this is null, otherwise it is the incoming operand to the CallInst. 5025 /// This gets modified as the asm is processed. 5026 SDValue CallOperand; 5027 5028 /// AssignedRegs - If this is a register or register class operand, this 5029 /// contains the set of register corresponding to the operand. 5030 RegsForValue AssignedRegs; 5031 5032 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5033 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5034 } 5035 5036 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5037 /// busy in OutputRegs/InputRegs. 5038 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5039 std::set<unsigned> &OutputRegs, 5040 std::set<unsigned> &InputRegs, 5041 const TargetRegisterInfo &TRI) const { 5042 if (isOutReg) { 5043 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5044 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5045 } 5046 if (isInReg) { 5047 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5048 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5049 } 5050 } 5051 5052 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5053 /// corresponds to. If there is no Value* for this operand, it returns 5054 /// MVT::Other. 5055 EVT getCallOperandValEVT(LLVMContext &Context, 5056 const TargetLowering &TLI, 5057 const TargetData *TD) const { 5058 if (CallOperandVal == 0) return MVT::Other; 5059 5060 if (isa<BasicBlock>(CallOperandVal)) 5061 return TLI.getPointerTy(); 5062 5063 const llvm::Type *OpTy = CallOperandVal->getType(); 5064 5065 // If this is an indirect operand, the operand is a pointer to the 5066 // accessed type. 5067 if (isIndirect) { 5068 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5069 if (!PtrTy) 5070 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5071 OpTy = PtrTy->getElementType(); 5072 } 5073 5074 // If OpTy is not a single value, it may be a struct/union that we 5075 // can tile with integers. 5076 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5077 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5078 switch (BitSize) { 5079 default: break; 5080 case 1: 5081 case 8: 5082 case 16: 5083 case 32: 5084 case 64: 5085 case 128: 5086 OpTy = IntegerType::get(Context, BitSize); 5087 break; 5088 } 5089 } 5090 5091 return TLI.getValueType(OpTy, true); 5092 } 5093 5094private: 5095 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5096 /// specified set. 5097 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5098 const TargetRegisterInfo &TRI) { 5099 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5100 Regs.insert(Reg); 5101 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5102 for (; *Aliases; ++Aliases) 5103 Regs.insert(*Aliases); 5104 } 5105}; 5106 5107} // end llvm namespace. 5108 5109/// isAllocatableRegister - If the specified register is safe to allocate, 5110/// i.e. it isn't a stack pointer or some other special register, return the 5111/// register class for the register. Otherwise, return null. 5112static const TargetRegisterClass * 5113isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5114 const TargetLowering &TLI, 5115 const TargetRegisterInfo *TRI) { 5116 EVT FoundVT = MVT::Other; 5117 const TargetRegisterClass *FoundRC = 0; 5118 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5119 E = TRI->regclass_end(); RCI != E; ++RCI) { 5120 EVT ThisVT = MVT::Other; 5121 5122 const TargetRegisterClass *RC = *RCI; 5123 // If none of the value types for this register class are valid, we 5124 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5125 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5126 I != E; ++I) { 5127 if (TLI.isTypeLegal(*I)) { 5128 // If we have already found this register in a different register class, 5129 // choose the one with the largest VT specified. For example, on 5130 // PowerPC, we favor f64 register classes over f32. 5131 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5132 ThisVT = *I; 5133 break; 5134 } 5135 } 5136 } 5137 5138 if (ThisVT == MVT::Other) continue; 5139 5140 // NOTE: This isn't ideal. In particular, this might allocate the 5141 // frame pointer in functions that need it (due to them not being taken 5142 // out of allocation, because a variable sized allocation hasn't been seen 5143 // yet). This is a slight code pessimization, but should still work. 5144 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5145 E = RC->allocation_order_end(MF); I != E; ++I) 5146 if (*I == Reg) { 5147 // We found a matching register class. Keep looking at others in case 5148 // we find one with larger registers that this physreg is also in. 5149 FoundRC = RC; 5150 FoundVT = ThisVT; 5151 break; 5152 } 5153 } 5154 return FoundRC; 5155} 5156 5157/// GetRegistersForValue - Assign registers (virtual or physical) for the 5158/// specified operand. We prefer to assign virtual registers, to allow the 5159/// register allocator to handle the assignment process. However, if the asm 5160/// uses features that we can't model on machineinstrs, we have SDISel do the 5161/// allocation. This produces generally horrible, but correct, code. 5162/// 5163/// OpInfo describes the operand. 5164/// Input and OutputRegs are the set of already allocated physical registers. 5165/// 5166void SelectionDAGBuilder:: 5167GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5168 std::set<unsigned> &OutputRegs, 5169 std::set<unsigned> &InputRegs) { 5170 LLVMContext &Context = FuncInfo.Fn->getContext(); 5171 5172 // Compute whether this value requires an input register, an output register, 5173 // or both. 5174 bool isOutReg = false; 5175 bool isInReg = false; 5176 switch (OpInfo.Type) { 5177 case InlineAsm::isOutput: 5178 isOutReg = true; 5179 5180 // If there is an input constraint that matches this, we need to reserve 5181 // the input register so no other inputs allocate to it. 5182 isInReg = OpInfo.hasMatchingInput(); 5183 break; 5184 case InlineAsm::isInput: 5185 isInReg = true; 5186 isOutReg = false; 5187 break; 5188 case InlineAsm::isClobber: 5189 isOutReg = true; 5190 isInReg = true; 5191 break; 5192 } 5193 5194 5195 MachineFunction &MF = DAG.getMachineFunction(); 5196 SmallVector<unsigned, 4> Regs; 5197 5198 // If this is a constraint for a single physreg, or a constraint for a 5199 // register class, find it. 5200 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5201 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5202 OpInfo.ConstraintVT); 5203 5204 unsigned NumRegs = 1; 5205 if (OpInfo.ConstraintVT != MVT::Other) { 5206 // If this is a FP input in an integer register (or visa versa) insert a bit 5207 // cast of the input value. More generally, handle any case where the input 5208 // value disagrees with the register class we plan to stick this in. 5209 if (OpInfo.Type == InlineAsm::isInput && 5210 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5211 // Try to convert to the first EVT that the reg class contains. If the 5212 // types are identical size, use a bitcast to convert (e.g. two differing 5213 // vector types). 5214 EVT RegVT = *PhysReg.second->vt_begin(); 5215 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5216 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5217 RegVT, OpInfo.CallOperand); 5218 OpInfo.ConstraintVT = RegVT; 5219 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5220 // If the input is a FP value and we want it in FP registers, do a 5221 // bitcast to the corresponding integer type. This turns an f64 value 5222 // into i64, which can be passed with two i32 values on a 32-bit 5223 // machine. 5224 RegVT = EVT::getIntegerVT(Context, 5225 OpInfo.ConstraintVT.getSizeInBits()); 5226 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5227 RegVT, OpInfo.CallOperand); 5228 OpInfo.ConstraintVT = RegVT; 5229 } 5230 } 5231 5232 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5233 } 5234 5235 EVT RegVT; 5236 EVT ValueVT = OpInfo.ConstraintVT; 5237 5238 // If this is a constraint for a specific physical register, like {r17}, 5239 // assign it now. 5240 if (unsigned AssignedReg = PhysReg.first) { 5241 const TargetRegisterClass *RC = PhysReg.second; 5242 if (OpInfo.ConstraintVT == MVT::Other) 5243 ValueVT = *RC->vt_begin(); 5244 5245 // Get the actual register value type. This is important, because the user 5246 // may have asked for (e.g.) the AX register in i32 type. We need to 5247 // remember that AX is actually i16 to get the right extension. 5248 RegVT = *RC->vt_begin(); 5249 5250 // This is a explicit reference to a physical register. 5251 Regs.push_back(AssignedReg); 5252 5253 // If this is an expanded reference, add the rest of the regs to Regs. 5254 if (NumRegs != 1) { 5255 TargetRegisterClass::iterator I = RC->begin(); 5256 for (; *I != AssignedReg; ++I) 5257 assert(I != RC->end() && "Didn't find reg!"); 5258 5259 // Already added the first reg. 5260 --NumRegs; ++I; 5261 for (; NumRegs; --NumRegs, ++I) { 5262 assert(I != RC->end() && "Ran out of registers to allocate!"); 5263 Regs.push_back(*I); 5264 } 5265 } 5266 5267 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5268 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5269 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5270 return; 5271 } 5272 5273 // Otherwise, if this was a reference to an LLVM register class, create vregs 5274 // for this reference. 5275 if (const TargetRegisterClass *RC = PhysReg.second) { 5276 RegVT = *RC->vt_begin(); 5277 if (OpInfo.ConstraintVT == MVT::Other) 5278 ValueVT = RegVT; 5279 5280 // Create the appropriate number of virtual registers. 5281 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5282 for (; NumRegs; --NumRegs) 5283 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5284 5285 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5286 return; 5287 } 5288 5289 // This is a reference to a register class that doesn't directly correspond 5290 // to an LLVM register class. Allocate NumRegs consecutive, available, 5291 // registers from the class. 5292 std::vector<unsigned> RegClassRegs 5293 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5294 OpInfo.ConstraintVT); 5295 5296 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5297 unsigned NumAllocated = 0; 5298 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5299 unsigned Reg = RegClassRegs[i]; 5300 // See if this register is available. 5301 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5302 (isInReg && InputRegs.count(Reg))) { // Already used. 5303 // Make sure we find consecutive registers. 5304 NumAllocated = 0; 5305 continue; 5306 } 5307 5308 // Check to see if this register is allocatable (i.e. don't give out the 5309 // stack pointer). 5310 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5311 if (!RC) { // Couldn't allocate this register. 5312 // Reset NumAllocated to make sure we return consecutive registers. 5313 NumAllocated = 0; 5314 continue; 5315 } 5316 5317 // Okay, this register is good, we can use it. 5318 ++NumAllocated; 5319 5320 // If we allocated enough consecutive registers, succeed. 5321 if (NumAllocated == NumRegs) { 5322 unsigned RegStart = (i-NumAllocated)+1; 5323 unsigned RegEnd = i+1; 5324 // Mark all of the allocated registers used. 5325 for (unsigned i = RegStart; i != RegEnd; ++i) 5326 Regs.push_back(RegClassRegs[i]); 5327 5328 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5329 OpInfo.ConstraintVT); 5330 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5331 return; 5332 } 5333 } 5334 5335 // Otherwise, we couldn't allocate enough registers for this. 5336} 5337 5338/// visitInlineAsm - Handle a call to an InlineAsm object. 5339/// 5340void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5341 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5342 5343 /// ConstraintOperands - Information about all of the constraints. 5344 std::vector<SDISelAsmOperandInfo> ConstraintOperands; 5345 5346 std::set<unsigned> OutputRegs, InputRegs; 5347 5348 std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(CS); 5349 bool hasMemory = false; 5350 5351 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5352 unsigned ResNo = 0; // ResNo - The result number of the next output. 5353 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5354 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5355 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5356 5357 EVT OpVT = MVT::Other; 5358 5359 // Compute the value type for each operand. 5360 switch (OpInfo.Type) { 5361 case InlineAsm::isOutput: 5362 // Indirect outputs just consume an argument. 5363 if (OpInfo.isIndirect) { 5364 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5365 break; 5366 } 5367 5368 // The return value of the call is this value. As such, there is no 5369 // corresponding argument. 5370 assert(!CS.getType()->isVoidTy() && 5371 "Bad inline asm!"); 5372 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5373 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5374 } else { 5375 assert(ResNo == 0 && "Asm only has one result!"); 5376 OpVT = TLI.getValueType(CS.getType()); 5377 } 5378 ++ResNo; 5379 break; 5380 case InlineAsm::isInput: 5381 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5382 break; 5383 case InlineAsm::isClobber: 5384 // Nothing to do. 5385 break; 5386 } 5387 5388 // If this is an input or an indirect output, process the call argument. 5389 // BasicBlocks are labels, currently appearing only in asm's. 5390 if (OpInfo.CallOperandVal) { 5391 // Strip bitcasts, if any. This mostly comes up for functions. 5392 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts(); 5393 5394 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5395 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5396 } else { 5397 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5398 } 5399 5400 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5401 } 5402 5403 OpInfo.ConstraintVT = OpVT; 5404 5405 // Indirect operand accesses access memory. 5406 if (OpInfo.isIndirect) 5407 hasMemory = true; 5408 else { 5409 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5410 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5411 if (CType == TargetLowering::C_Memory) { 5412 hasMemory = true; 5413 break; 5414 } 5415 } 5416 } 5417 } 5418 5419 SDValue Chain, Flag; 5420 5421 // We won't need to flush pending loads if this asm doesn't touch 5422 // memory and is nonvolatile. 5423 if (hasMemory || IA->hasSideEffects()) 5424 Chain = getRoot(); 5425 else 5426 Chain = DAG.getRoot(); 5427 5428 // Second pass over the constraints: compute which constraint option to use 5429 // and assign registers to constraints that want a specific physreg. 5430 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5431 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5432 5433 // Compute the constraint code and ConstraintType to use. 5434 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5435 5436 // If this is a memory input, and if the operand is not indirect, do what we 5437 // need to to provide an address for the memory input. 5438 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5439 !OpInfo.isIndirect) { 5440 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5441 "Can only indirectify direct input operands!"); 5442 5443 // Memory operands really want the address of the value. If we don't have 5444 // an indirect input, put it in the constpool if we can, otherwise spill 5445 // it to a stack slot. 5446 5447 // If the operand is a float, integer, or vector constant, spill to a 5448 // constant pool entry to get its address. 5449 const Value *OpVal = OpInfo.CallOperandVal; 5450 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5451 isa<ConstantVector>(OpVal)) { 5452 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5453 TLI.getPointerTy()); 5454 } else { 5455 // Otherwise, create a stack slot and emit a store to it before the 5456 // asm. 5457 const Type *Ty = OpVal->getType(); 5458 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5459 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5460 MachineFunction &MF = DAG.getMachineFunction(); 5461 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5462 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5463 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5464 OpInfo.CallOperand, StackSlot, 5465 MachinePointerInfo::getFixedStack(SSFI), 5466 false, false, 0); 5467 OpInfo.CallOperand = StackSlot; 5468 } 5469 5470 // There is no longer a Value* corresponding to this operand. 5471 OpInfo.CallOperandVal = 0; 5472 5473 // It is now an indirect operand. 5474 OpInfo.isIndirect = true; 5475 } 5476 5477 // If this constraint is for a specific register, allocate it before 5478 // anything else. 5479 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5480 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5481 } 5482 5483 // Second pass - Loop over all of the operands, assigning virtual or physregs 5484 // to register class operands. 5485 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5486 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5487 5488 // C_Register operands have already been allocated, Other/Memory don't need 5489 // to be. 5490 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5491 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5492 } 5493 5494 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5495 std::vector<SDValue> AsmNodeOperands; 5496 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5497 AsmNodeOperands.push_back( 5498 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5499 TLI.getPointerTy())); 5500 5501 // If we have a !srcloc metadata node associated with it, we want to attach 5502 // this to the ultimately generated inline asm machineinstr. To do this, we 5503 // pass in the third operand as this (potentially null) inline asm MDNode. 5504 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5505 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5506 5507 // Remember the AlignStack bit as operand 3. 5508 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5509 MVT::i1)); 5510 5511 // Loop over all of the inputs, copying the operand values into the 5512 // appropriate registers and processing the output regs. 5513 RegsForValue RetValRegs; 5514 5515 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5516 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5517 5518 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5519 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5520 5521 switch (OpInfo.Type) { 5522 case InlineAsm::isOutput: { 5523 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5524 OpInfo.ConstraintType != TargetLowering::C_Register) { 5525 // Memory output, or 'other' output (e.g. 'X' constraint). 5526 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5527 5528 // Add information to the INLINEASM node to know about this output. 5529 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5530 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5531 TLI.getPointerTy())); 5532 AsmNodeOperands.push_back(OpInfo.CallOperand); 5533 break; 5534 } 5535 5536 // Otherwise, this is a register or register class output. 5537 5538 // Copy the output from the appropriate register. Find a register that 5539 // we can use. 5540 if (OpInfo.AssignedRegs.Regs.empty()) 5541 report_fatal_error("Couldn't allocate output reg for constraint '" + 5542 Twine(OpInfo.ConstraintCode) + "'!"); 5543 5544 // If this is an indirect operand, store through the pointer after the 5545 // asm. 5546 if (OpInfo.isIndirect) { 5547 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5548 OpInfo.CallOperandVal)); 5549 } else { 5550 // This is the result value of the call. 5551 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5552 // Concatenate this output onto the outputs list. 5553 RetValRegs.append(OpInfo.AssignedRegs); 5554 } 5555 5556 // Add information to the INLINEASM node to know that this register is 5557 // set. 5558 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5559 InlineAsm::Kind_RegDefEarlyClobber : 5560 InlineAsm::Kind_RegDef, 5561 false, 5562 0, 5563 DAG, 5564 AsmNodeOperands); 5565 break; 5566 } 5567 case InlineAsm::isInput: { 5568 SDValue InOperandVal = OpInfo.CallOperand; 5569 5570 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5571 // If this is required to match an output register we have already set, 5572 // just use its register. 5573 unsigned OperandNo = OpInfo.getMatchedOperand(); 5574 5575 // Scan until we find the definition we already emitted of this operand. 5576 // When we find it, create a RegsForValue operand. 5577 unsigned CurOp = InlineAsm::Op_FirstOperand; 5578 for (; OperandNo; --OperandNo) { 5579 // Advance to the next operand. 5580 unsigned OpFlag = 5581 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5582 assert((InlineAsm::isRegDefKind(OpFlag) || 5583 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5584 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5585 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5586 } 5587 5588 unsigned OpFlag = 5589 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5590 if (InlineAsm::isRegDefKind(OpFlag) || 5591 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5592 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5593 if (OpInfo.isIndirect) { 5594 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5595 LLVMContext &Ctx = *DAG.getContext(); 5596 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5597 " don't know how to handle tied " 5598 "indirect register inputs"); 5599 } 5600 5601 RegsForValue MatchedRegs; 5602 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5603 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5604 MatchedRegs.RegVTs.push_back(RegVT); 5605 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5606 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5607 i != e; ++i) 5608 MatchedRegs.Regs.push_back 5609 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5610 5611 // Use the produced MatchedRegs object to 5612 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5613 Chain, &Flag); 5614 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5615 true, OpInfo.getMatchedOperand(), 5616 DAG, AsmNodeOperands); 5617 break; 5618 } 5619 5620 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5621 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5622 "Unexpected number of operands"); 5623 // Add information to the INLINEASM node to know about this input. 5624 // See InlineAsm.h isUseOperandTiedToDef. 5625 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5626 OpInfo.getMatchedOperand()); 5627 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5628 TLI.getPointerTy())); 5629 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5630 break; 5631 } 5632 5633 // Treat indirect 'X' constraint as memory. 5634 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5635 OpInfo.isIndirect) 5636 OpInfo.ConstraintType = TargetLowering::C_Memory; 5637 5638 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5639 std::vector<SDValue> Ops; 5640 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5641 Ops, DAG); 5642 if (Ops.empty()) 5643 report_fatal_error("Invalid operand for inline asm constraint '" + 5644 Twine(OpInfo.ConstraintCode) + "'!"); 5645 5646 // Add information to the INLINEASM node to know about this input. 5647 unsigned ResOpType = 5648 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5649 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5650 TLI.getPointerTy())); 5651 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5652 break; 5653 } 5654 5655 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5656 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5657 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5658 "Memory operands expect pointer values"); 5659 5660 // Add information to the INLINEASM node to know about this input. 5661 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5662 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5663 TLI.getPointerTy())); 5664 AsmNodeOperands.push_back(InOperandVal); 5665 break; 5666 } 5667 5668 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5669 OpInfo.ConstraintType == TargetLowering::C_Register) && 5670 "Unknown constraint type!"); 5671 assert(!OpInfo.isIndirect && 5672 "Don't know how to handle indirect register inputs yet!"); 5673 5674 // Copy the input into the appropriate registers. 5675 if (OpInfo.AssignedRegs.Regs.empty() || 5676 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5677 report_fatal_error("Couldn't allocate input reg for constraint '" + 5678 Twine(OpInfo.ConstraintCode) + "'!"); 5679 5680 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5681 Chain, &Flag); 5682 5683 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5684 DAG, AsmNodeOperands); 5685 break; 5686 } 5687 case InlineAsm::isClobber: { 5688 // Add the clobbered value to the operand list, so that the register 5689 // allocator is aware that the physreg got clobbered. 5690 if (!OpInfo.AssignedRegs.Regs.empty()) 5691 OpInfo.AssignedRegs.AddInlineAsmOperands( 5692 InlineAsm::Kind_RegDefEarlyClobber, 5693 false, 0, DAG, 5694 AsmNodeOperands); 5695 break; 5696 } 5697 } 5698 } 5699 5700 // Finish up input operands. Set the input chain and add the flag last. 5701 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5702 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5703 5704 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5705 DAG.getVTList(MVT::Other, MVT::Flag), 5706 &AsmNodeOperands[0], AsmNodeOperands.size()); 5707 Flag = Chain.getValue(1); 5708 5709 // If this asm returns a register value, copy the result from that register 5710 // and set it as the value of the call. 5711 if (!RetValRegs.Regs.empty()) { 5712 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5713 Chain, &Flag); 5714 5715 // FIXME: Why don't we do this for inline asms with MRVs? 5716 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5717 EVT ResultType = TLI.getValueType(CS.getType()); 5718 5719 // If any of the results of the inline asm is a vector, it may have the 5720 // wrong width/num elts. This can happen for register classes that can 5721 // contain multiple different value types. The preg or vreg allocated may 5722 // not have the same VT as was expected. Convert it to the right type 5723 // with bit_convert. 5724 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5725 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), 5726 ResultType, Val); 5727 5728 } else if (ResultType != Val.getValueType() && 5729 ResultType.isInteger() && Val.getValueType().isInteger()) { 5730 // If a result value was tied to an input value, the computed result may 5731 // have a wider width than the expected result. Extract the relevant 5732 // portion. 5733 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5734 } 5735 5736 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5737 } 5738 5739 setValue(CS.getInstruction(), Val); 5740 // Don't need to use this as a chain in this case. 5741 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5742 return; 5743 } 5744 5745 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5746 5747 // Process indirect outputs, first output all of the flagged copies out of 5748 // physregs. 5749 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5750 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5751 const Value *Ptr = IndirectStoresToEmit[i].second; 5752 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5753 Chain, &Flag); 5754 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5755 } 5756 5757 // Emit the non-flagged stores from the physregs. 5758 SmallVector<SDValue, 8> OutChains; 5759 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5760 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5761 StoresToEmit[i].first, 5762 getValue(StoresToEmit[i].second), 5763 StoresToEmit[i].second, 0, 5764 false, false, 0); 5765 OutChains.push_back(Val); 5766 } 5767 5768 if (!OutChains.empty()) 5769 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5770 &OutChains[0], OutChains.size()); 5771 5772 DAG.setRoot(Chain); 5773} 5774 5775void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5776 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5777 MVT::Other, getRoot(), 5778 getValue(I.getArgOperand(0)), 5779 DAG.getSrcValue(I.getArgOperand(0)))); 5780} 5781 5782void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 5783 const TargetData &TD = *TLI.getTargetData(); 5784 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 5785 getRoot(), getValue(I.getOperand(0)), 5786 DAG.getSrcValue(I.getOperand(0)), 5787 TD.getABITypeAlignment(I.getType())); 5788 setValue(&I, V); 5789 DAG.setRoot(V.getValue(1)); 5790} 5791 5792void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 5793 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 5794 MVT::Other, getRoot(), 5795 getValue(I.getArgOperand(0)), 5796 DAG.getSrcValue(I.getArgOperand(0)))); 5797} 5798 5799void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 5800 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 5801 MVT::Other, getRoot(), 5802 getValue(I.getArgOperand(0)), 5803 getValue(I.getArgOperand(1)), 5804 DAG.getSrcValue(I.getArgOperand(0)), 5805 DAG.getSrcValue(I.getArgOperand(1)))); 5806} 5807 5808/// TargetLowering::LowerCallTo - This is the default LowerCallTo 5809/// implementation, which just calls LowerCall. 5810/// FIXME: When all targets are 5811/// migrated to using LowerCall, this hook should be integrated into SDISel. 5812std::pair<SDValue, SDValue> 5813TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 5814 bool RetSExt, bool RetZExt, bool isVarArg, 5815 bool isInreg, unsigned NumFixedArgs, 5816 CallingConv::ID CallConv, bool isTailCall, 5817 bool isReturnValueUsed, 5818 SDValue Callee, 5819 ArgListTy &Args, SelectionDAG &DAG, 5820 DebugLoc dl) const { 5821 // Handle all of the outgoing arguments. 5822 SmallVector<ISD::OutputArg, 32> Outs; 5823 SmallVector<SDValue, 32> OutVals; 5824 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 5825 SmallVector<EVT, 4> ValueVTs; 5826 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 5827 for (unsigned Value = 0, NumValues = ValueVTs.size(); 5828 Value != NumValues; ++Value) { 5829 EVT VT = ValueVTs[Value]; 5830 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 5831 SDValue Op = SDValue(Args[i].Node.getNode(), 5832 Args[i].Node.getResNo() + Value); 5833 ISD::ArgFlagsTy Flags; 5834 unsigned OriginalAlignment = 5835 getTargetData()->getABITypeAlignment(ArgTy); 5836 5837 if (Args[i].isZExt) 5838 Flags.setZExt(); 5839 if (Args[i].isSExt) 5840 Flags.setSExt(); 5841 if (Args[i].isInReg) 5842 Flags.setInReg(); 5843 if (Args[i].isSRet) 5844 Flags.setSRet(); 5845 if (Args[i].isByVal) { 5846 Flags.setByVal(); 5847 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 5848 const Type *ElementTy = Ty->getElementType(); 5849 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 5850 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 5851 // For ByVal, alignment should come from FE. BE will guess if this 5852 // info is not there but there are cases it cannot get right. 5853 if (Args[i].Alignment) 5854 FrameAlign = Args[i].Alignment; 5855 Flags.setByValAlign(FrameAlign); 5856 Flags.setByValSize(FrameSize); 5857 } 5858 if (Args[i].isNest) 5859 Flags.setNest(); 5860 Flags.setOrigAlign(OriginalAlignment); 5861 5862 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 5863 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 5864 SmallVector<SDValue, 4> Parts(NumParts); 5865 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 5866 5867 if (Args[i].isSExt) 5868 ExtendKind = ISD::SIGN_EXTEND; 5869 else if (Args[i].isZExt) 5870 ExtendKind = ISD::ZERO_EXTEND; 5871 5872 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 5873 PartVT, ExtendKind); 5874 5875 for (unsigned j = 0; j != NumParts; ++j) { 5876 // if it isn't first piece, alignment must be 1 5877 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 5878 i < NumFixedArgs); 5879 if (NumParts > 1 && j == 0) 5880 MyFlags.Flags.setSplit(); 5881 else if (j != 0) 5882 MyFlags.Flags.setOrigAlign(1); 5883 5884 Outs.push_back(MyFlags); 5885 OutVals.push_back(Parts[j]); 5886 } 5887 } 5888 } 5889 5890 // Handle the incoming return values from the call. 5891 SmallVector<ISD::InputArg, 32> Ins; 5892 SmallVector<EVT, 4> RetTys; 5893 ComputeValueVTs(*this, RetTy, RetTys); 5894 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5895 EVT VT = RetTys[I]; 5896 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5897 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5898 for (unsigned i = 0; i != NumRegs; ++i) { 5899 ISD::InputArg MyFlags; 5900 MyFlags.VT = RegisterVT; 5901 MyFlags.Used = isReturnValueUsed; 5902 if (RetSExt) 5903 MyFlags.Flags.setSExt(); 5904 if (RetZExt) 5905 MyFlags.Flags.setZExt(); 5906 if (isInreg) 5907 MyFlags.Flags.setInReg(); 5908 Ins.push_back(MyFlags); 5909 } 5910 } 5911 5912 SmallVector<SDValue, 4> InVals; 5913 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 5914 Outs, OutVals, Ins, dl, DAG, InVals); 5915 5916 // Verify that the target's LowerCall behaved as expected. 5917 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 5918 "LowerCall didn't return a valid chain!"); 5919 assert((!isTailCall || InVals.empty()) && 5920 "LowerCall emitted a return value for a tail call!"); 5921 assert((isTailCall || InVals.size() == Ins.size()) && 5922 "LowerCall didn't emit the correct number of values!"); 5923 5924 // For a tail call, the return value is merely live-out and there aren't 5925 // any nodes in the DAG representing it. Return a special value to 5926 // indicate that a tail call has been emitted and no more Instructions 5927 // should be processed in the current block. 5928 if (isTailCall) { 5929 DAG.setRoot(Chain); 5930 return std::make_pair(SDValue(), SDValue()); 5931 } 5932 5933 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 5934 assert(InVals[i].getNode() && 5935 "LowerCall emitted a null value!"); 5936 assert(Ins[i].VT == InVals[i].getValueType() && 5937 "LowerCall emitted a value with the wrong type!"); 5938 }); 5939 5940 // Collect the legal value parts into potentially illegal values 5941 // that correspond to the original function's return values. 5942 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5943 if (RetSExt) 5944 AssertOp = ISD::AssertSext; 5945 else if (RetZExt) 5946 AssertOp = ISD::AssertZext; 5947 SmallVector<SDValue, 4> ReturnValues; 5948 unsigned CurReg = 0; 5949 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5950 EVT VT = RetTys[I]; 5951 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 5952 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 5953 5954 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 5955 NumRegs, RegisterVT, VT, 5956 AssertOp)); 5957 CurReg += NumRegs; 5958 } 5959 5960 // For a function returning void, there is no return value. We can't create 5961 // such a node, so we just return a null return value in that case. In 5962 // that case, nothing will actualy look at the value. 5963 if (ReturnValues.empty()) 5964 return std::make_pair(SDValue(), Chain); 5965 5966 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 5967 DAG.getVTList(&RetTys[0], RetTys.size()), 5968 &ReturnValues[0], ReturnValues.size()); 5969 return std::make_pair(Res, Chain); 5970} 5971 5972void TargetLowering::LowerOperationWrapper(SDNode *N, 5973 SmallVectorImpl<SDValue> &Results, 5974 SelectionDAG &DAG) const { 5975 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 5976 if (Res.getNode()) 5977 Results.push_back(Res); 5978} 5979 5980SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5981 llvm_unreachable("LowerOperation not implemented for this target!"); 5982 return SDValue(); 5983} 5984 5985void 5986SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 5987 SDValue Op = getNonRegisterValue(V); 5988 assert((Op.getOpcode() != ISD::CopyFromReg || 5989 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 5990 "Copy from a reg to the same reg!"); 5991 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 5992 5993 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 5994 SDValue Chain = DAG.getEntryNode(); 5995 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 5996 PendingExports.push_back(Chain); 5997} 5998 5999#include "llvm/CodeGen/SelectionDAGISel.h" 6000 6001void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6002 // If this is the entry block, emit arguments. 6003 const Function &F = *LLVMBB->getParent(); 6004 SelectionDAG &DAG = SDB->DAG; 6005 DebugLoc dl = SDB->getCurDebugLoc(); 6006 const TargetData *TD = TLI.getTargetData(); 6007 SmallVector<ISD::InputArg, 16> Ins; 6008 6009 // Check whether the function can return without sret-demotion. 6010 SmallVector<ISD::OutputArg, 4> Outs; 6011 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6012 Outs, TLI); 6013 6014 if (!FuncInfo->CanLowerReturn) { 6015 // Put in an sret pointer parameter before all the other parameters. 6016 SmallVector<EVT, 1> ValueVTs; 6017 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6018 6019 // NOTE: Assuming that a pointer will never break down to more than one VT 6020 // or one register. 6021 ISD::ArgFlagsTy Flags; 6022 Flags.setSRet(); 6023 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6024 ISD::InputArg RetArg(Flags, RegisterVT, true); 6025 Ins.push_back(RetArg); 6026 } 6027 6028 // Set up the incoming argument description vector. 6029 unsigned Idx = 1; 6030 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6031 I != E; ++I, ++Idx) { 6032 SmallVector<EVT, 4> ValueVTs; 6033 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6034 bool isArgValueUsed = !I->use_empty(); 6035 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6036 Value != NumValues; ++Value) { 6037 EVT VT = ValueVTs[Value]; 6038 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6039 ISD::ArgFlagsTy Flags; 6040 unsigned OriginalAlignment = 6041 TD->getABITypeAlignment(ArgTy); 6042 6043 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6044 Flags.setZExt(); 6045 if (F.paramHasAttr(Idx, Attribute::SExt)) 6046 Flags.setSExt(); 6047 if (F.paramHasAttr(Idx, Attribute::InReg)) 6048 Flags.setInReg(); 6049 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6050 Flags.setSRet(); 6051 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6052 Flags.setByVal(); 6053 const PointerType *Ty = cast<PointerType>(I->getType()); 6054 const Type *ElementTy = Ty->getElementType(); 6055 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6056 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6057 // For ByVal, alignment should be passed from FE. BE will guess if 6058 // this info is not there but there are cases it cannot get right. 6059 if (F.getParamAlignment(Idx)) 6060 FrameAlign = F.getParamAlignment(Idx); 6061 Flags.setByValAlign(FrameAlign); 6062 Flags.setByValSize(FrameSize); 6063 } 6064 if (F.paramHasAttr(Idx, Attribute::Nest)) 6065 Flags.setNest(); 6066 Flags.setOrigAlign(OriginalAlignment); 6067 6068 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6069 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6070 for (unsigned i = 0; i != NumRegs; ++i) { 6071 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6072 if (NumRegs > 1 && i == 0) 6073 MyFlags.Flags.setSplit(); 6074 // if it isn't first piece, alignment must be 1 6075 else if (i > 0) 6076 MyFlags.Flags.setOrigAlign(1); 6077 Ins.push_back(MyFlags); 6078 } 6079 } 6080 } 6081 6082 // Call the target to set up the argument values. 6083 SmallVector<SDValue, 8> InVals; 6084 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6085 F.isVarArg(), Ins, 6086 dl, DAG, InVals); 6087 6088 // Verify that the target's LowerFormalArguments behaved as expected. 6089 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6090 "LowerFormalArguments didn't return a valid chain!"); 6091 assert(InVals.size() == Ins.size() && 6092 "LowerFormalArguments didn't emit the correct number of values!"); 6093 DEBUG({ 6094 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6095 assert(InVals[i].getNode() && 6096 "LowerFormalArguments emitted a null value!"); 6097 assert(Ins[i].VT == InVals[i].getValueType() && 6098 "LowerFormalArguments emitted a value with the wrong type!"); 6099 } 6100 }); 6101 6102 // Update the DAG with the new chain value resulting from argument lowering. 6103 DAG.setRoot(NewRoot); 6104 6105 // Set up the argument values. 6106 unsigned i = 0; 6107 Idx = 1; 6108 if (!FuncInfo->CanLowerReturn) { 6109 // Create a virtual register for the sret pointer, and put in a copy 6110 // from the sret argument into it. 6111 SmallVector<EVT, 1> ValueVTs; 6112 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6113 EVT VT = ValueVTs[0]; 6114 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6115 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6116 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6117 RegVT, VT, AssertOp); 6118 6119 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6120 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6121 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6122 FuncInfo->DemoteRegister = SRetReg; 6123 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6124 SRetReg, ArgValue); 6125 DAG.setRoot(NewRoot); 6126 6127 // i indexes lowered arguments. Bump it past the hidden sret argument. 6128 // Idx indexes LLVM arguments. Don't touch it. 6129 ++i; 6130 } 6131 6132 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6133 ++I, ++Idx) { 6134 SmallVector<SDValue, 4> ArgValues; 6135 SmallVector<EVT, 4> ValueVTs; 6136 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6137 unsigned NumValues = ValueVTs.size(); 6138 6139 // If this argument is unused then remember its value. It is used to generate 6140 // debugging information. 6141 if (I->use_empty() && NumValues) 6142 SDB->setUnusedArgValue(I, InVals[i]); 6143 6144 for (unsigned Value = 0; Value != NumValues; ++Value) { 6145 EVT VT = ValueVTs[Value]; 6146 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6147 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6148 6149 if (!I->use_empty()) { 6150 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6151 if (F.paramHasAttr(Idx, Attribute::SExt)) 6152 AssertOp = ISD::AssertSext; 6153 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6154 AssertOp = ISD::AssertZext; 6155 6156 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6157 NumParts, PartVT, VT, 6158 AssertOp)); 6159 } 6160 6161 i += NumParts; 6162 } 6163 6164 // Note down frame index for byval arguments. 6165 if (I->hasByValAttr() && !ArgValues.empty()) 6166 if (FrameIndexSDNode *FI = 6167 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6168 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6169 6170 if (!I->use_empty()) { 6171 SDValue Res; 6172 if (!ArgValues.empty()) 6173 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6174 SDB->getCurDebugLoc()); 6175 SDB->setValue(I, Res); 6176 6177 // If this argument is live outside of the entry block, insert a copy from 6178 // whereever we got it to the vreg that other BB's will reference it as. 6179 SDB->CopyToExportRegsIfNeeded(I); 6180 } 6181 } 6182 6183 assert(i == InVals.size() && "Argument register count mismatch!"); 6184 6185 // Finally, if the target has anything special to do, allow it to do so. 6186 // FIXME: this should insert code into the DAG! 6187 EmitFunctionEntryCode(); 6188} 6189 6190/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6191/// ensure constants are generated when needed. Remember the virtual registers 6192/// that need to be added to the Machine PHI nodes as input. We cannot just 6193/// directly add them, because expansion might result in multiple MBB's for one 6194/// BB. As such, the start of the BB might correspond to a different MBB than 6195/// the end. 6196/// 6197void 6198SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6199 const TerminatorInst *TI = LLVMBB->getTerminator(); 6200 6201 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6202 6203 // Check successor nodes' PHI nodes that expect a constant to be available 6204 // from this block. 6205 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6206 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6207 if (!isa<PHINode>(SuccBB->begin())) continue; 6208 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6209 6210 // If this terminator has multiple identical successors (common for 6211 // switches), only handle each succ once. 6212 if (!SuccsHandled.insert(SuccMBB)) continue; 6213 6214 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6215 6216 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6217 // nodes and Machine PHI nodes, but the incoming operands have not been 6218 // emitted yet. 6219 for (BasicBlock::const_iterator I = SuccBB->begin(); 6220 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6221 // Ignore dead phi's. 6222 if (PN->use_empty()) continue; 6223 6224 unsigned Reg; 6225 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6226 6227 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6228 unsigned &RegOut = ConstantsOut[C]; 6229 if (RegOut == 0) { 6230 RegOut = FuncInfo.CreateRegs(C->getType()); 6231 CopyValueToVirtualRegister(C, RegOut); 6232 } 6233 Reg = RegOut; 6234 } else { 6235 DenseMap<const Value *, unsigned>::iterator I = 6236 FuncInfo.ValueMap.find(PHIOp); 6237 if (I != FuncInfo.ValueMap.end()) 6238 Reg = I->second; 6239 else { 6240 assert(isa<AllocaInst>(PHIOp) && 6241 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6242 "Didn't codegen value into a register!??"); 6243 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6244 CopyValueToVirtualRegister(PHIOp, Reg); 6245 } 6246 } 6247 6248 // Remember that this register needs to added to the machine PHI node as 6249 // the input for this MBB. 6250 SmallVector<EVT, 4> ValueVTs; 6251 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6252 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6253 EVT VT = ValueVTs[vti]; 6254 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6255 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6256 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6257 Reg += NumRegisters; 6258 } 6259 } 6260 } 6261 ConstantsOut.clear(); 6262} 6263