SelectionDAGBuilder.cpp revision 72ea0c9ffaa1700730c8ce36e9b73aef4b914988
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DebugInfo.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Function.h" 27#include "llvm/GlobalVariable.h" 28#include "llvm/InlineAsm.h" 29#include "llvm/Instructions.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/IntrinsicInst.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Module.h" 34#include "llvm/CodeGen/Analysis.h" 35#include "llvm/CodeGen/FastISel.h" 36#include "llvm/CodeGen/FunctionLoweringInfo.h" 37#include "llvm/CodeGen/GCStrategy.h" 38#include "llvm/CodeGen/GCMetadata.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineFrameInfo.h" 41#include "llvm/CodeGen/MachineInstrBuilder.h" 42#include "llvm/CodeGen/MachineJumpTableInfo.h" 43#include "llvm/CodeGen/MachineModuleInfo.h" 44#include "llvm/CodeGen/MachineRegisterInfo.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/IntegersSubsetMapping.h" 55#include "llvm/Support/Debug.h" 56#include "llvm/Support/ErrorHandling.h" 57#include "llvm/Support/MathExtras.h" 58#include "llvm/Support/raw_ostream.h" 59#include <algorithm> 60using namespace llvm; 61 62/// LimitFloatPrecision - Generate low-precision inline sequences for 63/// some float libcalls (6, 8 or 12 bits). 64static unsigned LimitFloatPrecision; 65 66static cl::opt<unsigned, true> 67LimitFPPrecision("limit-float-precision", 68 cl::desc("Generate low-precision inline sequences " 69 "for some float libcalls"), 70 cl::location(LimitFloatPrecision), 71 cl::init(0)); 72 73// Limit the width of DAG chains. This is important in general to prevent 74// prevent DAG-based analysis from blowing up. For example, alias analysis and 75// load clustering may not complete in reasonable time. It is difficult to 76// recognize and avoid this situation within each individual analysis, and 77// future analyses are likely to have the same behavior. Limiting DAG width is 78// the safe approach, and will be especially important with global DAGs. 79// 80// MaxParallelChains default is arbitrarily high to avoid affecting 81// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 82// sequence over this should have been converted to llvm.memcpy by the 83// frontend. It easy to induce this behavior with .ll code such as: 84// %buffer = alloca [4096 x i8] 85// %data = load [4096 x i8]* %argPtr 86// store [4096 x i8] %data, [4096 x i8]* %buffer 87static const unsigned MaxParallelChains = 64; 88 89static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 90 const SDValue *Parts, unsigned NumParts, 91 EVT PartVT, EVT ValueVT); 92 93/// getCopyFromParts - Create a value that contains the specified legal parts 94/// combined into the value they represent. If the parts combine to a type 95/// larger then ValueVT then AssertOp can be used to specify whether the extra 96/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 97/// (ISD::AssertSext). 98static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 99 const SDValue *Parts, 100 unsigned NumParts, EVT PartVT, EVT ValueVT, 101 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 102 if (ValueVT.isVector()) 103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 104 105 assert(NumParts > 0 && "No parts to assemble!"); 106 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 107 SDValue Val = Parts[0]; 108 109 if (NumParts > 1) { 110 // Assemble the value from multiple parts. 111 if (ValueVT.isInteger()) { 112 unsigned PartBits = PartVT.getSizeInBits(); 113 unsigned ValueBits = ValueVT.getSizeInBits(); 114 115 // Assemble the power of 2 part. 116 unsigned RoundParts = NumParts & (NumParts - 1) ? 117 1 << Log2_32(NumParts) : NumParts; 118 unsigned RoundBits = PartBits * RoundParts; 119 EVT RoundVT = RoundBits == ValueBits ? 120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 121 SDValue Lo, Hi; 122 123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 124 125 if (RoundParts > 2) { 126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 127 PartVT, HalfVT); 128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 129 RoundParts / 2, PartVT, HalfVT); 130 } else { 131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 133 } 134 135 if (TLI.isBigEndian()) 136 std::swap(Lo, Hi); 137 138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 139 140 if (RoundParts < NumParts) { 141 // Assemble the trailing non-power-of-2 part. 142 unsigned OddParts = NumParts - RoundParts; 143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 144 Hi = getCopyFromParts(DAG, DL, 145 Parts + RoundParts, OddParts, PartVT, OddVT); 146 147 // Combine the round and odd parts. 148 Lo = Val; 149 if (TLI.isBigEndian()) 150 std::swap(Lo, Hi); 151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 154 DAG.getConstant(Lo.getValueType().getSizeInBits(), 155 TLI.getPointerTy())); 156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 158 } 159 } else if (PartVT.isFloatingPoint()) { 160 // FP split into multiple FP parts (for ppcf128) 161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 162 "Unexpected split"); 163 SDValue Lo, Hi; 164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 166 if (TLI.isBigEndian()) 167 std::swap(Lo, Hi); 168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 169 } else { 170 // FP split into integer parts (soft fp) 171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 172 !PartVT.isVector() && "Unexpected split"); 173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 175 } 176 } 177 178 // There is now one part, held in Val. Correct it to match ValueVT. 179 PartVT = Val.getValueType(); 180 181 if (PartVT == ValueVT) 182 return Val; 183 184 if (PartVT.isInteger() && ValueVT.isInteger()) { 185 if (ValueVT.bitsLT(PartVT)) { 186 // For a truncate, see if we have any information to 187 // indicate whether the truncated bits will always be 188 // zero or sign-extension. 189 if (AssertOp != ISD::DELETED_NODE) 190 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 191 DAG.getValueType(ValueVT)); 192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 193 } 194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 195 } 196 197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 198 // FP_ROUND's are always exact here. 199 if (ValueVT.bitsLT(Val.getValueType())) 200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 201 DAG.getTargetConstant(1, TLI.getPointerTy())); 202 203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 204 } 205 206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 208 209 llvm_unreachable("Unknown mismatch!"); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 357 ValueVT.isInteger() && 358 "Unknown mismatch!"); 359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 361 if (PartVT == MVT::x86mmx) 362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 363 } 364 } else if (PartBits == ValueVT.getSizeInBits()) { 365 // Different types of the same size. 366 assert(NumParts == 1 && PartVT != ValueVT); 367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 369 // If the parts cover less bits than value has, truncate the value. 370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 371 ValueVT.isInteger() && 372 "Unknown mismatch!"); 373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 375 if (PartVT == MVT::x86mmx) 376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 377 } 378 379 // The value may have changed - recompute ValueVT. 380 ValueVT = Val.getValueType(); 381 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 382 "Failed to tile the value with PartVT!"); 383 384 if (NumParts == 1) { 385 assert(PartVT == ValueVT && "Type conversion failed!"); 386 Parts[0] = Val; 387 return; 388 } 389 390 // Expand the value into multiple parts. 391 if (NumParts & (NumParts - 1)) { 392 // The number of parts is not a power of 2. Split off and copy the tail. 393 assert(PartVT.isInteger() && ValueVT.isInteger() && 394 "Do not know what to expand to!"); 395 unsigned RoundParts = 1 << Log2_32(NumParts); 396 unsigned RoundBits = RoundParts * PartBits; 397 unsigned OddParts = NumParts - RoundParts; 398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 399 DAG.getIntPtrConstant(RoundBits)); 400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 401 402 if (TLI.isBigEndian()) 403 // The odd parts were reversed by getCopyToParts - unreverse them. 404 std::reverse(Parts + RoundParts, Parts + NumParts); 405 406 NumParts = RoundParts; 407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 409 } 410 411 // The number of parts is a power of 2. Repeatedly bisect the value using 412 // EXTRACT_ELEMENT. 413 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 414 EVT::getIntegerVT(*DAG.getContext(), 415 ValueVT.getSizeInBits()), 416 Val); 417 418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 419 for (unsigned i = 0; i < NumParts; i += StepSize) { 420 unsigned ThisBits = StepSize * PartBits / 2; 421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 422 SDValue &Part0 = Parts[i]; 423 SDValue &Part1 = Parts[i+StepSize/2]; 424 425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 426 ThisVT, Part0, DAG.getIntPtrConstant(1)); 427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 428 ThisVT, Part0, DAG.getIntPtrConstant(0)); 429 430 if (ThisBits == PartBits && ThisVT != PartVT) { 431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 433 } 434 } 435 } 436 437 if (TLI.isBigEndian()) 438 std::reverse(Parts, Parts + OrigNumParts); 439} 440 441 442/// getCopyToPartsVector - Create a series of nodes that contain the specified 443/// value split into legal parts. 444static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 445 SDValue Val, SDValue *Parts, unsigned NumParts, 446 EVT PartVT) { 447 EVT ValueVT = Val.getValueType(); 448 assert(ValueVT.isVector() && "Not a vector"); 449 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 450 451 if (NumParts == 1) { 452 if (PartVT == ValueVT) { 453 // Nothing to do. 454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 455 // Bitconvert vector->vector case. 456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 457 } else if (PartVT.isVector() && 458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 460 EVT ElementVT = PartVT.getVectorElementType(); 461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 462 // undef elements. 463 SmallVector<SDValue, 16> Ops; 464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 466 ElementVT, Val, DAG.getIntPtrConstant(i))); 467 468 for (unsigned i = ValueVT.getVectorNumElements(), 469 e = PartVT.getVectorNumElements(); i != e; ++i) 470 Ops.push_back(DAG.getUNDEF(ElementVT)); 471 472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 473 474 // FIXME: Use CONCAT for 2x -> 4x. 475 476 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 478 } else if (PartVT.isVector() && 479 PartVT.getVectorElementType().bitsGE( 480 ValueVT.getVectorElementType()) && 481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 482 483 // Promoted vector extract 484 bool Smaller = PartVT.bitsLE(ValueVT); 485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 486 DL, PartVT, Val); 487 } else{ 488 // Vector -> scalar conversion. 489 assert(ValueVT.getVectorNumElements() == 1 && 490 "Only trivial vector-to-scalar conversions should get here!"); 491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 492 PartVT, Val, DAG.getIntPtrConstant(0)); 493 494 bool Smaller = ValueVT.bitsLE(PartVT); 495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 496 DL, PartVT, Val); 497 } 498 499 Parts[0] = Val; 500 return; 501 } 502 503 // Handle a multi-element vector. 504 EVT IntermediateVT, RegisterVT; 505 unsigned NumIntermediates; 506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 507 IntermediateVT, 508 NumIntermediates, RegisterVT); 509 unsigned NumElements = ValueVT.getVectorNumElements(); 510 511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 512 NumParts = NumRegs; // Silence a compiler warning. 513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 514 515 // Split the vector into intermediate operands. 516 SmallVector<SDValue, 8> Ops(NumIntermediates); 517 for (unsigned i = 0; i != NumIntermediates; ++i) { 518 if (IntermediateVT.isVector()) 519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 520 IntermediateVT, Val, 521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 522 else 523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 524 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 525 } 526 527 // Split the intermediate operands into legal parts. 528 if (NumParts == NumIntermediates) { 529 // If the register was not expanded, promote or copy the value, 530 // as appropriate. 531 for (unsigned i = 0; i != NumParts; ++i) 532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 533 } else if (NumParts > 0) { 534 // If the intermediate type was expanded, split each the value into 535 // legal parts. 536 assert(NumParts % NumIntermediates == 0 && 537 "Must expand into a divisible number of parts!"); 538 unsigned Factor = NumParts / NumIntermediates; 539 for (unsigned i = 0; i != NumIntermediates; ++i) 540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 541 } 542} 543 544 545 546 547namespace { 548 /// RegsForValue - This struct represents the registers (physical or virtual) 549 /// that a particular set of values is assigned, and the type information 550 /// about the value. The most common situation is to represent one value at a 551 /// time, but struct or array values are handled element-wise as multiple 552 /// values. The splitting of aggregates is performed recursively, so that we 553 /// never have aggregate-typed registers. The values at this point do not 554 /// necessarily have legal types, so each value may require one or more 555 /// registers of some legal type. 556 /// 557 struct RegsForValue { 558 /// ValueVTs - The value types of the values, which may not be legal, and 559 /// may need be promoted or synthesized from one or more registers. 560 /// 561 SmallVector<EVT, 4> ValueVTs; 562 563 /// RegVTs - The value types of the registers. This is the same size as 564 /// ValueVTs and it records, for each value, what the type of the assigned 565 /// register or registers are. (Individual values are never synthesized 566 /// from more than one type of register.) 567 /// 568 /// With virtual registers, the contents of RegVTs is redundant with TLI's 569 /// getRegisterType member function, however when with physical registers 570 /// it is necessary to have a separate record of the types. 571 /// 572 SmallVector<EVT, 4> RegVTs; 573 574 /// Regs - This list holds the registers assigned to the values. 575 /// Each legal or promoted value requires one register, and each 576 /// expanded value requires multiple registers. 577 /// 578 SmallVector<unsigned, 4> Regs; 579 580 RegsForValue() {} 581 582 RegsForValue(const SmallVector<unsigned, 4> ®s, 583 EVT regvt, EVT valuevt) 584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 585 586 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 587 unsigned Reg, Type *Ty) { 588 ComputeValueVTs(tli, Ty, ValueVTs); 589 590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 591 EVT ValueVT = ValueVTs[Value]; 592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 594 for (unsigned i = 0; i != NumRegs; ++i) 595 Regs.push_back(Reg + i); 596 RegVTs.push_back(RegisterVT); 597 Reg += NumRegs; 598 } 599 } 600 601 /// areValueTypesLegal - Return true if types of all the values are legal. 602 bool areValueTypesLegal(const TargetLowering &TLI) { 603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 604 EVT RegisterVT = RegVTs[Value]; 605 if (!TLI.isTypeLegal(RegisterVT)) 606 return false; 607 } 608 return true; 609 } 610 611 /// append - Add the specified values to this one. 612 void append(const RegsForValue &RHS) { 613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 615 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 616 } 617 618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 619 /// this value and returns the result as a ValueVTs value. This uses 620 /// Chain/Flag as the input and updates them for the output Chain/Flag. 621 /// If the Flag pointer is NULL, no flag is used. 622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 623 DebugLoc dl, 624 SDValue &Chain, SDValue *Flag) const; 625 626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 627 /// specified value into the registers specified by this object. This uses 628 /// Chain/Flag as the input and updates them for the output Chain/Flag. 629 /// If the Flag pointer is NULL, no flag is used. 630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 631 SDValue &Chain, SDValue *Flag) const; 632 633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 634 /// operand list. This adds the code marker, matching input operand index 635 /// (if applicable), and includes the number of values added into it. 636 void AddInlineAsmOperands(unsigned Kind, 637 bool HasMatching, unsigned MatchingIdx, 638 SelectionDAG &DAG, 639 std::vector<SDValue> &Ops) const; 640 }; 641} 642 643/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 644/// this value and returns the result as a ValueVT value. This uses 645/// Chain/Flag as the input and updates them for the output Chain/Flag. 646/// If the Flag pointer is NULL, no flag is used. 647SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 648 FunctionLoweringInfo &FuncInfo, 649 DebugLoc dl, 650 SDValue &Chain, SDValue *Flag) const { 651 // A Value with type {} or [0 x %t] needs no registers. 652 if (ValueVTs.empty()) 653 return SDValue(); 654 655 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 656 657 // Assemble the legal parts into the final values. 658 SmallVector<SDValue, 4> Values(ValueVTs.size()); 659 SmallVector<SDValue, 8> Parts; 660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 661 // Copy the legal parts from the registers. 662 EVT ValueVT = ValueVTs[Value]; 663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 664 EVT RegisterVT = RegVTs[Value]; 665 666 Parts.resize(NumRegs); 667 for (unsigned i = 0; i != NumRegs; ++i) { 668 SDValue P; 669 if (Flag == 0) { 670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 671 } else { 672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 673 *Flag = P.getValue(2); 674 } 675 676 Chain = P.getValue(1); 677 Parts[i] = P; 678 679 // If the source register was virtual and if we know something about it, 680 // add an assert node. 681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 682 !RegisterVT.isInteger() || RegisterVT.isVector()) 683 continue; 684 685 const FunctionLoweringInfo::LiveOutInfo *LOI = 686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 687 if (!LOI) 688 continue; 689 690 unsigned RegSize = RegisterVT.getSizeInBits(); 691 unsigned NumSignBits = LOI->NumSignBits; 692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 693 694 // FIXME: We capture more information than the dag can represent. For 695 // now, just use the tightest assertzext/assertsext possible. 696 bool isSExt = true; 697 EVT FromVT(MVT::Other); 698 if (NumSignBits == RegSize) 699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 700 else if (NumZeroBits >= RegSize-1) 701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 702 else if (NumSignBits > RegSize-8) 703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 704 else if (NumZeroBits >= RegSize-8) 705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 706 else if (NumSignBits > RegSize-16) 707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 708 else if (NumZeroBits >= RegSize-16) 709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 710 else if (NumSignBits > RegSize-32) 711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 712 else if (NumZeroBits >= RegSize-32) 713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 714 else 715 continue; 716 717 // Add an assertion node. 718 assert(FromVT != MVT::Other); 719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 720 RegisterVT, P, DAG.getValueType(FromVT)); 721 } 722 723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 724 NumRegs, RegisterVT, ValueVT); 725 Part += NumRegs; 726 Parts.clear(); 727 } 728 729 return DAG.getNode(ISD::MERGE_VALUES, dl, 730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 731 &Values[0], ValueVTs.size()); 732} 733 734/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 735/// specified value into the registers specified by this object. This uses 736/// Chain/Flag as the input and updates them for the output Chain/Flag. 737/// If the Flag pointer is NULL, no flag is used. 738void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 739 SDValue &Chain, SDValue *Flag) const { 740 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 741 742 // Get the list of the values's legal parts. 743 unsigned NumRegs = Regs.size(); 744 SmallVector<SDValue, 8> Parts(NumRegs); 745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 746 EVT ValueVT = ValueVTs[Value]; 747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 748 EVT RegisterVT = RegVTs[Value]; 749 750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 751 &Parts[Part], NumParts, RegisterVT); 752 Part += NumParts; 753 } 754 755 // Copy the parts into the registers. 756 SmallVector<SDValue, 8> Chains(NumRegs); 757 for (unsigned i = 0; i != NumRegs; ++i) { 758 SDValue Part; 759 if (Flag == 0) { 760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 761 } else { 762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 763 *Flag = Part.getValue(1); 764 } 765 766 Chains[i] = Part.getValue(0); 767 } 768 769 if (NumRegs == 1 || Flag) 770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 771 // flagged to it. That is the CopyToReg nodes and the user are considered 772 // a single scheduling unit. If we create a TokenFactor and return it as 773 // chain, then the TokenFactor is both a predecessor (operand) of the 774 // user as well as a successor (the TF operands are flagged to the user). 775 // c1, f1 = CopyToReg 776 // c2, f2 = CopyToReg 777 // c3 = TokenFactor c1, c2 778 // ... 779 // = op c3, ..., f2 780 Chain = Chains[NumRegs-1]; 781 else 782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 783} 784 785/// AddInlineAsmOperands - Add this value to the specified inlineasm node 786/// operand list. This adds the code marker and includes the number of 787/// values added into it. 788void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 789 unsigned MatchingIdx, 790 SelectionDAG &DAG, 791 std::vector<SDValue> &Ops) const { 792 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 793 794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 795 if (HasMatching) 796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 797 else if (!Regs.empty() && 798 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 799 // Put the register class of the virtual registers in the flag word. That 800 // way, later passes can recompute register class constraints for inline 801 // assembly as well as normal instructions. 802 // Don't do this for tied operands that can use the regclass information 803 // from the def. 804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 807 } 808 809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 810 Ops.push_back(Res); 811 812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 814 EVT RegisterVT = RegVTs[Value]; 815 for (unsigned i = 0; i != NumRegs; ++i) { 816 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 818 } 819 } 820} 821 822void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 823 const TargetLibraryInfo *li) { 824 AA = &aa; 825 GFI = gfi; 826 LibInfo = li; 827 TD = DAG.getTarget().getTargetData(); 828 LPadToCallSiteMap.clear(); 829} 830 831/// clear - Clear out the current SelectionDAG and the associated 832/// state and prepare this SelectionDAGBuilder object to be used 833/// for a new block. This doesn't clear out information about 834/// additional blocks that are needed to complete switch lowering 835/// or PHI node updating; that information is cleared out as it is 836/// consumed. 837void SelectionDAGBuilder::clear() { 838 NodeMap.clear(); 839 UnusedArgNodeMap.clear(); 840 PendingLoads.clear(); 841 PendingExports.clear(); 842 CurDebugLoc = DebugLoc(); 843 HasTailCall = false; 844} 845 846/// clearDanglingDebugInfo - Clear the dangling debug information 847/// map. This function is separated from the clear so that debug 848/// information that is dangling in a basic block can be properly 849/// resolved in a different basic block. This allows the 850/// SelectionDAG to resolve dangling debug information attached 851/// to PHI nodes. 852void SelectionDAGBuilder::clearDanglingDebugInfo() { 853 DanglingDebugInfoMap.clear(); 854} 855 856/// getRoot - Return the current virtual root of the Selection DAG, 857/// flushing any PendingLoad items. This must be done before emitting 858/// a store or any other node that may need to be ordered after any 859/// prior load instructions. 860/// 861SDValue SelectionDAGBuilder::getRoot() { 862 if (PendingLoads.empty()) 863 return DAG.getRoot(); 864 865 if (PendingLoads.size() == 1) { 866 SDValue Root = PendingLoads[0]; 867 DAG.setRoot(Root); 868 PendingLoads.clear(); 869 return Root; 870 } 871 872 // Otherwise, we have to make a token factor node. 873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 874 &PendingLoads[0], PendingLoads.size()); 875 PendingLoads.clear(); 876 DAG.setRoot(Root); 877 return Root; 878} 879 880/// getControlRoot - Similar to getRoot, but instead of flushing all the 881/// PendingLoad items, flush all the PendingExports items. It is necessary 882/// to do this before emitting a terminator instruction. 883/// 884SDValue SelectionDAGBuilder::getControlRoot() { 885 SDValue Root = DAG.getRoot(); 886 887 if (PendingExports.empty()) 888 return Root; 889 890 // Turn all of the CopyToReg chains into one factored node. 891 if (Root.getOpcode() != ISD::EntryToken) { 892 unsigned i = 0, e = PendingExports.size(); 893 for (; i != e; ++i) { 894 assert(PendingExports[i].getNode()->getNumOperands() > 1); 895 if (PendingExports[i].getNode()->getOperand(0) == Root) 896 break; // Don't add the root if we already indirectly depend on it. 897 } 898 899 if (i == e) 900 PendingExports.push_back(Root); 901 } 902 903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingExports[0], 905 PendingExports.size()); 906 PendingExports.clear(); 907 DAG.setRoot(Root); 908 return Root; 909} 910 911void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 913 DAG.AssignOrdering(Node, SDNodeOrder); 914 915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 916 AssignOrderingToNode(Node->getOperand(I).getNode()); 917} 918 919void SelectionDAGBuilder::visit(const Instruction &I) { 920 // Set up outgoing PHI node register values before emitting the terminator. 921 if (isa<TerminatorInst>(&I)) 922 HandlePHINodesInSuccessorBlocks(I.getParent()); 923 924 CurDebugLoc = I.getDebugLoc(); 925 926 visit(I.getOpcode(), I); 927 928 if (!isa<TerminatorInst>(&I) && !HasTailCall) 929 CopyToExportRegsIfNeeded(&I); 930 931 CurDebugLoc = DebugLoc(); 932} 933 934void SelectionDAGBuilder::visitPHI(const PHINode &) { 935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 936} 937 938void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 939 // Note: this doesn't use InstVisitor, because it has to work with 940 // ConstantExpr's in addition to instructions. 941 switch (Opcode) { 942 default: llvm_unreachable("Unknown instruction type encountered!"); 943 // Build the switch statement using the Instruction.def file. 944#define HANDLE_INST(NUM, OPCODE, CLASS) \ 945 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 946#include "llvm/Instruction.def" 947 } 948 949 // Assign the ordering to the freshly created DAG nodes. 950 if (NodeMap.count(&I)) { 951 ++SDNodeOrder; 952 AssignOrderingToNode(getValue(&I).getNode()); 953 } 954} 955 956// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 957// generate the debug data structures now that we've seen its definition. 958void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 959 SDValue Val) { 960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 961 if (DDI.getDI()) { 962 const DbgValueInst *DI = DDI.getDI(); 963 DebugLoc dl = DDI.getdl(); 964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 965 MDNode *Variable = DI->getVariable(); 966 uint64_t Offset = DI->getOffset(); 967 SDDbgValue *SDV; 968 if (Val.getNode()) { 969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 970 SDV = DAG.getDbgValue(Variable, Val.getNode(), 971 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 972 DAG.AddDbgValue(SDV, Val.getNode(), false); 973 } 974 } else 975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 976 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 977 } 978} 979 980/// getValue - Return an SDValue for the given Value. 981SDValue SelectionDAGBuilder::getValue(const Value *V) { 982 // If we already have an SDValue for this value, use it. It's important 983 // to do this first, so that we don't create a CopyFromReg if we already 984 // have a regular SDValue. 985 SDValue &N = NodeMap[V]; 986 if (N.getNode()) return N; 987 988 // If there's a virtual register allocated and initialized for this 989 // value, use it. 990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 991 if (It != FuncInfo.ValueMap.end()) { 992 unsigned InReg = It->second; 993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 994 SDValue Chain = DAG.getEntryNode(); 995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 996 resolveDanglingDebugInfo(V, N); 997 return N; 998 } 999 1000 // Otherwise create a new SDValue and remember it. 1001 SDValue Val = getValueImpl(V); 1002 NodeMap[V] = Val; 1003 resolveDanglingDebugInfo(V, Val); 1004 return Val; 1005} 1006 1007/// getNonRegisterValue - Return an SDValue for the given Value, but 1008/// don't look in FuncInfo.ValueMap for a virtual register. 1009SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1010 // If we already have an SDValue for this value, use it. 1011 SDValue &N = NodeMap[V]; 1012 if (N.getNode()) return N; 1013 1014 // Otherwise create a new SDValue and remember it. 1015 SDValue Val = getValueImpl(V); 1016 NodeMap[V] = Val; 1017 resolveDanglingDebugInfo(V, Val); 1018 return Val; 1019} 1020 1021/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1022/// Create an SDValue for the given value. 1023SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1024 if (const Constant *C = dyn_cast<Constant>(V)) { 1025 EVT VT = TLI.getValueType(V->getType(), true); 1026 1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1028 return DAG.getConstant(*CI, VT); 1029 1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1032 1033 if (isa<ConstantPointerNull>(C)) 1034 return DAG.getConstant(0, TLI.getPointerTy()); 1035 1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1037 return DAG.getConstantFP(*CFP, VT); 1038 1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1040 return DAG.getUNDEF(VT); 1041 1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1043 visit(CE->getOpcode(), *CE); 1044 SDValue N1 = NodeMap[V]; 1045 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1046 return N1; 1047 } 1048 1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1050 SmallVector<SDValue, 4> Constants; 1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1052 OI != OE; ++OI) { 1053 SDNode *Val = getValue(*OI).getNode(); 1054 // If the operand is an empty aggregate, there are no values. 1055 if (!Val) continue; 1056 // Add each leaf value from the operand to the Constants list 1057 // to form a flattened list of all the values. 1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1059 Constants.push_back(SDValue(Val, i)); 1060 } 1061 1062 return DAG.getMergeValues(&Constants[0], Constants.size(), 1063 getCurDebugLoc()); 1064 } 1065 1066 if (const ConstantDataSequential *CDS = 1067 dyn_cast<ConstantDataSequential>(C)) { 1068 SmallVector<SDValue, 4> Ops; 1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1071 // Add each leaf value from the operand to the Constants list 1072 // to form a flattened list of all the values. 1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1074 Ops.push_back(SDValue(Val, i)); 1075 } 1076 1077 if (isa<ArrayType>(CDS->getType())) 1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1080 VT, &Ops[0], Ops.size()); 1081 } 1082 1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1085 "Unknown struct or array constant!"); 1086 1087 SmallVector<EVT, 4> ValueVTs; 1088 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1089 unsigned NumElts = ValueVTs.size(); 1090 if (NumElts == 0) 1091 return SDValue(); // empty struct 1092 SmallVector<SDValue, 4> Constants(NumElts); 1093 for (unsigned i = 0; i != NumElts; ++i) { 1094 EVT EltVT = ValueVTs[i]; 1095 if (isa<UndefValue>(C)) 1096 Constants[i] = DAG.getUNDEF(EltVT); 1097 else if (EltVT.isFloatingPoint()) 1098 Constants[i] = DAG.getConstantFP(0, EltVT); 1099 else 1100 Constants[i] = DAG.getConstant(0, EltVT); 1101 } 1102 1103 return DAG.getMergeValues(&Constants[0], NumElts, 1104 getCurDebugLoc()); 1105 } 1106 1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1108 return DAG.getBlockAddress(BA, VT); 1109 1110 VectorType *VecTy = cast<VectorType>(V->getType()); 1111 unsigned NumElements = VecTy->getNumElements(); 1112 1113 // Now that we know the number and type of the elements, get that number of 1114 // elements into the Ops array based on what kind of constant it is. 1115 SmallVector<SDValue, 16> Ops; 1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1117 for (unsigned i = 0; i != NumElements; ++i) 1118 Ops.push_back(getValue(CV->getOperand(i))); 1119 } else { 1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1121 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1122 1123 SDValue Op; 1124 if (EltVT.isFloatingPoint()) 1125 Op = DAG.getConstantFP(0, EltVT); 1126 else 1127 Op = DAG.getConstant(0, EltVT); 1128 Ops.assign(NumElements, Op); 1129 } 1130 1131 // Create a BUILD_VECTOR node. 1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1133 VT, &Ops[0], Ops.size()); 1134 } 1135 1136 // If this is a static alloca, generate it as the frameindex instead of 1137 // computation. 1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1139 DenseMap<const AllocaInst*, int>::iterator SI = 1140 FuncInfo.StaticAllocaMap.find(AI); 1141 if (SI != FuncInfo.StaticAllocaMap.end()) 1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1143 } 1144 1145 // If this is an instruction which fast-isel has deferred, select it now. 1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1149 SDValue Chain = DAG.getEntryNode(); 1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1151 } 1152 1153 llvm_unreachable("Can't get register for value!"); 1154} 1155 1156void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1157 SDValue Chain = getControlRoot(); 1158 SmallVector<ISD::OutputArg, 8> Outs; 1159 SmallVector<SDValue, 8> OutVals; 1160 1161 if (!FuncInfo.CanLowerReturn) { 1162 unsigned DemoteReg = FuncInfo.DemoteRegister; 1163 const Function *F = I.getParent()->getParent(); 1164 1165 // Emit a store of the return value through the virtual register. 1166 // Leave Outs empty so that LowerReturn won't try to load return 1167 // registers the usual way. 1168 SmallVector<EVT, 1> PtrValueVTs; 1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1170 PtrValueVTs); 1171 1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1173 SDValue RetOp = getValue(I.getOperand(0)); 1174 1175 SmallVector<EVT, 4> ValueVTs; 1176 SmallVector<uint64_t, 4> Offsets; 1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1178 unsigned NumValues = ValueVTs.size(); 1179 1180 SmallVector<SDValue, 4> Chains(NumValues); 1181 for (unsigned i = 0; i != NumValues; ++i) { 1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1183 RetPtr.getValueType(), RetPtr, 1184 DAG.getIntPtrConstant(Offsets[i])); 1185 Chains[i] = 1186 DAG.getStore(Chain, getCurDebugLoc(), 1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1188 // FIXME: better loc info would be nice. 1189 Add, MachinePointerInfo(), false, false, 0); 1190 } 1191 1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1193 MVT::Other, &Chains[0], NumValues); 1194 } else if (I.getNumOperands() != 0) { 1195 SmallVector<EVT, 4> ValueVTs; 1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1197 unsigned NumValues = ValueVTs.size(); 1198 if (NumValues) { 1199 SDValue RetOp = getValue(I.getOperand(0)); 1200 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1201 EVT VT = ValueVTs[j]; 1202 1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1204 1205 const Function *F = I.getParent()->getParent(); 1206 if (F->paramHasAttr(0, Attribute::SExt)) 1207 ExtendKind = ISD::SIGN_EXTEND; 1208 else if (F->paramHasAttr(0, Attribute::ZExt)) 1209 ExtendKind = ISD::ZERO_EXTEND; 1210 1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1213 1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1216 SmallVector<SDValue, 4> Parts(NumParts); 1217 getCopyToParts(DAG, getCurDebugLoc(), 1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1219 &Parts[0], NumParts, PartVT, ExtendKind); 1220 1221 // 'inreg' on function refers to return value 1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1223 if (F->paramHasAttr(0, Attribute::InReg)) 1224 Flags.setInReg(); 1225 1226 // Propagate extension type if any 1227 if (ExtendKind == ISD::SIGN_EXTEND) 1228 Flags.setSExt(); 1229 else if (ExtendKind == ISD::ZERO_EXTEND) 1230 Flags.setZExt(); 1231 1232 for (unsigned i = 0; i < NumParts; ++i) { 1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1234 /*isfixed=*/true)); 1235 OutVals.push_back(Parts[i]); 1236 } 1237 } 1238 } 1239 } 1240 1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1242 CallingConv::ID CallConv = 1243 DAG.getMachineFunction().getFunction()->getCallingConv(); 1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1245 Outs, OutVals, getCurDebugLoc(), DAG); 1246 1247 // Verify that the target's LowerReturn behaved as expected. 1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1249 "LowerReturn didn't return a valid chain!"); 1250 1251 // Update the DAG with the new chain value resulting from return lowering. 1252 DAG.setRoot(Chain); 1253} 1254 1255/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1256/// created for it, emit nodes to copy the value into the virtual 1257/// registers. 1258void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1259 // Skip empty types 1260 if (V->getType()->isEmptyTy()) 1261 return; 1262 1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1264 if (VMI != FuncInfo.ValueMap.end()) { 1265 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1266 CopyValueToVirtualRegister(V, VMI->second); 1267 } 1268} 1269 1270/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1271/// the current basic block, add it to ValueMap now so that we'll get a 1272/// CopyTo/FromReg. 1273void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1274 // No need to export constants. 1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1276 1277 // Already exported? 1278 if (FuncInfo.isExportedInst(V)) return; 1279 1280 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1281 CopyValueToVirtualRegister(V, Reg); 1282} 1283 1284bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1285 const BasicBlock *FromBB) { 1286 // The operands of the setcc have to be in this block. We don't know 1287 // how to export them from some other block. 1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1289 // Can export from current BB. 1290 if (VI->getParent() == FromBB) 1291 return true; 1292 1293 // Is already exported, noop. 1294 return FuncInfo.isExportedInst(V); 1295 } 1296 1297 // If this is an argument, we can export it if the BB is the entry block or 1298 // if it is already exported. 1299 if (isa<Argument>(V)) { 1300 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1301 return true; 1302 1303 // Otherwise, can only export this if it is already exported. 1304 return FuncInfo.isExportedInst(V); 1305 } 1306 1307 // Otherwise, constants can always be exported. 1308 return true; 1309} 1310 1311/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1312uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1313 const MachineBasicBlock *Dst) const { 1314 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1315 if (!BPI) 1316 return 0; 1317 const BasicBlock *SrcBB = Src->getBasicBlock(); 1318 const BasicBlock *DstBB = Dst->getBasicBlock(); 1319 return BPI->getEdgeWeight(SrcBB, DstBB); 1320} 1321 1322void SelectionDAGBuilder:: 1323addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1324 uint32_t Weight /* = 0 */) { 1325 if (!Weight) 1326 Weight = getEdgeWeight(Src, Dst); 1327 Src->addSuccessor(Dst, Weight); 1328} 1329 1330 1331static bool InBlock(const Value *V, const BasicBlock *BB) { 1332 if (const Instruction *I = dyn_cast<Instruction>(V)) 1333 return I->getParent() == BB; 1334 return true; 1335} 1336 1337/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1338/// This function emits a branch and is used at the leaves of an OR or an 1339/// AND operator tree. 1340/// 1341void 1342SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1343 MachineBasicBlock *TBB, 1344 MachineBasicBlock *FBB, 1345 MachineBasicBlock *CurBB, 1346 MachineBasicBlock *SwitchBB) { 1347 const BasicBlock *BB = CurBB->getBasicBlock(); 1348 1349 // If the leaf of the tree is a comparison, merge the condition into 1350 // the caseblock. 1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1352 // The operands of the cmp have to be in this block. We don't know 1353 // how to export them from some other block. If this is the first block 1354 // of the sequence, no exporting is needed. 1355 if (CurBB == SwitchBB || 1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1358 ISD::CondCode Condition; 1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1360 Condition = getICmpCondCode(IC->getPredicate()); 1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1362 Condition = getFCmpCondCode(FC->getPredicate()); 1363 if (TM.Options.NoNaNsFPMath) 1364 Condition = getFCmpCodeWithoutNaN(Condition); 1365 } else { 1366 Condition = ISD::SETEQ; // silence warning. 1367 llvm_unreachable("Unknown compare instruction"); 1368 } 1369 1370 CaseBlock CB(Condition, BOp->getOperand(0), 1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1372 SwitchCases.push_back(CB); 1373 return; 1374 } 1375 } 1376 1377 // Create a CaseBlock record representing this branch. 1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1379 NULL, TBB, FBB, CurBB); 1380 SwitchCases.push_back(CB); 1381} 1382 1383/// FindMergedConditions - If Cond is an expression like 1384void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1385 MachineBasicBlock *TBB, 1386 MachineBasicBlock *FBB, 1387 MachineBasicBlock *CurBB, 1388 MachineBasicBlock *SwitchBB, 1389 unsigned Opc) { 1390 // If this node is not part of the or/and tree, emit it as a branch. 1391 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1394 BOp->getParent() != CurBB->getBasicBlock() || 1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1398 return; 1399 } 1400 1401 // Create TmpBB after CurBB. 1402 MachineFunction::iterator BBI = CurBB; 1403 MachineFunction &MF = DAG.getMachineFunction(); 1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1405 CurBB->getParent()->insert(++BBI, TmpBB); 1406 1407 if (Opc == Instruction::Or) { 1408 // Codegen X | Y as: 1409 // jmp_if_X TBB 1410 // jmp TmpBB 1411 // TmpBB: 1412 // jmp_if_Y TBB 1413 // jmp FBB 1414 // 1415 1416 // Emit the LHS condition. 1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1418 1419 // Emit the RHS condition into TmpBB. 1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1421 } else { 1422 assert(Opc == Instruction::And && "Unknown merge op!"); 1423 // Codegen X & Y as: 1424 // jmp_if_X TmpBB 1425 // jmp FBB 1426 // TmpBB: 1427 // jmp_if_Y TBB 1428 // jmp FBB 1429 // 1430 // This requires creation of TmpBB after CurBB. 1431 1432 // Emit the LHS condition. 1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1434 1435 // Emit the RHS condition into TmpBB. 1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1437 } 1438} 1439 1440/// If the set of cases should be emitted as a series of branches, return true. 1441/// If we should emit this as a bunch of and/or'd together conditions, return 1442/// false. 1443bool 1444SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1445 if (Cases.size() != 2) return true; 1446 1447 // If this is two comparisons of the same values or'd or and'd together, they 1448 // will get folded into a single comparison, so don't emit two blocks. 1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1450 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1451 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1453 return false; 1454 } 1455 1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1459 Cases[0].CC == Cases[1].CC && 1460 isa<Constant>(Cases[0].CmpRHS) && 1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1463 return false; 1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1465 return false; 1466 } 1467 1468 return true; 1469} 1470 1471void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1472 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1473 1474 // Update machine-CFG edges. 1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1476 1477 // Figure out which block is immediately after the current one. 1478 MachineBasicBlock *NextBlock = 0; 1479 MachineFunction::iterator BBI = BrMBB; 1480 if (++BBI != FuncInfo.MF->end()) 1481 NextBlock = BBI; 1482 1483 if (I.isUnconditional()) { 1484 // Update machine-CFG edges. 1485 BrMBB->addSuccessor(Succ0MBB); 1486 1487 // If this is not a fall-through branch, emit the branch. 1488 if (Succ0MBB != NextBlock) 1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1490 MVT::Other, getControlRoot(), 1491 DAG.getBasicBlock(Succ0MBB))); 1492 1493 return; 1494 } 1495 1496 // If this condition is one of the special cases we handle, do special stuff 1497 // now. 1498 const Value *CondVal = I.getCondition(); 1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1500 1501 // If this is a series of conditions that are or'd or and'd together, emit 1502 // this as a sequence of branches instead of setcc's with and/or operations. 1503 // As long as jumps are not expensive, this should improve performance. 1504 // For example, instead of something like: 1505 // cmp A, B 1506 // C = seteq 1507 // cmp D, E 1508 // F = setle 1509 // or C, F 1510 // jnz foo 1511 // Emit: 1512 // cmp A, B 1513 // je foo 1514 // cmp D, E 1515 // jle foo 1516 // 1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1518 if (!TLI.isJumpExpensive() && 1519 BOp->hasOneUse() && 1520 (BOp->getOpcode() == Instruction::And || 1521 BOp->getOpcode() == Instruction::Or)) { 1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1523 BOp->getOpcode()); 1524 // If the compares in later blocks need to use values not currently 1525 // exported from this block, export them now. This block should always 1526 // be the first entry. 1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1528 1529 // Allow some cases to be rejected. 1530 if (ShouldEmitAsBranches(SwitchCases)) { 1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1534 } 1535 1536 // Emit the branch for this block. 1537 visitSwitchCase(SwitchCases[0], BrMBB); 1538 SwitchCases.erase(SwitchCases.begin()); 1539 return; 1540 } 1541 1542 // Okay, we decided not to do this, remove any inserted MBB's and clear 1543 // SwitchCases. 1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1546 1547 SwitchCases.clear(); 1548 } 1549 } 1550 1551 // Create a CaseBlock record representing this branch. 1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1553 NULL, Succ0MBB, Succ1MBB, BrMBB); 1554 1555 // Use visitSwitchCase to actually insert the fast branch sequence for this 1556 // cond branch. 1557 visitSwitchCase(CB, BrMBB); 1558} 1559 1560/// visitSwitchCase - Emits the necessary code to represent a single node in 1561/// the binary search tree resulting from lowering a switch instruction. 1562void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1563 MachineBasicBlock *SwitchBB) { 1564 SDValue Cond; 1565 SDValue CondLHS = getValue(CB.CmpLHS); 1566 DebugLoc dl = getCurDebugLoc(); 1567 1568 // Build the setcc now. 1569 if (CB.CmpMHS == NULL) { 1570 // Fold "(X == true)" to X and "(X == false)" to !X to 1571 // handle common cases produced by branch lowering. 1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1573 CB.CC == ISD::SETEQ) 1574 Cond = CondLHS; 1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1576 CB.CC == ISD::SETEQ) { 1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1579 } else 1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1581 } else { 1582 assert(CB.CC == ISD::SETCC_INVALID && 1583 "Condition is undefined for to-the-range belonging check."); 1584 1585 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1586 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1587 1588 SDValue CmpOp = getValue(CB.CmpMHS); 1589 EVT VT = CmpOp.getValueType(); 1590 1591 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1592 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1593 ISD::SETULE); 1594 } else { 1595 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1596 VT, CmpOp, DAG.getConstant(Low, VT)); 1597 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1598 DAG.getConstant(High-Low, VT), ISD::SETULE); 1599 } 1600 } 1601 1602 // Update successor info 1603 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1604 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1605 1606 // Set NextBlock to be the MBB immediately after the current one, if any. 1607 // This is used to avoid emitting unnecessary branches to the next block. 1608 MachineBasicBlock *NextBlock = 0; 1609 MachineFunction::iterator BBI = SwitchBB; 1610 if (++BBI != FuncInfo.MF->end()) 1611 NextBlock = BBI; 1612 1613 // If the lhs block is the next block, invert the condition so that we can 1614 // fall through to the lhs instead of the rhs block. 1615 if (CB.TrueBB == NextBlock) { 1616 std::swap(CB.TrueBB, CB.FalseBB); 1617 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1618 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1619 } 1620 1621 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1622 MVT::Other, getControlRoot(), Cond, 1623 DAG.getBasicBlock(CB.TrueBB)); 1624 1625 // Insert the false branch. Do this even if it's a fall through branch, 1626 // this makes it easier to do DAG optimizations which require inverting 1627 // the branch condition. 1628 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1629 DAG.getBasicBlock(CB.FalseBB)); 1630 1631 DAG.setRoot(BrCond); 1632} 1633 1634/// visitJumpTable - Emit JumpTable node in the current MBB 1635void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1636 // Emit the code for the jump table 1637 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1638 EVT PTy = TLI.getPointerTy(); 1639 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1640 JT.Reg, PTy); 1641 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1642 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1643 MVT::Other, Index.getValue(1), 1644 Table, Index); 1645 DAG.setRoot(BrJumpTable); 1646} 1647 1648/// visitJumpTableHeader - This function emits necessary code to produce index 1649/// in the JumpTable from switch case. 1650void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1651 JumpTableHeader &JTH, 1652 MachineBasicBlock *SwitchBB) { 1653 // Subtract the lowest switch case value from the value being switched on and 1654 // conditional branch to default mbb if the result is greater than the 1655 // difference between smallest and largest cases. 1656 SDValue SwitchOp = getValue(JTH.SValue); 1657 EVT VT = SwitchOp.getValueType(); 1658 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1659 DAG.getConstant(JTH.First, VT)); 1660 1661 // The SDNode we just created, which holds the value being switched on minus 1662 // the smallest case value, needs to be copied to a virtual register so it 1663 // can be used as an index into the jump table in a subsequent basic block. 1664 // This value may be smaller or larger than the target's pointer type, and 1665 // therefore require extension or truncating. 1666 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1667 1668 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1669 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1670 JumpTableReg, SwitchOp); 1671 JT.Reg = JumpTableReg; 1672 1673 // Emit the range check for the jump table, and branch to the default block 1674 // for the switch statement if the value being switched on exceeds the largest 1675 // case in the switch. 1676 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1677 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1678 DAG.getConstant(JTH.Last-JTH.First,VT), 1679 ISD::SETUGT); 1680 1681 // Set NextBlock to be the MBB immediately after the current one, if any. 1682 // This is used to avoid emitting unnecessary branches to the next block. 1683 MachineBasicBlock *NextBlock = 0; 1684 MachineFunction::iterator BBI = SwitchBB; 1685 1686 if (++BBI != FuncInfo.MF->end()) 1687 NextBlock = BBI; 1688 1689 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1690 MVT::Other, CopyTo, CMP, 1691 DAG.getBasicBlock(JT.Default)); 1692 1693 if (JT.MBB != NextBlock) 1694 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1695 DAG.getBasicBlock(JT.MBB)); 1696 1697 DAG.setRoot(BrCond); 1698} 1699 1700/// visitBitTestHeader - This function emits necessary code to produce value 1701/// suitable for "bit tests" 1702void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1703 MachineBasicBlock *SwitchBB) { 1704 // Subtract the minimum value 1705 SDValue SwitchOp = getValue(B.SValue); 1706 EVT VT = SwitchOp.getValueType(); 1707 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1708 DAG.getConstant(B.First, VT)); 1709 1710 // Check range 1711 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1712 TLI.getSetCCResultType(Sub.getValueType()), 1713 Sub, DAG.getConstant(B.Range, VT), 1714 ISD::SETUGT); 1715 1716 // Determine the type of the test operands. 1717 bool UsePtrType = false; 1718 if (!TLI.isTypeLegal(VT)) 1719 UsePtrType = true; 1720 else { 1721 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1722 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1723 // Switch table case range are encoded into series of masks. 1724 // Just use pointer type, it's guaranteed to fit. 1725 UsePtrType = true; 1726 break; 1727 } 1728 } 1729 if (UsePtrType) { 1730 VT = TLI.getPointerTy(); 1731 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1732 } 1733 1734 B.RegVT = VT; 1735 B.Reg = FuncInfo.CreateReg(VT); 1736 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1737 B.Reg, Sub); 1738 1739 // Set NextBlock to be the MBB immediately after the current one, if any. 1740 // This is used to avoid emitting unnecessary branches to the next block. 1741 MachineBasicBlock *NextBlock = 0; 1742 MachineFunction::iterator BBI = SwitchBB; 1743 if (++BBI != FuncInfo.MF->end()) 1744 NextBlock = BBI; 1745 1746 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1747 1748 addSuccessorWithWeight(SwitchBB, B.Default); 1749 addSuccessorWithWeight(SwitchBB, MBB); 1750 1751 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1752 MVT::Other, CopyTo, RangeCmp, 1753 DAG.getBasicBlock(B.Default)); 1754 1755 if (MBB != NextBlock) 1756 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1757 DAG.getBasicBlock(MBB)); 1758 1759 DAG.setRoot(BrRange); 1760} 1761 1762/// visitBitTestCase - this function produces one "bit test" 1763void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1764 MachineBasicBlock* NextMBB, 1765 unsigned Reg, 1766 BitTestCase &B, 1767 MachineBasicBlock *SwitchBB) { 1768 EVT VT = BB.RegVT; 1769 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1770 Reg, VT); 1771 SDValue Cmp; 1772 unsigned PopCount = CountPopulation_64(B.Mask); 1773 if (PopCount == 1) { 1774 // Testing for a single bit; just compare the shift count with what it 1775 // would need to be to shift a 1 bit in that position. 1776 Cmp = DAG.getSetCC(getCurDebugLoc(), 1777 TLI.getSetCCResultType(VT), 1778 ShiftOp, 1779 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1780 ISD::SETEQ); 1781 } else if (PopCount == BB.Range) { 1782 // There is only one zero bit in the range, test for it directly. 1783 Cmp = DAG.getSetCC(getCurDebugLoc(), 1784 TLI.getSetCCResultType(VT), 1785 ShiftOp, 1786 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1787 ISD::SETNE); 1788 } else { 1789 // Make desired shift 1790 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1791 DAG.getConstant(1, VT), ShiftOp); 1792 1793 // Emit bit tests and jumps 1794 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1795 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1796 Cmp = DAG.getSetCC(getCurDebugLoc(), 1797 TLI.getSetCCResultType(VT), 1798 AndOp, DAG.getConstant(0, VT), 1799 ISD::SETNE); 1800 } 1801 1802 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1803 addSuccessorWithWeight(SwitchBB, NextMBB); 1804 1805 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 Cmp, DAG.getBasicBlock(B.TargetBB)); 1808 1809 // Set NextBlock to be the MBB immediately after the current one, if any. 1810 // This is used to avoid emitting unnecessary branches to the next block. 1811 MachineBasicBlock *NextBlock = 0; 1812 MachineFunction::iterator BBI = SwitchBB; 1813 if (++BBI != FuncInfo.MF->end()) 1814 NextBlock = BBI; 1815 1816 if (NextMBB != NextBlock) 1817 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1818 DAG.getBasicBlock(NextMBB)); 1819 1820 DAG.setRoot(BrAnd); 1821} 1822 1823void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1824 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1825 1826 // Retrieve successors. 1827 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1828 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1829 1830 const Value *Callee(I.getCalledValue()); 1831 const Function *Fn = dyn_cast<Function>(Callee); 1832 if (isa<InlineAsm>(Callee)) 1833 visitInlineAsm(&I); 1834 else if (Fn && Fn->isIntrinsic()) { 1835 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1836 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1837 } else 1838 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1839 1840 // If the value of the invoke is used outside of its defining block, make it 1841 // available as a virtual register. 1842 CopyToExportRegsIfNeeded(&I); 1843 1844 // Update successor info 1845 addSuccessorWithWeight(InvokeMBB, Return); 1846 addSuccessorWithWeight(InvokeMBB, LandingPad); 1847 1848 // Drop into normal successor. 1849 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1850 MVT::Other, getControlRoot(), 1851 DAG.getBasicBlock(Return))); 1852} 1853 1854void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1855 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1856} 1857 1858void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1859 assert(FuncInfo.MBB->isLandingPad() && 1860 "Call to landingpad not in landing pad!"); 1861 1862 MachineBasicBlock *MBB = FuncInfo.MBB; 1863 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1864 AddLandingPadInfo(LP, MMI, MBB); 1865 1866 // If there aren't registers to copy the values into (e.g., during SjLj 1867 // exceptions), then don't bother to create these DAG nodes. 1868 if (TLI.getExceptionPointerRegister() == 0 && 1869 TLI.getExceptionSelectorRegister() == 0) 1870 return; 1871 1872 SmallVector<EVT, 2> ValueVTs; 1873 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1874 1875 // Insert the EXCEPTIONADDR instruction. 1876 assert(FuncInfo.MBB->isLandingPad() && 1877 "Call to eh.exception not in landing pad!"); 1878 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1879 SDValue Ops[2]; 1880 Ops[0] = DAG.getRoot(); 1881 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1882 SDValue Chain = Op1.getValue(1); 1883 1884 // Insert the EHSELECTION instruction. 1885 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1886 Ops[0] = Op1; 1887 Ops[1] = Chain; 1888 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1889 Chain = Op2.getValue(1); 1890 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1891 1892 Ops[0] = Op1; 1893 Ops[1] = Op2; 1894 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1895 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1896 &Ops[0], 2); 1897 1898 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1899 setValue(&LP, RetPair.first); 1900 DAG.setRoot(RetPair.second); 1901} 1902 1903/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1904/// small case ranges). 1905bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1906 CaseRecVector& WorkList, 1907 const Value* SV, 1908 MachineBasicBlock *Default, 1909 MachineBasicBlock *SwitchBB) { 1910 // Size is the number of Cases represented by this range. 1911 size_t Size = CR.Range.second - CR.Range.first; 1912 if (Size > 3) 1913 return false; 1914 1915 // Get the MachineFunction which holds the current MBB. This is used when 1916 // inserting any additional MBBs necessary to represent the switch. 1917 MachineFunction *CurMF = FuncInfo.MF; 1918 1919 // Figure out which block is immediately after the current one. 1920 MachineBasicBlock *NextBlock = 0; 1921 MachineFunction::iterator BBI = CR.CaseBB; 1922 1923 if (++BBI != FuncInfo.MF->end()) 1924 NextBlock = BBI; 1925 1926 // If any two of the cases has the same destination, and if one value 1927 // is the same as the other, but has one bit unset that the other has set, 1928 // use bit manipulation to do two compares at once. For example: 1929 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1930 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1931 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1932 if (Size == 2 && CR.CaseBB == SwitchBB) { 1933 Case &Small = *CR.Range.first; 1934 Case &Big = *(CR.Range.second-1); 1935 1936 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1937 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1938 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1939 1940 // Check that there is only one bit different. 1941 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1942 (SmallValue | BigValue) == BigValue) { 1943 // Isolate the common bit. 1944 APInt CommonBit = BigValue & ~SmallValue; 1945 assert((SmallValue | CommonBit) == BigValue && 1946 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1947 1948 SDValue CondLHS = getValue(SV); 1949 EVT VT = CondLHS.getValueType(); 1950 DebugLoc DL = getCurDebugLoc(); 1951 1952 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1953 DAG.getConstant(CommonBit, VT)); 1954 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1955 Or, DAG.getConstant(BigValue, VT), 1956 ISD::SETEQ); 1957 1958 // Update successor info. 1959 addSuccessorWithWeight(SwitchBB, Small.BB); 1960 addSuccessorWithWeight(SwitchBB, Default); 1961 1962 // Insert the true branch. 1963 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1964 getControlRoot(), Cond, 1965 DAG.getBasicBlock(Small.BB)); 1966 1967 // Insert the false branch. 1968 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1969 DAG.getBasicBlock(Default)); 1970 1971 DAG.setRoot(BrCond); 1972 return true; 1973 } 1974 } 1975 } 1976 1977 // Order cases by weight so the most likely case will be checked first. 1978 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1979 if (BPI) { 1980 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 1981 uint32_t IWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1982 I->BB->getBasicBlock()); 1983 for (CaseItr J = CR.Range.first; J < I; ++J) { 1984 uint32_t JWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(), 1985 J->BB->getBasicBlock()); 1986 if (IWeight > JWeight) 1987 std::swap(*I, *J); 1988 } 1989 } 1990 } 1991 // Rearrange the case blocks so that the last one falls through if possible. 1992 Case &BackCase = *(CR.Range.second-1); 1993 if (Size > 1 && 1994 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1995 // The last case block won't fall through into 'NextBlock' if we emit the 1996 // branches in this order. See if rearranging a case value would help. 1997 // We start at the bottom as it's the case with the least weight. 1998 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 1999 if (I->BB == NextBlock) { 2000 std::swap(*I, BackCase); 2001 break; 2002 } 2003 } 2004 } 2005 2006 // Create a CaseBlock record representing a conditional branch to 2007 // the Case's target mbb if the value being switched on SV is equal 2008 // to C. 2009 MachineBasicBlock *CurBlock = CR.CaseBB; 2010 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2011 MachineBasicBlock *FallThrough; 2012 if (I != E-1) { 2013 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2014 CurMF->insert(BBI, FallThrough); 2015 2016 // Put SV in a virtual register to make it available from the new blocks. 2017 ExportFromCurrentBlock(SV); 2018 } else { 2019 // If the last case doesn't match, go to the default block. 2020 FallThrough = Default; 2021 } 2022 2023 const Value *RHS, *LHS, *MHS; 2024 ISD::CondCode CC; 2025 if (I->High == I->Low) { 2026 // This is just small small case range :) containing exactly 1 case 2027 CC = ISD::SETEQ; 2028 LHS = SV; RHS = I->High; MHS = NULL; 2029 } else { 2030 CC = ISD::SETCC_INVALID; 2031 LHS = I->Low; MHS = SV; RHS = I->High; 2032 } 2033 2034 uint32_t ExtraWeight = I->ExtraWeight; 2035 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2036 /* me */ CurBlock, 2037 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2038 2039 // If emitting the first comparison, just call visitSwitchCase to emit the 2040 // code into the current block. Otherwise, push the CaseBlock onto the 2041 // vector to be later processed by SDISel, and insert the node's MBB 2042 // before the next MBB. 2043 if (CurBlock == SwitchBB) 2044 visitSwitchCase(CB, SwitchBB); 2045 else 2046 SwitchCases.push_back(CB); 2047 2048 CurBlock = FallThrough; 2049 } 2050 2051 return true; 2052} 2053 2054static inline bool areJTsAllowed(const TargetLowering &TLI) { 2055 return TLI.supportJumpTables() && 2056 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2057 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2058} 2059 2060static APInt ComputeRange(const APInt &First, const APInt &Last) { 2061 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2062 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2063 return (LastExt - FirstExt + 1ULL); 2064} 2065 2066/// handleJTSwitchCase - Emit jumptable for current switch case range 2067bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2068 CaseRecVector &WorkList, 2069 const Value *SV, 2070 MachineBasicBlock *Default, 2071 MachineBasicBlock *SwitchBB) { 2072 Case& FrontCase = *CR.Range.first; 2073 Case& BackCase = *(CR.Range.second-1); 2074 2075 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2076 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2077 2078 APInt TSize(First.getBitWidth(), 0); 2079 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2080 TSize += I->size(); 2081 2082 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2083 return false; 2084 2085 APInt Range = ComputeRange(First, Last); 2086 // The density is TSize / Range. Require at least 40%. 2087 // It should not be possible for IntTSize to saturate for sane code, but make 2088 // sure we handle Range saturation correctly. 2089 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2090 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2091 if (IntTSize * 10 < IntRange * 4) 2092 return false; 2093 2094 DEBUG(dbgs() << "Lowering jump table\n" 2095 << "First entry: " << First << ". Last entry: " << Last << '\n' 2096 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2097 2098 // Get the MachineFunction which holds the current MBB. This is used when 2099 // inserting any additional MBBs necessary to represent the switch. 2100 MachineFunction *CurMF = FuncInfo.MF; 2101 2102 // Figure out which block is immediately after the current one. 2103 MachineFunction::iterator BBI = CR.CaseBB; 2104 ++BBI; 2105 2106 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2107 2108 // Create a new basic block to hold the code for loading the address 2109 // of the jump table, and jumping to it. Update successor information; 2110 // we will either branch to the default case for the switch, or the jump 2111 // table. 2112 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2113 CurMF->insert(BBI, JumpTableBB); 2114 2115 addSuccessorWithWeight(CR.CaseBB, Default); 2116 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2117 2118 // Build a vector of destination BBs, corresponding to each target 2119 // of the jump table. If the value of the jump table slot corresponds to 2120 // a case statement, push the case's BB onto the vector, otherwise, push 2121 // the default BB. 2122 std::vector<MachineBasicBlock*> DestBBs; 2123 APInt TEI = First; 2124 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2125 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2126 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2127 2128 if (Low.ule(TEI) && TEI.ule(High)) { 2129 DestBBs.push_back(I->BB); 2130 if (TEI==High) 2131 ++I; 2132 } else { 2133 DestBBs.push_back(Default); 2134 } 2135 } 2136 2137 // Update successor info. Add one edge to each unique successor. 2138 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2139 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2140 E = DestBBs.end(); I != E; ++I) { 2141 if (!SuccsHandled[(*I)->getNumber()]) { 2142 SuccsHandled[(*I)->getNumber()] = true; 2143 addSuccessorWithWeight(JumpTableBB, *I); 2144 } 2145 } 2146 2147 // Create a jump table index for this jump table. 2148 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2149 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2150 ->createJumpTableIndex(DestBBs); 2151 2152 // Set the jump table information so that we can codegen it as a second 2153 // MachineBasicBlock 2154 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2155 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2156 if (CR.CaseBB == SwitchBB) 2157 visitJumpTableHeader(JT, JTH, SwitchBB); 2158 2159 JTCases.push_back(JumpTableBlock(JTH, JT)); 2160 return true; 2161} 2162 2163/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2164/// 2 subtrees. 2165bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2166 CaseRecVector& WorkList, 2167 const Value* SV, 2168 MachineBasicBlock *Default, 2169 MachineBasicBlock *SwitchBB) { 2170 // Get the MachineFunction which holds the current MBB. This is used when 2171 // inserting any additional MBBs necessary to represent the switch. 2172 MachineFunction *CurMF = FuncInfo.MF; 2173 2174 // Figure out which block is immediately after the current one. 2175 MachineFunction::iterator BBI = CR.CaseBB; 2176 ++BBI; 2177 2178 Case& FrontCase = *CR.Range.first; 2179 Case& BackCase = *(CR.Range.second-1); 2180 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2181 2182 // Size is the number of Cases represented by this range. 2183 unsigned Size = CR.Range.second - CR.Range.first; 2184 2185 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2186 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2187 double FMetric = 0; 2188 CaseItr Pivot = CR.Range.first + Size/2; 2189 2190 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2191 // (heuristically) allow us to emit JumpTable's later. 2192 APInt TSize(First.getBitWidth(), 0); 2193 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2194 I!=E; ++I) 2195 TSize += I->size(); 2196 2197 APInt LSize = FrontCase.size(); 2198 APInt RSize = TSize-LSize; 2199 DEBUG(dbgs() << "Selecting best pivot: \n" 2200 << "First: " << First << ", Last: " << Last <<'\n' 2201 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2202 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2203 J!=E; ++I, ++J) { 2204 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2205 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2206 APInt Range = ComputeRange(LEnd, RBegin); 2207 assert((Range - 2ULL).isNonNegative() && 2208 "Invalid case distance"); 2209 // Use volatile double here to avoid excess precision issues on some hosts, 2210 // e.g. that use 80-bit X87 registers. 2211 volatile double LDensity = 2212 (double)LSize.roundToDouble() / 2213 (LEnd - First + 1ULL).roundToDouble(); 2214 volatile double RDensity = 2215 (double)RSize.roundToDouble() / 2216 (Last - RBegin + 1ULL).roundToDouble(); 2217 double Metric = Range.logBase2()*(LDensity+RDensity); 2218 // Should always split in some non-trivial place 2219 DEBUG(dbgs() <<"=>Step\n" 2220 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2221 << "LDensity: " << LDensity 2222 << ", RDensity: " << RDensity << '\n' 2223 << "Metric: " << Metric << '\n'); 2224 if (FMetric < Metric) { 2225 Pivot = J; 2226 FMetric = Metric; 2227 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2228 } 2229 2230 LSize += J->size(); 2231 RSize -= J->size(); 2232 } 2233 if (areJTsAllowed(TLI)) { 2234 // If our case is dense we *really* should handle it earlier! 2235 assert((FMetric > 0) && "Should handle dense range earlier!"); 2236 } else { 2237 Pivot = CR.Range.first + Size/2; 2238 } 2239 2240 CaseRange LHSR(CR.Range.first, Pivot); 2241 CaseRange RHSR(Pivot, CR.Range.second); 2242 const Constant *C = Pivot->Low; 2243 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2244 2245 // We know that we branch to the LHS if the Value being switched on is 2246 // less than the Pivot value, C. We use this to optimize our binary 2247 // tree a bit, by recognizing that if SV is greater than or equal to the 2248 // LHS's Case Value, and that Case Value is exactly one less than the 2249 // Pivot's Value, then we can branch directly to the LHS's Target, 2250 // rather than creating a leaf node for it. 2251 if ((LHSR.second - LHSR.first) == 1 && 2252 LHSR.first->High == CR.GE && 2253 cast<ConstantInt>(C)->getValue() == 2254 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2255 TrueBB = LHSR.first->BB; 2256 } else { 2257 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2258 CurMF->insert(BBI, TrueBB); 2259 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2260 2261 // Put SV in a virtual register to make it available from the new blocks. 2262 ExportFromCurrentBlock(SV); 2263 } 2264 2265 // Similar to the optimization above, if the Value being switched on is 2266 // known to be less than the Constant CR.LT, and the current Case Value 2267 // is CR.LT - 1, then we can branch directly to the target block for 2268 // the current Case Value, rather than emitting a RHS leaf node for it. 2269 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2270 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2271 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2272 FalseBB = RHSR.first->BB; 2273 } else { 2274 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2275 CurMF->insert(BBI, FalseBB); 2276 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2277 2278 // Put SV in a virtual register to make it available from the new blocks. 2279 ExportFromCurrentBlock(SV); 2280 } 2281 2282 // Create a CaseBlock record representing a conditional branch to 2283 // the LHS node if the value being switched on SV is less than C. 2284 // Otherwise, branch to LHS. 2285 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2286 2287 if (CR.CaseBB == SwitchBB) 2288 visitSwitchCase(CB, SwitchBB); 2289 else 2290 SwitchCases.push_back(CB); 2291 2292 return true; 2293} 2294 2295/// handleBitTestsSwitchCase - if current case range has few destination and 2296/// range span less, than machine word bitwidth, encode case range into series 2297/// of masks and emit bit tests with these masks. 2298bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2299 CaseRecVector& WorkList, 2300 const Value* SV, 2301 MachineBasicBlock* Default, 2302 MachineBasicBlock *SwitchBB){ 2303 EVT PTy = TLI.getPointerTy(); 2304 unsigned IntPtrBits = PTy.getSizeInBits(); 2305 2306 Case& FrontCase = *CR.Range.first; 2307 Case& BackCase = *(CR.Range.second-1); 2308 2309 // Get the MachineFunction which holds the current MBB. This is used when 2310 // inserting any additional MBBs necessary to represent the switch. 2311 MachineFunction *CurMF = FuncInfo.MF; 2312 2313 // If target does not have legal shift left, do not emit bit tests at all. 2314 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2315 return false; 2316 2317 size_t numCmps = 0; 2318 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2319 I!=E; ++I) { 2320 // Single case counts one, case range - two. 2321 numCmps += (I->Low == I->High ? 1 : 2); 2322 } 2323 2324 // Count unique destinations 2325 SmallSet<MachineBasicBlock*, 4> Dests; 2326 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2327 Dests.insert(I->BB); 2328 if (Dests.size() > 3) 2329 // Don't bother the code below, if there are too much unique destinations 2330 return false; 2331 } 2332 DEBUG(dbgs() << "Total number of unique destinations: " 2333 << Dests.size() << '\n' 2334 << "Total number of comparisons: " << numCmps << '\n'); 2335 2336 // Compute span of values. 2337 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2338 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2339 APInt cmpRange = maxValue - minValue; 2340 2341 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2342 << "Low bound: " << minValue << '\n' 2343 << "High bound: " << maxValue << '\n'); 2344 2345 if (cmpRange.uge(IntPtrBits) || 2346 (!(Dests.size() == 1 && numCmps >= 3) && 2347 !(Dests.size() == 2 && numCmps >= 5) && 2348 !(Dests.size() >= 3 && numCmps >= 6))) 2349 return false; 2350 2351 DEBUG(dbgs() << "Emitting bit tests\n"); 2352 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2353 2354 // Optimize the case where all the case values fit in a 2355 // word without having to subtract minValue. In this case, 2356 // we can optimize away the subtraction. 2357 if (maxValue.ult(IntPtrBits)) { 2358 cmpRange = maxValue; 2359 } else { 2360 lowBound = minValue; 2361 } 2362 2363 CaseBitsVector CasesBits; 2364 unsigned i, count = 0; 2365 2366 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2367 MachineBasicBlock* Dest = I->BB; 2368 for (i = 0; i < count; ++i) 2369 if (Dest == CasesBits[i].BB) 2370 break; 2371 2372 if (i == count) { 2373 assert((count < 3) && "Too much destinations to test!"); 2374 CasesBits.push_back(CaseBits(0, Dest, 0)); 2375 count++; 2376 } 2377 2378 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2379 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2380 2381 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2382 uint64_t hi = (highValue - lowBound).getZExtValue(); 2383 2384 for (uint64_t j = lo; j <= hi; j++) { 2385 CasesBits[i].Mask |= 1ULL << j; 2386 CasesBits[i].Bits++; 2387 } 2388 2389 } 2390 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2391 2392 BitTestInfo BTC; 2393 2394 // Figure out which block is immediately after the current one. 2395 MachineFunction::iterator BBI = CR.CaseBB; 2396 ++BBI; 2397 2398 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2399 2400 DEBUG(dbgs() << "Cases:\n"); 2401 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2402 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2403 << ", Bits: " << CasesBits[i].Bits 2404 << ", BB: " << CasesBits[i].BB << '\n'); 2405 2406 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2407 CurMF->insert(BBI, CaseBB); 2408 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2409 CaseBB, 2410 CasesBits[i].BB)); 2411 2412 // Put SV in a virtual register to make it available from the new blocks. 2413 ExportFromCurrentBlock(SV); 2414 } 2415 2416 BitTestBlock BTB(lowBound, cmpRange, SV, 2417 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2418 CR.CaseBB, Default, BTC); 2419 2420 if (CR.CaseBB == SwitchBB) 2421 visitBitTestHeader(BTB, SwitchBB); 2422 2423 BitTestCases.push_back(BTB); 2424 2425 return true; 2426} 2427 2428/// Clusterify - Transform simple list of Cases into list of CaseRange's 2429size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2430 const SwitchInst& SI) { 2431 2432 /// Use a shorter form of declaration, and also 2433 /// show the we want to use CRSBuilder as Clusterifier. 2434 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2435 2436 Clusterifier TheClusterifier; 2437 2438 // Start with "simple" cases 2439 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2440 i != e; ++i) { 2441 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2442 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2443 2444 TheClusterifier.add(i.getCaseValueEx(), SMBB); 2445 } 2446 2447 TheClusterifier.optimize(); 2448 2449 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2450 size_t numCmps = 0; 2451 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2452 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2453 Clusterifier::Cluster &C = *i; 2454 unsigned W = 0; 2455 if (BPI) { 2456 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock()); 2457 if (!W) 2458 W = 16; 2459 W *= C.first.Weight; 2460 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W); 2461 } 2462 2463 // FIXME: Currently work with ConstantInt based numbers. 2464 // Changing it to APInt based is a pretty heavy for this commit. 2465 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2466 C.first.getHigh().toConstantInt(), C.second, W)); 2467 2468 if (C.first.getLow() != C.first.getHigh()) 2469 // A range counts double, since it requires two compares. 2470 ++numCmps; 2471 } 2472 2473 return numCmps; 2474} 2475 2476void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2477 MachineBasicBlock *Last) { 2478 // Update JTCases. 2479 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2480 if (JTCases[i].first.HeaderBB == First) 2481 JTCases[i].first.HeaderBB = Last; 2482 2483 // Update BitTestCases. 2484 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2485 if (BitTestCases[i].Parent == First) 2486 BitTestCases[i].Parent = Last; 2487} 2488 2489void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2490 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2491 2492 // Figure out which block is immediately after the current one. 2493 MachineBasicBlock *NextBlock = 0; 2494 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2495 2496 // If there is only the default destination, branch to it if it is not the 2497 // next basic block. Otherwise, just fall through. 2498 if (!SI.getNumCases()) { 2499 // Update machine-CFG edges. 2500 2501 // If this is not a fall-through branch, emit the branch. 2502 SwitchMBB->addSuccessor(Default); 2503 if (Default != NextBlock) 2504 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2505 MVT::Other, getControlRoot(), 2506 DAG.getBasicBlock(Default))); 2507 2508 return; 2509 } 2510 2511 // If there are any non-default case statements, create a vector of Cases 2512 // representing each one, and sort the vector so that we can efficiently 2513 // create a binary search tree from them. 2514 CaseVector Cases; 2515 size_t numCmps = Clusterify(Cases, SI); 2516 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2517 << ". Total compares: " << numCmps << '\n'); 2518 (void)numCmps; 2519 2520 // Get the Value to be switched on and default basic blocks, which will be 2521 // inserted into CaseBlock records, representing basic blocks in the binary 2522 // search tree. 2523 const Value *SV = SI.getCondition(); 2524 2525 // Push the initial CaseRec onto the worklist 2526 CaseRecVector WorkList; 2527 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2528 CaseRange(Cases.begin(),Cases.end()))); 2529 2530 while (!WorkList.empty()) { 2531 // Grab a record representing a case range to process off the worklist 2532 CaseRec CR = WorkList.back(); 2533 WorkList.pop_back(); 2534 2535 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2536 continue; 2537 2538 // If the range has few cases (two or less) emit a series of specific 2539 // tests. 2540 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2541 continue; 2542 2543 // If the switch has more than 5 blocks, and at least 40% dense, and the 2544 // target supports indirect branches, then emit a jump table rather than 2545 // lowering the switch to a binary tree of conditional branches. 2546 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2547 continue; 2548 2549 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2550 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2551 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2552 } 2553} 2554 2555void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2556 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2557 2558 // Update machine-CFG edges with unique successors. 2559 SmallVector<BasicBlock*, 32> succs; 2560 succs.reserve(I.getNumSuccessors()); 2561 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2562 succs.push_back(I.getSuccessor(i)); 2563 array_pod_sort(succs.begin(), succs.end()); 2564 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2565 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2566 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2567 addSuccessorWithWeight(IndirectBrMBB, Succ); 2568 } 2569 2570 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2571 MVT::Other, getControlRoot(), 2572 getValue(I.getAddress()))); 2573} 2574 2575void SelectionDAGBuilder::visitFSub(const User &I) { 2576 // -0.0 - X --> fneg 2577 Type *Ty = I.getType(); 2578 if (isa<Constant>(I.getOperand(0)) && 2579 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2580 SDValue Op2 = getValue(I.getOperand(1)); 2581 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2582 Op2.getValueType(), Op2)); 2583 return; 2584 } 2585 2586 visitBinary(I, ISD::FSUB); 2587} 2588 2589void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2590 SDValue Op1 = getValue(I.getOperand(0)); 2591 SDValue Op2 = getValue(I.getOperand(1)); 2592 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2593 Op1.getValueType(), Op1, Op2)); 2594} 2595 2596void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2597 SDValue Op1 = getValue(I.getOperand(0)); 2598 SDValue Op2 = getValue(I.getOperand(1)); 2599 2600 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2601 2602 // Coerce the shift amount to the right type if we can. 2603 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2604 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2605 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2606 DebugLoc DL = getCurDebugLoc(); 2607 2608 // If the operand is smaller than the shift count type, promote it. 2609 if (ShiftSize > Op2Size) 2610 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2611 2612 // If the operand is larger than the shift count type but the shift 2613 // count type has enough bits to represent any shift value, truncate 2614 // it now. This is a common case and it exposes the truncate to 2615 // optimization early. 2616 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2617 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2618 // Otherwise we'll need to temporarily settle for some other convenient 2619 // type. Type legalization will make adjustments once the shiftee is split. 2620 else 2621 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2622 } 2623 2624 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2625 Op1.getValueType(), Op1, Op2)); 2626} 2627 2628void SelectionDAGBuilder::visitSDiv(const User &I) { 2629 SDValue Op1 = getValue(I.getOperand(0)); 2630 SDValue Op2 = getValue(I.getOperand(1)); 2631 2632 // Turn exact SDivs into multiplications. 2633 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2634 // exact bit. 2635 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2636 !isa<ConstantSDNode>(Op1) && 2637 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2638 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2639 else 2640 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2641 Op1, Op2)); 2642} 2643 2644void SelectionDAGBuilder::visitICmp(const User &I) { 2645 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2646 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2647 predicate = IC->getPredicate(); 2648 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2649 predicate = ICmpInst::Predicate(IC->getPredicate()); 2650 SDValue Op1 = getValue(I.getOperand(0)); 2651 SDValue Op2 = getValue(I.getOperand(1)); 2652 ISD::CondCode Opcode = getICmpCondCode(predicate); 2653 2654 EVT DestVT = TLI.getValueType(I.getType()); 2655 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2656} 2657 2658void SelectionDAGBuilder::visitFCmp(const User &I) { 2659 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2660 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2661 predicate = FC->getPredicate(); 2662 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2663 predicate = FCmpInst::Predicate(FC->getPredicate()); 2664 SDValue Op1 = getValue(I.getOperand(0)); 2665 SDValue Op2 = getValue(I.getOperand(1)); 2666 ISD::CondCode Condition = getFCmpCondCode(predicate); 2667 if (TM.Options.NoNaNsFPMath) 2668 Condition = getFCmpCodeWithoutNaN(Condition); 2669 EVT DestVT = TLI.getValueType(I.getType()); 2670 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2671} 2672 2673void SelectionDAGBuilder::visitSelect(const User &I) { 2674 SmallVector<EVT, 4> ValueVTs; 2675 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2676 unsigned NumValues = ValueVTs.size(); 2677 if (NumValues == 0) return; 2678 2679 SmallVector<SDValue, 4> Values(NumValues); 2680 SDValue Cond = getValue(I.getOperand(0)); 2681 SDValue TrueVal = getValue(I.getOperand(1)); 2682 SDValue FalseVal = getValue(I.getOperand(2)); 2683 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2684 ISD::VSELECT : ISD::SELECT; 2685 2686 for (unsigned i = 0; i != NumValues; ++i) 2687 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2688 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2689 Cond, 2690 SDValue(TrueVal.getNode(), 2691 TrueVal.getResNo() + i), 2692 SDValue(FalseVal.getNode(), 2693 FalseVal.getResNo() + i)); 2694 2695 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2696 DAG.getVTList(&ValueVTs[0], NumValues), 2697 &Values[0], NumValues)); 2698} 2699 2700void SelectionDAGBuilder::visitTrunc(const User &I) { 2701 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2702 SDValue N = getValue(I.getOperand(0)); 2703 EVT DestVT = TLI.getValueType(I.getType()); 2704 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2705} 2706 2707void SelectionDAGBuilder::visitZExt(const User &I) { 2708 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2709 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2710 SDValue N = getValue(I.getOperand(0)); 2711 EVT DestVT = TLI.getValueType(I.getType()); 2712 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2713} 2714 2715void SelectionDAGBuilder::visitSExt(const User &I) { 2716 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2717 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2718 SDValue N = getValue(I.getOperand(0)); 2719 EVT DestVT = TLI.getValueType(I.getType()); 2720 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2721} 2722 2723void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2724 // FPTrunc is never a no-op cast, no need to check 2725 SDValue N = getValue(I.getOperand(0)); 2726 EVT DestVT = TLI.getValueType(I.getType()); 2727 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2728 DestVT, N, 2729 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2730} 2731 2732void SelectionDAGBuilder::visitFPExt(const User &I){ 2733 // FPExt is never a no-op cast, no need to check 2734 SDValue N = getValue(I.getOperand(0)); 2735 EVT DestVT = TLI.getValueType(I.getType()); 2736 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2737} 2738 2739void SelectionDAGBuilder::visitFPToUI(const User &I) { 2740 // FPToUI is never a no-op cast, no need to check 2741 SDValue N = getValue(I.getOperand(0)); 2742 EVT DestVT = TLI.getValueType(I.getType()); 2743 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2744} 2745 2746void SelectionDAGBuilder::visitFPToSI(const User &I) { 2747 // FPToSI is never a no-op cast, no need to check 2748 SDValue N = getValue(I.getOperand(0)); 2749 EVT DestVT = TLI.getValueType(I.getType()); 2750 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2751} 2752 2753void SelectionDAGBuilder::visitUIToFP(const User &I) { 2754 // UIToFP is never a no-op cast, no need to check 2755 SDValue N = getValue(I.getOperand(0)); 2756 EVT DestVT = TLI.getValueType(I.getType()); 2757 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2758} 2759 2760void SelectionDAGBuilder::visitSIToFP(const User &I){ 2761 // SIToFP is never a no-op cast, no need to check 2762 SDValue N = getValue(I.getOperand(0)); 2763 EVT DestVT = TLI.getValueType(I.getType()); 2764 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2765} 2766 2767void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2768 // What to do depends on the size of the integer and the size of the pointer. 2769 // We can either truncate, zero extend, or no-op, accordingly. 2770 SDValue N = getValue(I.getOperand(0)); 2771 EVT DestVT = TLI.getValueType(I.getType()); 2772 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2773} 2774 2775void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2776 // What to do depends on the size of the integer and the size of the pointer. 2777 // We can either truncate, zero extend, or no-op, accordingly. 2778 SDValue N = getValue(I.getOperand(0)); 2779 EVT DestVT = TLI.getValueType(I.getType()); 2780 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2781} 2782 2783void SelectionDAGBuilder::visitBitCast(const User &I) { 2784 SDValue N = getValue(I.getOperand(0)); 2785 EVT DestVT = TLI.getValueType(I.getType()); 2786 2787 // BitCast assures us that source and destination are the same size so this is 2788 // either a BITCAST or a no-op. 2789 if (DestVT != N.getValueType()) 2790 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2791 DestVT, N)); // convert types. 2792 else 2793 setValue(&I, N); // noop cast. 2794} 2795 2796void SelectionDAGBuilder::visitInsertElement(const User &I) { 2797 SDValue InVec = getValue(I.getOperand(0)); 2798 SDValue InVal = getValue(I.getOperand(1)); 2799 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2800 TLI.getPointerTy(), 2801 getValue(I.getOperand(2))); 2802 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2803 TLI.getValueType(I.getType()), 2804 InVec, InVal, InIdx)); 2805} 2806 2807void SelectionDAGBuilder::visitExtractElement(const User &I) { 2808 SDValue InVec = getValue(I.getOperand(0)); 2809 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2810 TLI.getPointerTy(), 2811 getValue(I.getOperand(1))); 2812 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2813 TLI.getValueType(I.getType()), InVec, InIdx)); 2814} 2815 2816// Utility for visitShuffleVector - Return true if every element in Mask, 2817// beginning from position Pos and ending in Pos+Size, falls within the 2818// specified sequential range [L, L+Pos). or is undef. 2819static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2820 unsigned Pos, unsigned Size, int Low) { 2821 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2822 if (Mask[i] >= 0 && Mask[i] != Low) 2823 return false; 2824 return true; 2825} 2826 2827void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2828 SDValue Src1 = getValue(I.getOperand(0)); 2829 SDValue Src2 = getValue(I.getOperand(1)); 2830 2831 SmallVector<int, 8> Mask; 2832 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2833 unsigned MaskNumElts = Mask.size(); 2834 2835 EVT VT = TLI.getValueType(I.getType()); 2836 EVT SrcVT = Src1.getValueType(); 2837 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2838 2839 if (SrcNumElts == MaskNumElts) { 2840 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2841 &Mask[0])); 2842 return; 2843 } 2844 2845 // Normalize the shuffle vector since mask and vector length don't match. 2846 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2847 // Mask is longer than the source vectors and is a multiple of the source 2848 // vectors. We can use concatenate vector to make the mask and vectors 2849 // lengths match. 2850 if (SrcNumElts*2 == MaskNumElts) { 2851 // First check for Src1 in low and Src2 in high 2852 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2853 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2854 // The shuffle is concatenating two vectors together. 2855 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2856 VT, Src1, Src2)); 2857 return; 2858 } 2859 // Then check for Src2 in low and Src1 in high 2860 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2861 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2862 // The shuffle is concatenating two vectors together. 2863 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2864 VT, Src2, Src1)); 2865 return; 2866 } 2867 } 2868 2869 // Pad both vectors with undefs to make them the same length as the mask. 2870 unsigned NumConcat = MaskNumElts / SrcNumElts; 2871 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2872 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2873 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2874 2875 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2876 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2877 MOps1[0] = Src1; 2878 MOps2[0] = Src2; 2879 2880 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2881 getCurDebugLoc(), VT, 2882 &MOps1[0], NumConcat); 2883 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2884 getCurDebugLoc(), VT, 2885 &MOps2[0], NumConcat); 2886 2887 // Readjust mask for new input vector length. 2888 SmallVector<int, 8> MappedOps; 2889 for (unsigned i = 0; i != MaskNumElts; ++i) { 2890 int Idx = Mask[i]; 2891 if (Idx >= (int)SrcNumElts) 2892 Idx -= SrcNumElts - MaskNumElts; 2893 MappedOps.push_back(Idx); 2894 } 2895 2896 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2897 &MappedOps[0])); 2898 return; 2899 } 2900 2901 if (SrcNumElts > MaskNumElts) { 2902 // Analyze the access pattern of the vector to see if we can extract 2903 // two subvectors and do the shuffle. The analysis is done by calculating 2904 // the range of elements the mask access on both vectors. 2905 int MinRange[2] = { static_cast<int>(SrcNumElts), 2906 static_cast<int>(SrcNumElts)}; 2907 int MaxRange[2] = {-1, -1}; 2908 2909 for (unsigned i = 0; i != MaskNumElts; ++i) { 2910 int Idx = Mask[i]; 2911 unsigned Input = 0; 2912 if (Idx < 0) 2913 continue; 2914 2915 if (Idx >= (int)SrcNumElts) { 2916 Input = 1; 2917 Idx -= SrcNumElts; 2918 } 2919 if (Idx > MaxRange[Input]) 2920 MaxRange[Input] = Idx; 2921 if (Idx < MinRange[Input]) 2922 MinRange[Input] = Idx; 2923 } 2924 2925 // Check if the access is smaller than the vector size and can we find 2926 // a reasonable extract index. 2927 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2928 // Extract. 2929 int StartIdx[2]; // StartIdx to extract from 2930 for (unsigned Input = 0; Input < 2; ++Input) { 2931 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2932 RangeUse[Input] = 0; // Unused 2933 StartIdx[Input] = 0; 2934 continue; 2935 } 2936 2937 // Find a good start index that is a multiple of the mask length. Then 2938 // see if the rest of the elements are in range. 2939 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2940 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2941 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2942 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2943 } 2944 2945 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2946 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2947 return; 2948 } 2949 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2950 // Extract appropriate subvector and generate a vector shuffle 2951 for (unsigned Input = 0; Input < 2; ++Input) { 2952 SDValue &Src = Input == 0 ? Src1 : Src2; 2953 if (RangeUse[Input] == 0) 2954 Src = DAG.getUNDEF(VT); 2955 else 2956 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2957 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2958 } 2959 2960 // Calculate new mask. 2961 SmallVector<int, 8> MappedOps; 2962 for (unsigned i = 0; i != MaskNumElts; ++i) { 2963 int Idx = Mask[i]; 2964 if (Idx >= 0) { 2965 if (Idx < (int)SrcNumElts) 2966 Idx -= StartIdx[0]; 2967 else 2968 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2969 } 2970 MappedOps.push_back(Idx); 2971 } 2972 2973 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2974 &MappedOps[0])); 2975 return; 2976 } 2977 } 2978 2979 // We can't use either concat vectors or extract subvectors so fall back to 2980 // replacing the shuffle with extract and build vector. 2981 // to insert and build vector. 2982 EVT EltVT = VT.getVectorElementType(); 2983 EVT PtrVT = TLI.getPointerTy(); 2984 SmallVector<SDValue,8> Ops; 2985 for (unsigned i = 0; i != MaskNumElts; ++i) { 2986 int Idx = Mask[i]; 2987 SDValue Res; 2988 2989 if (Idx < 0) { 2990 Res = DAG.getUNDEF(EltVT); 2991 } else { 2992 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 2993 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 2994 2995 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2996 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 2997 } 2998 2999 Ops.push_back(Res); 3000 } 3001 3002 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 3003 VT, &Ops[0], Ops.size())); 3004} 3005 3006void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3007 const Value *Op0 = I.getOperand(0); 3008 const Value *Op1 = I.getOperand(1); 3009 Type *AggTy = I.getType(); 3010 Type *ValTy = Op1->getType(); 3011 bool IntoUndef = isa<UndefValue>(Op0); 3012 bool FromUndef = isa<UndefValue>(Op1); 3013 3014 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3015 3016 SmallVector<EVT, 4> AggValueVTs; 3017 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3018 SmallVector<EVT, 4> ValValueVTs; 3019 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3020 3021 unsigned NumAggValues = AggValueVTs.size(); 3022 unsigned NumValValues = ValValueVTs.size(); 3023 SmallVector<SDValue, 4> Values(NumAggValues); 3024 3025 SDValue Agg = getValue(Op0); 3026 unsigned i = 0; 3027 // Copy the beginning value(s) from the original aggregate. 3028 for (; i != LinearIndex; ++i) 3029 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3030 SDValue(Agg.getNode(), Agg.getResNo() + i); 3031 // Copy values from the inserted value(s). 3032 if (NumValValues) { 3033 SDValue Val = getValue(Op1); 3034 for (; i != LinearIndex + NumValValues; ++i) 3035 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3036 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3037 } 3038 // Copy remaining value(s) from the original aggregate. 3039 for (; i != NumAggValues; ++i) 3040 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3041 SDValue(Agg.getNode(), Agg.getResNo() + i); 3042 3043 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3044 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3045 &Values[0], NumAggValues)); 3046} 3047 3048void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3049 const Value *Op0 = I.getOperand(0); 3050 Type *AggTy = Op0->getType(); 3051 Type *ValTy = I.getType(); 3052 bool OutOfUndef = isa<UndefValue>(Op0); 3053 3054 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3055 3056 SmallVector<EVT, 4> ValValueVTs; 3057 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3058 3059 unsigned NumValValues = ValValueVTs.size(); 3060 3061 // Ignore a extractvalue that produces an empty object 3062 if (!NumValValues) { 3063 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3064 return; 3065 } 3066 3067 SmallVector<SDValue, 4> Values(NumValValues); 3068 3069 SDValue Agg = getValue(Op0); 3070 // Copy out the selected value(s). 3071 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3072 Values[i - LinearIndex] = 3073 OutOfUndef ? 3074 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3075 SDValue(Agg.getNode(), Agg.getResNo() + i); 3076 3077 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3078 DAG.getVTList(&ValValueVTs[0], NumValValues), 3079 &Values[0], NumValValues)); 3080} 3081 3082void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3083 SDValue N = getValue(I.getOperand(0)); 3084 // Note that the pointer operand may be a vector of pointers. Take the scalar 3085 // element which holds a pointer. 3086 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3087 3088 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3089 OI != E; ++OI) { 3090 const Value *Idx = *OI; 3091 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3092 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3093 if (Field) { 3094 // N = N + Offset 3095 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3096 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3097 DAG.getIntPtrConstant(Offset)); 3098 } 3099 3100 Ty = StTy->getElementType(Field); 3101 } else { 3102 Ty = cast<SequentialType>(Ty)->getElementType(); 3103 3104 // If this is a constant subscript, handle it quickly. 3105 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3106 if (CI->isZero()) continue; 3107 uint64_t Offs = 3108 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3109 SDValue OffsVal; 3110 EVT PTy = TLI.getPointerTy(); 3111 unsigned PtrBits = PTy.getSizeInBits(); 3112 if (PtrBits < 64) 3113 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3114 TLI.getPointerTy(), 3115 DAG.getConstant(Offs, MVT::i64)); 3116 else 3117 OffsVal = DAG.getIntPtrConstant(Offs); 3118 3119 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3120 OffsVal); 3121 continue; 3122 } 3123 3124 // N = N + Idx * ElementSize; 3125 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3126 TD->getTypeAllocSize(Ty)); 3127 SDValue IdxN = getValue(Idx); 3128 3129 // If the index is smaller or larger than intptr_t, truncate or extend 3130 // it. 3131 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3132 3133 // If this is a multiply by a power of two, turn it into a shl 3134 // immediately. This is a very common case. 3135 if (ElementSize != 1) { 3136 if (ElementSize.isPowerOf2()) { 3137 unsigned Amt = ElementSize.logBase2(); 3138 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3139 N.getValueType(), IdxN, 3140 DAG.getConstant(Amt, IdxN.getValueType())); 3141 } else { 3142 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3143 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3144 N.getValueType(), IdxN, Scale); 3145 } 3146 } 3147 3148 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3149 N.getValueType(), N, IdxN); 3150 } 3151 } 3152 3153 setValue(&I, N); 3154} 3155 3156void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3157 // If this is a fixed sized alloca in the entry block of the function, 3158 // allocate it statically on the stack. 3159 if (FuncInfo.StaticAllocaMap.count(&I)) 3160 return; // getValue will auto-populate this. 3161 3162 Type *Ty = I.getAllocatedType(); 3163 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3164 unsigned Align = 3165 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3166 I.getAlignment()); 3167 3168 SDValue AllocSize = getValue(I.getArraySize()); 3169 3170 EVT IntPtr = TLI.getPointerTy(); 3171 if (AllocSize.getValueType() != IntPtr) 3172 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3173 3174 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3175 AllocSize, 3176 DAG.getConstant(TySize, IntPtr)); 3177 3178 // Handle alignment. If the requested alignment is less than or equal to 3179 // the stack alignment, ignore it. If the size is greater than or equal to 3180 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3181 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3182 if (Align <= StackAlign) 3183 Align = 0; 3184 3185 // Round the size of the allocation up to the stack alignment size 3186 // by add SA-1 to the size. 3187 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3188 AllocSize.getValueType(), AllocSize, 3189 DAG.getIntPtrConstant(StackAlign-1)); 3190 3191 // Mask out the low bits for alignment purposes. 3192 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3193 AllocSize.getValueType(), AllocSize, 3194 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3195 3196 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3197 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3198 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3199 VTs, Ops, 3); 3200 setValue(&I, DSA); 3201 DAG.setRoot(DSA.getValue(1)); 3202 3203 // Inform the Frame Information that we have just allocated a variable-sized 3204 // object. 3205 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3206} 3207 3208void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3209 if (I.isAtomic()) 3210 return visitAtomicLoad(I); 3211 3212 const Value *SV = I.getOperand(0); 3213 SDValue Ptr = getValue(SV); 3214 3215 Type *Ty = I.getType(); 3216 3217 bool isVolatile = I.isVolatile(); 3218 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3219 bool isInvariant = I.getMetadata("invariant.load") != 0; 3220 unsigned Alignment = I.getAlignment(); 3221 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3222 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3223 3224 SmallVector<EVT, 4> ValueVTs; 3225 SmallVector<uint64_t, 4> Offsets; 3226 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3227 unsigned NumValues = ValueVTs.size(); 3228 if (NumValues == 0) 3229 return; 3230 3231 SDValue Root; 3232 bool ConstantMemory = false; 3233 if (I.isVolatile() || NumValues > MaxParallelChains) 3234 // Serialize volatile loads with other side effects. 3235 Root = getRoot(); 3236 else if (AA->pointsToConstantMemory( 3237 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3238 // Do not serialize (non-volatile) loads of constant memory with anything. 3239 Root = DAG.getEntryNode(); 3240 ConstantMemory = true; 3241 } else { 3242 // Do not serialize non-volatile loads against each other. 3243 Root = DAG.getRoot(); 3244 } 3245 3246 SmallVector<SDValue, 4> Values(NumValues); 3247 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3248 NumValues)); 3249 EVT PtrVT = Ptr.getValueType(); 3250 unsigned ChainI = 0; 3251 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3252 // Serializing loads here may result in excessive register pressure, and 3253 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3254 // could recover a bit by hoisting nodes upward in the chain by recognizing 3255 // they are side-effect free or do not alias. The optimizer should really 3256 // avoid this case by converting large object/array copies to llvm.memcpy 3257 // (MaxParallelChains should always remain as failsafe). 3258 if (ChainI == MaxParallelChains) { 3259 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3260 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3261 MVT::Other, &Chains[0], ChainI); 3262 Root = Chain; 3263 ChainI = 0; 3264 } 3265 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3266 PtrVT, Ptr, 3267 DAG.getConstant(Offsets[i], PtrVT)); 3268 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3269 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3270 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3271 Ranges); 3272 3273 Values[i] = L; 3274 Chains[ChainI] = L.getValue(1); 3275 } 3276 3277 if (!ConstantMemory) { 3278 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3279 MVT::Other, &Chains[0], ChainI); 3280 if (isVolatile) 3281 DAG.setRoot(Chain); 3282 else 3283 PendingLoads.push_back(Chain); 3284 } 3285 3286 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3287 DAG.getVTList(&ValueVTs[0], NumValues), 3288 &Values[0], NumValues)); 3289} 3290 3291void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3292 if (I.isAtomic()) 3293 return visitAtomicStore(I); 3294 3295 const Value *SrcV = I.getOperand(0); 3296 const Value *PtrV = I.getOperand(1); 3297 3298 SmallVector<EVT, 4> ValueVTs; 3299 SmallVector<uint64_t, 4> Offsets; 3300 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3301 unsigned NumValues = ValueVTs.size(); 3302 if (NumValues == 0) 3303 return; 3304 3305 // Get the lowered operands. Note that we do this after 3306 // checking if NumResults is zero, because with zero results 3307 // the operands won't have values in the map. 3308 SDValue Src = getValue(SrcV); 3309 SDValue Ptr = getValue(PtrV); 3310 3311 SDValue Root = getRoot(); 3312 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3313 NumValues)); 3314 EVT PtrVT = Ptr.getValueType(); 3315 bool isVolatile = I.isVolatile(); 3316 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3317 unsigned Alignment = I.getAlignment(); 3318 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3319 3320 unsigned ChainI = 0; 3321 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3322 // See visitLoad comments. 3323 if (ChainI == MaxParallelChains) { 3324 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3325 MVT::Other, &Chains[0], ChainI); 3326 Root = Chain; 3327 ChainI = 0; 3328 } 3329 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3330 DAG.getConstant(Offsets[i], PtrVT)); 3331 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3332 SDValue(Src.getNode(), Src.getResNo() + i), 3333 Add, MachinePointerInfo(PtrV, Offsets[i]), 3334 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3335 Chains[ChainI] = St; 3336 } 3337 3338 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3339 MVT::Other, &Chains[0], ChainI); 3340 ++SDNodeOrder; 3341 AssignOrderingToNode(StoreNode.getNode()); 3342 DAG.setRoot(StoreNode); 3343} 3344 3345static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3346 SynchronizationScope Scope, 3347 bool Before, DebugLoc dl, 3348 SelectionDAG &DAG, 3349 const TargetLowering &TLI) { 3350 // Fence, if necessary 3351 if (Before) { 3352 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3353 Order = Release; 3354 else if (Order == Acquire || Order == Monotonic) 3355 return Chain; 3356 } else { 3357 if (Order == AcquireRelease) 3358 Order = Acquire; 3359 else if (Order == Release || Order == Monotonic) 3360 return Chain; 3361 } 3362 SDValue Ops[3]; 3363 Ops[0] = Chain; 3364 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3365 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3366 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3367} 3368 3369void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3370 DebugLoc dl = getCurDebugLoc(); 3371 AtomicOrdering Order = I.getOrdering(); 3372 SynchronizationScope Scope = I.getSynchScope(); 3373 3374 SDValue InChain = getRoot(); 3375 3376 if (TLI.getInsertFencesForAtomic()) 3377 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3378 DAG, TLI); 3379 3380 SDValue L = 3381 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3382 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3383 InChain, 3384 getValue(I.getPointerOperand()), 3385 getValue(I.getCompareOperand()), 3386 getValue(I.getNewValOperand()), 3387 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3388 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3389 Scope); 3390 3391 SDValue OutChain = L.getValue(1); 3392 3393 if (TLI.getInsertFencesForAtomic()) 3394 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3395 DAG, TLI); 3396 3397 setValue(&I, L); 3398 DAG.setRoot(OutChain); 3399} 3400 3401void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3402 DebugLoc dl = getCurDebugLoc(); 3403 ISD::NodeType NT; 3404 switch (I.getOperation()) { 3405 default: llvm_unreachable("Unknown atomicrmw operation"); 3406 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3407 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3408 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3409 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3410 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3411 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3412 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3413 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3414 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3415 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3416 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3417 } 3418 AtomicOrdering Order = I.getOrdering(); 3419 SynchronizationScope Scope = I.getSynchScope(); 3420 3421 SDValue InChain = getRoot(); 3422 3423 if (TLI.getInsertFencesForAtomic()) 3424 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3425 DAG, TLI); 3426 3427 SDValue L = 3428 DAG.getAtomic(NT, dl, 3429 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3430 InChain, 3431 getValue(I.getPointerOperand()), 3432 getValue(I.getValOperand()), 3433 I.getPointerOperand(), 0 /* Alignment */, 3434 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3435 Scope); 3436 3437 SDValue OutChain = L.getValue(1); 3438 3439 if (TLI.getInsertFencesForAtomic()) 3440 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3441 DAG, TLI); 3442 3443 setValue(&I, L); 3444 DAG.setRoot(OutChain); 3445} 3446 3447void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3448 DebugLoc dl = getCurDebugLoc(); 3449 SDValue Ops[3]; 3450 Ops[0] = getRoot(); 3451 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3452 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3453 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3454} 3455 3456void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3457 DebugLoc dl = getCurDebugLoc(); 3458 AtomicOrdering Order = I.getOrdering(); 3459 SynchronizationScope Scope = I.getSynchScope(); 3460 3461 SDValue InChain = getRoot(); 3462 3463 EVT VT = EVT::getEVT(I.getType()); 3464 3465 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3466 report_fatal_error("Cannot generate unaligned atomic load"); 3467 3468 SDValue L = 3469 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3470 getValue(I.getPointerOperand()), 3471 I.getPointerOperand(), I.getAlignment(), 3472 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3473 Scope); 3474 3475 SDValue OutChain = L.getValue(1); 3476 3477 if (TLI.getInsertFencesForAtomic()) 3478 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3479 DAG, TLI); 3480 3481 setValue(&I, L); 3482 DAG.setRoot(OutChain); 3483} 3484 3485void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3486 DebugLoc dl = getCurDebugLoc(); 3487 3488 AtomicOrdering Order = I.getOrdering(); 3489 SynchronizationScope Scope = I.getSynchScope(); 3490 3491 SDValue InChain = getRoot(); 3492 3493 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3494 3495 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3496 report_fatal_error("Cannot generate unaligned atomic store"); 3497 3498 if (TLI.getInsertFencesForAtomic()) 3499 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3500 DAG, TLI); 3501 3502 SDValue OutChain = 3503 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3504 InChain, 3505 getValue(I.getPointerOperand()), 3506 getValue(I.getValueOperand()), 3507 I.getPointerOperand(), I.getAlignment(), 3508 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3509 Scope); 3510 3511 if (TLI.getInsertFencesForAtomic()) 3512 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3513 DAG, TLI); 3514 3515 DAG.setRoot(OutChain); 3516} 3517 3518/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3519/// node. 3520void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3521 unsigned Intrinsic) { 3522 bool HasChain = !I.doesNotAccessMemory(); 3523 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3524 3525 // Build the operand list. 3526 SmallVector<SDValue, 8> Ops; 3527 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3528 if (OnlyLoad) { 3529 // We don't need to serialize loads against other loads. 3530 Ops.push_back(DAG.getRoot()); 3531 } else { 3532 Ops.push_back(getRoot()); 3533 } 3534 } 3535 3536 // Info is set by getTgtMemInstrinsic 3537 TargetLowering::IntrinsicInfo Info; 3538 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3539 3540 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3541 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3542 Info.opc == ISD::INTRINSIC_W_CHAIN) 3543 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3544 3545 // Add all operands of the call to the operand list. 3546 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3547 SDValue Op = getValue(I.getArgOperand(i)); 3548 Ops.push_back(Op); 3549 } 3550 3551 SmallVector<EVT, 4> ValueVTs; 3552 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3553 3554 if (HasChain) 3555 ValueVTs.push_back(MVT::Other); 3556 3557 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3558 3559 // Create the node. 3560 SDValue Result; 3561 if (IsTgtIntrinsic) { 3562 // This is target intrinsic that touches memory 3563 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3564 VTs, &Ops[0], Ops.size(), 3565 Info.memVT, 3566 MachinePointerInfo(Info.ptrVal, Info.offset), 3567 Info.align, Info.vol, 3568 Info.readMem, Info.writeMem); 3569 } else if (!HasChain) { 3570 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3571 VTs, &Ops[0], Ops.size()); 3572 } else if (!I.getType()->isVoidTy()) { 3573 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3574 VTs, &Ops[0], Ops.size()); 3575 } else { 3576 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3577 VTs, &Ops[0], Ops.size()); 3578 } 3579 3580 if (HasChain) { 3581 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3582 if (OnlyLoad) 3583 PendingLoads.push_back(Chain); 3584 else 3585 DAG.setRoot(Chain); 3586 } 3587 3588 if (!I.getType()->isVoidTy()) { 3589 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3590 EVT VT = TLI.getValueType(PTy); 3591 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3592 } 3593 3594 setValue(&I, Result); 3595 } else { 3596 // Assign order to result here. If the intrinsic does not produce a result, 3597 // it won't be mapped to a SDNode and visit() will not assign it an order 3598 // number. 3599 ++SDNodeOrder; 3600 AssignOrderingToNode(Result.getNode()); 3601 } 3602} 3603 3604/// GetSignificand - Get the significand and build it into a floating-point 3605/// number with exponent of 1: 3606/// 3607/// Op = (Op & 0x007fffff) | 0x3f800000; 3608/// 3609/// where Op is the hexidecimal representation of floating point value. 3610static SDValue 3611GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3612 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3613 DAG.getConstant(0x007fffff, MVT::i32)); 3614 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3615 DAG.getConstant(0x3f800000, MVT::i32)); 3616 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3617} 3618 3619/// GetExponent - Get the exponent: 3620/// 3621/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3622/// 3623/// where Op is the hexidecimal representation of floating point value. 3624static SDValue 3625GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3626 DebugLoc dl) { 3627 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3628 DAG.getConstant(0x7f800000, MVT::i32)); 3629 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3630 DAG.getConstant(23, TLI.getPointerTy())); 3631 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3632 DAG.getConstant(127, MVT::i32)); 3633 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3634} 3635 3636/// getF32Constant - Get 32-bit floating point constant. 3637static SDValue 3638getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3639 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3640} 3641 3642/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3643/// limited-precision mode. 3644void 3645SelectionDAGBuilder::visitExp(const CallInst &I) { 3646 SDValue result; 3647 DebugLoc dl = getCurDebugLoc(); 3648 3649 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3650 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3651 SDValue Op = getValue(I.getArgOperand(0)); 3652 3653 // Put the exponent in the right bit position for later addition to the 3654 // final result: 3655 // 3656 // #define LOG2OFe 1.4426950f 3657 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3658 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3659 getF32Constant(DAG, 0x3fb8aa3b)); 3660 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3661 3662 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3663 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3664 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3665 3666 // IntegerPartOfX <<= 23; 3667 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3668 DAG.getConstant(23, TLI.getPointerTy())); 3669 3670 if (LimitFloatPrecision <= 6) { 3671 // For floating-point precision of 6: 3672 // 3673 // TwoToFractionalPartOfX = 3674 // 0.997535578f + 3675 // (0.735607626f + 0.252464424f * x) * x; 3676 // 3677 // error 0.0144103317, which is 6 bits 3678 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3679 getF32Constant(DAG, 0x3e814304)); 3680 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3681 getF32Constant(DAG, 0x3f3c50c8)); 3682 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3683 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3684 getF32Constant(DAG, 0x3f7f5e7e)); 3685 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3686 3687 // Add the exponent into the result in integer domain. 3688 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3689 TwoToFracPartOfX, IntegerPartOfX); 3690 3691 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3692 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3693 // For floating-point precision of 12: 3694 // 3695 // TwoToFractionalPartOfX = 3696 // 0.999892986f + 3697 // (0.696457318f + 3698 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3699 // 3700 // 0.000107046256 error, which is 13 to 14 bits 3701 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3702 getF32Constant(DAG, 0x3da235e3)); 3703 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3704 getF32Constant(DAG, 0x3e65b8f3)); 3705 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3706 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3707 getF32Constant(DAG, 0x3f324b07)); 3708 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3709 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3710 getF32Constant(DAG, 0x3f7ff8fd)); 3711 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3712 3713 // Add the exponent into the result in integer domain. 3714 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3715 TwoToFracPartOfX, IntegerPartOfX); 3716 3717 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3718 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3719 // For floating-point precision of 18: 3720 // 3721 // TwoToFractionalPartOfX = 3722 // 0.999999982f + 3723 // (0.693148872f + 3724 // (0.240227044f + 3725 // (0.554906021e-1f + 3726 // (0.961591928e-2f + 3727 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3728 // 3729 // error 2.47208000*10^(-7), which is better than 18 bits 3730 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3731 getF32Constant(DAG, 0x3924b03e)); 3732 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3733 getF32Constant(DAG, 0x3ab24b87)); 3734 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3735 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3736 getF32Constant(DAG, 0x3c1d8c17)); 3737 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3738 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3739 getF32Constant(DAG, 0x3d634a1d)); 3740 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3741 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3742 getF32Constant(DAG, 0x3e75fe14)); 3743 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3744 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3745 getF32Constant(DAG, 0x3f317234)); 3746 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3747 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3748 getF32Constant(DAG, 0x3f800000)); 3749 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3750 MVT::i32, t13); 3751 3752 // Add the exponent into the result in integer domain. 3753 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3754 TwoToFracPartOfX, IntegerPartOfX); 3755 3756 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3757 } 3758 } else { 3759 // No special expansion. 3760 result = DAG.getNode(ISD::FEXP, dl, 3761 getValue(I.getArgOperand(0)).getValueType(), 3762 getValue(I.getArgOperand(0))); 3763 } 3764 3765 setValue(&I, result); 3766} 3767 3768/// visitLog - Lower a log intrinsic. Handles the special sequences for 3769/// limited-precision mode. 3770void 3771SelectionDAGBuilder::visitLog(const CallInst &I) { 3772 SDValue result; 3773 DebugLoc dl = getCurDebugLoc(); 3774 3775 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3776 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3777 SDValue Op = getValue(I.getArgOperand(0)); 3778 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3779 3780 // Scale the exponent by log(2) [0.69314718f]. 3781 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3782 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3783 getF32Constant(DAG, 0x3f317218)); 3784 3785 // Get the significand and build it into a floating-point number with 3786 // exponent of 1. 3787 SDValue X = GetSignificand(DAG, Op1, dl); 3788 3789 if (LimitFloatPrecision <= 6) { 3790 // For floating-point precision of 6: 3791 // 3792 // LogofMantissa = 3793 // -1.1609546f + 3794 // (1.4034025f - 0.23903021f * x) * x; 3795 // 3796 // error 0.0034276066, which is better than 8 bits 3797 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3798 getF32Constant(DAG, 0xbe74c456)); 3799 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3800 getF32Constant(DAG, 0x3fb3a2b1)); 3801 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3802 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3803 getF32Constant(DAG, 0x3f949a29)); 3804 3805 result = DAG.getNode(ISD::FADD, dl, 3806 MVT::f32, LogOfExponent, LogOfMantissa); 3807 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3808 // For floating-point precision of 12: 3809 // 3810 // LogOfMantissa = 3811 // -1.7417939f + 3812 // (2.8212026f + 3813 // (-1.4699568f + 3814 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3815 // 3816 // error 0.000061011436, which is 14 bits 3817 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3818 getF32Constant(DAG, 0xbd67b6d6)); 3819 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3820 getF32Constant(DAG, 0x3ee4f4b8)); 3821 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3822 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3823 getF32Constant(DAG, 0x3fbc278b)); 3824 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3825 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3826 getF32Constant(DAG, 0x40348e95)); 3827 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3828 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3829 getF32Constant(DAG, 0x3fdef31a)); 3830 3831 result = DAG.getNode(ISD::FADD, dl, 3832 MVT::f32, LogOfExponent, LogOfMantissa); 3833 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3834 // For floating-point precision of 18: 3835 // 3836 // LogOfMantissa = 3837 // -2.1072184f + 3838 // (4.2372794f + 3839 // (-3.7029485f + 3840 // (2.2781945f + 3841 // (-0.87823314f + 3842 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3843 // 3844 // error 0.0000023660568, which is better than 18 bits 3845 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3846 getF32Constant(DAG, 0xbc91e5ac)); 3847 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3848 getF32Constant(DAG, 0x3e4350aa)); 3849 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3850 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3851 getF32Constant(DAG, 0x3f60d3e3)); 3852 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3853 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3854 getF32Constant(DAG, 0x4011cdf0)); 3855 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3856 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3857 getF32Constant(DAG, 0x406cfd1c)); 3858 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3859 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3860 getF32Constant(DAG, 0x408797cb)); 3861 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3862 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3863 getF32Constant(DAG, 0x4006dcab)); 3864 3865 result = DAG.getNode(ISD::FADD, dl, 3866 MVT::f32, LogOfExponent, LogOfMantissa); 3867 } 3868 } else { 3869 // No special expansion. 3870 result = DAG.getNode(ISD::FLOG, dl, 3871 getValue(I.getArgOperand(0)).getValueType(), 3872 getValue(I.getArgOperand(0))); 3873 } 3874 3875 setValue(&I, result); 3876} 3877 3878/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3879/// limited-precision mode. 3880void 3881SelectionDAGBuilder::visitLog2(const CallInst &I) { 3882 SDValue result; 3883 DebugLoc dl = getCurDebugLoc(); 3884 3885 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3886 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3887 SDValue Op = getValue(I.getArgOperand(0)); 3888 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3889 3890 // Get the exponent. 3891 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3892 3893 // Get the significand and build it into a floating-point number with 3894 // exponent of 1. 3895 SDValue X = GetSignificand(DAG, Op1, dl); 3896 3897 // Different possible minimax approximations of significand in 3898 // floating-point for various degrees of accuracy over [1,2]. 3899 if (LimitFloatPrecision <= 6) { 3900 // For floating-point precision of 6: 3901 // 3902 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3903 // 3904 // error 0.0049451742, which is more than 7 bits 3905 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3906 getF32Constant(DAG, 0xbeb08fe0)); 3907 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3908 getF32Constant(DAG, 0x40019463)); 3909 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3910 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3911 getF32Constant(DAG, 0x3fd6633d)); 3912 3913 result = DAG.getNode(ISD::FADD, dl, 3914 MVT::f32, LogOfExponent, Log2ofMantissa); 3915 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3916 // For floating-point precision of 12: 3917 // 3918 // Log2ofMantissa = 3919 // -2.51285454f + 3920 // (4.07009056f + 3921 // (-2.12067489f + 3922 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3923 // 3924 // error 0.0000876136000, which is better than 13 bits 3925 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3926 getF32Constant(DAG, 0xbda7262e)); 3927 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3928 getF32Constant(DAG, 0x3f25280b)); 3929 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3930 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3931 getF32Constant(DAG, 0x4007b923)); 3932 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3933 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3934 getF32Constant(DAG, 0x40823e2f)); 3935 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3936 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3937 getF32Constant(DAG, 0x4020d29c)); 3938 3939 result = DAG.getNode(ISD::FADD, dl, 3940 MVT::f32, LogOfExponent, Log2ofMantissa); 3941 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3942 // For floating-point precision of 18: 3943 // 3944 // Log2ofMantissa = 3945 // -3.0400495f + 3946 // (6.1129976f + 3947 // (-5.3420409f + 3948 // (3.2865683f + 3949 // (-1.2669343f + 3950 // (0.27515199f - 3951 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3952 // 3953 // error 0.0000018516, which is better than 18 bits 3954 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3955 getF32Constant(DAG, 0xbcd2769e)); 3956 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3957 getF32Constant(DAG, 0x3e8ce0b9)); 3958 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3959 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3960 getF32Constant(DAG, 0x3fa22ae7)); 3961 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3962 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3963 getF32Constant(DAG, 0x40525723)); 3964 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3965 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3966 getF32Constant(DAG, 0x40aaf200)); 3967 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3968 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3969 getF32Constant(DAG, 0x40c39dad)); 3970 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3971 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3972 getF32Constant(DAG, 0x4042902c)); 3973 3974 result = DAG.getNode(ISD::FADD, dl, 3975 MVT::f32, LogOfExponent, Log2ofMantissa); 3976 } 3977 } else { 3978 // No special expansion. 3979 result = DAG.getNode(ISD::FLOG2, dl, 3980 getValue(I.getArgOperand(0)).getValueType(), 3981 getValue(I.getArgOperand(0))); 3982 } 3983 3984 setValue(&I, result); 3985} 3986 3987/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3988/// limited-precision mode. 3989void 3990SelectionDAGBuilder::visitLog10(const CallInst &I) { 3991 SDValue result; 3992 DebugLoc dl = getCurDebugLoc(); 3993 3994 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3995 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3996 SDValue Op = getValue(I.getArgOperand(0)); 3997 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3998 3999 // Scale the exponent by log10(2) [0.30102999f]. 4000 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4001 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4002 getF32Constant(DAG, 0x3e9a209a)); 4003 4004 // Get the significand and build it into a floating-point number with 4005 // exponent of 1. 4006 SDValue X = GetSignificand(DAG, Op1, dl); 4007 4008 if (LimitFloatPrecision <= 6) { 4009 // For floating-point precision of 6: 4010 // 4011 // Log10ofMantissa = 4012 // -0.50419619f + 4013 // (0.60948995f - 0.10380950f * x) * x; 4014 // 4015 // error 0.0014886165, which is 6 bits 4016 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4017 getF32Constant(DAG, 0xbdd49a13)); 4018 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4019 getF32Constant(DAG, 0x3f1c0789)); 4020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4021 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4022 getF32Constant(DAG, 0x3f011300)); 4023 4024 result = DAG.getNode(ISD::FADD, dl, 4025 MVT::f32, LogOfExponent, Log10ofMantissa); 4026 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4027 // For floating-point precision of 12: 4028 // 4029 // Log10ofMantissa = 4030 // -0.64831180f + 4031 // (0.91751397f + 4032 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4033 // 4034 // error 0.00019228036, which is better than 12 bits 4035 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4036 getF32Constant(DAG, 0x3d431f31)); 4037 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4038 getF32Constant(DAG, 0x3ea21fb2)); 4039 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4040 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4041 getF32Constant(DAG, 0x3f6ae232)); 4042 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4043 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4044 getF32Constant(DAG, 0x3f25f7c3)); 4045 4046 result = DAG.getNode(ISD::FADD, dl, 4047 MVT::f32, LogOfExponent, Log10ofMantissa); 4048 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4049 // For floating-point precision of 18: 4050 // 4051 // Log10ofMantissa = 4052 // -0.84299375f + 4053 // (1.5327582f + 4054 // (-1.0688956f + 4055 // (0.49102474f + 4056 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4057 // 4058 // error 0.0000037995730, which is better than 18 bits 4059 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4060 getF32Constant(DAG, 0x3c5d51ce)); 4061 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4062 getF32Constant(DAG, 0x3e00685a)); 4063 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4064 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4065 getF32Constant(DAG, 0x3efb6798)); 4066 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4067 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4068 getF32Constant(DAG, 0x3f88d192)); 4069 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4070 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4071 getF32Constant(DAG, 0x3fc4316c)); 4072 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4073 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4074 getF32Constant(DAG, 0x3f57ce70)); 4075 4076 result = DAG.getNode(ISD::FADD, dl, 4077 MVT::f32, LogOfExponent, Log10ofMantissa); 4078 } 4079 } else { 4080 // No special expansion. 4081 result = DAG.getNode(ISD::FLOG10, dl, 4082 getValue(I.getArgOperand(0)).getValueType(), 4083 getValue(I.getArgOperand(0))); 4084 } 4085 4086 setValue(&I, result); 4087} 4088 4089/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4090/// limited-precision mode. 4091void 4092SelectionDAGBuilder::visitExp2(const CallInst &I) { 4093 SDValue result; 4094 DebugLoc dl = getCurDebugLoc(); 4095 4096 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4097 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4098 SDValue Op = getValue(I.getArgOperand(0)); 4099 4100 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4101 4102 // FractionalPartOfX = x - (float)IntegerPartOfX; 4103 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4104 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4105 4106 // IntegerPartOfX <<= 23; 4107 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4108 DAG.getConstant(23, TLI.getPointerTy())); 4109 4110 if (LimitFloatPrecision <= 6) { 4111 // For floating-point precision of 6: 4112 // 4113 // TwoToFractionalPartOfX = 4114 // 0.997535578f + 4115 // (0.735607626f + 0.252464424f * x) * x; 4116 // 4117 // error 0.0144103317, which is 6 bits 4118 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4119 getF32Constant(DAG, 0x3e814304)); 4120 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4121 getF32Constant(DAG, 0x3f3c50c8)); 4122 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4123 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4124 getF32Constant(DAG, 0x3f7f5e7e)); 4125 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4126 SDValue TwoToFractionalPartOfX = 4127 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4128 4129 result = DAG.getNode(ISD::BITCAST, dl, 4130 MVT::f32, TwoToFractionalPartOfX); 4131 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4132 // For floating-point precision of 12: 4133 // 4134 // TwoToFractionalPartOfX = 4135 // 0.999892986f + 4136 // (0.696457318f + 4137 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4138 // 4139 // error 0.000107046256, which is 13 to 14 bits 4140 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4141 getF32Constant(DAG, 0x3da235e3)); 4142 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4143 getF32Constant(DAG, 0x3e65b8f3)); 4144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4146 getF32Constant(DAG, 0x3f324b07)); 4147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4148 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4149 getF32Constant(DAG, 0x3f7ff8fd)); 4150 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4151 SDValue TwoToFractionalPartOfX = 4152 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4153 4154 result = DAG.getNode(ISD::BITCAST, dl, 4155 MVT::f32, TwoToFractionalPartOfX); 4156 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4157 // For floating-point precision of 18: 4158 // 4159 // TwoToFractionalPartOfX = 4160 // 0.999999982f + 4161 // (0.693148872f + 4162 // (0.240227044f + 4163 // (0.554906021e-1f + 4164 // (0.961591928e-2f + 4165 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4166 // error 2.47208000*10^(-7), which is better than 18 bits 4167 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4168 getF32Constant(DAG, 0x3924b03e)); 4169 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4170 getF32Constant(DAG, 0x3ab24b87)); 4171 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4172 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4173 getF32Constant(DAG, 0x3c1d8c17)); 4174 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4175 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4176 getF32Constant(DAG, 0x3d634a1d)); 4177 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4178 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4179 getF32Constant(DAG, 0x3e75fe14)); 4180 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4181 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4182 getF32Constant(DAG, 0x3f317234)); 4183 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4184 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4185 getF32Constant(DAG, 0x3f800000)); 4186 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4187 SDValue TwoToFractionalPartOfX = 4188 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4189 4190 result = DAG.getNode(ISD::BITCAST, dl, 4191 MVT::f32, TwoToFractionalPartOfX); 4192 } 4193 } else { 4194 // No special expansion. 4195 result = DAG.getNode(ISD::FEXP2, dl, 4196 getValue(I.getArgOperand(0)).getValueType(), 4197 getValue(I.getArgOperand(0))); 4198 } 4199 4200 setValue(&I, result); 4201} 4202 4203/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4204/// limited-precision mode with x == 10.0f. 4205void 4206SelectionDAGBuilder::visitPow(const CallInst &I) { 4207 SDValue result; 4208 const Value *Val = I.getArgOperand(0); 4209 DebugLoc dl = getCurDebugLoc(); 4210 bool IsExp10 = false; 4211 4212 if (getValue(Val).getValueType() == MVT::f32 && 4213 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4214 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4215 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4216 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4217 APFloat Ten(10.0f); 4218 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4219 } 4220 } 4221 } 4222 4223 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4224 SDValue Op = getValue(I.getArgOperand(1)); 4225 4226 // Put the exponent in the right bit position for later addition to the 4227 // final result: 4228 // 4229 // #define LOG2OF10 3.3219281f 4230 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4231 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4232 getF32Constant(DAG, 0x40549a78)); 4233 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4234 4235 // FractionalPartOfX = x - (float)IntegerPartOfX; 4236 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4237 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4238 4239 // IntegerPartOfX <<= 23; 4240 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4241 DAG.getConstant(23, TLI.getPointerTy())); 4242 4243 if (LimitFloatPrecision <= 6) { 4244 // For floating-point precision of 6: 4245 // 4246 // twoToFractionalPartOfX = 4247 // 0.997535578f + 4248 // (0.735607626f + 0.252464424f * x) * x; 4249 // 4250 // error 0.0144103317, which is 6 bits 4251 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4252 getF32Constant(DAG, 0x3e814304)); 4253 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4254 getF32Constant(DAG, 0x3f3c50c8)); 4255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4257 getF32Constant(DAG, 0x3f7f5e7e)); 4258 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4259 SDValue TwoToFractionalPartOfX = 4260 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4261 4262 result = DAG.getNode(ISD::BITCAST, dl, 4263 MVT::f32, TwoToFractionalPartOfX); 4264 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4265 // For floating-point precision of 12: 4266 // 4267 // TwoToFractionalPartOfX = 4268 // 0.999892986f + 4269 // (0.696457318f + 4270 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4271 // 4272 // error 0.000107046256, which is 13 to 14 bits 4273 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4274 getF32Constant(DAG, 0x3da235e3)); 4275 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4276 getF32Constant(DAG, 0x3e65b8f3)); 4277 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4278 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4279 getF32Constant(DAG, 0x3f324b07)); 4280 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4281 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4282 getF32Constant(DAG, 0x3f7ff8fd)); 4283 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4284 SDValue TwoToFractionalPartOfX = 4285 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4286 4287 result = DAG.getNode(ISD::BITCAST, dl, 4288 MVT::f32, TwoToFractionalPartOfX); 4289 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4290 // For floating-point precision of 18: 4291 // 4292 // TwoToFractionalPartOfX = 4293 // 0.999999982f + 4294 // (0.693148872f + 4295 // (0.240227044f + 4296 // (0.554906021e-1f + 4297 // (0.961591928e-2f + 4298 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4299 // error 2.47208000*10^(-7), which is better than 18 bits 4300 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4301 getF32Constant(DAG, 0x3924b03e)); 4302 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4303 getF32Constant(DAG, 0x3ab24b87)); 4304 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4305 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4306 getF32Constant(DAG, 0x3c1d8c17)); 4307 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4308 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4309 getF32Constant(DAG, 0x3d634a1d)); 4310 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4311 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4312 getF32Constant(DAG, 0x3e75fe14)); 4313 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4314 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4315 getF32Constant(DAG, 0x3f317234)); 4316 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4317 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4318 getF32Constant(DAG, 0x3f800000)); 4319 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4320 SDValue TwoToFractionalPartOfX = 4321 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4322 4323 result = DAG.getNode(ISD::BITCAST, dl, 4324 MVT::f32, TwoToFractionalPartOfX); 4325 } 4326 } else { 4327 // No special expansion. 4328 result = DAG.getNode(ISD::FPOW, dl, 4329 getValue(I.getArgOperand(0)).getValueType(), 4330 getValue(I.getArgOperand(0)), 4331 getValue(I.getArgOperand(1))); 4332 } 4333 4334 setValue(&I, result); 4335} 4336 4337 4338/// ExpandPowI - Expand a llvm.powi intrinsic. 4339static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4340 SelectionDAG &DAG) { 4341 // If RHS is a constant, we can expand this out to a multiplication tree, 4342 // otherwise we end up lowering to a call to __powidf2 (for example). When 4343 // optimizing for size, we only want to do this if the expansion would produce 4344 // a small number of multiplies, otherwise we do the full expansion. 4345 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4346 // Get the exponent as a positive value. 4347 unsigned Val = RHSC->getSExtValue(); 4348 if ((int)Val < 0) Val = -Val; 4349 4350 // powi(x, 0) -> 1.0 4351 if (Val == 0) 4352 return DAG.getConstantFP(1.0, LHS.getValueType()); 4353 4354 const Function *F = DAG.getMachineFunction().getFunction(); 4355 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4356 // If optimizing for size, don't insert too many multiplies. This 4357 // inserts up to 5 multiplies. 4358 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4359 // We use the simple binary decomposition method to generate the multiply 4360 // sequence. There are more optimal ways to do this (for example, 4361 // powi(x,15) generates one more multiply than it should), but this has 4362 // the benefit of being both really simple and much better than a libcall. 4363 SDValue Res; // Logically starts equal to 1.0 4364 SDValue CurSquare = LHS; 4365 while (Val) { 4366 if (Val & 1) { 4367 if (Res.getNode()) 4368 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4369 else 4370 Res = CurSquare; // 1.0*CurSquare. 4371 } 4372 4373 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4374 CurSquare, CurSquare); 4375 Val >>= 1; 4376 } 4377 4378 // If the original was negative, invert the result, producing 1/(x*x*x). 4379 if (RHSC->getSExtValue() < 0) 4380 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4381 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4382 return Res; 4383 } 4384 } 4385 4386 // Otherwise, expand to a libcall. 4387 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4388} 4389 4390// getTruncatedArgReg - Find underlying register used for an truncated 4391// argument. 4392static unsigned getTruncatedArgReg(const SDValue &N) { 4393 if (N.getOpcode() != ISD::TRUNCATE) 4394 return 0; 4395 4396 const SDValue &Ext = N.getOperand(0); 4397 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4398 const SDValue &CFR = Ext.getOperand(0); 4399 if (CFR.getOpcode() == ISD::CopyFromReg) 4400 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4401 if (CFR.getOpcode() == ISD::TRUNCATE) 4402 return getTruncatedArgReg(CFR); 4403 } 4404 return 0; 4405} 4406 4407/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4408/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4409/// At the end of instruction selection, they will be inserted to the entry BB. 4410bool 4411SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4412 int64_t Offset, 4413 const SDValue &N) { 4414 const Argument *Arg = dyn_cast<Argument>(V); 4415 if (!Arg) 4416 return false; 4417 4418 MachineFunction &MF = DAG.getMachineFunction(); 4419 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4420 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4421 4422 // Ignore inlined function arguments here. 4423 DIVariable DV(Variable); 4424 if (DV.isInlinedFnArgument(MF.getFunction())) 4425 return false; 4426 4427 unsigned Reg = 0; 4428 // Some arguments' frame index is recorded during argument lowering. 4429 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4430 if (Offset) 4431 Reg = TRI->getFrameRegister(MF); 4432 4433 if (!Reg && N.getNode()) { 4434 if (N.getOpcode() == ISD::CopyFromReg) 4435 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4436 else 4437 Reg = getTruncatedArgReg(N); 4438 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4439 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4440 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4441 if (PR) 4442 Reg = PR; 4443 } 4444 } 4445 4446 if (!Reg) { 4447 // Check if ValueMap has reg number. 4448 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4449 if (VMI != FuncInfo.ValueMap.end()) 4450 Reg = VMI->second; 4451 } 4452 4453 if (!Reg && N.getNode()) { 4454 // Check if frame index is available. 4455 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4456 if (FrameIndexSDNode *FINode = 4457 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4458 Reg = TRI->getFrameRegister(MF); 4459 Offset = FINode->getIndex(); 4460 } 4461 } 4462 4463 if (!Reg) 4464 return false; 4465 4466 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4467 TII->get(TargetOpcode::DBG_VALUE)) 4468 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4469 FuncInfo.ArgDbgValues.push_back(&*MIB); 4470 return true; 4471} 4472 4473// VisualStudio defines setjmp as _setjmp 4474#if defined(_MSC_VER) && defined(setjmp) && \ 4475 !defined(setjmp_undefined_for_msvc) 4476# pragma push_macro("setjmp") 4477# undef setjmp 4478# define setjmp_undefined_for_msvc 4479#endif 4480 4481/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4482/// we want to emit this as a call to a named external function, return the name 4483/// otherwise lower it and return null. 4484const char * 4485SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4486 DebugLoc dl = getCurDebugLoc(); 4487 SDValue Res; 4488 4489 switch (Intrinsic) { 4490 default: 4491 // By default, turn this into a target intrinsic node. 4492 visitTargetIntrinsic(I, Intrinsic); 4493 return 0; 4494 case Intrinsic::vastart: visitVAStart(I); return 0; 4495 case Intrinsic::vaend: visitVAEnd(I); return 0; 4496 case Intrinsic::vacopy: visitVACopy(I); return 0; 4497 case Intrinsic::returnaddress: 4498 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4499 getValue(I.getArgOperand(0)))); 4500 return 0; 4501 case Intrinsic::frameaddress: 4502 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4503 getValue(I.getArgOperand(0)))); 4504 return 0; 4505 case Intrinsic::setjmp: 4506 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4507 case Intrinsic::longjmp: 4508 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4509 case Intrinsic::memcpy: { 4510 // Assert for address < 256 since we support only user defined address 4511 // spaces. 4512 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4513 < 256 && 4514 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4515 < 256 && 4516 "Unknown address space"); 4517 SDValue Op1 = getValue(I.getArgOperand(0)); 4518 SDValue Op2 = getValue(I.getArgOperand(1)); 4519 SDValue Op3 = getValue(I.getArgOperand(2)); 4520 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4521 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4522 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4523 MachinePointerInfo(I.getArgOperand(0)), 4524 MachinePointerInfo(I.getArgOperand(1)))); 4525 return 0; 4526 } 4527 case Intrinsic::memset: { 4528 // Assert for address < 256 since we support only user defined address 4529 // spaces. 4530 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4531 < 256 && 4532 "Unknown address space"); 4533 SDValue Op1 = getValue(I.getArgOperand(0)); 4534 SDValue Op2 = getValue(I.getArgOperand(1)); 4535 SDValue Op3 = getValue(I.getArgOperand(2)); 4536 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4537 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4538 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4539 MachinePointerInfo(I.getArgOperand(0)))); 4540 return 0; 4541 } 4542 case Intrinsic::memmove: { 4543 // Assert for address < 256 since we support only user defined address 4544 // spaces. 4545 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4546 < 256 && 4547 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4548 < 256 && 4549 "Unknown address space"); 4550 SDValue Op1 = getValue(I.getArgOperand(0)); 4551 SDValue Op2 = getValue(I.getArgOperand(1)); 4552 SDValue Op3 = getValue(I.getArgOperand(2)); 4553 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4554 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4555 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4556 MachinePointerInfo(I.getArgOperand(0)), 4557 MachinePointerInfo(I.getArgOperand(1)))); 4558 return 0; 4559 } 4560 case Intrinsic::dbg_declare: { 4561 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4562 MDNode *Variable = DI.getVariable(); 4563 const Value *Address = DI.getAddress(); 4564 if (!Address || !DIVariable(Variable).Verify()) { 4565 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4566 return 0; 4567 } 4568 4569 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4570 // but do not always have a corresponding SDNode built. The SDNodeOrder 4571 // absolute, but not relative, values are different depending on whether 4572 // debug info exists. 4573 ++SDNodeOrder; 4574 4575 // Check if address has undef value. 4576 if (isa<UndefValue>(Address) || 4577 (Address->use_empty() && !isa<Argument>(Address))) { 4578 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4579 return 0; 4580 } 4581 4582 SDValue &N = NodeMap[Address]; 4583 if (!N.getNode() && isa<Argument>(Address)) 4584 // Check unused arguments map. 4585 N = UnusedArgNodeMap[Address]; 4586 SDDbgValue *SDV; 4587 if (N.getNode()) { 4588 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4589 Address = BCI->getOperand(0); 4590 // Parameters are handled specially. 4591 bool isParameter = 4592 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4593 isa<Argument>(Address)); 4594 4595 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4596 4597 if (isParameter && !AI) { 4598 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4599 if (FINode) 4600 // Byval parameter. We have a frame index at this point. 4601 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4602 0, dl, SDNodeOrder); 4603 else { 4604 // Address is an argument, so try to emit its dbg value using 4605 // virtual register info from the FuncInfo.ValueMap. 4606 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4607 return 0; 4608 } 4609 } else if (AI) 4610 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4611 0, dl, SDNodeOrder); 4612 else { 4613 // Can't do anything with other non-AI cases yet. 4614 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4615 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4616 DEBUG(Address->dump()); 4617 return 0; 4618 } 4619 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4620 } else { 4621 // If Address is an argument then try to emit its dbg value using 4622 // virtual register info from the FuncInfo.ValueMap. 4623 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4624 // If variable is pinned by a alloca in dominating bb then 4625 // use StaticAllocaMap. 4626 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4627 if (AI->getParent() != DI.getParent()) { 4628 DenseMap<const AllocaInst*, int>::iterator SI = 4629 FuncInfo.StaticAllocaMap.find(AI); 4630 if (SI != FuncInfo.StaticAllocaMap.end()) { 4631 SDV = DAG.getDbgValue(Variable, SI->second, 4632 0, dl, SDNodeOrder); 4633 DAG.AddDbgValue(SDV, 0, false); 4634 return 0; 4635 } 4636 } 4637 } 4638 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4639 } 4640 } 4641 return 0; 4642 } 4643 case Intrinsic::dbg_value: { 4644 const DbgValueInst &DI = cast<DbgValueInst>(I); 4645 if (!DIVariable(DI.getVariable()).Verify()) 4646 return 0; 4647 4648 MDNode *Variable = DI.getVariable(); 4649 uint64_t Offset = DI.getOffset(); 4650 const Value *V = DI.getValue(); 4651 if (!V) 4652 return 0; 4653 4654 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4655 // but do not always have a corresponding SDNode built. The SDNodeOrder 4656 // absolute, but not relative, values are different depending on whether 4657 // debug info exists. 4658 ++SDNodeOrder; 4659 SDDbgValue *SDV; 4660 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4661 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4662 DAG.AddDbgValue(SDV, 0, false); 4663 } else { 4664 // Do not use getValue() in here; we don't want to generate code at 4665 // this point if it hasn't been done yet. 4666 SDValue N = NodeMap[V]; 4667 if (!N.getNode() && isa<Argument>(V)) 4668 // Check unused arguments map. 4669 N = UnusedArgNodeMap[V]; 4670 if (N.getNode()) { 4671 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4672 SDV = DAG.getDbgValue(Variable, N.getNode(), 4673 N.getResNo(), Offset, dl, SDNodeOrder); 4674 DAG.AddDbgValue(SDV, N.getNode(), false); 4675 } 4676 } else if (!V->use_empty() ) { 4677 // Do not call getValue(V) yet, as we don't want to generate code. 4678 // Remember it for later. 4679 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4680 DanglingDebugInfoMap[V] = DDI; 4681 } else { 4682 // We may expand this to cover more cases. One case where we have no 4683 // data available is an unreferenced parameter. 4684 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4685 } 4686 } 4687 4688 // Build a debug info table entry. 4689 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4690 V = BCI->getOperand(0); 4691 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4692 // Don't handle byval struct arguments or VLAs, for example. 4693 if (!AI) { 4694 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4695 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4696 return 0; 4697 } 4698 DenseMap<const AllocaInst*, int>::iterator SI = 4699 FuncInfo.StaticAllocaMap.find(AI); 4700 if (SI == FuncInfo.StaticAllocaMap.end()) 4701 return 0; // VLAs. 4702 int FI = SI->second; 4703 4704 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4705 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4706 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4707 return 0; 4708 } 4709 4710 case Intrinsic::eh_typeid_for: { 4711 // Find the type id for the given typeinfo. 4712 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4713 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4714 Res = DAG.getConstant(TypeID, MVT::i32); 4715 setValue(&I, Res); 4716 return 0; 4717 } 4718 4719 case Intrinsic::eh_return_i32: 4720 case Intrinsic::eh_return_i64: 4721 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4722 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4723 MVT::Other, 4724 getControlRoot(), 4725 getValue(I.getArgOperand(0)), 4726 getValue(I.getArgOperand(1)))); 4727 return 0; 4728 case Intrinsic::eh_unwind_init: 4729 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4730 return 0; 4731 case Intrinsic::eh_dwarf_cfa: { 4732 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4733 TLI.getPointerTy()); 4734 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4735 TLI.getPointerTy(), 4736 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4737 TLI.getPointerTy()), 4738 CfaArg); 4739 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4740 TLI.getPointerTy(), 4741 DAG.getConstant(0, TLI.getPointerTy())); 4742 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4743 FA, Offset)); 4744 return 0; 4745 } 4746 case Intrinsic::eh_sjlj_callsite: { 4747 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4748 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4749 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4750 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4751 4752 MMI.setCurrentCallSite(CI->getZExtValue()); 4753 return 0; 4754 } 4755 case Intrinsic::eh_sjlj_functioncontext: { 4756 // Get and store the index of the function context. 4757 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4758 AllocaInst *FnCtx = 4759 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4760 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4761 MFI->setFunctionContextIndex(FI); 4762 return 0; 4763 } 4764 case Intrinsic::eh_sjlj_setjmp: { 4765 SDValue Ops[2]; 4766 Ops[0] = getRoot(); 4767 Ops[1] = getValue(I.getArgOperand(0)); 4768 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4769 DAG.getVTList(MVT::i32, MVT::Other), 4770 Ops, 2); 4771 setValue(&I, Op.getValue(0)); 4772 DAG.setRoot(Op.getValue(1)); 4773 return 0; 4774 } 4775 case Intrinsic::eh_sjlj_longjmp: { 4776 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4777 getRoot(), getValue(I.getArgOperand(0)))); 4778 return 0; 4779 } 4780 4781 case Intrinsic::x86_mmx_pslli_w: 4782 case Intrinsic::x86_mmx_pslli_d: 4783 case Intrinsic::x86_mmx_pslli_q: 4784 case Intrinsic::x86_mmx_psrli_w: 4785 case Intrinsic::x86_mmx_psrli_d: 4786 case Intrinsic::x86_mmx_psrli_q: 4787 case Intrinsic::x86_mmx_psrai_w: 4788 case Intrinsic::x86_mmx_psrai_d: { 4789 SDValue ShAmt = getValue(I.getArgOperand(1)); 4790 if (isa<ConstantSDNode>(ShAmt)) { 4791 visitTargetIntrinsic(I, Intrinsic); 4792 return 0; 4793 } 4794 unsigned NewIntrinsic = 0; 4795 EVT ShAmtVT = MVT::v2i32; 4796 switch (Intrinsic) { 4797 case Intrinsic::x86_mmx_pslli_w: 4798 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4799 break; 4800 case Intrinsic::x86_mmx_pslli_d: 4801 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4802 break; 4803 case Intrinsic::x86_mmx_pslli_q: 4804 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4805 break; 4806 case Intrinsic::x86_mmx_psrli_w: 4807 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4808 break; 4809 case Intrinsic::x86_mmx_psrli_d: 4810 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4811 break; 4812 case Intrinsic::x86_mmx_psrli_q: 4813 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4814 break; 4815 case Intrinsic::x86_mmx_psrai_w: 4816 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4817 break; 4818 case Intrinsic::x86_mmx_psrai_d: 4819 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4820 break; 4821 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4822 } 4823 4824 // The vector shift intrinsics with scalars uses 32b shift amounts but 4825 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4826 // to be zero. 4827 // We must do this early because v2i32 is not a legal type. 4828 DebugLoc dl = getCurDebugLoc(); 4829 SDValue ShOps[2]; 4830 ShOps[0] = ShAmt; 4831 ShOps[1] = DAG.getConstant(0, MVT::i32); 4832 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4833 EVT DestVT = TLI.getValueType(I.getType()); 4834 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4835 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4836 DAG.getConstant(NewIntrinsic, MVT::i32), 4837 getValue(I.getArgOperand(0)), ShAmt); 4838 setValue(&I, Res); 4839 return 0; 4840 } 4841 case Intrinsic::x86_avx_vinsertf128_pd_256: 4842 case Intrinsic::x86_avx_vinsertf128_ps_256: 4843 case Intrinsic::x86_avx_vinsertf128_si_256: 4844 case Intrinsic::x86_avx2_vinserti128: { 4845 DebugLoc dl = getCurDebugLoc(); 4846 EVT DestVT = TLI.getValueType(I.getType()); 4847 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4848 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4849 ElVT.getVectorNumElements(); 4850 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4851 getValue(I.getArgOperand(0)), 4852 getValue(I.getArgOperand(1)), 4853 DAG.getConstant(Idx, MVT::i32)); 4854 setValue(&I, Res); 4855 return 0; 4856 } 4857 case Intrinsic::convertff: 4858 case Intrinsic::convertfsi: 4859 case Intrinsic::convertfui: 4860 case Intrinsic::convertsif: 4861 case Intrinsic::convertuif: 4862 case Intrinsic::convertss: 4863 case Intrinsic::convertsu: 4864 case Intrinsic::convertus: 4865 case Intrinsic::convertuu: { 4866 ISD::CvtCode Code = ISD::CVT_INVALID; 4867 switch (Intrinsic) { 4868 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4869 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4870 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4871 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4872 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4873 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4874 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4875 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4876 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4877 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4878 } 4879 EVT DestVT = TLI.getValueType(I.getType()); 4880 const Value *Op1 = I.getArgOperand(0); 4881 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4882 DAG.getValueType(DestVT), 4883 DAG.getValueType(getValue(Op1).getValueType()), 4884 getValue(I.getArgOperand(1)), 4885 getValue(I.getArgOperand(2)), 4886 Code); 4887 setValue(&I, Res); 4888 return 0; 4889 } 4890 case Intrinsic::sqrt: 4891 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4892 getValue(I.getArgOperand(0)).getValueType(), 4893 getValue(I.getArgOperand(0)))); 4894 return 0; 4895 case Intrinsic::powi: 4896 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4897 getValue(I.getArgOperand(1)), DAG)); 4898 return 0; 4899 case Intrinsic::sin: 4900 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4901 getValue(I.getArgOperand(0)).getValueType(), 4902 getValue(I.getArgOperand(0)))); 4903 return 0; 4904 case Intrinsic::cos: 4905 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4906 getValue(I.getArgOperand(0)).getValueType(), 4907 getValue(I.getArgOperand(0)))); 4908 return 0; 4909 case Intrinsic::log: 4910 visitLog(I); 4911 return 0; 4912 case Intrinsic::log2: 4913 visitLog2(I); 4914 return 0; 4915 case Intrinsic::log10: 4916 visitLog10(I); 4917 return 0; 4918 case Intrinsic::exp: 4919 visitExp(I); 4920 return 0; 4921 case Intrinsic::exp2: 4922 visitExp2(I); 4923 return 0; 4924 case Intrinsic::pow: 4925 visitPow(I); 4926 return 0; 4927 case Intrinsic::fabs: 4928 setValue(&I, DAG.getNode(ISD::FABS, dl, 4929 getValue(I.getArgOperand(0)).getValueType(), 4930 getValue(I.getArgOperand(0)))); 4931 return 0; 4932 case Intrinsic::fma: 4933 setValue(&I, DAG.getNode(ISD::FMA, dl, 4934 getValue(I.getArgOperand(0)).getValueType(), 4935 getValue(I.getArgOperand(0)), 4936 getValue(I.getArgOperand(1)), 4937 getValue(I.getArgOperand(2)))); 4938 return 0; 4939 case Intrinsic::fmuladd: { 4940 EVT VT = TLI.getValueType(I.getType()); 4941 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4942 TLI.isOperationLegal(ISD::FMA, VT) && 4943 TLI.isFMAFasterThanMulAndAdd(VT)){ 4944 setValue(&I, DAG.getNode(ISD::FMA, dl, 4945 getValue(I.getArgOperand(0)).getValueType(), 4946 getValue(I.getArgOperand(0)), 4947 getValue(I.getArgOperand(1)), 4948 getValue(I.getArgOperand(2)))); 4949 } else { 4950 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4951 getValue(I.getArgOperand(0)).getValueType(), 4952 getValue(I.getArgOperand(0)), 4953 getValue(I.getArgOperand(1))); 4954 SDValue Add = DAG.getNode(ISD::FADD, dl, 4955 getValue(I.getArgOperand(0)).getValueType(), 4956 Mul, 4957 getValue(I.getArgOperand(2))); 4958 setValue(&I, Add); 4959 } 4960 return 0; 4961 } 4962 case Intrinsic::convert_to_fp16: 4963 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4964 MVT::i16, getValue(I.getArgOperand(0)))); 4965 return 0; 4966 case Intrinsic::convert_from_fp16: 4967 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4968 MVT::f32, getValue(I.getArgOperand(0)))); 4969 return 0; 4970 case Intrinsic::pcmarker: { 4971 SDValue Tmp = getValue(I.getArgOperand(0)); 4972 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4973 return 0; 4974 } 4975 case Intrinsic::readcyclecounter: { 4976 SDValue Op = getRoot(); 4977 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4978 DAG.getVTList(MVT::i64, MVT::Other), 4979 &Op, 1); 4980 setValue(&I, Res); 4981 DAG.setRoot(Res.getValue(1)); 4982 return 0; 4983 } 4984 case Intrinsic::bswap: 4985 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4986 getValue(I.getArgOperand(0)).getValueType(), 4987 getValue(I.getArgOperand(0)))); 4988 return 0; 4989 case Intrinsic::cttz: { 4990 SDValue Arg = getValue(I.getArgOperand(0)); 4991 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4992 EVT Ty = Arg.getValueType(); 4993 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4994 dl, Ty, Arg)); 4995 return 0; 4996 } 4997 case Intrinsic::ctlz: { 4998 SDValue Arg = getValue(I.getArgOperand(0)); 4999 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 5000 EVT Ty = Arg.getValueType(); 5001 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 5002 dl, Ty, Arg)); 5003 return 0; 5004 } 5005 case Intrinsic::ctpop: { 5006 SDValue Arg = getValue(I.getArgOperand(0)); 5007 EVT Ty = Arg.getValueType(); 5008 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 5009 return 0; 5010 } 5011 case Intrinsic::stacksave: { 5012 SDValue Op = getRoot(); 5013 Res = DAG.getNode(ISD::STACKSAVE, dl, 5014 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 5015 setValue(&I, Res); 5016 DAG.setRoot(Res.getValue(1)); 5017 return 0; 5018 } 5019 case Intrinsic::stackrestore: { 5020 Res = getValue(I.getArgOperand(0)); 5021 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 5022 return 0; 5023 } 5024 case Intrinsic::stackprotector: { 5025 // Emit code into the DAG to store the stack guard onto the stack. 5026 MachineFunction &MF = DAG.getMachineFunction(); 5027 MachineFrameInfo *MFI = MF.getFrameInfo(); 5028 EVT PtrTy = TLI.getPointerTy(); 5029 5030 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5031 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5032 5033 int FI = FuncInfo.StaticAllocaMap[Slot]; 5034 MFI->setStackProtectorIndex(FI); 5035 5036 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5037 5038 // Store the stack protector onto the stack. 5039 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5040 MachinePointerInfo::getFixedStack(FI), 5041 true, false, 0); 5042 setValue(&I, Res); 5043 DAG.setRoot(Res); 5044 return 0; 5045 } 5046 case Intrinsic::objectsize: { 5047 // If we don't know by now, we're never going to know. 5048 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5049 5050 assert(CI && "Non-constant type in __builtin_object_size?"); 5051 5052 SDValue Arg = getValue(I.getCalledValue()); 5053 EVT Ty = Arg.getValueType(); 5054 5055 if (CI->isZero()) 5056 Res = DAG.getConstant(-1ULL, Ty); 5057 else 5058 Res = DAG.getConstant(0, Ty); 5059 5060 setValue(&I, Res); 5061 return 0; 5062 } 5063 case Intrinsic::var_annotation: 5064 // Discard annotate attributes 5065 return 0; 5066 5067 case Intrinsic::init_trampoline: { 5068 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5069 5070 SDValue Ops[6]; 5071 Ops[0] = getRoot(); 5072 Ops[1] = getValue(I.getArgOperand(0)); 5073 Ops[2] = getValue(I.getArgOperand(1)); 5074 Ops[3] = getValue(I.getArgOperand(2)); 5075 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5076 Ops[5] = DAG.getSrcValue(F); 5077 5078 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5079 5080 DAG.setRoot(Res); 5081 return 0; 5082 } 5083 case Intrinsic::adjust_trampoline: { 5084 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5085 TLI.getPointerTy(), 5086 getValue(I.getArgOperand(0)))); 5087 return 0; 5088 } 5089 case Intrinsic::gcroot: 5090 if (GFI) { 5091 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5092 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5093 5094 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5095 GFI->addStackRoot(FI->getIndex(), TypeMap); 5096 } 5097 return 0; 5098 case Intrinsic::gcread: 5099 case Intrinsic::gcwrite: 5100 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5101 case Intrinsic::flt_rounds: 5102 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5103 return 0; 5104 5105 case Intrinsic::expect: { 5106 // Just replace __builtin_expect(exp, c) with EXP. 5107 setValue(&I, getValue(I.getArgOperand(0))); 5108 return 0; 5109 } 5110 5111 case Intrinsic::trap: { 5112 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5113 if (TrapFuncName.empty()) { 5114 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5115 return 0; 5116 } 5117 TargetLowering::ArgListTy Args; 5118 TargetLowering:: 5119 CallLoweringInfo CLI(getRoot(), I.getType(), 5120 false, false, false, false, 0, CallingConv::C, 5121 /*isTailCall=*/false, 5122 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5123 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5124 Args, DAG, getCurDebugLoc()); 5125 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5126 DAG.setRoot(Result.second); 5127 return 0; 5128 } 5129 case Intrinsic::debugtrap: { 5130 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot())); 5131 return 0; 5132 } 5133 case Intrinsic::uadd_with_overflow: 5134 case Intrinsic::sadd_with_overflow: 5135 case Intrinsic::usub_with_overflow: 5136 case Intrinsic::ssub_with_overflow: 5137 case Intrinsic::umul_with_overflow: 5138 case Intrinsic::smul_with_overflow: { 5139 ISD::NodeType Op; 5140 switch (Intrinsic) { 5141 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5142 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5143 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5144 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5145 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5146 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5147 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5148 } 5149 SDValue Op1 = getValue(I.getArgOperand(0)); 5150 SDValue Op2 = getValue(I.getArgOperand(1)); 5151 5152 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5153 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 5154 return 0; 5155 } 5156 case Intrinsic::prefetch: { 5157 SDValue Ops[5]; 5158 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5159 Ops[0] = getRoot(); 5160 Ops[1] = getValue(I.getArgOperand(0)); 5161 Ops[2] = getValue(I.getArgOperand(1)); 5162 Ops[3] = getValue(I.getArgOperand(2)); 5163 Ops[4] = getValue(I.getArgOperand(3)); 5164 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5165 DAG.getVTList(MVT::Other), 5166 &Ops[0], 5, 5167 EVT::getIntegerVT(*Context, 8), 5168 MachinePointerInfo(I.getArgOperand(0)), 5169 0, /* align */ 5170 false, /* volatile */ 5171 rw==0, /* read */ 5172 rw==1)); /* write */ 5173 return 0; 5174 } 5175 5176 case Intrinsic::invariant_start: 5177 case Intrinsic::lifetime_start: 5178 // Discard region information. 5179 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5180 return 0; 5181 case Intrinsic::invariant_end: 5182 case Intrinsic::lifetime_end: 5183 // Discard region information. 5184 return 0; 5185 case Intrinsic::donothing: 5186 // ignore 5187 return 0; 5188 } 5189} 5190 5191void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5192 bool isTailCall, 5193 MachineBasicBlock *LandingPad) { 5194 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5195 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5196 Type *RetTy = FTy->getReturnType(); 5197 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5198 MCSymbol *BeginLabel = 0; 5199 5200 TargetLowering::ArgListTy Args; 5201 TargetLowering::ArgListEntry Entry; 5202 Args.reserve(CS.arg_size()); 5203 5204 // Check whether the function can return without sret-demotion. 5205 SmallVector<ISD::OutputArg, 4> Outs; 5206 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5207 Outs, TLI); 5208 5209 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5210 DAG.getMachineFunction(), 5211 FTy->isVarArg(), Outs, 5212 FTy->getContext()); 5213 5214 SDValue DemoteStackSlot; 5215 int DemoteStackIdx = -100; 5216 5217 if (!CanLowerReturn) { 5218 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5219 FTy->getReturnType()); 5220 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5221 FTy->getReturnType()); 5222 MachineFunction &MF = DAG.getMachineFunction(); 5223 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5224 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5225 5226 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5227 Entry.Node = DemoteStackSlot; 5228 Entry.Ty = StackSlotPtrType; 5229 Entry.isSExt = false; 5230 Entry.isZExt = false; 5231 Entry.isInReg = false; 5232 Entry.isSRet = true; 5233 Entry.isNest = false; 5234 Entry.isByVal = false; 5235 Entry.Alignment = Align; 5236 Args.push_back(Entry); 5237 RetTy = Type::getVoidTy(FTy->getContext()); 5238 } 5239 5240 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5241 i != e; ++i) { 5242 const Value *V = *i; 5243 5244 // Skip empty types 5245 if (V->getType()->isEmptyTy()) 5246 continue; 5247 5248 SDValue ArgNode = getValue(V); 5249 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5250 5251 unsigned attrInd = i - CS.arg_begin() + 1; 5252 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5253 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5254 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5255 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5256 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5257 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5258 Entry.Alignment = CS.getParamAlignment(attrInd); 5259 Args.push_back(Entry); 5260 } 5261 5262 if (LandingPad) { 5263 // Insert a label before the invoke call to mark the try range. This can be 5264 // used to detect deletion of the invoke via the MachineModuleInfo. 5265 BeginLabel = MMI.getContext().CreateTempSymbol(); 5266 5267 // For SjLj, keep track of which landing pads go with which invokes 5268 // so as to maintain the ordering of pads in the LSDA. 5269 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5270 if (CallSiteIndex) { 5271 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5272 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5273 5274 // Now that the call site is handled, stop tracking it. 5275 MMI.setCurrentCallSite(0); 5276 } 5277 5278 // Both PendingLoads and PendingExports must be flushed here; 5279 // this call might not return. 5280 (void)getRoot(); 5281 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5282 } 5283 5284 // Check if target-independent constraints permit a tail call here. 5285 // Target-dependent constraints are checked within TLI.LowerCallTo. 5286 if (isTailCall && 5287 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5288 isTailCall = false; 5289 5290 // If there's a possibility that fast-isel has already selected some amount 5291 // of the current basic block, don't emit a tail call. 5292 if (isTailCall && TM.Options.EnableFastISel) 5293 isTailCall = false; 5294 5295 TargetLowering:: 5296 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5297 getCurDebugLoc(), CS); 5298 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5299 assert((isTailCall || Result.second.getNode()) && 5300 "Non-null chain expected with non-tail call!"); 5301 assert((Result.second.getNode() || !Result.first.getNode()) && 5302 "Null value expected with tail call!"); 5303 if (Result.first.getNode()) { 5304 setValue(CS.getInstruction(), Result.first); 5305 } else if (!CanLowerReturn && Result.second.getNode()) { 5306 // The instruction result is the result of loading from the 5307 // hidden sret parameter. 5308 SmallVector<EVT, 1> PVTs; 5309 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5310 5311 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5312 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5313 EVT PtrVT = PVTs[0]; 5314 5315 SmallVector<EVT, 4> RetTys; 5316 SmallVector<uint64_t, 4> Offsets; 5317 RetTy = FTy->getReturnType(); 5318 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5319 5320 unsigned NumValues = RetTys.size(); 5321 SmallVector<SDValue, 4> Values(NumValues); 5322 SmallVector<SDValue, 4> Chains(NumValues); 5323 5324 for (unsigned i = 0; i < NumValues; ++i) { 5325 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5326 DemoteStackSlot, 5327 DAG.getConstant(Offsets[i], PtrVT)); 5328 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5329 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5330 false, false, false, 1); 5331 Values[i] = L; 5332 Chains[i] = L.getValue(1); 5333 } 5334 5335 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5336 MVT::Other, &Chains[0], NumValues); 5337 PendingLoads.push_back(Chain); 5338 5339 setValue(CS.getInstruction(), 5340 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5341 DAG.getVTList(&RetTys[0], RetTys.size()), 5342 &Values[0], Values.size())); 5343 } 5344 5345 // Assign order to nodes here. If the call does not produce a result, it won't 5346 // be mapped to a SDNode and visit() will not assign it an order number. 5347 if (!Result.second.getNode()) { 5348 // As a special case, a null chain means that a tail call has been emitted and 5349 // the DAG root is already updated. 5350 HasTailCall = true; 5351 ++SDNodeOrder; 5352 AssignOrderingToNode(DAG.getRoot().getNode()); 5353 } else { 5354 DAG.setRoot(Result.second); 5355 ++SDNodeOrder; 5356 AssignOrderingToNode(Result.second.getNode()); 5357 } 5358 5359 if (LandingPad) { 5360 // Insert a label at the end of the invoke call to mark the try range. This 5361 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5362 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5363 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5364 5365 // Inform MachineModuleInfo of range. 5366 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5367 } 5368} 5369 5370/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5371/// value is equal or not-equal to zero. 5372static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5373 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5374 UI != E; ++UI) { 5375 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5376 if (IC->isEquality()) 5377 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5378 if (C->isNullValue()) 5379 continue; 5380 // Unknown instruction. 5381 return false; 5382 } 5383 return true; 5384} 5385 5386static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5387 Type *LoadTy, 5388 SelectionDAGBuilder &Builder) { 5389 5390 // Check to see if this load can be trivially constant folded, e.g. if the 5391 // input is from a string literal. 5392 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5393 // Cast pointer to the type we really want to load. 5394 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5395 PointerType::getUnqual(LoadTy)); 5396 5397 if (const Constant *LoadCst = 5398 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5399 Builder.TD)) 5400 return Builder.getValue(LoadCst); 5401 } 5402 5403 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5404 // still constant memory, the input chain can be the entry node. 5405 SDValue Root; 5406 bool ConstantMemory = false; 5407 5408 // Do not serialize (non-volatile) loads of constant memory with anything. 5409 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5410 Root = Builder.DAG.getEntryNode(); 5411 ConstantMemory = true; 5412 } else { 5413 // Do not serialize non-volatile loads against each other. 5414 Root = Builder.DAG.getRoot(); 5415 } 5416 5417 SDValue Ptr = Builder.getValue(PtrVal); 5418 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5419 Ptr, MachinePointerInfo(PtrVal), 5420 false /*volatile*/, 5421 false /*nontemporal*/, 5422 false /*isinvariant*/, 1 /* align=1 */); 5423 5424 if (!ConstantMemory) 5425 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5426 return LoadVal; 5427} 5428 5429 5430/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5431/// If so, return true and lower it, otherwise return false and it will be 5432/// lowered like a normal call. 5433bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5434 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5435 if (I.getNumArgOperands() != 3) 5436 return false; 5437 5438 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5439 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5440 !I.getArgOperand(2)->getType()->isIntegerTy() || 5441 !I.getType()->isIntegerTy()) 5442 return false; 5443 5444 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5445 5446 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5447 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5448 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5449 bool ActuallyDoIt = true; 5450 MVT LoadVT; 5451 Type *LoadTy; 5452 switch (Size->getZExtValue()) { 5453 default: 5454 LoadVT = MVT::Other; 5455 LoadTy = 0; 5456 ActuallyDoIt = false; 5457 break; 5458 case 2: 5459 LoadVT = MVT::i16; 5460 LoadTy = Type::getInt16Ty(Size->getContext()); 5461 break; 5462 case 4: 5463 LoadVT = MVT::i32; 5464 LoadTy = Type::getInt32Ty(Size->getContext()); 5465 break; 5466 case 8: 5467 LoadVT = MVT::i64; 5468 LoadTy = Type::getInt64Ty(Size->getContext()); 5469 break; 5470 /* 5471 case 16: 5472 LoadVT = MVT::v4i32; 5473 LoadTy = Type::getInt32Ty(Size->getContext()); 5474 LoadTy = VectorType::get(LoadTy, 4); 5475 break; 5476 */ 5477 } 5478 5479 // This turns into unaligned loads. We only do this if the target natively 5480 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5481 // we'll only produce a small number of byte loads. 5482 5483 // Require that we can find a legal MVT, and only do this if the target 5484 // supports unaligned loads of that type. Expanding into byte loads would 5485 // bloat the code. 5486 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5487 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5488 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5489 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5490 ActuallyDoIt = false; 5491 } 5492 5493 if (ActuallyDoIt) { 5494 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5495 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5496 5497 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5498 ISD::SETNE); 5499 EVT CallVT = TLI.getValueType(I.getType(), true); 5500 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5501 return true; 5502 } 5503 } 5504 5505 5506 return false; 5507} 5508 5509 5510void SelectionDAGBuilder::visitCall(const CallInst &I) { 5511 // Handle inline assembly differently. 5512 if (isa<InlineAsm>(I.getCalledValue())) { 5513 visitInlineAsm(&I); 5514 return; 5515 } 5516 5517 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5518 ComputeUsesVAFloatArgument(I, &MMI); 5519 5520 const char *RenameFn = 0; 5521 if (Function *F = I.getCalledFunction()) { 5522 if (F->isDeclaration()) { 5523 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5524 if (unsigned IID = II->getIntrinsicID(F)) { 5525 RenameFn = visitIntrinsicCall(I, IID); 5526 if (!RenameFn) 5527 return; 5528 } 5529 } 5530 if (unsigned IID = F->getIntrinsicID()) { 5531 RenameFn = visitIntrinsicCall(I, IID); 5532 if (!RenameFn) 5533 return; 5534 } 5535 } 5536 5537 // Check for well-known libc/libm calls. If the function is internal, it 5538 // can't be a library call. 5539 if (!F->hasLocalLinkage() && F->hasName()) { 5540 StringRef Name = F->getName(); 5541 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5542 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5543 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5544 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5545 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5546 I.getType() == I.getArgOperand(0)->getType() && 5547 I.getType() == I.getArgOperand(1)->getType()) { 5548 SDValue LHS = getValue(I.getArgOperand(0)); 5549 SDValue RHS = getValue(I.getArgOperand(1)); 5550 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5551 LHS.getValueType(), LHS, RHS)); 5552 return; 5553 } 5554 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5555 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5556 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5557 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5558 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5559 I.getType() == I.getArgOperand(0)->getType()) { 5560 SDValue Tmp = getValue(I.getArgOperand(0)); 5561 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5562 Tmp.getValueType(), Tmp)); 5563 return; 5564 } 5565 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5566 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5567 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5568 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5569 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5570 I.getType() == I.getArgOperand(0)->getType() && 5571 I.onlyReadsMemory()) { 5572 SDValue Tmp = getValue(I.getArgOperand(0)); 5573 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5574 Tmp.getValueType(), Tmp)); 5575 return; 5576 } 5577 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5578 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5579 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5580 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5581 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5582 I.getType() == I.getArgOperand(0)->getType() && 5583 I.onlyReadsMemory()) { 5584 SDValue Tmp = getValue(I.getArgOperand(0)); 5585 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5586 Tmp.getValueType(), Tmp)); 5587 return; 5588 } 5589 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5590 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5591 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5592 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5593 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5594 I.getType() == I.getArgOperand(0)->getType() && 5595 I.onlyReadsMemory()) { 5596 SDValue Tmp = getValue(I.getArgOperand(0)); 5597 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5598 Tmp.getValueType(), Tmp)); 5599 return; 5600 } 5601 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5602 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5603 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5604 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5605 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5606 I.getType() == I.getArgOperand(0)->getType()) { 5607 SDValue Tmp = getValue(I.getArgOperand(0)); 5608 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5609 Tmp.getValueType(), Tmp)); 5610 return; 5611 } 5612 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5613 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5614 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5615 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5616 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5617 I.getType() == I.getArgOperand(0)->getType()) { 5618 SDValue Tmp = getValue(I.getArgOperand(0)); 5619 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5620 Tmp.getValueType(), Tmp)); 5621 return; 5622 } 5623 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5624 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5625 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5626 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5627 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5628 I.getType() == I.getArgOperand(0)->getType()) { 5629 SDValue Tmp = getValue(I.getArgOperand(0)); 5630 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5631 Tmp.getValueType(), Tmp)); 5632 return; 5633 } 5634 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5635 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5636 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5637 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5638 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5639 I.getType() == I.getArgOperand(0)->getType()) { 5640 SDValue Tmp = getValue(I.getArgOperand(0)); 5641 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5642 Tmp.getValueType(), Tmp)); 5643 return; 5644 } 5645 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5646 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5647 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5648 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5649 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5650 I.getType() == I.getArgOperand(0)->getType()) { 5651 SDValue Tmp = getValue(I.getArgOperand(0)); 5652 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5653 Tmp.getValueType(), Tmp)); 5654 return; 5655 } 5656 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5657 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5658 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5659 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5660 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5661 I.getType() == I.getArgOperand(0)->getType() && 5662 I.onlyReadsMemory()) { 5663 SDValue Tmp = getValue(I.getArgOperand(0)); 5664 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5665 Tmp.getValueType(), Tmp)); 5666 return; 5667 } 5668 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5669 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5670 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5671 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5672 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5673 I.getType() == I.getArgOperand(0)->getType() && 5674 I.onlyReadsMemory()) { 5675 SDValue Tmp = getValue(I.getArgOperand(0)); 5676 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5677 Tmp.getValueType(), Tmp)); 5678 return; 5679 } 5680 } else if (Name == "memcmp") { 5681 if (visitMemCmpCall(I)) 5682 return; 5683 } 5684 } 5685 } 5686 5687 SDValue Callee; 5688 if (!RenameFn) 5689 Callee = getValue(I.getCalledValue()); 5690 else 5691 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5692 5693 // Check if we can potentially perform a tail call. More detailed checking is 5694 // be done within LowerCallTo, after more information about the call is known. 5695 LowerCallTo(&I, Callee, I.isTailCall()); 5696} 5697 5698namespace { 5699 5700/// AsmOperandInfo - This contains information for each constraint that we are 5701/// lowering. 5702class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5703public: 5704 /// CallOperand - If this is the result output operand or a clobber 5705 /// this is null, otherwise it is the incoming operand to the CallInst. 5706 /// This gets modified as the asm is processed. 5707 SDValue CallOperand; 5708 5709 /// AssignedRegs - If this is a register or register class operand, this 5710 /// contains the set of register corresponding to the operand. 5711 RegsForValue AssignedRegs; 5712 5713 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5714 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5715 } 5716 5717 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5718 /// corresponds to. If there is no Value* for this operand, it returns 5719 /// MVT::Other. 5720 EVT getCallOperandValEVT(LLVMContext &Context, 5721 const TargetLowering &TLI, 5722 const TargetData *TD) const { 5723 if (CallOperandVal == 0) return MVT::Other; 5724 5725 if (isa<BasicBlock>(CallOperandVal)) 5726 return TLI.getPointerTy(); 5727 5728 llvm::Type *OpTy = CallOperandVal->getType(); 5729 5730 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5731 // If this is an indirect operand, the operand is a pointer to the 5732 // accessed type. 5733 if (isIndirect) { 5734 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5735 if (!PtrTy) 5736 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5737 OpTy = PtrTy->getElementType(); 5738 } 5739 5740 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5741 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5742 if (STy->getNumElements() == 1) 5743 OpTy = STy->getElementType(0); 5744 5745 // If OpTy is not a single value, it may be a struct/union that we 5746 // can tile with integers. 5747 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5748 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5749 switch (BitSize) { 5750 default: break; 5751 case 1: 5752 case 8: 5753 case 16: 5754 case 32: 5755 case 64: 5756 case 128: 5757 OpTy = IntegerType::get(Context, BitSize); 5758 break; 5759 } 5760 } 5761 5762 return TLI.getValueType(OpTy, true); 5763 } 5764}; 5765 5766typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5767 5768} // end anonymous namespace 5769 5770/// GetRegistersForValue - Assign registers (virtual or physical) for the 5771/// specified operand. We prefer to assign virtual registers, to allow the 5772/// register allocator to handle the assignment process. However, if the asm 5773/// uses features that we can't model on machineinstrs, we have SDISel do the 5774/// allocation. This produces generally horrible, but correct, code. 5775/// 5776/// OpInfo describes the operand. 5777/// 5778static void GetRegistersForValue(SelectionDAG &DAG, 5779 const TargetLowering &TLI, 5780 DebugLoc DL, 5781 SDISelAsmOperandInfo &OpInfo) { 5782 LLVMContext &Context = *DAG.getContext(); 5783 5784 MachineFunction &MF = DAG.getMachineFunction(); 5785 SmallVector<unsigned, 4> Regs; 5786 5787 // If this is a constraint for a single physreg, or a constraint for a 5788 // register class, find it. 5789 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5790 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5791 OpInfo.ConstraintVT); 5792 5793 unsigned NumRegs = 1; 5794 if (OpInfo.ConstraintVT != MVT::Other) { 5795 // If this is a FP input in an integer register (or visa versa) insert a bit 5796 // cast of the input value. More generally, handle any case where the input 5797 // value disagrees with the register class we plan to stick this in. 5798 if (OpInfo.Type == InlineAsm::isInput && 5799 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5800 // Try to convert to the first EVT that the reg class contains. If the 5801 // types are identical size, use a bitcast to convert (e.g. two differing 5802 // vector types). 5803 EVT RegVT = *PhysReg.second->vt_begin(); 5804 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5805 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5806 RegVT, OpInfo.CallOperand); 5807 OpInfo.ConstraintVT = RegVT; 5808 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5809 // If the input is a FP value and we want it in FP registers, do a 5810 // bitcast to the corresponding integer type. This turns an f64 value 5811 // into i64, which can be passed with two i32 values on a 32-bit 5812 // machine. 5813 RegVT = EVT::getIntegerVT(Context, 5814 OpInfo.ConstraintVT.getSizeInBits()); 5815 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5816 RegVT, OpInfo.CallOperand); 5817 OpInfo.ConstraintVT = RegVT; 5818 } 5819 } 5820 5821 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5822 } 5823 5824 EVT RegVT; 5825 EVT ValueVT = OpInfo.ConstraintVT; 5826 5827 // If this is a constraint for a specific physical register, like {r17}, 5828 // assign it now. 5829 if (unsigned AssignedReg = PhysReg.first) { 5830 const TargetRegisterClass *RC = PhysReg.second; 5831 if (OpInfo.ConstraintVT == MVT::Other) 5832 ValueVT = *RC->vt_begin(); 5833 5834 // Get the actual register value type. This is important, because the user 5835 // may have asked for (e.g.) the AX register in i32 type. We need to 5836 // remember that AX is actually i16 to get the right extension. 5837 RegVT = *RC->vt_begin(); 5838 5839 // This is a explicit reference to a physical register. 5840 Regs.push_back(AssignedReg); 5841 5842 // If this is an expanded reference, add the rest of the regs to Regs. 5843 if (NumRegs != 1) { 5844 TargetRegisterClass::iterator I = RC->begin(); 5845 for (; *I != AssignedReg; ++I) 5846 assert(I != RC->end() && "Didn't find reg!"); 5847 5848 // Already added the first reg. 5849 --NumRegs; ++I; 5850 for (; NumRegs; --NumRegs, ++I) { 5851 assert(I != RC->end() && "Ran out of registers to allocate!"); 5852 Regs.push_back(*I); 5853 } 5854 } 5855 5856 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5857 return; 5858 } 5859 5860 // Otherwise, if this was a reference to an LLVM register class, create vregs 5861 // for this reference. 5862 if (const TargetRegisterClass *RC = PhysReg.second) { 5863 RegVT = *RC->vt_begin(); 5864 if (OpInfo.ConstraintVT == MVT::Other) 5865 ValueVT = RegVT; 5866 5867 // Create the appropriate number of virtual registers. 5868 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5869 for (; NumRegs; --NumRegs) 5870 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5871 5872 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5873 return; 5874 } 5875 5876 // Otherwise, we couldn't allocate enough registers for this. 5877} 5878 5879/// visitInlineAsm - Handle a call to an InlineAsm object. 5880/// 5881void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5882 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5883 5884 /// ConstraintOperands - Information about all of the constraints. 5885 SDISelAsmOperandInfoVector ConstraintOperands; 5886 5887 TargetLowering::AsmOperandInfoVector 5888 TargetConstraints = TLI.ParseConstraints(CS); 5889 5890 bool hasMemory = false; 5891 5892 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5893 unsigned ResNo = 0; // ResNo - The result number of the next output. 5894 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5895 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5896 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5897 5898 EVT OpVT = MVT::Other; 5899 5900 // Compute the value type for each operand. 5901 switch (OpInfo.Type) { 5902 case InlineAsm::isOutput: 5903 // Indirect outputs just consume an argument. 5904 if (OpInfo.isIndirect) { 5905 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5906 break; 5907 } 5908 5909 // The return value of the call is this value. As such, there is no 5910 // corresponding argument. 5911 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5912 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5913 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5914 } else { 5915 assert(ResNo == 0 && "Asm only has one result!"); 5916 OpVT = TLI.getValueType(CS.getType()); 5917 } 5918 ++ResNo; 5919 break; 5920 case InlineAsm::isInput: 5921 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5922 break; 5923 case InlineAsm::isClobber: 5924 // Nothing to do. 5925 break; 5926 } 5927 5928 // If this is an input or an indirect output, process the call argument. 5929 // BasicBlocks are labels, currently appearing only in asm's. 5930 if (OpInfo.CallOperandVal) { 5931 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5932 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5933 } else { 5934 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5935 } 5936 5937 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5938 } 5939 5940 OpInfo.ConstraintVT = OpVT; 5941 5942 // Indirect operand accesses access memory. 5943 if (OpInfo.isIndirect) 5944 hasMemory = true; 5945 else { 5946 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5947 TargetLowering::ConstraintType 5948 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5949 if (CType == TargetLowering::C_Memory) { 5950 hasMemory = true; 5951 break; 5952 } 5953 } 5954 } 5955 } 5956 5957 SDValue Chain, Flag; 5958 5959 // We won't need to flush pending loads if this asm doesn't touch 5960 // memory and is nonvolatile. 5961 if (hasMemory || IA->hasSideEffects()) 5962 Chain = getRoot(); 5963 else 5964 Chain = DAG.getRoot(); 5965 5966 // Second pass over the constraints: compute which constraint option to use 5967 // and assign registers to constraints that want a specific physreg. 5968 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5969 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5970 5971 // If this is an output operand with a matching input operand, look up the 5972 // matching input. If their types mismatch, e.g. one is an integer, the 5973 // other is floating point, or their sizes are different, flag it as an 5974 // error. 5975 if (OpInfo.hasMatchingInput()) { 5976 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5977 5978 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5979 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5980 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5981 OpInfo.ConstraintVT); 5982 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5983 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5984 Input.ConstraintVT); 5985 if ((OpInfo.ConstraintVT.isInteger() != 5986 Input.ConstraintVT.isInteger()) || 5987 (MatchRC.second != InputRC.second)) { 5988 report_fatal_error("Unsupported asm: input constraint" 5989 " with a matching output constraint of" 5990 " incompatible type!"); 5991 } 5992 Input.ConstraintVT = OpInfo.ConstraintVT; 5993 } 5994 } 5995 5996 // Compute the constraint code and ConstraintType to use. 5997 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5998 5999 // If this is a memory input, and if the operand is not indirect, do what we 6000 // need to to provide an address for the memory input. 6001 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6002 !OpInfo.isIndirect) { 6003 assert((OpInfo.isMultipleAlternative || 6004 (OpInfo.Type == InlineAsm::isInput)) && 6005 "Can only indirectify direct input operands!"); 6006 6007 // Memory operands really want the address of the value. If we don't have 6008 // an indirect input, put it in the constpool if we can, otherwise spill 6009 // it to a stack slot. 6010 // TODO: This isn't quite right. We need to handle these according to 6011 // the addressing mode that the constraint wants. Also, this may take 6012 // an additional register for the computation and we don't want that 6013 // either. 6014 6015 // If the operand is a float, integer, or vector constant, spill to a 6016 // constant pool entry to get its address. 6017 const Value *OpVal = OpInfo.CallOperandVal; 6018 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6019 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6020 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6021 TLI.getPointerTy()); 6022 } else { 6023 // Otherwise, create a stack slot and emit a store to it before the 6024 // asm. 6025 Type *Ty = OpVal->getType(); 6026 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6027 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6028 MachineFunction &MF = DAG.getMachineFunction(); 6029 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6030 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6031 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6032 OpInfo.CallOperand, StackSlot, 6033 MachinePointerInfo::getFixedStack(SSFI), 6034 false, false, 0); 6035 OpInfo.CallOperand = StackSlot; 6036 } 6037 6038 // There is no longer a Value* corresponding to this operand. 6039 OpInfo.CallOperandVal = 0; 6040 6041 // It is now an indirect operand. 6042 OpInfo.isIndirect = true; 6043 } 6044 6045 // If this constraint is for a specific register, allocate it before 6046 // anything else. 6047 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6048 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6049 } 6050 6051 // Second pass - Loop over all of the operands, assigning virtual or physregs 6052 // to register class operands. 6053 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6054 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6055 6056 // C_Register operands have already been allocated, Other/Memory don't need 6057 // to be. 6058 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6059 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6060 } 6061 6062 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6063 std::vector<SDValue> AsmNodeOperands; 6064 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6065 AsmNodeOperands.push_back( 6066 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6067 TLI.getPointerTy())); 6068 6069 // If we have a !srcloc metadata node associated with it, we want to attach 6070 // this to the ultimately generated inline asm machineinstr. To do this, we 6071 // pass in the third operand as this (potentially null) inline asm MDNode. 6072 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6073 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6074 6075 // Remember the HasSideEffect and AlignStack bits as operand 3. 6076 unsigned ExtraInfo = 0; 6077 if (IA->hasSideEffects()) 6078 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6079 if (IA->isAlignStack()) 6080 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6081 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6082 TLI.getPointerTy())); 6083 6084 // Loop over all of the inputs, copying the operand values into the 6085 // appropriate registers and processing the output regs. 6086 RegsForValue RetValRegs; 6087 6088 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6089 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6090 6091 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6092 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6093 6094 switch (OpInfo.Type) { 6095 case InlineAsm::isOutput: { 6096 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6097 OpInfo.ConstraintType != TargetLowering::C_Register) { 6098 // Memory output, or 'other' output (e.g. 'X' constraint). 6099 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6100 6101 // Add information to the INLINEASM node to know about this output. 6102 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6103 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6104 TLI.getPointerTy())); 6105 AsmNodeOperands.push_back(OpInfo.CallOperand); 6106 break; 6107 } 6108 6109 // Otherwise, this is a register or register class output. 6110 6111 // Copy the output from the appropriate register. Find a register that 6112 // we can use. 6113 if (OpInfo.AssignedRegs.Regs.empty()) { 6114 LLVMContext &Ctx = *DAG.getContext(); 6115 Ctx.emitError(CS.getInstruction(), 6116 "couldn't allocate output register for constraint '" + 6117 Twine(OpInfo.ConstraintCode) + "'"); 6118 break; 6119 } 6120 6121 // If this is an indirect operand, store through the pointer after the 6122 // asm. 6123 if (OpInfo.isIndirect) { 6124 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6125 OpInfo.CallOperandVal)); 6126 } else { 6127 // This is the result value of the call. 6128 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6129 // Concatenate this output onto the outputs list. 6130 RetValRegs.append(OpInfo.AssignedRegs); 6131 } 6132 6133 // Add information to the INLINEASM node to know that this register is 6134 // set. 6135 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6136 InlineAsm::Kind_RegDefEarlyClobber : 6137 InlineAsm::Kind_RegDef, 6138 false, 6139 0, 6140 DAG, 6141 AsmNodeOperands); 6142 break; 6143 } 6144 case InlineAsm::isInput: { 6145 SDValue InOperandVal = OpInfo.CallOperand; 6146 6147 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6148 // If this is required to match an output register we have already set, 6149 // just use its register. 6150 unsigned OperandNo = OpInfo.getMatchedOperand(); 6151 6152 // Scan until we find the definition we already emitted of this operand. 6153 // When we find it, create a RegsForValue operand. 6154 unsigned CurOp = InlineAsm::Op_FirstOperand; 6155 for (; OperandNo; --OperandNo) { 6156 // Advance to the next operand. 6157 unsigned OpFlag = 6158 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6159 assert((InlineAsm::isRegDefKind(OpFlag) || 6160 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6161 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6162 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6163 } 6164 6165 unsigned OpFlag = 6166 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6167 if (InlineAsm::isRegDefKind(OpFlag) || 6168 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6169 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6170 if (OpInfo.isIndirect) { 6171 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6172 LLVMContext &Ctx = *DAG.getContext(); 6173 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6174 " don't know how to handle tied " 6175 "indirect register inputs"); 6176 } 6177 6178 RegsForValue MatchedRegs; 6179 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6180 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6181 MatchedRegs.RegVTs.push_back(RegVT); 6182 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6183 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6184 i != e; ++i) 6185 MatchedRegs.Regs.push_back 6186 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6187 6188 // Use the produced MatchedRegs object to 6189 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6190 Chain, &Flag); 6191 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6192 true, OpInfo.getMatchedOperand(), 6193 DAG, AsmNodeOperands); 6194 break; 6195 } 6196 6197 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6198 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6199 "Unexpected number of operands"); 6200 // Add information to the INLINEASM node to know about this input. 6201 // See InlineAsm.h isUseOperandTiedToDef. 6202 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6203 OpInfo.getMatchedOperand()); 6204 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6205 TLI.getPointerTy())); 6206 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6207 break; 6208 } 6209 6210 // Treat indirect 'X' constraint as memory. 6211 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6212 OpInfo.isIndirect) 6213 OpInfo.ConstraintType = TargetLowering::C_Memory; 6214 6215 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6216 std::vector<SDValue> Ops; 6217 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6218 Ops, DAG); 6219 if (Ops.empty()) { 6220 LLVMContext &Ctx = *DAG.getContext(); 6221 Ctx.emitError(CS.getInstruction(), 6222 "invalid operand for inline asm constraint '" + 6223 Twine(OpInfo.ConstraintCode) + "'"); 6224 break; 6225 } 6226 6227 // Add information to the INLINEASM node to know about this input. 6228 unsigned ResOpType = 6229 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6230 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6231 TLI.getPointerTy())); 6232 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6233 break; 6234 } 6235 6236 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6237 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6238 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6239 "Memory operands expect pointer values"); 6240 6241 // Add information to the INLINEASM node to know about this input. 6242 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6243 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6244 TLI.getPointerTy())); 6245 AsmNodeOperands.push_back(InOperandVal); 6246 break; 6247 } 6248 6249 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6250 OpInfo.ConstraintType == TargetLowering::C_Register) && 6251 "Unknown constraint type!"); 6252 6253 // TODO: Support this. 6254 if (OpInfo.isIndirect) { 6255 LLVMContext &Ctx = *DAG.getContext(); 6256 Ctx.emitError(CS.getInstruction(), 6257 "Don't know how to handle indirect register inputs yet " 6258 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6259 break; 6260 } 6261 6262 // Copy the input into the appropriate registers. 6263 if (OpInfo.AssignedRegs.Regs.empty()) { 6264 LLVMContext &Ctx = *DAG.getContext(); 6265 Ctx.emitError(CS.getInstruction(), 6266 "couldn't allocate input reg for constraint '" + 6267 Twine(OpInfo.ConstraintCode) + "'"); 6268 break; 6269 } 6270 6271 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6272 Chain, &Flag); 6273 6274 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6275 DAG, AsmNodeOperands); 6276 break; 6277 } 6278 case InlineAsm::isClobber: { 6279 // Add the clobbered value to the operand list, so that the register 6280 // allocator is aware that the physreg got clobbered. 6281 if (!OpInfo.AssignedRegs.Regs.empty()) 6282 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6283 false, 0, DAG, 6284 AsmNodeOperands); 6285 break; 6286 } 6287 } 6288 } 6289 6290 // Finish up input operands. Set the input chain and add the flag last. 6291 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6292 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6293 6294 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6295 DAG.getVTList(MVT::Other, MVT::Glue), 6296 &AsmNodeOperands[0], AsmNodeOperands.size()); 6297 Flag = Chain.getValue(1); 6298 6299 // If this asm returns a register value, copy the result from that register 6300 // and set it as the value of the call. 6301 if (!RetValRegs.Regs.empty()) { 6302 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6303 Chain, &Flag); 6304 6305 // FIXME: Why don't we do this for inline asms with MRVs? 6306 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6307 EVT ResultType = TLI.getValueType(CS.getType()); 6308 6309 // If any of the results of the inline asm is a vector, it may have the 6310 // wrong width/num elts. This can happen for register classes that can 6311 // contain multiple different value types. The preg or vreg allocated may 6312 // not have the same VT as was expected. Convert it to the right type 6313 // with bit_convert. 6314 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6315 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6316 ResultType, Val); 6317 6318 } else if (ResultType != Val.getValueType() && 6319 ResultType.isInteger() && Val.getValueType().isInteger()) { 6320 // If a result value was tied to an input value, the computed result may 6321 // have a wider width than the expected result. Extract the relevant 6322 // portion. 6323 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6324 } 6325 6326 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6327 } 6328 6329 setValue(CS.getInstruction(), Val); 6330 // Don't need to use this as a chain in this case. 6331 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6332 return; 6333 } 6334 6335 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6336 6337 // Process indirect outputs, first output all of the flagged copies out of 6338 // physregs. 6339 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6340 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6341 const Value *Ptr = IndirectStoresToEmit[i].second; 6342 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6343 Chain, &Flag); 6344 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6345 } 6346 6347 // Emit the non-flagged stores from the physregs. 6348 SmallVector<SDValue, 8> OutChains; 6349 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6350 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6351 StoresToEmit[i].first, 6352 getValue(StoresToEmit[i].second), 6353 MachinePointerInfo(StoresToEmit[i].second), 6354 false, false, 0); 6355 OutChains.push_back(Val); 6356 } 6357 6358 if (!OutChains.empty()) 6359 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6360 &OutChains[0], OutChains.size()); 6361 6362 DAG.setRoot(Chain); 6363} 6364 6365void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6366 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6367 MVT::Other, getRoot(), 6368 getValue(I.getArgOperand(0)), 6369 DAG.getSrcValue(I.getArgOperand(0)))); 6370} 6371 6372void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6373 const TargetData &TD = *TLI.getTargetData(); 6374 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6375 getRoot(), getValue(I.getOperand(0)), 6376 DAG.getSrcValue(I.getOperand(0)), 6377 TD.getABITypeAlignment(I.getType())); 6378 setValue(&I, V); 6379 DAG.setRoot(V.getValue(1)); 6380} 6381 6382void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6383 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6384 MVT::Other, getRoot(), 6385 getValue(I.getArgOperand(0)), 6386 DAG.getSrcValue(I.getArgOperand(0)))); 6387} 6388 6389void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6390 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6391 MVT::Other, getRoot(), 6392 getValue(I.getArgOperand(0)), 6393 getValue(I.getArgOperand(1)), 6394 DAG.getSrcValue(I.getArgOperand(0)), 6395 DAG.getSrcValue(I.getArgOperand(1)))); 6396} 6397 6398/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6399/// implementation, which just calls LowerCall. 6400/// FIXME: When all targets are 6401/// migrated to using LowerCall, this hook should be integrated into SDISel. 6402std::pair<SDValue, SDValue> 6403TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6404 // Handle all of the outgoing arguments. 6405 CLI.Outs.clear(); 6406 CLI.OutVals.clear(); 6407 ArgListTy &Args = CLI.Args; 6408 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6409 SmallVector<EVT, 4> ValueVTs; 6410 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6411 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6412 Value != NumValues; ++Value) { 6413 EVT VT = ValueVTs[Value]; 6414 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6415 SDValue Op = SDValue(Args[i].Node.getNode(), 6416 Args[i].Node.getResNo() + Value); 6417 ISD::ArgFlagsTy Flags; 6418 unsigned OriginalAlignment = 6419 getTargetData()->getABITypeAlignment(ArgTy); 6420 6421 if (Args[i].isZExt) 6422 Flags.setZExt(); 6423 if (Args[i].isSExt) 6424 Flags.setSExt(); 6425 if (Args[i].isInReg) 6426 Flags.setInReg(); 6427 if (Args[i].isSRet) 6428 Flags.setSRet(); 6429 if (Args[i].isByVal) { 6430 Flags.setByVal(); 6431 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6432 Type *ElementTy = Ty->getElementType(); 6433 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6434 // For ByVal, alignment should come from FE. BE will guess if this 6435 // info is not there but there are cases it cannot get right. 6436 unsigned FrameAlign; 6437 if (Args[i].Alignment) 6438 FrameAlign = Args[i].Alignment; 6439 else 6440 FrameAlign = getByValTypeAlignment(ElementTy); 6441 Flags.setByValAlign(FrameAlign); 6442 } 6443 if (Args[i].isNest) 6444 Flags.setNest(); 6445 Flags.setOrigAlign(OriginalAlignment); 6446 6447 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6448 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6449 SmallVector<SDValue, 4> Parts(NumParts); 6450 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6451 6452 if (Args[i].isSExt) 6453 ExtendKind = ISD::SIGN_EXTEND; 6454 else if (Args[i].isZExt) 6455 ExtendKind = ISD::ZERO_EXTEND; 6456 6457 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6458 PartVT, ExtendKind); 6459 6460 for (unsigned j = 0; j != NumParts; ++j) { 6461 // if it isn't first piece, alignment must be 1 6462 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6463 i < CLI.NumFixedArgs); 6464 if (NumParts > 1 && j == 0) 6465 MyFlags.Flags.setSplit(); 6466 else if (j != 0) 6467 MyFlags.Flags.setOrigAlign(1); 6468 6469 CLI.Outs.push_back(MyFlags); 6470 CLI.OutVals.push_back(Parts[j]); 6471 } 6472 } 6473 } 6474 6475 // Handle the incoming return values from the call. 6476 CLI.Ins.clear(); 6477 SmallVector<EVT, 4> RetTys; 6478 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6479 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6480 EVT VT = RetTys[I]; 6481 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6482 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6483 for (unsigned i = 0; i != NumRegs; ++i) { 6484 ISD::InputArg MyFlags; 6485 MyFlags.VT = RegisterVT.getSimpleVT(); 6486 MyFlags.Used = CLI.IsReturnValueUsed; 6487 if (CLI.RetSExt) 6488 MyFlags.Flags.setSExt(); 6489 if (CLI.RetZExt) 6490 MyFlags.Flags.setZExt(); 6491 if (CLI.IsInReg) 6492 MyFlags.Flags.setInReg(); 6493 CLI.Ins.push_back(MyFlags); 6494 } 6495 } 6496 6497 SmallVector<SDValue, 4> InVals; 6498 CLI.Chain = LowerCall(CLI, InVals); 6499 6500 // Verify that the target's LowerCall behaved as expected. 6501 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6502 "LowerCall didn't return a valid chain!"); 6503 assert((!CLI.IsTailCall || InVals.empty()) && 6504 "LowerCall emitted a return value for a tail call!"); 6505 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6506 "LowerCall didn't emit the correct number of values!"); 6507 6508 // For a tail call, the return value is merely live-out and there aren't 6509 // any nodes in the DAG representing it. Return a special value to 6510 // indicate that a tail call has been emitted and no more Instructions 6511 // should be processed in the current block. 6512 if (CLI.IsTailCall) { 6513 CLI.DAG.setRoot(CLI.Chain); 6514 return std::make_pair(SDValue(), SDValue()); 6515 } 6516 6517 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6518 assert(InVals[i].getNode() && 6519 "LowerCall emitted a null value!"); 6520 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6521 "LowerCall emitted a value with the wrong type!"); 6522 }); 6523 6524 // Collect the legal value parts into potentially illegal values 6525 // that correspond to the original function's return values. 6526 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6527 if (CLI.RetSExt) 6528 AssertOp = ISD::AssertSext; 6529 else if (CLI.RetZExt) 6530 AssertOp = ISD::AssertZext; 6531 SmallVector<SDValue, 4> ReturnValues; 6532 unsigned CurReg = 0; 6533 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6534 EVT VT = RetTys[I]; 6535 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6536 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6537 6538 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6539 NumRegs, RegisterVT, VT, 6540 AssertOp)); 6541 CurReg += NumRegs; 6542 } 6543 6544 // For a function returning void, there is no return value. We can't create 6545 // such a node, so we just return a null return value in that case. In 6546 // that case, nothing will actually look at the value. 6547 if (ReturnValues.empty()) 6548 return std::make_pair(SDValue(), CLI.Chain); 6549 6550 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6551 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6552 &ReturnValues[0], ReturnValues.size()); 6553 return std::make_pair(Res, CLI.Chain); 6554} 6555 6556void TargetLowering::LowerOperationWrapper(SDNode *N, 6557 SmallVectorImpl<SDValue> &Results, 6558 SelectionDAG &DAG) const { 6559 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6560 if (Res.getNode()) 6561 Results.push_back(Res); 6562} 6563 6564SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6565 llvm_unreachable("LowerOperation not implemented for this target!"); 6566} 6567 6568void 6569SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6570 SDValue Op = getNonRegisterValue(V); 6571 assert((Op.getOpcode() != ISD::CopyFromReg || 6572 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6573 "Copy from a reg to the same reg!"); 6574 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6575 6576 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6577 SDValue Chain = DAG.getEntryNode(); 6578 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6579 PendingExports.push_back(Chain); 6580} 6581 6582#include "llvm/CodeGen/SelectionDAGISel.h" 6583 6584/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6585/// entry block, return true. This includes arguments used by switches, since 6586/// the switch may expand into multiple basic blocks. 6587static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6588 // With FastISel active, we may be splitting blocks, so force creation 6589 // of virtual registers for all non-dead arguments. 6590 if (FastISel) 6591 return A->use_empty(); 6592 6593 const BasicBlock *Entry = A->getParent()->begin(); 6594 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6595 UI != E; ++UI) { 6596 const User *U = *UI; 6597 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6598 return false; // Use not in entry block. 6599 } 6600 return true; 6601} 6602 6603void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6604 // If this is the entry block, emit arguments. 6605 const Function &F = *LLVMBB->getParent(); 6606 SelectionDAG &DAG = SDB->DAG; 6607 DebugLoc dl = SDB->getCurDebugLoc(); 6608 const TargetData *TD = TLI.getTargetData(); 6609 SmallVector<ISD::InputArg, 16> Ins; 6610 6611 // Check whether the function can return without sret-demotion. 6612 SmallVector<ISD::OutputArg, 4> Outs; 6613 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6614 Outs, TLI); 6615 6616 if (!FuncInfo->CanLowerReturn) { 6617 // Put in an sret pointer parameter before all the other parameters. 6618 SmallVector<EVT, 1> ValueVTs; 6619 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6620 6621 // NOTE: Assuming that a pointer will never break down to more than one VT 6622 // or one register. 6623 ISD::ArgFlagsTy Flags; 6624 Flags.setSRet(); 6625 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6626 ISD::InputArg RetArg(Flags, RegisterVT, true); 6627 Ins.push_back(RetArg); 6628 } 6629 6630 // Set up the incoming argument description vector. 6631 unsigned Idx = 1; 6632 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6633 I != E; ++I, ++Idx) { 6634 SmallVector<EVT, 4> ValueVTs; 6635 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6636 bool isArgValueUsed = !I->use_empty(); 6637 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6638 Value != NumValues; ++Value) { 6639 EVT VT = ValueVTs[Value]; 6640 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6641 ISD::ArgFlagsTy Flags; 6642 unsigned OriginalAlignment = 6643 TD->getABITypeAlignment(ArgTy); 6644 6645 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6646 Flags.setZExt(); 6647 if (F.paramHasAttr(Idx, Attribute::SExt)) 6648 Flags.setSExt(); 6649 if (F.paramHasAttr(Idx, Attribute::InReg)) 6650 Flags.setInReg(); 6651 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6652 Flags.setSRet(); 6653 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6654 Flags.setByVal(); 6655 PointerType *Ty = cast<PointerType>(I->getType()); 6656 Type *ElementTy = Ty->getElementType(); 6657 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6658 // For ByVal, alignment should be passed from FE. BE will guess if 6659 // this info is not there but there are cases it cannot get right. 6660 unsigned FrameAlign; 6661 if (F.getParamAlignment(Idx)) 6662 FrameAlign = F.getParamAlignment(Idx); 6663 else 6664 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6665 Flags.setByValAlign(FrameAlign); 6666 } 6667 if (F.paramHasAttr(Idx, Attribute::Nest)) 6668 Flags.setNest(); 6669 Flags.setOrigAlign(OriginalAlignment); 6670 6671 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6672 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6673 for (unsigned i = 0; i != NumRegs; ++i) { 6674 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6675 if (NumRegs > 1 && i == 0) 6676 MyFlags.Flags.setSplit(); 6677 // if it isn't first piece, alignment must be 1 6678 else if (i > 0) 6679 MyFlags.Flags.setOrigAlign(1); 6680 Ins.push_back(MyFlags); 6681 } 6682 } 6683 } 6684 6685 // Call the target to set up the argument values. 6686 SmallVector<SDValue, 8> InVals; 6687 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6688 F.isVarArg(), Ins, 6689 dl, DAG, InVals); 6690 6691 // Verify that the target's LowerFormalArguments behaved as expected. 6692 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6693 "LowerFormalArguments didn't return a valid chain!"); 6694 assert(InVals.size() == Ins.size() && 6695 "LowerFormalArguments didn't emit the correct number of values!"); 6696 DEBUG({ 6697 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6698 assert(InVals[i].getNode() && 6699 "LowerFormalArguments emitted a null value!"); 6700 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6701 "LowerFormalArguments emitted a value with the wrong type!"); 6702 } 6703 }); 6704 6705 // Update the DAG with the new chain value resulting from argument lowering. 6706 DAG.setRoot(NewRoot); 6707 6708 // Set up the argument values. 6709 unsigned i = 0; 6710 Idx = 1; 6711 if (!FuncInfo->CanLowerReturn) { 6712 // Create a virtual register for the sret pointer, and put in a copy 6713 // from the sret argument into it. 6714 SmallVector<EVT, 1> ValueVTs; 6715 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6716 EVT VT = ValueVTs[0]; 6717 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6718 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6719 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6720 RegVT, VT, AssertOp); 6721 6722 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6723 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6724 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6725 FuncInfo->DemoteRegister = SRetReg; 6726 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6727 SRetReg, ArgValue); 6728 DAG.setRoot(NewRoot); 6729 6730 // i indexes lowered arguments. Bump it past the hidden sret argument. 6731 // Idx indexes LLVM arguments. Don't touch it. 6732 ++i; 6733 } 6734 6735 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6736 ++I, ++Idx) { 6737 SmallVector<SDValue, 4> ArgValues; 6738 SmallVector<EVT, 4> ValueVTs; 6739 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6740 unsigned NumValues = ValueVTs.size(); 6741 6742 // If this argument is unused then remember its value. It is used to generate 6743 // debugging information. 6744 if (I->use_empty() && NumValues) 6745 SDB->setUnusedArgValue(I, InVals[i]); 6746 6747 for (unsigned Val = 0; Val != NumValues; ++Val) { 6748 EVT VT = ValueVTs[Val]; 6749 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6750 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6751 6752 if (!I->use_empty()) { 6753 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6754 if (F.paramHasAttr(Idx, Attribute::SExt)) 6755 AssertOp = ISD::AssertSext; 6756 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6757 AssertOp = ISD::AssertZext; 6758 6759 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6760 NumParts, PartVT, VT, 6761 AssertOp)); 6762 } 6763 6764 i += NumParts; 6765 } 6766 6767 // We don't need to do anything else for unused arguments. 6768 if (ArgValues.empty()) 6769 continue; 6770 6771 // Note down frame index. 6772 if (FrameIndexSDNode *FI = 6773 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6774 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6775 6776 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6777 SDB->getCurDebugLoc()); 6778 6779 SDB->setValue(I, Res); 6780 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6781 if (LoadSDNode *LNode = 6782 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6783 if (FrameIndexSDNode *FI = 6784 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6785 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6786 } 6787 6788 // If this argument is live outside of the entry block, insert a copy from 6789 // wherever we got it to the vreg that other BB's will reference it as. 6790 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6791 // If we can, though, try to skip creating an unnecessary vreg. 6792 // FIXME: This isn't very clean... it would be nice to make this more 6793 // general. It's also subtly incompatible with the hacks FastISel 6794 // uses with vregs. 6795 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6796 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6797 FuncInfo->ValueMap[I] = Reg; 6798 continue; 6799 } 6800 } 6801 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6802 FuncInfo->InitializeRegForValue(I); 6803 SDB->CopyToExportRegsIfNeeded(I); 6804 } 6805 } 6806 6807 assert(i == InVals.size() && "Argument register count mismatch!"); 6808 6809 // Finally, if the target has anything special to do, allow it to do so. 6810 // FIXME: this should insert code into the DAG! 6811 EmitFunctionEntryCode(); 6812} 6813 6814/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6815/// ensure constants are generated when needed. Remember the virtual registers 6816/// that need to be added to the Machine PHI nodes as input. We cannot just 6817/// directly add them, because expansion might result in multiple MBB's for one 6818/// BB. As such, the start of the BB might correspond to a different MBB than 6819/// the end. 6820/// 6821void 6822SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6823 const TerminatorInst *TI = LLVMBB->getTerminator(); 6824 6825 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6826 6827 // Check successor nodes' PHI nodes that expect a constant to be available 6828 // from this block. 6829 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6830 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6831 if (!isa<PHINode>(SuccBB->begin())) continue; 6832 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6833 6834 // If this terminator has multiple identical successors (common for 6835 // switches), only handle each succ once. 6836 if (!SuccsHandled.insert(SuccMBB)) continue; 6837 6838 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6839 6840 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6841 // nodes and Machine PHI nodes, but the incoming operands have not been 6842 // emitted yet. 6843 for (BasicBlock::const_iterator I = SuccBB->begin(); 6844 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6845 // Ignore dead phi's. 6846 if (PN->use_empty()) continue; 6847 6848 // Skip empty types 6849 if (PN->getType()->isEmptyTy()) 6850 continue; 6851 6852 unsigned Reg; 6853 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6854 6855 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6856 unsigned &RegOut = ConstantsOut[C]; 6857 if (RegOut == 0) { 6858 RegOut = FuncInfo.CreateRegs(C->getType()); 6859 CopyValueToVirtualRegister(C, RegOut); 6860 } 6861 Reg = RegOut; 6862 } else { 6863 DenseMap<const Value *, unsigned>::iterator I = 6864 FuncInfo.ValueMap.find(PHIOp); 6865 if (I != FuncInfo.ValueMap.end()) 6866 Reg = I->second; 6867 else { 6868 assert(isa<AllocaInst>(PHIOp) && 6869 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6870 "Didn't codegen value into a register!??"); 6871 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6872 CopyValueToVirtualRegister(PHIOp, Reg); 6873 } 6874 } 6875 6876 // Remember that this register needs to added to the machine PHI node as 6877 // the input for this MBB. 6878 SmallVector<EVT, 4> ValueVTs; 6879 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6880 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6881 EVT VT = ValueVTs[vti]; 6882 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6883 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6884 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6885 Reg += NumRegisters; 6886 } 6887 } 6888 } 6889 ConstantsOut.clear(); 6890} 6891